Error rate measuring device and automatic phase adjustment method using said device

Abstract

To precisely match the phase of a clock input to a device under test with the center of a phase margin.SOLUTION: A phase amount calculation unit 6b calculates, as a phase amount for coarse adjustment for each component of a device 2 to be adjusted, a phase amount corresponding to a center position between an upper limit position and a lower limit position where an error is detected using an error detection unit 6a by varying the phase of a clock under the control of increase and decrease of the phase amount of a coarse adjustment phase variable device 5a, and calculates, as a phase amount for fine adjustment for each component of the device 2 to be adjusted, a phase amount corresponding to the presence or absence of an error detected by the error detection unit 6a when the phase of the clock is varied by controlling the increase and decrease of the phase amount of a fine adjustment phase variable device 5b. A phase amount control unit 6c controls the phase amount of the coarse adjustment phase variable device 5a for each component of the adjusted device 2 such that the clock phase becomes the phase amount for coarse adjustment, and then controls the phase amount of the fine adjustment phase variable device 5b such that the clock phase becomes the phase amount for fine adjustment.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an error rate measuring apparatus capable of automatic phase adjustment of an adjusted device (such as a waveform shaping IC) that requires clock phase adjustment to synchronize data input from a control unit such as an FPGA (field-programmable gate array) built into the apparatus, and an automatic phase adjustment method using the apparatus. [Background technology]

[0002] In recent years, datacenter and network traffic volumes have been steadily increasing, and the transmission speeds of devices and communication standards used in the physical layer are also becoming faster and larger in capacity. Accordingly, error rate measurement devices are also required to have higher bit rates and modulation rates. For example, PCI Express 5.0, which uses NRZ signals at 32 Gbit / s per lane, and 400G Ethernet (registered trademark), which uses PAM4 signals at a modulation rate of 53.125 Gbaud per lane, have been established.

[0003] Incidentally, in ICs used in error rate measurement equipment that have data inputs and clock inputs for timing synchronization, such as MUX (multiplexer), DEMUX (demultiplexer), and D-FF (delay flip-flop), the phase relationship between the data input and the clock input must be within a tolerance, i.e., within a phase margin. If the phase relationship between the data and clock deviates from the phase margin, bit errors will occur within the error rate measurement equipment, preventing the user from measuring the error rate accurately. Therefore, error rate measurement equipment is equipped with a phase variable device that allows the clock phase to be adjusted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-175277 Summary of the Invention [Problem to be solved by the invention]

[0005] However, if the bit rate of the data input to these ICs is increased in order to speed up the error rate measurement equipment, the phase margin will become narrower accordingly, posing a problem that requires highly accurate clock phase adjustment.

[0006] Furthermore, because the data and clock input to these ICs pass through different paths with different components inside the error rate measurement device, the amount of phase change due to temperature differs for each path. This creates the problem that the more the temperature changes from the time of adjustment, the more the phase relationship between the data and clock deviates. If the phase relationship deviates from the optimal value, bit errors become more likely to occur inside the error rate measurement device, and there is no room for adding jitter.

[0007] Furthermore, digitally controlled variable phase devices (variable delay ICs) have a maximum phase variation and a setting resolution, which generally represent a trade-off. If a variable phase device is selected to satisfy the phase variation required to adjust the phase relationship within an error rate measurement device, the resolution may be too coarse for high bit rates, resulting in insufficient phase adjustment precision. For example, an 8-bit digitally controlled variable phase device with a resolution of 12 ps can achieve 21 phase settings for the ideal phase margin of 250 ps at 4 Gbit / s (without jitter), but only 6 points can be achieved for the ideal phase margin of 62.5 ps at 16 Gbit / s, resulting in insufficient setting resolution. In actual waveforms, the phase margin becomes even narrower due to the effects of jitter, resulting in only 3 or 4 points being achieved, making it difficult to accurately center the clock phase within the phase margin.

[0008] Therefore, the present invention has been made in consideration of the above problems, and has as its object to provide an error rate measuring apparatus that can accurately align the phase of a clock input to a device under test to the center of the phase margin, and an automatic phase adjustment method using said apparatus. [Means for solving the problem]

[0009] In order to achieve the above object, the error rate measurement apparatus according to claim 1 of the present invention is an error rate measurement apparatus 1 including a device under test 2 that processes data from a control unit 6 at the timing of a clock input via a phase variable device 5 whose phase amount is controllable, in order to automatically perform phase adjustment for each of a plurality of components of the device under test 2 inside the error rate measurement apparatus, and outputs a test signal for measuring the error rate to the device under test, a phase changer including a coarse adjustment phase changer 5a and a fine adjustment phase changer 5b having a resolution finer than that of the coarse adjustment phase changer, the number of which corresponds to the number of components of the device to be adjusted; The control unit a phase amount control unit 6c that varies the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and then varies the phase of the clock by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted, based on a coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased; an error detection unit 6a that detects upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and that detects a position where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock; the phase of the clock is varied by controlling the increase / decrease of the phase amount of the coarse adjustment phase variable device, and a phase amount corresponding to a center position between the upper limit position and the lower limit position at which an error is detected by the error detection unit is calculated as a phase amount for coarse adjustment for each component of the device to be adjusted, and the phase of the clock is varied by controlling the increase / decrease of the phase amount of the fine adjustment phase variable device; When the error detection unit detects only the upper limit position where an error occurs, the value obtained by subtracting half the value of the phase margin from the value of the upper limit position where the error is detected is set to a phase amount calculation unit (6b) for calculating a phase amount for fine adjustment for each component of the device to be adjusted, The phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted is controlled so that the phase of the clock becomes the phase amount for coarse adjustment, and then the phase amount of the fine adjustment phase variable device is controlled so that the phase of the clock becomes the phase amount for fine adjustment, thereby automatically adjusting the phase of the clock for each component of the device to be adjusted.

[0013] Claim 2 The error rate measurement device described in An error rate measurement apparatus (1) including a device (2) to be adjusted, which processes data from a control unit (6) at the timing of a clock input via a phase variable device (5) whose phase amount is controllable, in order to automatically perform phase adjustment for each of a plurality of components of the device (2) to be adjusted inside the error rate measurement apparatus, and outputs a test signal for measuring the error rate of the device to be measured, a phase changer including a coarse adjustment phase changer 5a and a fine adjustment phase changer 5b having a resolution finer than that of the coarse adjustment phase changer, the number of which corresponds to the number of components of the device to be adjusted; The control unit a phase amount control unit 6c that varies the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and then varies the phase of the clock by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted, based on a coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased; an error detection unit 6a that detects upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and that detects a position where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock; a phase amount for coarse adjustment corresponding to a center position between an upper limit position and a lower limit position where an error is detected by the error detection unit is calculated for each component of the device to be adjusted by varying the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase variable device; When the phase of the clock is varied by increasing or decreasing the phase amount of the fine-adjustment phase variable device, if the error detection unit detects only the lower limit position where an error occurs, the value obtained by adding the value of the lower limit position where the error is detected and half the value of the phase margin is calculated. A little Calculating a phase amount for adjustment for each component of the device to be adjusted a phase amount calculation unit 6b; After controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, the phase amount of the fine adjustment phase variable device is controlled so that the phase of the clock becomes the phase amount for fine adjustment, thereby automatically adjusting the phase of the clock for each component of the device to be adjusted. It is characterized by:

[0014] Claim 3 The automatic phase adjustment method using an error rate measurement apparatus described in the above is an automatic phase adjustment method using an error rate measurement apparatus 1 including an adjusted device 2 that processes data from a control unit 6 at the timing of a clock input via a phase variable device 5 whose phase amount is controllable, in order to automatically perform phase adjustment for each of a plurality of components of the adjusted device 2 inside the error rate measurement apparatus, and outputs a test signal for measuring the error rate to the device under test, providing a number of phase changers corresponding to the number of components of the device to be adjusted, the phase changers including a coarse adjustment phase changer and a fine adjustment phase changer having a finer resolution than the coarse adjustment phase changer; a step of increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and then increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted based on the coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased, to vary the phase of the clock; detecting upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and detecting a position where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted; the phase of the clock is varied by controlling the increase / decrease of the phase amount of the coarse adjustment phase variable device, and a phase amount corresponding to the center position between the upper limit position and the lower limit position where the error is detected is calculated as a phase amount for coarse adjustment for each component of the device to be adjusted, and the phase of the clock is varied by controlling the increase / decrease of the phase amount of the fine adjustment phase variable device; When only the upper limit position where an error occurs is detected, the value obtained by subtracting half the value of the phase margin from the upper limit position where the error was detected is used. calculating a phase amount for fine adjustment for each component of the device to be adjusted; and after controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, controlling the phase amount of the fine adjustment phase variable device so that the phase of the clock becomes the phase amount for fine adjustment, thereby automatically adjusting the phase of the clock for each component of the device to be adjusted.

[0018] Claim 4 The automatic phase adjustment method using the error rate measurement device described in An automatic phase adjustment method using an error rate measurement apparatus (1) including a device (2) to be adjusted, which processes data from a control unit (6) at the timing of a clock input via a phase variable device (5) whose phase amount is controllable, and outputs a test signal for measuring the error rate to the device under test, in order to automatically perform phase adjustment for each of a plurality of components of the device (2) to be adjusted inside the error rate measurement apparatus, providing a number of phase changers corresponding to the number of components of the device to be adjusted, the phase changers including a coarse adjustment phase changer and a fine adjustment phase changer having a finer resolution than the coarse adjustment phase changer; a step of increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and then increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted based on the coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased, to vary the phase of the clock; detecting upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and detecting a position where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted; a phase amount for coarse adjustment corresponding to a center position between the upper limit position and the lower limit position where the error is detected is calculated for each component of the device to be adjusted by varying the phase of the clock by controlling an increase or decrease in the phase amount of the coarse adjustment phase variable device;When the phase of the clock is varied by increasing or decreasing the phase amount of the fine-adjustment phase variable device, if only the lower limit position where an error occurs is detected, the value obtained by adding the value of the lower limit position where the error is detected and half the value of the phase margin is calculated. A little calculating a phase amount for adjustment for each component of the device to be adjusted; and, a step of controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, and then controlling the phase amount of the fine adjustment phase variable device so that the phase of the clock becomes the phase amount for fine adjustment, thereby automatically adjusting the phase of the clock for each component of the device to be adjusted; The present invention is characterized by comprising:

[0019] Claim 5 The error rate measurement device described in claim 1 or 2 In the error rate measuring device The error detection unit 6a is characterized in that it detects bit errors in input data received from the device under test in response to the input of the test signal.

[0020] Claim 6 The automatic phase adjustment method using the error rate measurement device described in claim 3 or 4 In the automatic phase adjustment method using the error rate measurement device of The method is characterized by including a step of detecting a bit error in input data received from the device under test in response to input of the test signal. [Effects of the Invention]

[0021] According to the present invention, the phase of the clock input to the device under test can be aligned with high precision to the center of the phase margin. In particular, even when the phase margin is narrowed due to an increase in bit rate, the clock phase can be aligned with high precision to the center of the phase margin, making it less likely that bit errors will occur in the error rate measurement device even if the phase relationship between the data and clock drifts due to temperature changes. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a block diagram showing a schematic configuration of an error rate measurement apparatus and a device under test according to the present invention; [Figure 2]10 is an explanatory diagram of an automatic phase adjustment method at a low bit rate using a coarse adjustment phase variable device of the error rate measuring device according to the present invention; FIG. [Figure 3] 10 is an explanatory diagram of an automatic phase adjustment method at a high bit rate using a coarse adjustment phase variable device of the error rate measurement device according to the present invention; FIG. [Figure 4] 10 is an explanatory diagram of an automatic phase adjustment method when upper and lower limits are found by phase adjustment by a fine adjustment phase variable device after phase adjustment by a coarse adjustment phase variable device of the error rate measurement device according to the present invention. FIG. [Figure 5] 10 is an explanatory diagram of an automatic phase adjustment method when the upper and lower limits cannot be found by phase adjustment by a fine adjustment phase variable device after phase adjustment by a coarse adjustment phase variable device of the error rate measurement device according to the present invention. FIG. [Figure 6] 10 is an explanatory diagram of an automatic phase adjustment method when only a lower limit is found by phase adjustment using a fine adjustment phase variable device after phase adjustment using a coarse adjustment phase variable device of the error rate measurement device according to the present invention. FIG. [Figure 7] 10 is an explanatory diagram of an automatic phase adjustment method when only an upper limit is found by phase adjustment using a fine adjustment phase variable device after phase adjustment using a coarse adjustment phase variable device of the error rate measurement device according to the present invention. FIG. [Figure 8] FIG. 10 is a diagram illustrating an example of a table showing the relationship between the bit rate and the phase offset amount equivalent to half the phase margin. DETAILED DESCRIPTION OF THE INVENTION

[0023] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0024] The error rate measurement device according to the present invention inputs a pattern signal of a known pattern to a device under test, and measures the bit error rate of input data received from the device under test in response to the input of this pattern signal. The device has the function of automatically adjusting the phase of a clock input to a device under test that processes data from a control unit such as an FPGA built into the device.

[0025] Fig. 1 is a block diagram showing the schematic configuration of an error rate measurement apparatus 1 according to this embodiment. The error rate measurement apparatus 1 incorporates a device to be adjusted 2, a clock distributor 3, a 1 / N frequency divider 4, a phase changer 5, and a control unit (FPGA) 6. Note that Fig. 1 shows only the configuration necessary to perform automatic phase adjustment of the device to be adjusted 2, which is the main part of the present invention. The configuration of each unit will be explained below.

[0026] The device to be adjusted 2 is a device that requires clock phase adjustment to synchronize data. In this example, the device to be adjusted 2 is a waveform shaping IC that shapes the waveform of data Tx (Tx1 to Tx5) output from the control unit 6.

[0027] As shown in Figure 1, the waveform shaping IC 2 is a device that processes data input from the control unit 6 and is configured with MUX (multiplexer) 2a, MUX (multiplexer) 2b, and D-FF (D-type flip-flop). MUX 2a uses the clock input via the clock distributor 3 and phase shifter 5 as a timing signal to select and output either data Tx1 or data Tx2 from the control unit 6. MUX 2b uses the clock input via the clock distributor 3 and phase shifter 5 as a timing signal to select and output either data Tx3 or data Tx4 from the control unit 6. D-FF 2c holds the value of its D input (data Tx5 from the control unit 6) as its Q output at the rising edge of the clock input via the clock distributor 3 and phase shifter 5.

[0028] The data output from these MUX2a, MUX2b, and D-FF2c can be used as a test signal for measuring the error rate of a device under test (not shown), for example.

[0029] The clock distributor 3 distributes a clock, which is input as a periodic signal for synchronizing each part, to the 1 / N frequency divider 4 and the phase changer 5, and outputs the divided signal.

[0030] The 1 / N frequency divider 4 divides the frequency of the clock input via the clock distributor 3 by 1 / N and inputs the result to the control unit 6 .

[0031] The phase changers 5 can automatically control the phase amount by a phase amount control unit 6c of the control unit 6, which will be described later, and the number of phase changers 5 corresponds to the components of the adjusted device (waveform shaping IC) 2. The phase changers 5 in Fig. 1 are composed of a phase changer 5A corresponding to MUX 2a, a phase changer 5B corresponding to MUX 2b, and a phase changer 5C corresponding to D-FF 2c.

[0032] The phase amount of each of the phase changers 5A, 5B, and 5C is automatically controlled by a control signal from the control unit 6, and changes the phase of the clock input via the clock distributor 3.

[0033] Here, the phase difference between the data path and the clock path can be up to several nanoseconds, so a maximum phase variation is required (Requirement 1).Furthermore, the phase margin decreases to about several tens of picoseconds at high bit rates or when jitter is applied, so high resolution is required (Requirement 2).

[0034] Therefore, in this embodiment, in order to meet the above-mentioned requirements (requirement 1 and requirement 2), as shown in FIG. 1, each phase changer 5A, 5B, 5C is configured to include a coarse adjustment phase changer 5a and a fine adjustment phase changer 5b.

[0035] In order to meet the above-mentioned requirement 1, the coarse adjustment phase variable device 5a has, for example, a resolution of 12 ps, 8-bit control, and a maximum variable amount of 12 ps × 255 = 3.06 ns, and roughly adjusts the phase relationship between the data and clock using a control signal from the control unit 6.

[0036] The fine-adjustment phase changer 5b is a phase changer with a finer resolution than the coarse-adjustment phase changer 5a. To meet the requirement 2 described above, the fine-adjustment phase changer 5b has, for example, a resolution of 3 ps, 5-bit control, and a maximum variable amount of 3 ps × 31 = 93 ps. After the phase relationship between the data and clock is coarsely adjusted by the coarse-adjustment phase changer 5a, the phase relationship between the data and clock is finely adjusted by a control signal from the control unit 6, and the clock phase is accurately aligned with the center of the phase margin.

[0037] The control unit 6 uses the clock from the 1 / N divider 4 as a timing signal to output data consisting of a binary pattern such as PRBS to the device to be adjusted (waveform shaping IC) 2. In the example of Fig. 1, data Tx1 and Tx2 are output to MUX 2a of the device to be adjusted (waveform shaping IC) 2, data Tx3 and Tx4 are output to MUX 2b, and data Tx5 is output to D-FF 2c.

[0038] The control unit 6 includes an error detection unit 6a, a phase amount calculation unit 6b, and a phase amount control unit 6c as components for controlling the phase amount of the phase changer 5 (coarse adjustment phase changer 5a, fine adjustment phase changer 5b).

[0039] The error detection unit 6a receives as input the data Rx1, Rx2, and Rx3 from the MUX2a, MUX2b, and D-FF2c of the device to be adjusted (waveform shaping IC) 2, and first increases or decreases the phase amount of the coarse adjustment phase variable device 5a to detect two positions (upper limit position and lower limit position) where errors will occur when the clock phase is changed, for each piece of data in MUX2a, MUX2b, and D-FF2c.

[0040] More specifically, the error detection unit 6a receives data Rx1 from MUX 2a, increases or decreases the phase amount of the coarse adjustment phase changer 5a, changes the phase of the clock input to the coarse adjustment phase changer 5a, and detects two positions (upper limit position, lower limit position) where an error occurs in data Rx1. The error detection unit 6a receives data Rx2 from MUX 2b, increases or decreases the phase amount of the coarse adjustment phase changer 5a, changes the phase of the clock input to the coarse adjustment phase changer 5a, and detects two positions (upper limit position, lower limit position) where an error occurs in Rx2. The error detection unit 6a receives data Rx3 from D-FF 2c, increases or decreases the phase amount of the coarse adjustment phase changer 5a, changes the phase of the clock input to the coarse adjustment phase changer 5a, and detects two positions (upper limit position, lower limit position) where an error occurs in Rx3.

[0041] Furthermore, after adjusting the phase amount using the coarse adjustment phase variable device 5a, the error detection unit 6a increases or decreases the phase amount of the fine adjustment phase variable device 5b using the coarse adjustment result as a reference (the value of the phase amount as a result of the coarse adjustment is used as the initial value), and detects the position (upper limit position, lower limit position) where an error occurs when the clock phase is changed for each data of MUX2a, MUX2b, and D-FF2c.

[0042] In this way, for each of MUX2a, MUX2b, and D-FF2c that require clock phase adjustment, the error detection unit 6a detects the positions (upper limit position, lower limit position) where an error will occur when the phase of the clock input to the corresponding phase changer 5 (5A, 5B, 5C) is delayed or advanced.

[0043] The phase amount calculation unit 6b calculates, as a phase amount for coarse adjustment, a phase amount corresponding to the center position between the position (upper limit position) where an error is detected by delaying the phase of the clock input to the coarse adjustment phase variable device 5a and the position (lower limit position) where an error is detected by advancing the phase of the clock input to the coarse adjustment phase variable device 5a. The calculation of this phase amount for coarse adjustment is performed for each of MUX2a, MUX2b, and D-FF 2c of the device to be adjusted (waveform shaping IC) 2.

[0044] After the coarse adjustment, the phase amount calculation unit 6b calculates, as a phase amount for fine adjustment, a phase amount corresponding to whether or not an error is detected by the error detection unit 6a (whether or not there is an error at the upper and lower limit positions of the phase margin) when the phase of the clock input to the fine adjustment phase variable device 5b is delayed and advanced, using the coarse adjustment result as a reference (the value of the phase amount as a result of the coarse adjustment as an initial value). The calculation of this phase amount for fine adjustment is performed for each of MUX2a, MUX2b, and D-FF 2c of the device to be adjusted (waveform shaping IC) 2.

[0045] More specifically, if the error detection unit 6a detects errors at both the upper and lower limit positions after the coarse adjustment, the phase amount corresponding to the center position between the upper and lower limit positions where the errors were detected is calculated as the phase amount for fine adjustment.If the error detection unit 6a does not detect errors at both the upper and lower limit positions after the coarse adjustment, the phase amount during coarse adjustment is calculated as the phase amount for fine adjustment.If the error detection unit 6a detects an error at either the upper or lower limit position after the coarse adjustment, the phase amount for fine adjustment is calculated based on the value of the position where the error was detected (upper or lower limit position) and half the value of the phase margin.

[0046] That is, when the error detection unit 6a detects only the upper limit position of the error after the coarse adjustment, the value obtained by subtracting half the value of the phase margin (a phase offset amount equivalent to half the phase margin in FIG. 8, which will be described later) from the value of the upper limit position where the error was detected is calculated as the phase amount for fine adjustment. On the other hand, when the error detection unit 6a detects only the lower limit position of the error after the coarse adjustment, the value obtained by adding half the value of the phase margin (a phase offset amount equivalent to half the phase margin in FIG. 8, which will be described later) is calculated as the phase amount for fine adjustment.

[0047] The phase amount control unit 6c controls the phase amount of the coarse adjustment phase variable device 5a so that the phase amount becomes the phase amount for coarse adjustment calculated by the phase amount calculation unit 6b. After the coarse adjustment, the phase amount control unit 6c controls the phase amount of the fine adjustment variable device 5b so that the phase amount becomes the phase amount for fine adjustment calculated by the phase amount calculation unit 6b.

[0048] In the error rate measurement apparatus of this example, the device 2 to be adjusted, whose clock phase is adjusted, is a waveform shaping IC including MUXes 2a and 2b and a D-FF 2c, but the invention is not limited to this. Any device that requires clock phase adjustment in the error rate measurement apparatus 1 can be used, and for example, it can be used for automatic phase adjustment of the clock and data input to a DEMUX (demultiplexer).

[0049] Next, we will explain the automatic phase adjustment method of the error rate measurement apparatus 1 configured as described above. Here, we will explain an example in which the phase of the clock of MUX 2a of the device to be adjusted (waveform shaping IC) 2 is adjusted by the coarse adjustment phase changer 5a and fine adjustment phase changer 5b of phase changer 5A, but phase adjustment is performed in a similar manner for MUX 2b by the coarse adjustment phase changer 5a and fine adjustment phase changer 5b of phase changer 5B, and for D-FF 2c by the coarse adjustment phase changer 5a and fine adjustment phase changer 5b of phase changer 5C.

[0050] First, the phase amount control unit 6c of the control unit 6 controls the phase amount so that the phase of the clock input to the coarse adjustment phase changer 5a of the phase changer 5A is delayed by a predetermined number of steps until the error detection unit 6a detects the upper limit position of the phase margin where an error occurs.

[0051] Next, the phase amount control unit 6c of the control unit 6 controls the phase amount of the coarse adjustment phase changer 5a of the phase changer 5A to the state before the phase delay, thereby returning the phase of the clock input to the coarse adjustment phase changer 5a. Thereafter, the phase amount control unit 6c of the control unit 6 controls the phase amount so that the phase of the clock input to the coarse adjustment phase changer 5a advances by a predetermined number of steps until the error detection unit 6a detects the lower limit position of the phase margin where an error occurs.

[0052] Then, the phase amount calculation unit 6b of the control unit 6 calculates a phase amount for coarse adjustment corresponding to the center position between the upper limit position where an error is detected by delaying the phase of the clock and the lower limit position where an error is detected by advancing the phase of the clock.

[0053] The phase amount control unit 6c of the control unit 6 controls the phase amount of the coarse adjustment phase changer 5a of the phase changer 5A so that the phase of the clock is adjusted by the phase amount for coarse adjustment calculated by the phase amount calculation unit 6b, and automatically coarsely adjusts the phase of the clock input to the MUX 2a.

[0054] Thereafter, the phase amount control unit 6c of the control unit 6 controls the phase amount of the fine adjustment phase changer 5b of the phase changer 5A, using the coarse adjustment result by the coarse adjustment phase changer 5a of the phase changer 5A as an initial value. That is, the phase amount control unit 6c of the control unit 6 controls the phase amount so that the phase of the clock input to the fine adjustment phase changer 5b is delayed by a predetermined number of steps, using the coarse adjustment result as an initial value, and then controls the phase amount so that the phase of the clock input to the fine adjustment phase changer 5b is advanced by a predetermined number of steps.

[0055] Then, the phase amount calculation unit 6b of the control unit 6 calculates the phase amount for fine adjustment depending on whether or not an error is detected by the error detection unit 6a when controlling the phase amount of the fine adjustment phase changer 5b of the phase changer 5A (whether or not an error is detected at the upper and lower limit positions of the phase margin).

[0056] The phase amount control unit 6c of the control unit 6 controls the phase amount of the fine adjustment phase changer 5b of the phase changer 5A so that the phase of the clock is adjusted by the fine adjustment phase amount calculated by the phase amount calculation unit 6b, and automatically fine-adjusts the phase of the clock input to the MUX 2a.

[0057] Here, specific examples of phase adjustment by the coarse adjustment phase changer 5a and the fine adjustment phase changer 5b of the phase changer 5 (5A, 5B, 5C) in the above-mentioned automatic phase adjustment method will be explained for each case with reference to Figures 2 to 8. Note that in Figures 2 to 7, as an example of specific numerical settings of the phase changer 5, the setting values ​​of the coarse adjustment phase changer 5a are 0 to 255, and the setting values ​​of the fine adjustment phase changer 5b are 0 to 31.

[0058] (1) Automatic phase adjustment by the coarse adjustment phase variable device 5a in the case of a low bit rate (for example, less than 5 Gbit / s) will be described with reference to FIG.

[0059] When the phase amount of the coarse adjustment phase variable device 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper and lower limit positions of the phase margin, and obtains a value of 98 for the lower limit position of the phase margin and a value of 107 for the upper limit position of the phase margin, as shown in Fig. 2. As a result, the central value of the phase margin obtained by the coarse adjustment phase variable device 5a = (value of the lower limit position of the phase margin + value of the upper limit position of the phase margin) / 2 = (98 + 107) / 2 = 102.5, and the value 102, with the decimal points discarded, is the result of coarse adjustment by the coarse adjustment phase variable device 5a, as shown in Fig. 2.

[0060] 2, the phase margin is wide, so the clock phase can be adjusted to the center of the phase margin with a certain degree of accuracy even with the resolution of the coarse adjustment phase variable device 5a. In other words, the clock phase can be adjusted to the center of the phase margin using only the coarse adjustment phase variable device 5a, without using the fine adjustment phase variable device 5b.

[0061] (2) Automatic phase adjustment by the coarse adjustment phase variable device 5a in the case of a high bit rate (for example, 5 Gbit / s or more) will be described with reference to FIG.

[0062] When the phase amount of the coarse adjustment phase variable device 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper and lower limit positions of the phase margin, and obtains the value of the lower limit position of the phase margin: 101 and the value of the upper limit position of the phase margin: 104, as shown in Fig. 3. As a result, the central value of the phase margin by the coarse adjustment phase variable device 5a = (value of the lower limit position of the phase margin + value of the upper limit position of the phase margin) / 2 = (101 + 104) / 2 = 102.5, and the value 102, with the decimal points discarded, is the result of coarse adjustment by the coarse adjustment phase variable device 5a, as shown in Fig. 3.

[0063] 3, the phase margin is narrow and is only several times (for example, four times) the resolution of the coarse adjustment phase variable device 5a, which causes the problem that the clock phase cannot be accurately aligned to the center of the phase margin. In other words, unlike the low bit rate, the clock phase cannot be aligned to the center of the phase margin using only the coarse adjustment phase variable device 5a.

[0064] Furthermore, today's error rate measuring devices 1 must be able to handle a wide range of bit rates, from low bit rates (e.g., bit rates of less than 5 Gbit / s, such as PCI Express 1.0 (2.5 Gbit / s)) to high bit rates (e.g., bit rates of 5 Gbit / s or more, such as PCI Express 5.0 (32 Gbit / s)), and this cannot be achieved with just one type of coarse adjustment phase variable device 5a.

[0065] Therefore, in the error rate measuring device of this embodiment, in order to solve the above-mentioned problem, after the phase is adjusted by the coarse adjustment phase variable device 5a, the phase is finely adjusted by the fine adjustment phase variable device 5b.

[0066] (3) Automatic phase adjustment when upper and lower limits of error are found in phase adjustment by the fine adjustment phase variable device 5b after phase adjustment by the coarse adjustment phase variable device 5a will be described with reference to FIG.

[0067] When the phase amount of the coarse adjustment phase variable device 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper and lower limit positions of the phase margin, and obtains the value of the lower limit position of the phase margin: 101 and the value of the upper limit position of the phase margin: 104, as shown in Fig. 4. As a result, the central value of the phase margin by the coarse adjustment phase variable device 5a = (value of the lower limit position of the phase margin + value of the upper limit position of the phase margin) / 2 = (101 + 104) / 2 = 102.5, and the value 102, with the decimal points discarded, is the result of coarse adjustment by the coarse adjustment phase variable device 5a, as shown in Fig. 4.

[0068] Then, when the phase of the fine-adjustment phase variable device 5b is controlled by the phase amount control unit 6c of the control unit 6 after the coarse adjustment, the error detection unit 6a detects errors at both the upper and lower limit positions of the phase margin, and obtains a value of 11 for the lower limit position of the phase margin and a value of 26 for the upper limit position of the phase margin, as shown in Fig. 4. As a result, the central value of the phase margin obtained by the fine-adjustment phase variable device 5b = (value of the lower limit position of the phase margin + value of the upper limit position of the phase margin) / 2 = (11 + 26) / 2 = 18.5, and the value 18, with the decimal points discarded, becomes the fine-adjustment result (final adjustment result) obtained by the fine-adjustment phase variable device 5b, as shown in Fig. 4.

[0069] (4) Automatic phase adjustment when the upper and lower limits of the error cannot be found by phase adjustment by the fine adjustment phase variable device 5b after phase adjustment by the coarse adjustment phase variable device 5a will be described with reference to FIG.

[0070] When the phase amount of the coarse adjustment phase variable device 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper and lower limit positions of the phase margin, and obtains a value of 98 for the lower limit position of the phase margin and a value of 107 for the upper limit position of the phase margin, as shown in Fig. 5. As a result, the central value of the phase margin obtained by the coarse adjustment phase variable device 5a = (value of the lower limit position of the phase margin + value of the upper limit position of the phase margin) / 2 = (98 + 107) / 2 = 102.5, and the value 102, with the decimal points discarded, is the result of coarse adjustment by the coarse adjustment phase variable device 5a, as shown in Fig. 5.

[0071] In this case, when the phase amount of the fine adjustment phase variable device 5b is controlled by the phase amount control section 6c of the control section 6 after the coarse adjustment, the error detection section 6a does not detect an error even if the phase is adjusted to the upper or lower limit of the phase margin, so the initial value: 16, which is the result of the coarse adjustment by the coarse adjustment phase variable device 5a, is reset. In this case, the phase margin is wide, so as in the case of (1) above, the clock phase can be aligned to the center of the phase margin with a certain degree of accuracy even with the resolution of the coarse adjustment phase variable device 5a.

[0072] (5) Automatic phase adjustment when only the lower limit of the error is found by phase adjustment using the fine adjustment phase variable device 5b after phase adjustment using the coarse adjustment phase variable device 5a will be described with reference to Figures 6 and 8. The data bit rate is 8 Gbit / s and the jitter is 30 ps.

[0073] When the phase amount of the coarse adjustment phase variable device 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper and lower limit positions of the phase margin, and obtains a value of 98 for the lower limit position of the phase margin and a value of 105 for the upper limit position of the phase margin, as shown in Fig. 6. As a result, the central value of the phase margin obtained by the coarse adjustment phase variable device 5a = (value of the lower limit position of the phase margin + value of the upper limit position of the phase margin) / 2 = (98 + 105) / 2 = 101.5, and the value 101, with the decimal points discarded, is the result of coarse adjustment by the coarse adjustment phase variable device, as shown in Fig. 6.

[0074] Then, after the coarse adjustment, when the phase amount of the fine-adjustment phase variable device 5b is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects an error only in the lower limit position of the phase margin and acquires only the value of the lower limit position of the phase margin: 4. According to the table of FIG. 8, the phase offset amount, which corresponds to half the phase margin corresponding to the data bit rate: 8 Gbit / s, is 16, so the fine-adjustment result by the fine-adjustment phase variable device 5b = value of the lower limit position of the phase margin + half the value of the phase margin = 4 + 16 = 20.

[0075] (6) Automatic phase adjustment when only the upper limit of the error is found by phase adjustment using the fine adjustment phase variable device 5b after phase adjustment using the coarse adjustment phase variable device 5a will be described with reference to Figures 7 and 8. The data bit rate is 8 Gbit / s and the jitter is 30 ps.

[0076] When the phase amount of the coarse adjustment phase variable device 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects an error at the lower limit position of the phase margin and acquires the value of the lower limit position of the phase margin: 98. In contrast, the true error-free upper limit value at the upper limit position of the phase margin is 105, but as shown in Figure 7, due to an error caused by jitter, 106 is acquired as the value of the upper limit position of the phase margin. As a result, as shown in Figure 7, the center value of the phase margin by the coarse adjustment phase variable device 5a = (98 + 106) / 2 = 102 becomes the coarse adjustment result.

[0077] Then, after the coarse adjustment, when the phase amount of the fine-adjustment phase variable device 5b is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects an error only in the upper limit position of the phase margin and acquires only the value of the upper limit position of the phase margin: 28. According to the table of FIG. 8, the phase offset amount, which corresponds to half the phase margin corresponding to the data bit rate of 8 Gbit / s, is 16, so the fine-adjustment result by the fine-adjustment phase variable device 5b = value of the upper limit position of the phase margin - half the value of the phase margin = 28 - 16 = 12.

[0078] The table in Fig. 8 used in (5) and (6) above is an example of a table showing the relationship between the bit rate and the phase offset amount equivalent to half the phase margin. The values ​​in the table in Fig. 8 can be calculated based on the measurement results using an actual device (error rate measurement device 1), or can be calculated in advance based on the bit rate and jitter using the following formula: phase offset amount equivalent to half the phase margin = ((1000 / bit rate [Gbit / s]) - jitter [ps]) / (2 × 3 [ps]). Note that 3 [ps] in the formula is the resolution of the fine-adjustment phase variable device 5b.

[0079] In the above-described embodiment, the error detection unit 6a configured in the control unit 6 is used as part of the configuration for automatically adjusting the phase of the clock input to the device under test 2, but it can also serve as a function for detecting bit errors in input data received from the device under test (not shown) in association with input of a pattern signal of a known pattern to the device under test. Also, a configuration may be provided in which an error detection unit that detects bit errors in input data received from the device under test is provided separately from the error detection unit 6a.

[0080] As described above, according to this embodiment, the error rate measurement device alone can automatically adjust the phase of the clock input to the device to be adjusted (waveform shaping IC) 2, without requiring any other measuring equipment, by using the error detection function of the control unit (FPGA) provided inside the error rate measurement device.

[0081] In this case, automatic phase adjustment of the clock can be performed without using devices such as logic circuits and flip-flop circuits as disclosed in the conventional Patent Document 2.

[0082] To explain further, in this embodiment, the error rate measuring device 1 is equipped with phase changers 5 (5A, 5B, 5C) consisting of a coarse adjustment phase changer 5a with a large amount of change but coarse resolution and a fine adjustment phase changer 5b with a small amount of change but fine resolution, and under the control of the control unit 6, the fine adjustment phase changer 5b is controlled from a state in which coarse adjustment has been previously performed by the coarse adjustment phase changer 5a, thereby completing adjustment in a short time and optimizing the phase.

[0083] In this case, by using a fine-resolution phase adjuster to make adjustments, the clock phase can be aligned with high precision to the center of the phase margin, even when the phase margin has narrowed due to an increase in bit rate. This makes it less likely that bit errors will occur within the error rate measurement device even if the phase relationship between the data and clock drifts due to temperature changes.

[0084] Furthermore, a high-resolution fine-tuning phase comparator can perform phase adjustment even on phase margins that have become extremely small due to the application of jitter, making it possible to apply larger jitter without generating bit errors within the error rate measurement device.

[0085] Furthermore, by controlling the phase variable devices (coarse adjustment phase variable device and fine adjustment phase variable device) with the control unit, adjustment can be performed in a short time, so that the adjustment is performed automatically before starting the error rate measurement, and the phase can be always adjusted when the user starts using it. Moreover, by adjusting it just before the user starts using it, differences due to the user's usage environment can be absorbed, and it can operate with stable performance.

[0086] Although the best mode of the error rate measuring device and the automatic phase adjustment method using the device according to the present invention has been described above, the present invention is not limited to the description and drawings of this mode. In other words, all other modes, embodiments, and operation techniques that are made by those skilled in the art based on this mode are naturally included in the scope of the present invention. [Explanation of symbols]

[0087] 1 Error rate measurement device 2 Adjusted Device 2a,2b MUX 2c D-FF 3 Clock distributor 4 1 / N divider 5 (5A, 5B, 5C) Phase variable 5a Coarse adjustment phase variable 5b Phase variable for fine adjustment 6 Control unit (FPGA) 6a Error detection section 6b Phase amount calculation section 6c Phase amount control section

Claims

1. An error rate measurement device (1) including an adjusted device (2) that processes data from a control unit (6) at the timing of a clock input via a phase variable device (5) capable of controlling the phase amount, in order to automatically perform phase adjustment for each of a plurality of components of the adjusted device (2) inside the error rate measurement device, and outputs a test signal for measuring the error rate to the device under test, a phase changer including a coarse adjustment phase changer (5a) and a fine adjustment phase changer (5b) having a resolution finer than that of the coarse adjustment phase changer, the number of which corresponds to the number of components of the device to be adjusted; The control unit a phase amount control section (6c) that varies the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and then varies the phase of the clock by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted, based on a coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased; an error detection unit (6a) for detecting upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and for detecting a position where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock; a phase amount calculation unit (6b) for varying the phase of the clock by controlling the increase / decrease of the phase amount of the coarse adjustment phase variable device, and calculating, for each component of the device to be adjusted, a phase amount for coarse adjustment corresponding to a center position between an upper limit position and a lower limit position where an error is detected by the error detection unit, and for calculating, for each component of the device to be adjusted, a value obtained by subtracting half the value of the phase margin from the value of the upper limit position where the error is detected when the phase of the clock is varied by controlling the increase / decrease of the phase amount of the fine adjustment phase variable device, if the error detection unit detects only the upper limit position where an error occurs, an error rate measuring device for automatically adjusting the phase of the clock for each component of the device to be adjusted, by controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, and then controlling the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for fine adjustment.

2. An error rate measuring device (1) comprising an adjusted device (2) that processes data from a control unit (6) at the timing of a clock input via a phase variable device (5) whose phase amount is controllable, in order to automatically perform phase adjustment for each of a plurality of components of the adjusted device (2) inside the error rate measuring device, and outputs a test signal for measuring the error rate of the device under test, a phase changer including a coarse adjustment phase changer (5a) and a fine adjustment phase changer (5b) having a resolution finer than that of the coarse adjustment phase changer, the number of which corresponds to the number of components of the device to be adjusted; The control unit a phase amount control section (6c) that varies the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and then varies the phase of the clock by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted, based on a coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased; an error detection unit (6a) for detecting upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and for detecting a position where an error occurs for each component of the device to be adjusted when the phase amount control unit increases or decreases the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock; a phase amount calculation unit (6b) for varying the phase of the clock by controlling the increase / decrease of the phase amount of the coarse adjustment phase variable device, and calculating, for each component of the device to be adjusted, a phase amount for coarse adjustment corresponding to a center position between an upper limit position and a lower limit position where an error is detected by the error detection unit, and for calculating, for each component of the device to be adjusted, a value obtained by adding the value of the lower limit position where the error is detected and half the value of a phase margin when the error detection unit detects only the lower limit position where an error occurs when the phase of the clock is varied by controlling the increase / decrease of the phase amount of the fine adjustment phase variable device, an error rate measuring device for automatically adjusting the phase of the clock for each component of the device to be adjusted, by controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, and then controlling the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for fine adjustment.

3. An automatic phase adjustment method using an error rate measurement device (1) including an adjusted device (2) that processes data from a control unit (6) at the timing of a clock input via a phase variable device (5) capable of controlling the phase amount, and outputs a test signal for measuring the error rate to the device under test, in order to automatically perform phase adjustment for each of a plurality of components of the adjusted device (2) inside the error rate measurement device, providing a number of phase changers corresponding to the number of components of the device to be adjusted, the phase changers including a coarse adjustment phase changer and a fine adjustment phase changer having a finer resolution than the coarse adjustment phase changer; a step of increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and then increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted based on the coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased, to vary the phase of the clock; detecting upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and detecting a position where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted; a step of varying the phase of the clock by controlling the increase / decrease of the phase amount of the coarse adjustment phase variable device, and calculating, for each component of the device to be adjusted, a phase amount for coarse adjustment corresponding to a center position between the upper limit position and the lower limit position where the error is detected; and, when the phase of the clock is varied by controlling the increase / decrease of the phase amount of the fine adjustment phase variable device and only the upper limit position where the error occurs is detected, calculating, for each component of the device to be adjusted, a value obtained by subtracting half the value of the phase margin from the value of the upper limit position where the error is detected; and after controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, controlling the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for fine adjustment, thereby automatically adjusting the phase of the clock for each component of the device to be adjusted.

4. An automatic phase adjustment method using an error rate measuring device (1) equipped with an adjusted device (2) that processes data from a control unit (6) at the timing of a clock input via a phase variable device (5) whose phase amount is controllable, in order to automatically perform phase adjustment for each of a plurality of components of the adjusted device (2) inside the error rate measuring device, and outputs a test signal for measuring the error rate of the device under test, providing a number of phase changers corresponding to the number of components of the device to be adjusted, the phase changers including a coarse adjustment phase changer and a fine adjustment phase changer having a finer resolution than the coarse adjustment phase changer; a step of increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted to vary the phase of the clock, and then increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted based on the coarse adjustment result obtained when the phase amount of the coarse adjustment phase variable device is increased or decreased, to vary the phase of the clock; detecting upper and lower limit positions where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted, and detecting a position where an error occurs for each component of the device to be adjusted when the phase of the clock is varied by increasing or decreasing the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted; a step of varying the phase of the clock by controlling the increase / decrease of the phase amount of the coarse adjustment phase variable device, and calculating, for each component of the device to be adjusted, a phase amount for coarse adjustment that corresponds to a center position between the upper limit position and the lower limit position where the error is detected; and when the phase of the clock is varied by controlling the increase / decrease of the phase amount of the fine adjustment phase variable device and only the lower limit position where the error occurs is detected, calculating, for each component of the device to be adjusted, a value obtained by adding the value of the lower limit position where the error is detected and half the value of the phase margin; and after controlling the phase amount of the coarse adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, controlling the phase amount of the fine adjustment phase variable device for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for fine adjustment, thereby automatically adjusting the phase of the clock for each component of the device to be adjusted.

5. 3. The error rate measuring device according to claim 1, wherein the error detecting section (6a) detects bit errors in input data received from the device under test in response to input of the test signal.

6. 5. The automatic phase adjustment method using an error rate measurement apparatus according to claim 3, further comprising the step of detecting a bit error in input data received from the device under test in response to input of the test signal.

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