Integrated circuits and power modules

Abstract

To provide an integrated circuit capable of reducing the influence of noise and operating at appropriate drive capability.SOLUTION: A power module 1 comprises: a signal output circuit 10 that outputs a first timing for a first switching element 5X and a second timing for a second switching element 5Y; a first holding circuit 30X that outputs a first voltage ToX depending on a temperature of the first switching element; a second holding circuit 30Y that outputs a second voltage ToY depending on a temperature of the second switching element; a first control circuit 40X that controls switching of the first switching element at a first drive capability depending on the temperature of the first switching element on the basis of the first voltage outputted from the first holding circuit, and a first drive signal InX; and a second control circuit 40Y that controls switching of the second switching element at a second drive capability depending on the temperature of the second switching element on the basis of a second voltage outputted from the second holding circuit and a second drive signal for driving the second switching element.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit and a power module. [Background technology]

[0002] There is known an IPM (Intelligent Power Module) for a power conversion device that includes a semiconductor chip on which a switching element such as an IGBT and a diode for temperature detection are formed, and an integrated circuit (IC) that drives the switching element in response to the detection result of the diode (see, for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-110677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-219633 [Patent Document 3] Japanese Patent Application Laid-Open No. 2018-157670 Summary of the Invention [Problem to be solved by the invention]

[0004] In the IPMs described in Patent Documents 1 to 3, the driving capacity of the switching element is adjusted according to the voltage of the diode (in other words, the temperature of the switching element). Furthermore, noise generated when driving the switching element is suppressed from affecting the voltage of the diode on the same chip.

[0005] However, when multiple semiconductor chips like those described above are provided for a load (when multiple combinations of switching elements and diodes exist), noise generated when driving the switching element of one semiconductor chip may affect the voltage of the diode of another semiconductor chip (causing noise to be generated in the voltage).

[0006] The present invention has been made in consideration of the above-mentioned problems in the conventional art, and an object of the present invention is to provide an integrated circuit and a power module that can reduce the effects of noise and operate with appropriate driving capability. [Means for solving the problem]

[0007] The integrated circuit of the present invention, which primarily solves the above-mentioned problems, comprises a signal output circuit that outputs a timing signal indicating a first timing at which a first switching element is switched and a second timing at which a second switching element is switched; a first holding circuit that receives a first voltage corresponding to the temperature of the first switching element and the timing signal, holds the first voltage for a first period after the timing signal is input, and outputs the first voltage that is input when the first period has elapsed; and a second holding circuit that receives a second voltage corresponding to the temperature of the second switching element and the timing signal, and holds the second voltage when the timing signal is input. a first control circuit that controls switching of the first switching element at a first driving capacity corresponding to the temperature of the first switching element, based on the first voltage output from the first holding circuit and a first drive signal for driving the first switching element; and a second control circuit that controls switching of the second switching element at a second driving capacity corresponding to the temperature of the second switching element, based on the second voltage output from the second holding circuit and a second drive signal for driving the second switching element. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide an integrated circuit and a power module that can reduce the influence of noise and operate with an appropriate driving capability. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing the overall configuration of a power module 1. FIG. [Figure 2] FIG. 2 is a block diagram showing an example of a configuration on the lower arm side. [Figure 3] 1 is a circuit diagram showing an example of the configuration of an edge detection circuit 10. FIG. [Figure 4] 3 is a waveform diagram showing an example of the waveform of each signal in the edge detection circuit 10. FIG. [Figure 5] 4 is a circuit diagram showing an example of the configuration of a control circuit 40X. FIG. [Figure 6] 10 is a diagram showing the relationship of operations in the drive capacity adjustment circuit 50X. FIG. [Figure 7] 3 is a waveform diagram showing an example of an operating waveform on the lower arm side of the power module 1. FIG. [Figure 8] FIG. 2 is a block diagram showing an example of the configuration of an upper arm side. [Figure 9] FIG. 10 is a block diagram showing a modified example of the configuration of the upper arm side. DETAILED DESCRIPTION OF THE INVENTION

[0010] At least the following matters will become clear from the description of this specification and the accompanying drawings. =====This embodiment===== <<<Overall configuration of power module 1>>> FIG. 1 is a block diagram showing the overall configuration of a power module 1 according to this embodiment.

[0011] The power module 1 of this embodiment is an IPM (Intelligent Power Module) that drives a three-phase motor 7, which is a load, based on instructions from a microcomputer 2. The power module 1 is configured to include semiconductor chips 4U, 4V, 4W, 4X, 4Y, and 4Z, an LVIC 3, and HVICs 3U, 3V, and 3W.

[0012] Semiconductor chip 4U includes a U-phase switching element 5U and a diode 6U for detecting the temperature of switching element 5U. Similarly, semiconductor chips 4V, 4W, 4X, 4Y, and 4Z include switching elements 5V, 5W, 5X, 5Y, and 5Z for each phase (V-phase, W-phase, X-phase, Y-phase, and W-phase) and diodes 6V, 6W, 6X, 6Y, and 6Z for detecting the temperature, respectively.

[0013] In this embodiment, IGBTs (Insulated Gate Bipolar Transistors) are used as the switching elements 5U, 5V, 5W, 5X, 5Y, and 5Z. However, the elements are not limited to IGBTs and may be, for example, bipolar transistors or MOS transistors.

[0014] Each of the HVICs 3U, 3V, and 3W is an integrated circuit (IC) for switching the switching elements 5U, 5V, and 5W on the upper arm side of the bridge circuit in response to drive signals InU, InV, and InW input from the microcomputer 2.

[0015] The LVIC 3 is an integrated circuit (IC) for switching the switching elements 5X, 5Y, and 5Z on the lower arm side of the bridge circuit in response to drive signals InX, InY, and InZ input from the microcomputer 2.

[0016] <<Example of lower arm configuration>> FIG. 2 is a block diagram showing an example of the configuration of the lower arm side. As shown in FIG. 2, the power module 1 has semiconductor chips 4X, 4Y, and 4Z and an LVIC 3 provided on the lower arm side.

[0017] <Semiconductor chip configuration> As described above, the semiconductor chip 4X includes a switching element 5X and a diode 6X within the same chip.

[0018] The switching element 5X is an element for driving the three-phase motor 7. The switching element 5X is turned on and off in response to a signal OutX applied to the gate from the LVIC 3, and when turned on, a current flows from the collector to the emitter (ground).

[0019] The diode 6X is a temperature-detection diode for detecting the chip temperature (more specifically, the operating temperature of the switching element 5X). In the semiconductor chip 4X, the diode 6X is provided corresponding to the switching element 5X (in a region suitable for temperature detection), with its cathode grounded and its anode connected to the constant current source 20X of the LVIC 3. A constant current is supplied from the constant current source 20X of the LVIC 3 to the diode 6X, generating a voltage (forward voltage) that corresponds to the temperature across the diode 6X. Therefore, the operating temperature of the switching element 5X can be detected based on the temperature dependency of the diode 6X, as shown in FIG. 2 for simplicity. However, this is not limiting; for example, multiple diodes 6X may be connected in series.

[0020] The semiconductor chips 4Y and 4Z have the same configuration as the semiconductor chip 4X, and therefore the description thereof will be omitted.

[0021] Note that any one of the semiconductor chips 4X, 4Y, and 4Z (here, the semiconductor chip 4X) corresponds to the "first semiconductor chip." Furthermore, the switching element 5X provided on the semiconductor chip 4X corresponds to the "first switching element," and the diode 6X corresponds to the "first diode." Furthermore, the output (voltage TiX) of the diode 6X corresponds to the "first voltage."

[0022] Furthermore, any one of the semiconductor chips other than the first semiconductor chip (here, the semiconductor chip 4Y) corresponds to the "second semiconductor chip." Furthermore, the switching element 5Y provided on the semiconductor chip 4Y corresponds to the "second switching element," and the diode 6Y corresponds to the "second diode." Furthermore, the output of the diode 6Y (voltage TiY) corresponds to the "second voltage."

[0023] <Configuration of LVIC3> LVIC3 has a function of adjusting the driving capabilities of the switching elements 5X, 5Y, and 5Z according to the operating temperatures of the switching elements 5X, 5Y, and 5Z (the voltages of the diodes 6X, 6Y, and 6Z). As shown in FIG. 2, LVIC3 includes an edge detection circuit 10, constant current sources 20X, 20Y, and 20Z, sample and hold circuits 30X, 30Y, and 30Z, and control circuits 40X, 40Y, and 40Z. Among the above circuits, the circuits other than the edge detection circuit 10 are provided corresponding to the semiconductor chips 4X, 4Y, and 4Z (X phase, Y phase, Z phase), respectively. Since the configurations of these circuits (circuits other than the edge detection circuit 10) are the same for each phase, hereinafter, mainly the part corresponding to the X phase (semiconductor chip 4X: the first semiconductor chip) will be described, and other descriptions will be omitted.

[0024] The edge detection circuit 10 detects the falling edges and rising edges of the drive signals InX, InY, and InZ input from the microcomputer 2 to LVIC3, and outputs a signal Hold including pulses with a predetermined pulse width according to the detection results. In the present embodiment, the edge detection circuit 10 corresponds to a "signal output circuit", and the signal Hold corresponds to a "timing signal" indicating the timing when the switching elements 5X, 5Y, and 5Z are switched. The details of the edge detection circuit 10 will be described later.

[0025] The constant current source 20X generates a predetermined constant current from the power supply voltage VCC and supplies it to the anode of the diode 6X.

[0026] The sample-and-hold circuit 30X has a function of holding the output (voltage TiX) of the diode 6X for a certain period based on the signal Hold. Specifically, the sample-and-hold circuit 30X receives the output (voltage TiX) of the diode 6X and the signal Hold. The sample-and-hold circuit 30X holds the voltage TiX for a certain period (first period) corresponding to the pulse width of the signal Hold after the pulse (described below) is input, and outputs the input voltage TiX as is after the certain period has elapsed. That is, the output (voltage ToX) of the sample-and-hold circuit 30X is constant during the period during which the pulse of the signal Hold is generated, and is the same as the output (voltage TiX) of the diode 6X during other periods (see FIG. 6). Although not shown in FIG. 2, a resistor 21 and a capacitor 22 constituting a noise-removing filter are provided between the sample-and-hold circuit 30X and the anode of the diode 6X, as shown in FIG. 5.

[0027] The control circuit 40X is a circuit that controls the switching of the switching element 5X with a drive capacity appropriate for the temperature of the switching element 5X, based on the voltage ToX output from the sample and hold circuit 30X and a drive signal InX for driving the switching element 5X. The control circuit 40X of this embodiment includes a drive capacity adjustment circuit 50X and a drive circuit 60X.

[0028] The drive capacity adjustment circuit 50X adjusts the drive capacity of the switching element 5X by the drive circuit 60X (specifically, the magnitude of the drive current supplied from the drive circuit 60X to the switching element 5X) according to the output of the diode 6X (in this embodiment, the output of the sample and hold circuit 30X).

[0029] The drive circuit 60X drives the switching element 5X based on the drive signal InX with a drive capability according to the output of the drive capability adjustment circuit 50X. Note that an example configuration of the control circuit 40X (drive capability adjustment circuit 50X, drive circuit 60X) will be described later.

[0030] In this embodiment, the X-phase control circuit 40X corresponds to the "first control circuit," the sample-and-hold circuit 30X corresponds to the "first holding circuit," and the voltage ToX corresponds to the "first voltage." The drive signal InX corresponds to the "first drive signal." The Y-phase control circuit 40Y corresponds to the "second control circuit," the sample-and-hold circuit 30Y corresponds to the "second holding circuit," and the voltage ToY corresponds to the "second voltage." The drive signal InY corresponds to the "second drive signal."

[0031] In the power module 1 of this embodiment, for example, the diode 6X detects the temperature of the switching element 5X of the semiconductor chip 4X and adjusts the driving capacity of the switching element 5X based on the temperature detection result. In this case, accurate temperature detection of the switching element 5X requires accurate detection of the voltage of the diode 6X. However, noise may be generated by the current flowing when the switching element 5X is switched, and this noise may be carried over to the signal connecting the diode 6X and the LVIC 3 (noise may be generated in the voltage TiX of the diode 6X). This may also cause noise to be generated in the voltages (voltages TiY and TiZ) of the diodes 6Y and 6Z of other chips. Similarly, noise may also be generated in the output of the diode 6X when switching switching elements of other chips (e.g., switching elements 5Y and 5Z) (see FIG. 6). When multiple switching elements are provided for a load, noise may affect not only the diodes of the switching element being driven but also diodes of other chips. Such noise may prevent the switching elements from operating at an appropriate driving capacity.

[0032] Therefore, in this embodiment, by providing an edge detection circuit 10 and sample-and-hold circuits 30X, 30Y, and 30Z, the influence of noise on the same chip and other chips when each switching element is driven is reduced, allowing it to operate with appropriate driving capabilities.

[0033] <<Edge detection circuit 10>> Fig. 3 is a circuit diagram showing an example of the configuration of the edge detection circuit 10. Fig. 4 is a waveform diagram showing an example of the waveforms of the signals in the edge detection circuit 10.

[0034] As shown in FIG. 3, the edge detection circuit 10 includes pulse generation circuits 11X, 11Y, and 11Z, and an OR circuit 12.

[0035] A drive signal InX is input to the pulse generation circuit 11X. The pulse generation circuit 11X outputs a pulse signal O1 containing a pulse of a predetermined pulse width in response to a change (switching of the logical level) of the drive signal InX. For example, at time T1 in FIG. 4, the drive signal InX falls from a high level (hereinafter referred to as H level) to a low level (hereinafter referred to as L level). The pulse generation circuit 11X detects the falling edge of this drive signal InX and outputs a pulse signal O1 containing a pulse with a pulse width from time T2 to time T3. In other words, the pulse generation circuit 11X delays the start timing of the pulse of the pulse signal O1 with respect to the switch timing of the logical level of the drive signal InX. The start timing and pulse width (period) of the pulse of the pulse signal O1 are predetermined in accordance with the noise generation status (see FIG. 6).

[0036] Similarly, the drive signal InY is input to the pulse generation circuit 11Y. The pulse generation circuit 11Y then outputs a pulse signal O2 containing a pulse of a predetermined pulse width in response to a change (switching of the logical level) in the drive signal InY. For example, at time T4 in FIG. 4, the drive signal InY falls from H level to L level. The pulse generation circuit 11Y detects the falling edge of the drive signal InY and outputs a pulse signal O2 containing a pulse with a pulse width from time T5 to time T6. In other words, the pulse generation circuit 11Y delays the start timing of the pulse of the pulse signal O2 with respect to the switching timing of the logical level of the drive signal InY.

[0037] Similarly, the drive signal InZ is input to the pulse generating circuit 11Z. The pulse generating circuit 11Z outputs a pulse signal O3 including a pulse of a predetermined pulse width in response to a change in the drive signal InZ (a change in the logical level). The pulse generating circuit 11Y delays the start timing of the pulse of the pulse signal O3 (time T8 in FIG. 4) relative to the change in the logical level of the drive signal InZ (time T7 in FIG. 4).

[0038] In this embodiment, the pulse generating circuit 11X corresponds to the “first pulse generating circuit,” and the pulse signal O1 corresponds to the “first pulse signal.” Furthermore, the period during which the pulses of the pulse signal O1 are generated (from time T2 to T3) corresponds to the “first period.”

[0039] In this embodiment, the pulse generating circuit 11Y corresponds to a “second pulse generating circuit,” and the pulse signal O2 corresponds to a “second pulse signal.” The period during which the pulses of the pulse signal O2 are generated (from time T5 to T6) corresponds to a “second period.”

[0040] The OR circuit 12 performs a logical OR operation on the pulse signals O1, O2, and O3 and outputs the result as a signal Hold. The OR circuit 12 corresponds to an "output circuit." The signal Hold output from the OR circuit 12 is a signal in which the pulses of the pulse signals O1, O2, and O3 are superimposed, as shown in FIG. 4. In other words, the signal Hold indicates the timing at which the switching elements 5X, 5Y, and 5Z are switched. For example, in the signal Hold shown in FIG. 4, the pulse from time T2 to T3 indicates the timing at which the switching element 5X is switched in response to a change in the drive signal InX at time T1. This timing corresponds to the "first timing." The pulse from time T5 to T6 indicates the timing at which the switching element 5Y is switched in response to a change in the drive signal InY at time T4. This timing corresponds to the "second timing." In this embodiment (FIG. 4), a pulse is generated when the drive signals InX, InY, and InZ change from H level to L level (when each switching element turns on), but a pulse is also generated when they change from L level to H level (when each switching element turns off). Note that a pulse may be generated only when they change from H level to L level (when each switching element turns on).

[0041] In this manner, in this embodiment, the pulse generation circuits 11X, 11Y, and 11Z delay the start timing of the pulses relative to the timing of switching the logic levels of the drive signals InX, InY, and InZ, thereby generating pulses during periods when noise is likely to occur, thereby efficiently reducing the effects of noise.

[0042] Furthermore, the pulse width of the signal Hold (pulse signals O1 to O3) is shorter than the period during which the switching elements 5X, 5Y, and 5Z are turned on, thereby shortening the time (described later) during which the detection results of the diodes 6X, 6Y, and 6Z are not reflected in the adjustment of the driving capabilities.

[0043] Alternatively, the pulse generating circuits 11X, 11Y, and 11Z may not be provided with a delay function, and a delay circuit that delays the signal Hold output from the OR circuit 12 may be provided downstream of the OR circuit 12. In this case as well, the influence of noise can be efficiently reduced.

[0044] <<Control circuit 40X>> 5 is a circuit diagram showing an example of the configuration of the control circuit 40X. As described above, the control circuit 40X is a circuit that controls the switching of the switching element 5X with a driving capacity appropriate for the temperature of the switching element 5X based on the voltage ToX output from the sample and hold circuit 30X and the driving signal InX, and includes a driving capacity adjustment circuit 50X and a driving circuit 60X.

[0045] <Driving capacity adjustment circuit 50X> The drive capacity adjustment circuit 50X is a circuit for adjusting the drive capacity of the switching element 5X in accordance with the detection result of the diode 6X. Specifically, when the voltage of the diode 6X is low (when the temperature is high), the drive circuit 60X is controlled to increase the drive capacity of the switching element 5X, and conversely, when the voltage of the diode 6X is high (when the temperature is low), the drive circuit 60X is controlled to decrease the drive capacity of the switching element 5X. The drive capacity adjustment circuit 50X of this embodiment includes comparators 51 and 52, a selection circuit 54, resistors R1 to R4, and switches SW1 to SW3.

[0046] A voltage ToX output from the sample-and-hold circuit 30X is applied to an inverting input terminal (negative terminal) of the comparator 51, and a reference voltage Vref1 is applied to an inverting input terminal (positive terminal) of the comparator 51. The reference voltage Vref1 is a reference voltage for the forward voltage of the diode 6X at a temperature between high and medium temperatures (for example, 110 degrees). When the voltage at the negative terminal (voltage ToX) is higher than the voltage at the positive terminal (reference voltage Vref1), the comparator 51 outputs an L-level signal, and when the voltage at the negative terminal (voltage ToX) is lower than the voltage at the positive terminal (reference voltage Vref1), the comparator 51 outputs an H-level signal.

[0047] The inverting input terminal (negative terminal) of comparator 52 receives voltage ToX output from sample-and-hold circuit 30X, and the inverting input terminal (positive terminal) of comparator 53 receives reference voltage Vref2. Reference voltage Vref2 is a reference voltage (<reference voltage Vref1) for the forward voltage of diode 6X at a temperature between medium and low temperatures (e.g., 90 degrees). Comparator 52 outputs an L-level signal when the voltage at its negative terminal (voltage ToX) is higher than the voltage at its positive terminal (reference voltage Vref2), and outputs an H-level signal when the voltage at its negative terminal (voltage ToX) is lower than the voltage at its positive terminal (reference voltage Vref2).

[0048] The selection circuit 54 turns on one of the switches SW1 to SW3 in accordance with the output of the comparator 51 and the output of the comparator 52. The selection method of the selection circuit 44 will be described later. This selection adjusts the driving capability of the switching element 5X by the drive circuit 60X.

[0049] The resistors R1 to R4 are connected in series between a power supply voltage VCC2 (for example, 5 V) and the ground.

[0050] One end of switch SW1 is connected to the connection point between resistors R1 and R2. One end of switch SW2 is connected to the connection point between resistors R2 and R3. One end of switch SW3 is connected to the connection point between resistors R3 and R4. The other ends of switches SW1, SW2, and SW3 are connected to the non-inverting input terminal (+ terminal) of an operational amplifier 61 of a drive circuit 60X (described later).

[0051] <Drive circuit 60X> The drive circuit 60X is a circuit that switches (ON / OFF) the switching element 5X based on the drive signal InX. The drive circuit 60X also drives the switching element with a drive capacity according to the output of the drive capacity adjustment circuit 50X.

[0052] The drive circuit 60X includes an operational amplifier 61, NMOS transistors 62 to 64, PMOS transistors 65 and 66, and a resistor 67.

[0053] The output of the drive capacity adjustment circuit 50X is applied to the non-inverting input terminal (+ terminal) of the operational amplifier 61. The inverting input terminal (- terminal) of the operational amplifier 61 is connected to one end of a resistor 67 and the source of an NMOS transistor 62. The operational amplifier 61 controls the NMOS transistor 62 so that the voltage at the - terminal becomes the voltage at the + terminal (the output voltage of the drive capacity adjustment circuit 50X).

[0054] The drain of the NMOS transistor 62 is connected to the drain of the PMOS transistor 65 , and the gate of the NMOS transistor 62 is connected to the drain of the NMOS transistor 64 .

[0055] The drain of the NMOS transistor 63 is connected to the drain of the PMOS transistor 66. A drive signal InX is applied to the gates of the NMOS transistors 63 and 64. The sources of the NMOS transistors 63 and 64 and the other end of the resistor 67 are grounded.

[0056] The PMOS transistor 65 and the PMOS transistor 66 form a current mirror circuit. The drain of the PMOS transistor 66 is connected to the gate of the switching element 5X. Therefore, a current corresponding to the current flowing through the PMOS transistor 65 and the NMOS transistor 62 flows through the PMOS transistor 66.

[0057] Next, the operation of the drive circuit 60X will be described.

[0058] When the drive signal InX applied to the gates of the NMOS transistors 63 and 64 is at H level, the NMOS transistors 63 and 64 turn on. This turns off the NMOS transistor 62, and the PMOS transistors 65 and 66 that make up the current mirror circuit also turn off. Furthermore, when the NMOS transistor 63 turns on, charge is extracted from the gate of the switching element 5X, turning off the switching element 5X.

[0059] On the other hand, when the drive signal InX applied to the gates of the NMOS transistor 63 and the NMOS transistor 64 is at L level, the NMOS transistor 63 and the NMOS transistor 64 are turned off. This turns on the NMOS transistor 62, and the PMOS transistors 65 and 66 that make up the current mirror circuit are also turned on. Furthermore, with the NMOS transistor 63 turned off and the PMOS transistor 66 turned on, charge is supplied to the gate of the switching element 5X, and the switching element 5X is turned on.

[0060] As described above, a current corresponding to the current flowing through the NMOS transistor 62 flows from the PMOS transistor 66 to the switching element 5X. The operational amplifier 61 controls the NMOS transistor 62 so that the voltage at its negative terminal (the source voltage of the NMOS transistor 62) becomes equal to the voltage at its positive terminal (the output voltage of the drive capability adjustment circuit 50X). More specifically, a voltage generated across the resistor 67 according to the value of the current flowing through the NMOS transistor 62 is applied to the negative terminal of the operational amplifier 61. The operational amplifier 61 controls the value of the current flowing through the NMOS transistor 62 so that the difference between the voltages at the positive and negative terminals becomes zero. As a result, a current determined by the voltage at the positive terminal and the resistance value of the resistor R67 flows through the NMOS transistor 62. As the voltage at the positive terminal increases, the current flowing through the NMOS transistor 62 increases in proportion to the voltage at the positive terminal (voltage-current conversion). In other words, the current supplied from the PMOS transistor 66 to the switching element 5X is determined according to the voltage applied to the positive terminal of the operational amplifier 61. In this embodiment, as will be described later, when the temperature rises, the voltage at the positive terminal of the operational amplifier 61 increases, and the current flowing through the NMOS transistor 62 (and the PMOS transistor 66) increases.

[0061] <<Adjusting the driving capacity>> The on-resistance of each switching element (for example, switching element 5X) has temperature characteristics, and the higher the temperature, the greater the on-resistance.

[0062] If the amount of current supplied from the LVIC 3 to the gate of the switching element 5X is constant regardless of temperature, the driving capacity (current supply capacity) for driving the switching element 5X will be insufficient at high temperatures and excessive at low temperatures. In other words, the turn-on time (switching time) will be longer at high temperatures and shorter at low temperatures (the higher the temperature, the longer the turn-on time of the switching element 5X).

[0063] For this reason, the drive capacity adjustment circuit 50X of this embodiment adjusts the drive capacity of the switching element 5X of the drive circuit 60X in accordance with the detection result of the diode 6X.

[0064] Specifically, when the temperature is low, the driving capability (current supply capability) of the switching element 5X is reduced, and when the temperature is high, the driving capability (current supply capability) of the switching element 5X is increased. In this way, the magnitude of the current supplied to the switching element 5X is adjusted according to the temperature. The same applies to the driving capability adjustment circuits 50Y and 50Z.

[0065] In this embodiment, the reference voltage Vref1 is set to correspond to the output voltage (forward voltage) of the diode 6X when the temperature of the switching element 5X is 90 degrees. The reference voltage Vref2 is set to correspond to the voltage (forward voltage) of the diode 6X when the temperature of the switching element 5X is 110 degrees. As described above, the diode 6X has a negative temperature characteristic, and the voltage decreases as the temperature increases and increases as the temperature decreases. In the following description, it is assumed that the voltage ToX of the sample-and-hold circuit 30X applied to the negative terminals of the comparators 51 and 52 is the same as the voltage TiX of the diode 6X.

[0066] FIG. 6 is a diagram showing the operational relationship in the drive capability adjustment circuit 50X. When the operating temperature of the switching element 5X is low (below 90 degrees), as shown in FIG. 6, the voltage ToX (voltage TiX) becomes higher than the reference voltages Vref1 and Vref2. Therefore, the outputs of the comparators 51 and 52 both become L level. In this case (when the outputs of the comparators 51 and 52 are both L level), the selection circuit 54 turns on the switch SW1. As a result, a voltage (low voltage) obtained by dividing the power supply voltage VCC2 by the resistors R1 to R3 and the resistor R4 is applied to the positive terminal of the operational amplifier 61. Therefore, the current flowing through the NMOS transistor 62 becomes smaller, and the current supplied from the PMOS transistor 56 to the switching element 5X also becomes smaller (small driving capability).

[0067] 6, when the operating temperature of the switching element 5X is 90 to 110 degrees, the voltage ToX (voltage TiX) is lower than the reference voltage Vref1 and higher than the reference voltage Vref2. Therefore, the output of the comparator 51 becomes H level, and the output of the comparator 52 becomes L level. In this case (when the output of the comparator 51 is H level and the output of the comparator 52 is L level), the selection circuit 54 turns on the switch SW2. As a result, a voltage (medium voltage) obtained by dividing the power supply voltage VCC2 by the resistors R1, R2 and resistors R3, R4 is applied to the positive terminal of the operational amplifier 61. Therefore, the current flowing through the NMOS transistor 62 becomes medium, and the current supplied from the PMOS transistor 56 to the switching element 5X also becomes medium (medium driving capability).

[0068] 6, when the temperature of the switching element 5X is high (110 degrees or higher), the voltage ToX (voltage TiX) becomes lower than the reference voltages Vref1 and Vref2. Therefore, the outputs of the comparators 51 and 52 both become H level. In this case (when the outputs of the comparators 51 and 52 are both H level), the selection circuit 54 turns on the switch SW3. As a result, a voltage (high voltage) obtained by dividing the power supply voltage VCC2 by the resistor R1 and resistors R2 to R4 is applied to the positive terminal of the operational amplifier 61. Therefore, the current flowing through the NMOS transistor 62 increases, and the current supplied from the PMOS transistor 56 to the switching element 5X also increases (large driving capability).

[0069] In this way, the control circuit 40X of the power module 1 of this embodiment adjusts the drive capacity of the switching element 5X in accordance with the temperature of the switching element 5X. This drive capacity according to the temperature of the switching element 5X corresponds to the "first drive capacity." Similarly, the control circuit 40Y adjusts the drive capacity of the switching element 5Y in accordance with the temperature of the switching element 5Y. This drive capacity according to the temperature of the switching element 5Y corresponds to the "second drive capacity." Furthermore, the control circuit 40Z adjusts the drive capacity of the switching element 5Z in accordance with the temperature of the switching element 5Z.

[0070] The method for adjusting the driving capacity is not limited to the above, and any method may be used.

[0071] <<Power Module 1 Operating Waveforms>> FIG. 7 is a waveform diagram showing an example of an operating waveform on the lower arm side of the power module 1. In FIG.

[0072] FIG. 7 shows an example in which the drive signal InX (drive signal for the switching element 5X) and the drive signal InY (drive signal for the switching element 5Y) change.

[0073] For example, at time T1, the drive signal InX switches (falls) from H level to L level. In response, the signal OutX output from the drive circuit 60X switches from L level to H level, turning on the switching element 5X. When the switching element 5X is driven, noise occurs in the voltage TiX of the diode 6X of the same chip from time T2 to time T3. During this period (from time T2 to time T3), noise also occurs in the voltage TiY of the diode 6Y of a chip other than the same chip (semiconductor chip 4Y in the figure). Although not shown, noise also occurs in the voltage TiZ of the diode 6Z. If noise is present in each of the voltages TiX, TiY, and TiZ, the accuracy of the drive capacity adjustment by the drive capacity adjustment circuits 50X, 50Y, and 50Z may be reduced. For example, noise may cause the outputs of the comparators 51 and 52 to switch, resulting in the selection circuit 54 not selecting (turning on) the appropriate one of the switches SW1 to SW3.

[0074] Therefore, in this embodiment, an edge detection circuit 10 and sample-and-hold circuits 30X-30Z are provided. The sample-and-hold circuit 30X holds the voltage TiX immediately before the pulse of the signal Hold from the edge detection circuit 10 is generated (from time T2 to T3), and outputs the input voltage TiX during the other period (period when no pulse is generated). As a result, the voltage ToX output from the sample-and-hold circuit 30X is not affected by fluctuations in the anode potential of the diode 6X (noise is removed).

[0075] Furthermore, sample and hold circuits 30Y and 30Z also perform similar processing based on signal Hold, so that noise generated in diodes 6Y and 6Z is not reflected in voltages ToY and ToZ. In this way, even if noise is generated in diodes 6X, 6Y, and 6Z when switching element 5X is turned on, the noise is not reflected in the outputs (voltages ToX, ToY, and ToZ) of sample and hold circuits 30X, 30Y, and 30Z.

[0076] Also, at time T4, the drive signal InY switches (falls) from H level to L level. In response to this, the signal OutY output from the drive circuit 60Y changes from L level to H level, turning on the switching element 5Y. At this time, from time T5 to time T6, noise is generated in the voltage TiY of the diode 6Y and the voltage TiX of the diode 6X (and the voltage TiZ of the diode 6Z). In this case, too, the pulse of the signal Hold during the period from time T5 to time T6 performs the same processing as that performed during times T2 to T3, so that noise is not reflected in the outputs (voltages ToX, ToY, ToZ) of the sample-and-hold circuits 30X, 30Y, and 30Z. Note that the same applies when the level of the drive signal InZ changes (when the switching element 5Z is driven), although this is not shown.

[0077] In this way, even if noise occurs in the output of each of the diodes 6X, 6Y, and 6Z due to the driving of any of the switching elements 5X, 5Y, and 5Z, the holding operation of the edge detection circuit 10 and the sample-and-hold circuits 30X, 30Y, and 30Z can completely eliminate the influence of the noise. This reduces the influence of noise and allows operation with appropriate driving capability.

[0078] Furthermore, in this example, a case has been described in which noise is suppressed when the drive signal InX etc. switches from H level to L level (when each switching element turns on), but similar processing is also performed when the drive signal InX etc. switches from L level to H level (when each switching element turns off) to prevent noise from being reflected. Note that noise may be suppressed only when the drive signal InX etc. switches from H level to L level (when each switching element turns on).

[0079] <<<Configuration example for the upper arm>>> In the above embodiment, the configuration of the lower arm side has been described, but the present invention can be similarly applied to the upper arm side. Hereinafter, the description of the lower arm side will be omitted because it has the shape of the above embodiment, and only the necessary parts of the upper arm side will be described.

[0080] FIG. 8 is a block diagram showing an example of the configuration of the upper arm side. 8, on the upper arm side, HVICs 3U, 3V, and 3W and semiconductor chips 4U, 4V, and 4W are provided for three phases (U phase, V phase, and W phase), respectively. Furthermore, level shift circuits 100U, 100V, and 100W are provided in HVICs 3U, 3V, and 3Z, respectively.

[0081] The semiconductor chips 4U, 4V, and 4W each have a switching element 5U, 5V, and 5W and a diode 6U, 6V, and 6W. The configuration of these elements is similar to that of the lower arm (semiconductor chips 4X, 4Y, and 4Z), so a description thereof will be omitted. However, the switching elements 5U, 5V, and 5Z included in the semiconductor chips 4U, 4V, and 4W each have a high power supply voltage (e.g., 600 V) applied to their collectors, and when turned on, supply power to the three-phase motor 7 on the emitter side.

[0082] Note that any one of the semiconductor chips 4U, 4V, and 4W (here referred to as semiconductor chip 4U) corresponds to the "first semiconductor chip," and any other one (here referred to as semiconductor chip 4V) corresponds to the "second semiconductor chip."

[0083] Moreover, the switching element 5U provided on the semiconductor chip 4U corresponds to a “first switching element,” and the diode 6U corresponds to a “first diode.” Moreover, the output (voltage TiX) of the diode 6U corresponds to a “first voltage.”

[0084] Moreover, the switching element 5V corresponds to a “second switching element,” and the diode 6V corresponds to a “first diode.” Moreover, the output of the diode 6V (voltage TiX) corresponds to a “second voltage.”

[0085] The HVIC3U includes a level shift circuit 100U, an edge detection circuit 10U, a constant current source 20U, a sample-and-hold circuit 30U, and a control circuit 40U (a drive capability adjustment circuit 50U, a drive circuit 60U). The HVIC3V and 3W have a similar configuration. The HVIC3U corresponds to the "first integrated circuit," and the HVIC3V corresponds to the "second integrated circuit."

[0086] The level shift circuit 100U converts (shifts) the voltage level of the drive signal InU output from the microcomputer 2 to a voltage level that can drive the switching element 5U, and outputs the drive signal InU1. Similarly, the level shift circuits 100V and 100W convert the levels of the drive signals InV and InW output from the microcomputer 2, and output the drive signals InV1 and InW1, respectively. The level shift circuit 100U corresponds to the "first level shift circuit," the drive signal InU corresponds to the "first drive signal," and the drive signal InU1 corresponds to the "level-shifted first drive signal." The level shift circuit 100V corresponds to the "second level shift circuit," the drive signal InV corresponds to the "second drive signal," and the drive signal InV1 corresponds to the "level-shifted second drive signal."

[0087] The edge detection circuits 10U, 10V, and 10W have the same configuration as the edge detection circuit 10, and detect the edges of each signal from the drive signals InU1, InV1, and InW1 and output a signal Hold. As shown in FIG. 8, the edge detection circuits 10U, 10V, and 10W are provided in the HVICs 3U, 3V, and 3W on the upper arm side, respectively. The edge detection circuit 10U corresponds to the "first signal output circuit," and the edge detection circuit 10V corresponds to the "second signal output circuit." The signal Hold corresponds to the "timing signal."

[0088] The sample and hold circuit 30U and control circuit 40U (drive capacity adjustment circuit 50U, drive circuit 60U) have the same configuration as the lower arm side, so their explanations will be omitted. The configurations of HVIC3V and 3W are also similar to HVIC3U, so their explanations will be omitted. The sample and hold circuit 30U corresponds to the "first holding circuit," and the control circuit 40U corresponds to the "first control circuit." The sample and hold circuit 30V corresponds to the "second holding circuit," and the control circuit 40V corresponds to the "second control circuit."

[0089] With this configuration, the influence of noise can be reduced even on the upper arm side, and the upper arm can be operated with an appropriate driving capability.

[0090] <<Modification of the upper arm side>> Figure 9 is a block diagram showing a modified example of the configuration on the upper arm side. In Figure 9, parts having the same configuration as in Figure 8 are given the same reference numerals, and description thereof will be omitted. The power module 200 shown in Figure 9 includes HVICs 300U, 300V, and 300W. HVICs 300U, 300V, and 300W differ from HVICs 3U, 3V, and 3W in that they do not include level shift circuits 100U, 100V, and 100W, respectively.

[0091] In this modified example, the level shift circuits 100U, 100V, and 100W are provided outside the power module 200. In this manner, the level shift circuits 100U, 100V, and 100W may be provided outside the power module 200 (HVIC 300U, 300V, and 300W).

[0092] =====Summary===== The power module 1 according to one embodiment of the present invention has been described above. The lower-arm LVIC 3 includes an edge detection circuit 10, sample-and-hold circuits 30X, 30Y, and 30Z, and control circuits 40X, 40Y, and 40Z. The edge detection circuit 10 outputs a signal Hold indicating the timing at which the switching elements 5X, 5Y, and 5Z are switched. The sample-and-hold circuit 30X receives the signal Hold and a voltage TiX across the diode 6X that corresponds to the temperature of the switching element 5X. The sample-and-hold circuit 30X holds the voltage TiX for a predetermined period after the pulse of the signal Hold is input, and then outputs the input voltage TiX after the predetermined period has elapsed (the same applies to the sample-and-hold circuits 30Y and 30Z). The control circuit 40X controls the switching of the switching element 5X with a drive capacity that corresponds to the temperature of the switching element 5X, based on the voltage ToX output from the sample-and-hold circuit 30X and a drive signal InX for driving the switching element 5X (the same applies to the control circuits 40Y and 40Z). This makes it possible to reduce the influence of noise in each phase and to operate with an appropriate driving capacity.

[0093] The edge detection circuit 10 also outputs a signal Hold that indicates the timings at which the switching elements 5X, 5Y, and 5Z are turned on and off, thereby suppressing the influence of noise generated in the outputs of the diodes 6X, 6Y, and 6Z when the switching elements 5X, 5Y, and 5Z are turned on and off.

[0094] The edge detection circuit 10 also includes a pulse generation circuit 11X that outputs a pulse signal O1 containing pulses with a fixed pulse width based on the drive signal InX, a pulse generation circuit 11Y that outputs a pulse signal O2 containing pulses with a fixed pulse width based on the drive signal InY, a pulse generation circuit 11Z that outputs a pulse signal O3 containing pulses with a fixed pulse width based on the drive signal InZ, and an OR circuit 12 that outputs a logical OR of the pulse signals O1, O2, and O3 as a signal Hold. This allows the generation of a signal Hold that indicates the timing at which the switching elements 5X, 5Y, and 5Z are switched.

[0095] Furthermore, the pulse generation circuit 11X delays the start timing (time T2) of the pulse of the pulse signal O1 relative to the timing (time T1) at which the logic level of the drive signal InX changes. The pulse generation circuit 11Y delays the start timing (time T5) of the pulse of the pulse signal O2 relative to the timing (time T4) at which the logic level of the drive signal InY changes. The pulse generation circuit 11Z delays the start timing (time T8) of the pulse of the pulse signal O3 relative to the timing (time T7) at which the logic level of the drive signal InZ changes. This allows pulses to be generated during periods when noise is likely to occur, thereby efficiently reducing the effects of noise.

[0096] Alternatively, the pulse generating circuits 11X, 11Y, and 11Z may not be provided with a delay function, and a delay circuit that delays the signal Hold output from the OR circuit 12 may be provided downstream of the OR circuit 12. In this case as well, pulses can be generated during periods when noise is likely to occur, and the effects of noise can be efficiently reduced.

[0097] Furthermore, the pulse width of the signal Hold (pulse signals O1 to O3) is shorter than the period during which each of the switching elements 5X, 5Y, and 5Z is on, thereby reducing the time during which the detection results of the diodes 6X, 6Y, and 6Z are not reflected in the adjustment of the driving capabilities.

[0098] The power module 1 also includes, as its lower arm configuration, a semiconductor chip 4X having a switching element 5X and a diode 6X that outputs a voltage TiX according to the temperature of the switching element 5X, a semiconductor chip 4Y having a switching element 5Y and a diode 6Y that outputs a voltage TiY according to the temperature of the switching element 5Y, a semiconductor chip 4Z having a switching element 5Z and a diode 6Z that outputs a voltage TiZ according to the temperature of the switching element 5Z, and the above-mentioned LVIC 3 that drives the switching elements 5X, 5Y, and 5Z. This reduces the effects of noise in each phase and allows operation with appropriate driving capacity.

[0099] The upper arm of the power module 1 includes a semiconductor chip 4U having a switching element 5U and a diode 6U that outputs a voltage TiU corresponding to the temperature of the switching element 5U, and an HVIC 3U that includes a level shift circuit 100U that shifts the level of a drive signal InU for driving the switching element 5U. Similarly, the V-phase and W-phase power modules 10A, 10B, and 10C include semiconductor chips 4V and 4W, respectively, and an HVIC 3W. The HVICs 3U, 3V, and 3W are each provided with edge detection circuits 10U, 10V, and 10W, sample-and-hold circuits 30U, 30V, and 30W, and control circuits 40U, 40V, and 40W, respectively. This reduces the effects of noise on the upper arm, enabling operation with appropriate drive capability.

[0100] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0101] 1 Power Module 2 Microcomputer 3 LVIC 3U, 3V, 3W HVIC 4X, 4Y, 4Z, 4U, 4V, 4W semiconductor chips 5X, 5Y, 5Z, 5U, 5V, 5W switching elements 6X, 6Y, 6Z, 6U, 6V, 6W diodes 7. Three-phase motor 10, 10U, 10V, 10W edge detection circuit 11X, 11Y, 11Z pulse generation circuit 12 OR Circuit 20X,20Y,20Z,20U,20V,20W constant current source 21 Resistance 22 Capacitor 30X, 30Y, 30Z, 30U, 30V, 30W Sample and hold circuit 40X, 40Y, 40Z, 40U, 40V, 40W control circuit 50X, 50Y, 50Z, 50U, 50V, 50W drive capacity adjustment circuit 51,52 Comparator 54 Selection circuit 60X, 60Y, 60Z, 60U, 60V, 60W drive circuit 61 Operational Amplifier 62, 63, 64 NMOS transistors 65,66 PMOS transistors 67 Resistance 100U, 100V, 100W level shift circuit 200 Power Module 300U, 300V, 300W HVIC R1~R4 resistance SW1~SW3 switches InX, InY, InZ, InU, InV, InW drive signal InU1, InV1, InW1 drive signal O1, O2, O3 pulse signal

Claims

1. a signal output circuit that outputs a timing signal indicating a first timing at which the first switching element is switched and a second timing at which the second switching element is switched; a first holding circuit that receives the timing signal and a first voltage corresponding to the temperature of the first switching element detected by a first diode, holds the first voltage for a first period after the timing signal is input, and outputs the first voltage when the first period has elapsed; a second holding circuit that receives the timing signal and a second voltage corresponding to the temperature of the second switching element detected by a second diode, holds the second voltage for a second period after the timing signal is input, and outputs the second voltage after the second period has elapsed; a first control circuit that controls switching of the first switching element with a first driving capability according to the temperature of the first switching element, based on the first voltage output from the first holding circuit and a first driving signal for driving the first switching element; a second control circuit that controls switching of the second switching element with a second driving capability according to the temperature of the second switching element, based on the second voltage output from the second holding circuit and a second driving signal for driving the second switching element; Equipped with the first holding circuit outputs the held result as the first voltage during the first period; the second holding circuit outputs the held result as the second voltage during the second period; Integrated circuit.

2. 10. The integrated circuit of claim 1, the signal output circuit outputs the timing signal indicating the timings at which the first and second switching elements are turned on and off, respectively. Integrated circuit.

3. 3. An integrated circuit according to claim 1 or 2, The signal output circuit a first pulse generating circuit that generates a first pulse signal including a pulse having a pulse width of the first period based on the first drive signal; a second pulse generating circuit that generates a second pulse signal including a pulse having a pulse width of the second period based on the second drive signal; an output circuit that outputs the first and second pulse signals as the timing signal; An integrated circuit having

4. 4. An integrated circuit according to claim 3, The first pulse generating circuit delaying a start timing of the first period of the first pulse signal with respect to a switching timing of the logic level of the first drive signal; The second pulse generating circuit delaying the start timing of the second period of the second pulse signal with respect to the switching timing of the logic level of the second drive signal; Integrated circuit.

5. 4. An integrated circuit according to claim 3, a delay circuit that delays the timing signal output from the output circuit; Integrated circuit.

6. An integrated circuit according to any one of claims 1 to 5, the first and second periods are shorter than the periods during which the first and second switching elements are turned on, respectively; Integrated circuit.

7. a first semiconductor chip having a first switching element and a first diode that outputs a first voltage according to the temperature of the first switching element; a second semiconductor chip having a second switching element and a second diode that outputs a second voltage according to the temperature of the second switching element; an integrated circuit that drives the first and second switching elements; A power module comprising: The integrated circuit comprises: a signal output circuit that outputs a timing signal indicating a first timing at which the first switching element is switched and a second timing at which the second switching element is switched; a first holding circuit that receives the first voltage and the timing signal, holds the first voltage for a first period from when the timing signal is input, and outputs the first voltage when the first period has elapsed; a second holding circuit that receives the second voltage and the timing signal, holds the second voltage for a second period from when the timing signal is input, and outputs the second voltage when the second period has elapsed; a first control circuit that drives the first switching element with a first driving capability according to the temperature of the first switching element, based on the first voltage output from the first holding circuit and a first driving signal for driving the first switching element; a second control circuit that drives the second switching element with a second driving capability according to the temperature of the second switching element, based on the second voltage output from the second holding circuit and a second driving signal for driving the second switching element; Equipped with the first holding circuit outputs the held result as the first voltage during the first period; the second holding circuit outputs the held result as the second voltage during the second period; Power module.

8. a first semiconductor chip having a first switching element and a first diode that outputs a first voltage according to the temperature of the first switching element; a first integrated circuit for driving the first switching element, the first integrated circuit including a first level shift circuit for shifting a level of a first drive signal for driving the first switching element; a second semiconductor chip having a second switching element and a second diode that outputs a second voltage according to the temperature of the second switching element; a second integrated circuit for driving the second switching element, the second integrated circuit including a second level shift circuit for shifting a level of a second driving signal for driving the second switching element; A power module comprising: The first integrated circuit comprises: a first signal output circuit that outputs a timing signal indicating a first timing at which the first switching element is switched and a second timing at which the second switching element is switched; a first holding circuit that receives the first voltage and the timing signal, holds the first voltage for a first period from when the timing signal is input, and outputs the first voltage when the first period has elapsed; a first control circuit that controls switching of the first switching element with a first driving capability according to the temperature of the first switching element, based on the first voltage output from the first holding circuit and the level-shifted first drive signal; Equipped with The second integrated circuit comprises: a second signal output circuit that outputs the timing signal; a second holding circuit that receives the second voltage and the timing signal, holds the second voltage for a second period from when the timing signal is input, and outputs the second voltage when the second period has elapsed; a second control circuit that controls switching of the second switching element with a second driving capability according to the temperature of the second switching element, based on the second voltage output from the second holding circuit and the level-shifted second driving signal; Equipped with the first holding circuit outputs the held result as the first voltage during the first period; the second holding circuit outputs the held result as the second voltage during the second period; Power module.

9. The integrated circuit of claim 1, the first holding circuit outputs the result of holding in the first holding circuit as the first voltage during the first period, and after the first period has elapsed, outputs the first voltage from the first diode as is; the second holding circuit outputs the result of holding in the second holding circuit as the second voltage during the second period, and after the second period has elapsed, outputs the second voltage from the second diode as is; Integrated circuit.

10. The power module of claim 7, the first holding circuit outputs the result of holding in the first holding circuit as the first voltage during the first period, and after the first period has elapsed, outputs the first voltage from the first diode as is; the second holding circuit outputs the result of holding in the second holding circuit as the second voltage during the second period, and after the second period has elapsed, outputs the second voltage from the second diode as is; Power module.

11. The power module according to claim 8, the first holding circuit outputs the result of holding in the first holding circuit as the first voltage during the first period, and after the first period has elapsed, outputs the first voltage from the first diode as is; the second holding circuit outputs the result of holding in the second holding circuit as the second voltage during the second period, and after the second period has elapsed, outputs the second voltage from the second diode as is; Power module.

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