Printed wiring board and its manufacturing method

Abstract

There is a problem that a signal wave transmitted by a post-type waveguide leaks from between adjacent via conductors.　A printed wiring board 1 is provided with a dielectric layer 10, a plurality of inner conductors 22, and a plurality of via conductors. The dielectric layer 10 has a first surface 10a and a second surface 10b that spread in a planar direction while facing in opposite directions, an internal dielectric 11 that is formed in the shape of a closed region spreading in the planar direction, and an external dielectric 12 that surrounds the internal dielectric 11 on the outside of the internal dielectric 11 in the planar direction. The inner conductors 22 are formed on an outer peripheral surface 11a of the internal dielectric 11, and arranged at intervals in the circumferential direction of the outer peripheral surface 11a on the outer peripheral surface 11a of the internal dielectric 11. The via conductors 28 are arranged at intervals in the circumferential direction between the outer peripheral surface 11a of the internal dielectric 11 and an inner peripheral surface 12a of the external dielectric 12, fill up the space between the inner conductors 22 adjacent to each other within the outer peripheral surface 11a of the internal dielectric 11, and are connected to the inner conductors 22.

Description

[Technical Field]

[0001] The present disclosure relates to printed wiring boards and methods for manufacturing the same. [Background technology]

[0002] Patent Documents 1 and 2 disclose technologies in which a waveguide for transmitting high-frequency signals such as microwaves (including millimeter waves) is built into a multilayer printed wiring board. The waveguides disclosed in Patent Documents 1 and 2 are provided so as to extend in a planar direction perpendicular to the thickness direction of the printed wiring board, and transmit high-frequency signals in the planar direction. Patent Document 2 discloses a post-type waveguide in which a plurality of via conductors for interlayer connection, known as via posts, are arranged at intervals in the planar direction (see paragraphs 0003 to 0006). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-97854 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-16007 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a dielectric separate from the insulating layer is embedded in a waveguide extending in a plane direction perpendicular to the thickness direction, and the insulating layer and the dielectric have different dielectric properties. Furthermore, since the dielectric to be embedded in the waveguide has physical properties that prioritize embeddability, there is a problem that dielectrics with the low dielectric constant and low dielectric loss tangent required for waveguides are not available. Patent Document 2 has a problem in that a signal wave transmitted by a post-type waveguide leaks from between adjacent via conductors. [Means for solving the problem]

[0005] One aspect of the present disclosure is a dielectric layer, a plurality of inner conductors, and a plurality of via conductors; the dielectric layer has a first surface and a second surface facing opposite to each other and extending in a planar direction, an internal dielectric formed in the shape of a closed region extending in the planar direction, and an external dielectric surrounding the internal dielectric on the outside of the internal dielectric in the planar direction, the plurality of inner conductors are formed on an outer periphery of the inner dielectric and are arranged at intervals in a circumferential direction of the outer periphery of the inner dielectric, The via conductors are arranged at intervals in the circumferential direction between the outer periphery of the internal dielectric and the inner periphery of the external dielectric, and are connected to the internal conductors by filling the spaces between adjacent internal conductors on the outer periphery of the internal dielectric. It is a printed wiring board.

[0006] One aspect of the present disclosure is a step of passing slots through a dielectric layer having a first surface and a second surface facing opposite to each other and extending in a planar direction, from the first surface to the second surface around a closed region such that the closed region extending in the planar direction is surrounded by the slots; forming a metal plating layer on the inner surface of the slot; filling a resin inside the metal plating layer in the slot and hardening the resin; drilling holes in the dielectric layer between adjacent slots from the first surface to the second surface; forming a via conductor on the inner surface of the hole and electrically connecting the via conductor to the metal plating layer; The method for manufacturing a printed wiring board includes the steps of: [Effects of the Invention]

[0007] According to the teachings of the present disclosure, a signal wave propagating through the inner dielectric from the first surface to the second surface or vice versa does not leak toward the outer dielectric. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 shows a printed wiring board according to the first embodiment. [Figure 2] FIG. 2 shows the top surface of the printed wiring board. [Figure 3] FIG. 3 shows a cross section taken along line III-III in FIG. [Figure 4] FIG. 4 shows a cross section taken along line IV-IV in FIG. [Figure 5] FIG. 5 shows a cross section taken along line VV in FIG. [Figure 6A] FIG. 6A shows the stack at one stage in the manufacture of a printed wiring board. [Figure 6B] FIG. 6B shows an enlarged cross section of the laminate at a stage in the manufacture of a printed wiring board. [Figure 7A] FIG. 7A shows the stack in a step after that of FIG. 6A. [Figure 7B] FIG. 7B shows an enlarged cross section of the laminate in a step subsequent to the step of FIG. 6B. [Figure 8A] FIG. 8A shows the stack in a step after that of FIG. 7A. [Figure 8B] FIG. 8B shows an enlarged cross section of the laminate in a step subsequent to the step of FIG. 7B. [Figure 9A] FIG. 9A shows the stack in a step after the step of FIG. 8A. [Figure 9B] FIG. 9B shows an enlarged cross section of the laminate in a step subsequent to the step of FIG. 8B. [Figure 10A] FIG. 10A shows the stack in a step after that of FIG. 9A. [Figure 10B] FIG. 10B shows an enlarged cross section of the laminate in a step subsequent to the step of FIG. 9B. [Figure 11A] FIG. 11A shows the stack in a step after that of FIG. 10A. [Figure 11B] FIG. 11B shows an enlarged cross section of the laminate in a step subsequent to the step of FIG. 10B. [Figure 12] FIG. 12 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 13] FIG. 13 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 14] FIG. 14 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 15] FIG. 15 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 16] FIG. 16 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 17] FIG. 17 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 18] FIG. 18 shows an enlarged cross section of a printed wiring board in a modified example. [Figure 19] FIG. 19 shows a printed wiring board according to the second embodiment. [Figure 20] FIG. 20 shows the top surface of the printed wiring board in the second embodiment. [Figure 21] FIG. 21 shows a cross section taken along line XXI-XXI in FIG. [Figure 22] FIG. 22 shows a cross section taken along line XXII-XXII in FIG. [Figure 23] FIG. 23 shows a cross section taken along line XXIII-XXIII in FIG. [Figure 24] FIG. 24 shows a cross section of a laminate at one stage in the manufacture of a printed wiring board. [Figure 25] FIG. 25 shows a cross section of the laminate in a step subsequent to the step of FIG. [Figure 26] FIG. 26 shows a cross section of the laminate in a step subsequent to the step of FIG. [Figure 27] FIG. 27 shows the top surface of the printed wiring board in the third embodiment. [Figure 28] FIG. 28 shows a cross section taken along line XXVIII-XXVIII in FIG. [Figure 29] FIG. 29 shows a cross section taken along line XXIX-XXIX in FIG. [Figure 30A] FIG. 30A shows a cross section of a laminate at one stage in the manufacture of a printed wiring board. [Figure 30B]FIG. 30B shows a cross section of the laminate at one stage in the manufacture of a printed wiring board. [Figure 31A] FIG. 31A shows a cross section of the laminate in a step subsequent to the step of FIG. 30A. [Figure 31B] FIG. 31B shows a cross section of the laminate in a step subsequent to the step of FIG. 30B. [Figure 32A] FIG. 32A shows a cross section of the laminate in a step subsequent to the step of FIG. 31A. [Figure 32B] FIG. 32B shows a cross section of the laminate in a step subsequent to the step of FIG. 31B. [Figure 33A] FIG. 33A shows a cross section of the laminate at a stage subsequent to the stage of FIG. 32A. [Figure 34A] FIG. 34A shows a cross section of the laminate at a step subsequent to that of FIG. 33A. [Figure 35A] FIG. 35A shows a cross section of the laminate at a step subsequent to the step of FIG. 34A. [Figure 36B] FIG. 36B shows a cross section of the laminate at a step subsequent to that of FIG. 35A. [Figure 37A] FIG. 37A shows a cross section of the laminate at a step subsequent to the step of FIG. 36B. [Figure 37B] FIG. 37B shows a cross section of the laminate at a step subsequent to the step of FIG. 36B. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. However, for the sake of convenience, each of the drawings hereinafter shows a simplified view of only the main components necessary for explaining the embodiments. Therefore, the printed wiring boards 1, 100, and 200 of the present disclosure may include optional components not shown in the drawings. Furthermore, the dimensions and dimensional ratios of the components in the drawings do not faithfully represent the dimensions and dimensional ratios of the actual components.

[0010] <<First embodiment>> [1. Printed wiring board] A printed wiring board 1 will be described with reference to FIGS. 1 to 5. FIG. 1 is a perspective view of printed wiring board 1. FIG. 2 is a plan view of printed wiring board 1. FIG. 3 shows a cross section taken along III-III in FIG. 2. FIG. 4 shows a cross section taken along IV-IV in FIG. 2. FIG. 5 shows a cross section taken along VV in FIG. 4. FIG. 1 shows a portion of printed wiring board 1, and printed wiring board 1 extends over a wider area than the illustrated range of FIG. 1. Hereinafter, the so-called double-sided board shown in FIG. 1 may be referred to as a core substrate when it is necessary to distinguish it from the printed wiring board shown in FIG. 19.

[0011] The printed wiring board 1 is a substrate with a waveguide. The printed wiring board 1 has a dielectric layer 10, a perimeter section 20, and conductor layers 30 and 40. The waveguide is formed by the perimeter section 20 and its inner portion. Printed wiring board 1 may be used as a core substrate of build-up type printed wiring board 100. The use of printed wiring board 1 as a core substrate will be described in detail later.

[0012] The dielectric layer 10 is a substrate formed into a flat plate shape. As shown in FIG. 3, the dielectric layer 10 has a first surface 10a and a second surface 10b opposite the first surface 10a. The first surface 10a and the second surface 10b face in opposite directions. The dielectric layer 10 has a thickness from the first surface 10a to the second surface 10b. The thickness of the dielectric layer 10 is, for example, 1.0 mm. Hereinafter, the thickness direction refers to the direction from the first surface 10a to the second surface 10b and the reverse direction. The surface direction refers to the direction along the first surface 10a and the second surface 10b.

[0013] The dielectric layer 10 is formed from a dielectric material. Examples of such dielectric materials include organic resins such as liquid crystal polymers, epoxy resins, bismaleimide-triazine resins, polyimide resins, polyphenylene ether (PPE) resins, polyphenylene oxide (PPO) resins, and cyanate ester resins. Two or more of these organic resins may be mixed together. One or more of these organic resins may contain a reinforcing material. Examples of reinforcing materials include glass fiber, glass nonwoven fabric, aramid fiber, aramid nonwoven fabric, polyester fiber, and polyester nonwoven fabric. One or more of these organic resins may contain an inorganic filler such as barium sulfate, talc, clay, glass, calcium carbonate, and titanium.

[0014] As shown in FIGS. 2 and 3, the dielectric layer 10 has an inner dielectric 11 and an outer dielectric 12 . The internal dielectric 11 extends in the planar direction in the shape of a closed region, specifically, a rectangle. The term "rectangle" here includes a square. The internal dielectric 11 may also extend in a circular, elliptical, or other shape. The external dielectric 12 surrounds the internal dielectric 11 on the outside in the planar direction and is a region that extends in the planar direction. The internal dielectric 11 and the external dielectric 12 were originally formed integrally, but are separated from each other by a frame-like perimeter portion 20 (described below) that surrounds the internal dielectric 11. Since the internal dielectric 11 and the external dielectric 12 are cured and formed simultaneously through the same process, the internal dielectric 11 and the external dielectric 12 have the same dielectric properties. Planar low-dielectric-constant, low-dielectric-loss-tangent materials suitable for the dielectric layer 10 are commercially available, so it is easy to construct an internal dielectric with a low dielectric constant and low-dielectric-loss-tangent that is required for a waveguide.

[0015] 5, the inner dielectric 11 has a plurality of dielectric protrusions 11b on its outer peripheral surface 11a, which are arranged at intervals in the circumferential direction of the outer peripheral surface 11a of the inner dielectric 11. The outer dielectric 12 has a plurality of dielectric protrusions 12b on its inner peripheral surface 12a, which are arranged at intervals in the circumferential direction of the inner peripheral surface 12a of the outer dielectric 12.

[0016] In the internal dielectric 11, a signal wave propagates in the thickness direction, and leakage of the signal wave from the internal dielectric 11 to the external dielectric 12 is suppressed by the perimeter portion 20. The signal wave is a high frequency wave such as a microwave (including a millimeter wave). A microwave is a radio wave with a frequency of 300 MHz to 3 THz and a wavelength of 1 m to 0.1 mm. In particular, a millimeter wave is a radio wave with a frequency of 30 GHz to 300 GHz and a wavelength of 10 mm to 1 mm.

[0017] 2 and 5, the perimeter portion 20 is formed between the outer peripheral surface 11a of the inner dielectric 11 and the inner peripheral surface 12a of the outer dielectric 12. The width W1 of the perimeter portion 20, that is, the width W1 from the outer peripheral surface 11a of the inner dielectric 11 to the inner peripheral surface 12a of the outer dielectric 12, is, for example, 500 μm. In this case, the perimeter portion 20 preferably has a plurality of surrounding conductors 21, a plurality of filling resins 26, and a plurality of via conductors 28.

[0018] 2 and 5, a plurality of surrounding conductors 21 are arranged circumferentially at intervals on the outer peripheral surface 11a of the inner dielectric 11 and the inner peripheral surface 12a of the outer dielectric 12, and surround the inner dielectric 11. In this case, as shown in Fig. 3, the surrounding conductors 21 exist throughout the entire thickness of the dielectric layer 10, from the first surface 10a to the second surface 10b. As shown in Fig. 4, via conductors 28 exist between adjacent surrounding conductors 21, from the first surface 10a to the second surface 10b of the dielectric layer 10, and electrically connect adjacent surrounding conductors 21.

[0019] As shown in FIG. 5, each of the surrounding conductors 21 includes an inner conductor 22 and an outer conductor 24 . The inner conductors 22 are present on the outer peripheral surface 11a of the internal dielectric 11 across the entire thickness of the dielectric layer 10, from the first surface 10a to the second surface 10b. The inner conductors 22 are arranged circumferentially around the outer peripheral surface 11a of the internal dielectric 11 at intervals 22a. Hereinafter, the intervals 22a between adjacent inner conductors 22 are referred to as discontinuities 22a. The positions of the discontinuities 22a are midpoints between adjacent corners on the outer peripheral surface 11a of the internal dielectric 11, but may be shifted from that midpoint. The positions of the discontinuities 22a correspond to the positions of the dielectric protrusions 11b, which are located within the discontinuities 22a. Although adjacent inner conductors 22 are separated by the discontinuities 22a, via conductors 28 electrically connect adjacent inner conductors 22 in the circumferential direction at the discontinuities 22a. The inner conductor 22 has a conductor protrusion 22b that protrudes outward from each edge that forms the discontinuity 22a. The outward direction refers to the direction from the inner conductor 22 toward the outer conductor 24.

[0020] The outer conductor 24 is present on the inner circumferential surface 12a of the external dielectric 12 across the entire thickness of the dielectric layer 10, from the first surface 10a to the second surface 10b. The outer conductor 24 is disposed outwardly away from the inner conductor 22. The outer conductors 24 are arranged circumferentially around the inner circumferential surface 12a of the external dielectric 12 at intervals 24a. Hereinafter, the intervals 24a between adjacent outer conductors 24 are referred to as discontinuities 24a. The positions of the discontinuities 24a are midpoints between adjacent corners on the inner circumferential surface 12a of the external dielectric 12, but may be offset from that midpoint. The positions of the discontinuities 24a correspond to the positions of the dielectric protrusions 12b, and the dielectric protrusions 12b are within the discontinuities 24a. Although adjacent outer conductors 24 are separated by the discontinuities 24a, via conductors 28 electrically connect adjacent outer conductors 24 in the circumferential direction at the discontinuities 24a. The outer conductor 24 has a conductor protrusion 24b that protrudes inward from each edge that forms the discontinuity 24a. The inward direction refers to the direction from the outer conductor 24 toward the inner conductor 22.

[0021] The discontinuities 24a of the outer conductor 24 and the discontinuities 22a of the inner conductor 22 face each other in the inner-outer direction, and the positions of the discontinuities 24a and 22a in the circumferential direction are aligned with each other. The inner-outer direction refers to the direction from the outer conductor 24 toward the inner conductor 22 and the opposite direction.

[0022] As shown in Figures 3 and 5, the filled resin 26 is located between the inner conductor 22 and the outer conductor 24. The filled resins 26 are arranged at intervals in the circumferential direction of the outer peripheral surface 11a of the internal dielectric 11. The spaces between adjacent filled resins 26 form circular holes 25 that penetrate from the first surface 10a to the second surface 10b of the dielectric layer 10. In addition to adjacent filled resins 26, the dielectric protrusions 11b and 12b of the internal dielectric 11 and external dielectric 12 also form holes 25. The holes 25 are also called vias. The shape of the holes 25 is circular, and the term "circular" here means not only a perfect circle but also a shape that approximates a perfect circle. Therefore, the shape of the holes 25 may be a circle that is basically a perfect circle but has projections and recesses. The diameter of the hole 25 is preferably equal to the width W1 from the outer peripheral surface 11a of the inner dielectric 11 to the inner circumference of the outer dielectric 12. Here, "equal" does not only mean "completely equal" but also "almost equal and approximate." The central axis 25c of the hole 25 is preferably located on the intermediate plane 20c of the perimeter portion 20. The intermediate plane 20c of the perimeter portion 20 refers to a plane that passes through the midpoint between the outer peripheral surface 11a of the inner dielectric 11 and the inner peripheral surface 12a of the outer dielectric 12 and is parallel to the direction along these outer peripheral surface 11a and inner peripheral surface 12a. Since the diameter of the hole 25 is equal to the width W1 and the central axis 25c of the hole 25 is located on the midplane of the perimeter portion 20, the via conductor 28 does not protrude beyond the outer peripheral surface 11a of the inner dielectric 11 toward the center of the inner dielectric 11. Furthermore, the via conductor 28 does not protrude beyond the inner peripheral surface 12a of the outer dielectric 12.

[0023] Filled resin 26 is made of a dielectric material. Examples of such dielectric materials include organic resins such as liquid crystal polymers, epoxy resins, bismaleimide-triazine resins, polyimide resins, polyphenylene ether (PPE) resins, polyphenylene oxide (PPO) resins, and cyanate ester resins. Two or more of these organic resins may be mixed together. One or more of these organic resins may be blended with a reinforcing material. Examples of reinforcing materials include inorganic fillers such as barium sulfate, talc, clay, glass, calcium carbonate, and titanium. The material of filled resin 26 and the materials of inner dielectric 11 and outer dielectric 12 may be the same or different.

[0024] The via conductor 28 is located along the inside of the hole 25. More specifically, the via conductor 28 is present on the inner wall surface of the hole 25 across the entire thickness from the first surface 10a to the second surface 10b of the dielectric layer 10. The via conductor 28 is made of a metal plating such as copper plating. Since the hole 25 has a circular shape in a plan view, the via conductor 28 has a cylindrical shape.

[0025] The via conductor 28 is electrically connected to the inner conductor 22 and the outer conductor 24. Specifically, the via conductor 28 is electrically connected to the conductor protrusions 22b of the inner conductor 22 on both ends of the discontinuity 22a, and is also electrically connected to the conductor protrusions 24b of the outer conductor 24 on both ends of the discontinuity 24a.

[0026] The via conductor 28 has four conductive portions 28a to 28d arranged in the circumferential direction of the hole 25. The conductive portion 28a is located along the dielectric protrusion 11b of the inner dielectric 11, filling the discontinuity 22a between adjacent inner conductors 22. The conductive portion 28a electrically connects the inner conductors 22 at both ends of the discontinuity 22a. The conductive portion 28c is located on the opposite side of the central axis of the hole 25 from the conductive portion 28a. The conductive portion 28c is located along the dielectric protrusion 12b of the outer dielectric 12, filling the discontinuity 24a between adjacent outer conductors 24. The conductive portion 28c electrically connects the outer conductors 24 at both ends of the discontinuity 24a. Because the conductive portions 28a and 28c are made of a metal (particularly, copper) having a higher Young's modulus and a lower thermal expansion coefficient than resin, the conductive portions 28a and 28c contribute to improving the strength of the perimeter portion 20 in the circumferential direction of the outer peripheral surface 11a of the internal dielectric 11 or the inner peripheral surface 12a of the external dielectric 12. The conductive portions 28b and 28d are formed on the wall surface of the filled resin 26 within the hole 25 across the width direction from the outer peripheral surface 11a of the internal dielectric 11 to the inner peripheral surface 12a of the external dielectric 12. The conductive portions 28b and 28d are disposed between the conductive portions 28a and 28c. The conductive portions 28b and 28d electrically connect the inner conductor 22 and the outer conductor 24. Because the conductive portions 28b and 28d are made of a metal (particularly, copper) having a higher Young's modulus and a lower thermal expansion coefficient than resin, the conductive portions 28b and 28d contribute to improving the strength of the perimeter portion 20 in the width direction. In this case, it is preferable that the portion of the conductive portion 28a in the via conductor 28 that is closest to the center of the internal dielectric 11 (denoted by reference symbol 28aa in FIG. 5) is close to the plane extending from the inner conductor 22. This reduces the reflection of radio waves in the connection region between the inner conductor 22 and the via conductor 28, thereby improving the characteristics of the waveguide formed in the region inside the inner conductor 22. Here, the plane extending from the inner conductor 22 is the plane corresponding to the plane 11aa obtained by extending the outer peripheral surface 11a of the internal dielectric 11 in the direction along the outer peripheral surface 11a.

[0027] As shown in FIG. 1, the conductor layer 30 is disposed on the first surface 10a of the dielectric layer 10. In this case, as shown in FIG. 3, the conductor layer 30 covers not only the first surface 10a of the dielectric layer 10 but also the filling resin 26. The conductor layer 40 is disposed on the second surface 10b of the dielectric layer 10. The conductor layer 40 covers not only the second surface 10b of the dielectric layer 10 but also the filling resin 26. The conductor layers 30, 40 are made of a conductive metal such as copper. The conductor layers 30, 40 are electrically connected to the inner conductor 22, the outer conductor 24, and the via conductor 28. The conductor layers 30, 40 are ground conductors, and the inner conductor 22, the outer conductor 24, and the via conductor 28 are also ground conductors.

[0028] The conductor layer 30 has an open rectangular port 31 at a position overlapping the internal dielectric 11. The port 31 and the internal dielectric 11 are concentric, and the edge of the port 31 is inside the outer peripheral surface 11a of the internal dielectric 11. The four sides of the port 31 are parallel to the four faces of the outer peripheral surface 11a of the internal dielectric 11. The size of the port 31 may be the same as or different from the size of the port 41 of the conductor layer 40. The conductor layer 30 has an opening 32 at a position corresponding to the hole 25. The opening 32 and the hole 25 are coaxial in the thickness direction.

[0029] The conductor layer 40 has an open rectangular port 41 at a position overlapping the internal dielectric 11. The port 41 and the internal dielectric 11 are concentric, and the edge of the port 41 is inside the outer circumferential surface 11a of the internal dielectric 11. The four sides of the port 41 are parallel to the four faces of the outer circumferential surface 11a of the internal dielectric 11. The size of the port 41 may be the same as or different from the size of the port 31 of the conductor layer 30. The conductor layer 40 has an opening 42 at a position corresponding to the hole 25. The opening 42 and the hole 25 are coaxial in the thickness direction.

[0030] Incidentally, outside the illustrated range of FIG. 1, wiring patterns may be formed on the conductor layers 30 and 40.

[0031] 4 and 5, the inside of the via conductor 28 is hollow. Alternatively, a filling resin may be filled inside the via conductor 28. In this case, the filling resin may be present throughout the entire thickness of the dielectric layer 10, and the conductor layer 30 may cover the filling resin inside the via conductor 28. Similarly, the conductor layer 40 may cover the filling resin inside the via conductor 28.

[0032] 3, the conductor layer 30 covers the filling resin 26. Alternatively, the conductor layer 30 may not cover the filling resin 26, leaving the filling resin 26 exposed. Similarly, the conductor layer 40 may not cover the filling resin 26, leaving the filling resin 26 exposed.

[0033] The perimeter section 20 and the internal dielectric 11 inside it, which are provided as described above, constitute a tubular waveguide that transmits a signal wave, i.e., a waveguide. The signal wave is transmitted from port 31 through the internal dielectric 11 to port 41. The signal wave is, for example, a transverse electric wave (TE wave) or a transverse magnetic wave (TM wave). Since the gaps 22a between adjacent inner conductors 22 are short-circuited by the via conductors 28, the signal wave does not leak from the internal dielectric 11 to the external dielectric 12 through the gaps 22a.

[0034] [2. Printed wiring board manufacturing method] Next, a method for manufacturing printed wiring board 1 according to the first embodiment will be described with reference to Figures 6A to 11A and 6B to 11B. Figures 6A to 11A are perspective views of laminate 1A, which is the base of printed wiring board 1. Figures 6B to 11B are cross-sectional views of laminate 1A. The positions of the cross sections in Figures 6B to 11B are the same as those in Figure 5.

[0035] (1) Preparation First, a laminate 1A is prepared as shown in Figures 6A and 6B. The laminate 1A is formed by laminating a conductor layer 30 and a conductor layer 40 on the first surface 10a and the second surface 10b of a dielectric layer 10, respectively. At this stage, the dielectric layer 10 is not divided into an inner dielectric 11 and an outer dielectric 12. The conductor layer 30 extends over the entire first surface 10a of the dielectric layer 10, and no ports 31 or openings 32 are formed in the conductor layer 30. Similarly, the conductor layer 40 extends over the entire second surface 10b of the dielectric layer 10, and no ports 41 or openings 42 are formed in the conductor layer 40.

[0036] (2) Slot formation Next, as shown in Figures 7A and 7B, multiple slots 20A are formed in the laminate 1A. In this case, the multiple slots 20A are formed in the laminate 1A so as to surround a rectangular closed region 11A. The multiple slots 20A penetrate the laminate 1A from the conductor layer 30 to the conductor layer 40 around the closed region 11A. The width W1 of the slot 20A is the distance from the outer peripheral surface 11a of the inner dielectric 11 to the inner peripheral surface 12a of the outer dielectric 12. The width W1 is, for example, 500 µm. When forming these slots 20A, a predetermined gap is left between adjacent slots 20A in the circumferential direction of the closed region 11A as an unmachined portion. In this case, a portion 28A (hereinafter referred to as a connecting portion 28A) exists between two adjacent slots 20A. The connecting portion 28A connects the closed region 11A to the region 12A outside it. This prevents the closed region 11A from falling off the region 12A outside it. The width W2 of the connecting portion 28A is preferably less than the diameter of the hole 25 to be formed later. The slots 20A preferably have an L-shape that forms a corner of the closed region 11A. The slots 20A can be formed using, for example, etching, laser beam cutting, sandblast cutting, liquid jet cutting, or mechanical cutting. A router, for example, can be used as a tool for mechanical cutting. Resin residue in the slot 20A may be removed by desmearing.

[0037] (3) Plating 8A and 8B, the laminate 1A with the slots 20A formed therein is plated to form a metal plating layer 21A on the inner surface of the slots 20A. This plating process causes the metal plating layer 21A to grow on the conductor layers 30 and 40, thickening the conductor layers 30 and 40. The metal plating layer 21A is the source of the inner conductor 22 and the outer conductor 24.

[0038] (4) Resin filling 9A and 9B, resin is filled inside metal plating layer 21A and cured, thereby forming filled resin 26. Here, the inside of metal plating layer 21A refers to the exposed surface side of the surface (main surface) of metal plating layer 21A formed on the inner surface (wall surface) of slot 20A that faces away from the inner surface of slot 20A.

[0039] (5) Drilling Next, as shown in FIGS. 10A and 10B, holes 25 are drilled in the connecting portions 28A, penetrating from the conductor layer 30 to the conductor layer 40. The diameter of the holes 25 is sufficient if it exceeds the spacing between adjacent slots 20A, i.e., the width W2 of the connecting portions 28A (see FIG. 7B). The diameter of the holes 25 may be equal to the width of the slots 20A, i.e., the width W1 from the outer peripheral surface 11a of the inner dielectric 11 to the inner periphery of the outer dielectric 12 (see FIG. 5). The holes 25 are preferably formed by etching, laser beam drilling, sandblasting, liquid jet drilling, or mechanical drilling. A drill, for example, can be used as a tool for mechanical drilling. By forming the holes 25 in the connecting portions 28A, the dielectric layer 10 is divided into the inner dielectric 11 and the outer dielectric 12. In this case, it is preferable to leave part of the dielectric layer 10 as the dielectric protrusions 11b and 12b in the locations that were the connecting portions 28A. Furthermore, the formation of the holes 25 separates the metal plating layer 21A in the holes 25 into the inner conductor 22 and the outer conductor 24. Furthermore, the formation of the holes 25 removes part of the filled resin 26 from the slots 20A. Resin residue in the holes 25 may be removed by desmearing.

[0040] (6) Plating 11A and 11B, the laminate 1A with the holes 25 formed therein is plated to form via conductors 28 on the inner surfaces of the holes 25. The via conductors 28 are electrically connected to the inner conductors 22 and the outer conductors 24. A plating film formed by such plating is also formed on the conductor layers 30 and 40. As a result, the via conductors 28 are electrically connected to the conductor layers 30 and 40. After the via conductors 28 are formed, the inside of the via conductors 28 may be filled with resin, and the resin may be cured.

[0041] (7) Port formation Next, the conductor layers 30, 40 are covered with a mask, and regions of the conductor layers 30, 40 corresponding to the internal dielectric 11 are removed by etching to form ports 31, 41 in the conductor layers 30, 40, respectively (see FIGS. 1 and 3). When forming the ports 31, 41, wiring patterns may be formed in regions of the conductor layers 30, 40 that are distant from the ports 31, 41. In this case, the regions distant from the ports 31, 41 refer to regions outside the illustrated range in FIG. 1. In this way, the printed wiring board 1 is completed.

[0042] 3. Variations Modifications made to the above-described embodiment will be described below. Modifications made to the above-described embodiment will be described below. Several of the modifications described below may be combined and adopted.

[0043] (1) According to the above description, as shown in Fig. 5, the diameter of hole 25 is equal to width W1 from the outer peripheral surface 11a of inner dielectric 11 to the inner periphery of outer dielectric 12. However, as shown in Figs. 12 and 13, the diameter of hole 25 may be smaller than width W1.

[0044] In the example shown in FIG. 12, the central axis 25c of the hole 25 is located on the intermediate surface 20c of the perimeter portion 20. In the example shown in FIG. 13, the central axis 25 c of the hole 25 is located from the mid-plane 20 c of the perimeter portion 20 toward the inner dielectric 11 . Although not shown, the central axis 25c of the hole 25 may be displaced by a finite distance from the intermediate surface 20c of the perimeter portion 20 toward the external dielectric 12. In any of the cases of FIGS. 12 and 13 and not shown, it is preferable that the via conductor 28 does not protrude beyond the outer peripheral surface 11a of the inner dielectric 11 toward the center of the inner dielectric 11. This is because the waveguide characteristics in the inner region of the perimeter section 20 can be improved if the via conductor 28 does not protrude toward the center of the inner dielectric 11. Specifically, it is possible to reduce the transmission loss of the waveguide. In this case, it is preferable that part of the inner wall of the hole 25 rests on a surface 11aa obtained by extending the outer peripheral surface 11a of the inner dielectric 11 in the direction along the outer peripheral surface 11a. It is also preferable that the via conductor 28, which will be described later, does not protrude beyond the inner peripheral surface 12a of the outer dielectric 12.

[0045] (2) According to the above description, as shown in FIG. 5, it is preferable that the diameter of the hole 25 is equal to the width W1 from the outer peripheral surface 11a of the internal dielectric 11 to the inner periphery of the external dielectric 12. However, as long as the desired characteristics of the waveguide can be achieved, the diameter of the hole 25 and the width W1 from the outer peripheral surface 11a of the internal dielectric 11 to the inner periphery of the external dielectric 12 may not be equal. Alternatively, a portion of the via conductor 28 (the portion 28aa of the conductive portion 28a in FIG. 5 that is closest to the center of the internal dielectric 11) may be offset from the plane 11aa extending in the direction along the outer peripheral surface 11a of the internal dielectric 11. In this case, the inner wall of the hole 25, which corresponds to the diameter of the hole 25, corresponds to the plane with which the via conductor 28 is in contact. Specifically, as shown in FIGS. 14 and 15, the diameter of the hole 25 may be greater than the width W1.

[0046] 14, the central axis 25c of the hole 25 is shifted by a finite distance from the mid-plane 20c of the perimeter portion 20 toward the external dielectric 12. In this case, too, if the desired characteristics as a waveguide can be achieved, the via conductor 28 does not protrude beyond the outer peripheral surface 11a of the internal dielectric 11 toward the center of the internal dielectric 11, but may protrude beyond the inner peripheral surface 12a of the external dielectric 12.

[0047] 15, the central axis 25c of the hole 25 is shifted by a finite distance from the mid-plane 20c of the perimeter portion 20 toward the internal dielectric 11. In this case, too, if the desired characteristics as a waveguide can be achieved, the via conductor 28 does not protrude outward beyond the inner peripheral surface 12a of the external dielectric 12, but may protrude beyond the outer peripheral surface 11a of the internal dielectric 11 toward the center of the internal dielectric 11. In the example shown in FIG. 15, the inner conductor 22 does not have a conductor protrusion 22b, and the internal dielectric 11 does not have a dielectric protrusion 11b.

[0048] Although not shown, the printed wiring board of the embodiment may include a case where the diameter of hole 25 is longer than width W1, as long as central axis 25c of hole 25 is located on midplane 20c of perimeter portion 20. Even in this case, as long as the desired characteristics as a waveguide can be satisfied, inner conductor 22 may not have conductor protrusion 22b, inner dielectric 11 may not have dielectric protrusion 11b, outer conductor 24 may not have conductor protrusion 24b, and outer dielectric 12 may not have dielectric protrusion 12b.

[0049] (3) Furthermore, when the diameter of hole 25 is equal to width W1 from the outer peripheral surface 11a of inner dielectric 11 to inner peripheral surface 12a of outer dielectric 12, the central axis 25c of hole 25 may be shifted by a finite distance from the mid-plane 20c of perimeter portion 20 toward inner dielectric 11, provided that the desired characteristics of the waveguide can be achieved. In this case, inner conductor 22 does not have conductor protrusion 22b, and inner dielectric 11 does not have dielectric protrusion 11b. Furthermore, although not shown in the following example, when the diameter of hole 25 is equal to width W1 from the outer peripheral surface 11a of inner dielectric 11 to inner peripheral surface 12a of outer dielectric 12, the central axis 25c of hole 25 may be shifted by a finite distance from the mid-plane 20c of perimeter portion 20 toward outer dielectric 12, provided that the desired characteristics of the waveguide can be achieved. In this case, the outer conductor 24 does not have a conductor protrusion 24b, and the outer dielectric 12 does not have a dielectric protrusion 12b.

[0050] (4) For example, as shown in FIG. 7A , according to the above description, the slots 20A are L-shaped so as to form corners of the rectangular closed region 11A. Alternatively, the slots 20A may be linear so as to form four sides of the periphery of the closed region 11A. In this case, the connecting portions 28A between adjacent slots 20A connect the corners 11AC of the closed region 11A to the corners 12AC of the outer region 12A. Therefore, as shown in FIGS. 16 to 18 , the holes 25 and the via conductors 28 are arranged in the area of ​​the corners 11AC of the outer peripheral surface 11a of the inner dielectric 11 and the area of ​​the corners 12AC of the inner peripheral surface 12a of the outer dielectric 12. The inner conductors 22 on both sides of the portion corresponding to the corner 11AC of the outer peripheral surface 11a of the internal dielectric 11 are electrically connected by via conductors 28, and the outer conductors 24 on both sides of the portion corresponding to the corner 12AC of the inner peripheral surface 12a of the external dielectric 12 are electrically connected by via conductors 28.

[0051] 16, when forming hole 25 in connecting portion 28A, metal plating layer 21A in slot 20A arranged so as to face hole 25 from two directions is divided into inner conductor 22 and outer conductor 24 by hole 25. In this case, part of filled resin 26 in slot 20A arranged so as to face hole 25 from two directions is removed. As a result, no dielectric protrusion 11b is formed at corner 11AC of outer peripheral surface 11a of inner dielectric 11, and inner conductor 22 does not have conductor protrusion 22b. On the other hand, corner 12AC of inner peripheral surface 12a of outer dielectric 12 is provided with dielectric protrusion 12b.

[0052] 17, when forming the hole 25 in the connecting portion 28A, the metal plating layer 21A in the slot 20A arranged so as to face the hole 25 from two directions is not divided into the inner conductor 22 and the outer conductor 24 by the hole 25, and the metal plating layer 21A is exposed inside the hole 25. Therefore, the conductor protrusion 22b of the inner conductor 22 is integrated with the conductor protrusion 24b of the outer conductor 24. The dielectric protrusion 11b is formed at a corner 11AC of the outer peripheral surface 11a of the inner dielectric 11. The dielectric protrusion 12b is formed at a corner 12AC of the inner peripheral surface 12a of the outer dielectric 12.

[0053] 18, when the hole 25 is formed in the connecting portion 28A, the metal plating layer 21A on one side (the slot 20AR side) of the hole 25 is not divided into the inner conductor 22 and the outer conductor 24 by the hole 25, and the metal plating layer 21A is exposed inside the hole 25. Therefore, the conductor protrusion 22b of the undivided inner conductor 22 is integrated with the conductor protrusion 24b of the undivided outer conductor 24. Furthermore, when the hole 25 is formed in the connecting portion 28A, the metal plating layer 21A on the other side (the slot 20AU side) is divided into the inner conductor 22 and the outer conductor 24 by the hole 25. The divided inner conductor 22 has the conductor protrusion 22b, and the divided outer conductor 24 does not have a conductor protrusion. Dielectric protrusions 11b are formed at the corners of the outer peripheral surface 11a of the internal dielectric 11. The outer dielectric 12 has dielectric protrusions 12b formed at corners of the inner peripheral surface 12a. 17 and 18, care must be taken to ensure that metal plating layer 21A is not divided into inner conductor 22 and outer conductor 24 by hole 25 and that hole 25 is not separated from metal plating layer 21A. If hole 25 is separated from metal plating layer 21A, its function as a ground conductor will be reduced.

[0054] 4. Beneficial Effects (1) Because adjacent inner conductors 22 are short-circuited by via conductors 28, signal waves propagating in the thickness direction do not leak from the inner dielectric 11 through the discontinuities 22a to the filled resin 26 and the outer dielectric 12. This minimizes transmission loss of signal waves.

[0055] (2) As shown in Figs. 16 to 18, via conductors 28 are arranged at corners 11AC of the outer peripheral surface 11a of the internal dielectric 11 and corners 12AC of the inner peripheral surface 12a of the external dielectric 12. Therefore, the four faces of the outer peripheral surface 11a of the internal dielectric 11 are flat. This contributes to suppressing non-uniformity in the characteristic impedance of the internal dielectric 11 and to improving the gain of the internal dielectric 11. Furthermore, as shown in Fig. 16, since the corners 11AC on the outer periphery of the internal dielectric 11 are rounded, noise is less likely to occur in the signal wave.

[0056] (3) Since adjacent outer conductors 24 are short-circuited by the via conductors 28, the outer conductors 24 reinforce the effect of the inner conductors 22 in preventing leakage of signal waves.

[0057] (4) Because the filling resin 26 is filled between the inner conductor 22 and the outer conductor 24, the inner dielectric 11 does not fall off from the outer dielectric 12. Before the filling resin 26 is formed but after the slot 20A is formed, the connecting portion 28A connects the closed region 11A to the outer region 12A, so the closed region 11A does not fall off from the outer region 12A.

[0058] (5) The conductive portions 28b, 28d of the via conductor 28 are formed in the filled resin 26 within the hole 25 across the width direction from the outer peripheral surface 11a of the internal dielectric 11 to the inner peripheral surface 12a of the external dielectric 12. This not only strengthens the electrical connection between the via conductor 28 and the surrounding conductor 21 but also improves the mechanical strength of the surrounding conductor 21 in the width direction from the outer peripheral surface 11a of the internal dielectric 11 to the inner peripheral surface 12a of the external dielectric 12. This contributes to preventing disconnection between the via conductor 28 and the surrounding conductor 21 even when the printed wiring board 1 is deformed by a mechanical load and contributes to improving the reliability of signal wave transmission.

[0059] (6) The inner conductor 22 is formed on the outer peripheral surface 11a of the inner dielectric 11 across the entire thickness from the first surface 10a to the second surface 10b of the dielectric layer 10. The outer conductor 24 is formed on the inner peripheral surface 12a of the outer dielectric 12 across the entire thickness from the first surface 10a to the second surface 10b of the dielectric layer 10. This prevents leakage of signal waves propagating in the thickness direction, minimizing transmission loss of the signal waves.

[0060] (7) The inner conductor 22 has a conductor protrusion 22b at the edge forming the discontinuous portion 22a. Because the conductor protrusion 22b penetrates into the boundary between the dielectric protrusion 11b of the inner dielectric 11 and the filled resin 26, the conductor protrusion 22b contributes to improving the strength of the perimeter portion 20 in the circumferential direction of the outer peripheral surface 11a of the inner dielectric 11 or the inner peripheral surface 12a of the outer dielectric 12, and in the width direction from the outer peripheral surface 11a of the inner dielectric 11 to the inner circumference of the outer dielectric 12. Furthermore, because the conductor protrusion 22b is made of a metal with a higher Young's modulus and a lower thermal expansion coefficient than resin, the conductor protrusion 22b contributes to improving the strength of the perimeter portion 20 in the circumferential direction and width direction described in this paragraph. Similarly, the conductor protrusion 24b of the outer conductor 24 contributes to improving the strength of the perimeter portion 20 in the circumferential direction and width direction described in this paragraph. Furthermore, even if printed wiring board 1 is deformed by a mechanical load, conductor protrusions 22b and 24b contribute to preventing disconnection between via conductor 28 and surrounding conductor 21, and also contribute to suppressing transmission loss of signal waves.

[0061] (8) Since the inner dielectric 11 and the outer dielectric 12 are cured and formed simultaneously through the same process, the dielectric properties of the inner dielectric 11 and the outer dielectric 12 are identical. This reduces the transmission loss of signal waves in the inner dielectric 11.

[0062] (9) As shown in Figures 5, 12, 13, 14, 17, and 18, the via conductors 28 do not protrude further toward the center of the internal dielectric 11 than the outer peripheral surface 11a of the internal dielectric 11. Therefore, the signal wave propagating inside the internal dielectric 11 in the thickness direction is less likely to be diffused by the via conductors 28. This reduces the transmission loss of the signal wave in the internal dielectric 11.

[0063] <<Second embodiment>> [1. Printed wiring board] The printed wiring board 100 will be described with reference to Figures 19 to 23. Figure 19 is a perspective view of the printed wiring board 100. Figure 20 is a plan view of the printed wiring board 100. Figure 21 shows a cross section taken along line XXI-XXI in Figure 20. Figure 22 shows a cross section taken along line XXII-XXII in Figure 20. Figure 23 shows a cross section taken along line XXIII-XXIII in Figure 20. Figure 19 shows a portion of the printed wiring board 100, and the printed wiring board 100 extends over a wider area than the illustrated range in Figure 1.

[0064] The printed wiring board 100 is a multilayer board. The printed wiring board 100 includes a core substrate 101, a first buildup layer 150, and a second buildup layer 160. The second buildup layer 160, the core substrate 101, and the first buildup layer 150 are stacked in this order.

[0065] Core substrate 101 is provided in the same manner as printed wiring board 1 of the first embodiment. The components of core substrate 101 are the same as the corresponding components of printed wiring board 1. Therefore, the components of core substrate 101 are given the same reference numerals as the reference numerals of the corresponding components of printed wiring board 1, and detailed description of the components of core substrate 101 will be omitted.

[0066] The inside of the via conductor 28 is filled with a filling resin 29.

[0067] The first buildup layer 150 includes a dielectric layer 151 , a plurality of via conductors 152 , and a surface conductor layer 153 .

[0068] The dielectric layer 151 is laminated on the first surface 101a of the core substrate 101. The first surface 101a of the core substrate 101 refers to the surface of the conductor layer 30 of the core substrate 101 and the portion of the first surface 10a of the dielectric layer 10 of the core substrate 101 that is not covered by the conductor layer 30. Therefore, the dielectric layer 151 covers the conductor layer 30 and also covers the portion of the first surface 10a of the dielectric layer 10 that is not covered by the conductor layer 30.

[0069] The dielectric layer 151 is formed from a dielectric material. Examples of such dielectric materials include organic resins such as liquid crystal polymers, epoxy resins, bismaleimide-triazine resins, polyimide resins, polyphenylene ether (PPE) resins, polyphenylene oxide (PPO) resins, and cyanate ester resins. Two or more of these organic resins may be mixed together. One or more of these organic resins may contain a reinforcing material. Examples of reinforcing materials include glass fiber, glass nonwoven fabric, aramid fiber, aramid nonwoven fabric, polyester fiber, and polyester nonwoven fabric. One or more of these organic resins may contain an inorganic filler such as barium sulfate, talc, clay, glass, calcium carbonate, and titanium.

[0070] The via conductors 152 penetrate the dielectric layer 151 in the thickness direction. Specifically, the dielectric layer 151 has a plurality of holes 151a that penetrate the dielectric layer 151 in the thickness direction, and the via conductors 152 are filled in the holes 151a. The material of the via conductors 152 is a conductive metal such as copper. The via conductors 152 are coupled to the conductor layer 30 of the core substrate 101 and are electrically connected to the conductor layer 30.

[0071] A plurality of via conductors 152 are arranged at intervals along the outer peripheral surface 11a of the internal dielectric 11. When viewed in the thickness direction, these via conductors 152 overlap the perimeter portion 20. When viewed in the thickness direction, some of these via conductors 152 overlap via conductors 28. In the region of the dielectric layer 151 surrounded by these via conductors 152, a signal wave propagates in the thickness direction. The gap between these via conductors 152 is shorter than one-tenth of the wavelength of the signal wave, making it difficult for the signal wave to leak through the region between the via conductors 152.

[0072] The surface conductor layer 153 is laminated on a surface 151b of the dielectric layer 151, on the side opposite to the core substrate 101 with respect to the dielectric layer 151. The surface conductor layer 153 is electrically connected to the via conductors 152. An opening 153b and a slit 153c are formed in the surface conductor layer 153. When viewed in the thickness direction, the opening 153b is positioned so as to overlap with the ports 31 and 41. The opening 153b is shaped like a rectangle, and the four sides of the opening 153b are parallel to the four sides of the port 31, respectively. The surface conductor layer 153 is grounded.

[0073] The slit 153c extends linearly along the surface direction, and one end of the slit 153c is connected to the opening 153b.

[0074] A signal line 154 is formed on the surface 151b of the dielectric layer 151 inside the slit 153c. The signal line 154 extends linearly along the slit 153c and reaches the inside of the opening 153b. The signal line 154 has a land 154a, the diameter of which is greater than the width of the signal line 154, at an end of the signal line 154 inside the opening 153b. The signal line 154 is electrically insulated from the surface conductor layer 153. Since the surface conductor layers 153 exist on both sides of the signal line 154, the signal line 154 is a coplanar line. Note that the signal line 154 may also be a microstrip line.

[0075] The second buildup layer 160 includes a dielectric layer 161 , a plurality of via conductors 162 , and a surface conductor layer 163 .

[0076] The dielectric layer 161 is laminated on the second surface 101b of the core substrate 101. The second surface 101b of the core substrate 101 refers to the surface of the conductor layer 40 of the core substrate 101 and the portion of the second surface 10b of the dielectric layer 10 of the core substrate 101 that is not covered by the conductor layer 40. Therefore, the dielectric layer 161 not only covers the conductor layer 40, but also covers the portion of the second surface 10b of the dielectric layer 10 that is not covered by the conductor layer 40.

[0077] The dielectric layer 161 is formed of a material having dielectric properties, similar to the dielectric layer 151. The materials listed as examples of the material for the dielectric layer 151 are used as the material for the dielectric layer 161. The material for the dielectric layer 161 may be the same as or different from the material for the dielectric layer 151.

[0078] The dielectric layer 161 has a plurality of holes 161a that penetrate the dielectric layer 161 in the thickness direction. Via conductors 162 are filled in the holes 161a and penetrate the dielectric layer 161 in the thickness direction. The via conductors 162 are coupled to the conductor layer 40 of the core substrate 101 and are electrically connected to the conductor layer 30.

[0079] The via conductors 162 are arranged at intervals along the outer peripheral surface 11a of the internal dielectric 11. When viewed in the thickness direction, these via conductors 162 overlap the perimeter portion 20. When viewed in the thickness direction, some of these via conductors 162 overlap the via conductors 28, respectively.

[0080] The surface conductor layer 163 is laminated on a surface 161b of the dielectric layer 161, on the side opposite the core substrate 101 with respect to the dielectric layer 161. The surface conductor layer 163 is electrically connected to the via conductors 162. Similar to the surface conductor layer 153, the surface conductor layer 163 also has an opening 163b and a slit. A signal line 164 serving as a coplanar line is formed on the surface 161b of the dielectric layer 161 inside the slit of the surface conductor layer 163. The signal line 164 extends linearly along the slit of the surface conductor layer 163 and reaches the inside of the opening 163b. A land 164a is formed at the end of the signal line 164 within the opening 163b, and the land 164a is electromagnetically coupled to the land 154a of the signal line 154 via the dielectric layer 161, the internal dielectric 11, and the dielectric layer 151. The signal line 164 may be a microstrip line.

[0081] When a signal wave is transmitted by signal line 154 along signal line 154 to land 154a, the signal wave is transmitted in the thickness direction from land 154a through dielectric layer 151, inner dielectric 11, and dielectric layer 161 to land 164a of signal line 164. The signal wave is transmitted from land 164a by signal line 164.

[0082] Although not shown, the signal line 154 is connected to one of an RFIC (Radio Frequency Integrated Circuit) and an antenna, and the signal line 164 is connected to the other.

[0083] [2. Printed wiring board manufacturing method] 24 to 26, a method for manufacturing printed wiring board 100 will be described. The cross-sectional positions in FIGS. 24 to 26 are the same as the cross-sectional position in FIG.

[0084] (1) Preparation of the core board Core substrate 101 is prepared. Specifically, core substrate 101 is created in the same manner as in manufacturing printed wiring board 1 of the first embodiment. That is, the steps "(1) Preparation" to "(7) Formation of ports" in manufacturing printed wiring board 1 of the first embodiment are carried out. Note that in the first embodiment, it was optional to fill via conductors 28 with a filling resin and have conductor layer 30 cover the filling resin in via conductors 28, but in the second embodiment, it is essential that via conductors 28 are filled with a filling resin and have conductor layer 30 cover the filling resin in via conductors 28.

[0085] (2) Lamination of dielectric layers and surface conductor layers 24, dielectric layers 151 and 161 are laminated on the first surface 101a and the second surface 101b of the core substrate 101, respectively, and surface conductor layers 153 and 163 are formed on the dielectric layers 151 and 161, respectively, by, for example, electroless plating or vapor deposition. Alternatively, copper foil is laminated on the dielectric layers 151 and 161, respectively. Here, either the step of laminating the dielectric layers 151 and 161 on the first surface 101a and the second surface 101b of the core substrate 101, respectively, or the step of forming the surface conductor layers 153 and 163 on the dielectric layers 151 and 161, respectively, may be performed first, or they may be performed simultaneously.

[0086] (3) Drilling 25, a plurality of holes 151a are opened in the surface conductor layer 153 and the dielectric layer 151 from the surface conductor layer 153 to the first surface 101a of the core substrate 101. When forming these holes 151a, these holes 151a are arranged at intervals along the outer peripheral surface 11a of the inner dielectric 11 and the inner peripheral surface 12a of the outer dielectric 12. The holes 151a are formed using an etching method or a laser beam drilling method. Similarly, a plurality of holes 161 a are opened in the surface conductor layer 163 and the dielectric layer 161 from the surface conductor layer 163 to the second surface 101 b of the core substrate 101 . Smears in the holes 151a and 161a may be removed by desmearing.

[0087] (4) Plating 26, a plating process is performed on a laminate including the surface conductor layer 163, the dielectric layer 161, the core substrate 101, the dielectric layer 151, and the surface conductor layer 153, thereby forming via conductors 152, 162 in the holes 151a, 161a. This plating process also causes the surface conductor layers 153, 163 to grow, thickening the surface conductor layers 153, 163, and electrically connecting the via conductor 152 to the surface conductor layer 153, and the via conductor layer 163 to the surface conductor layer 163. This plating may be performed by filling plating, which fills the holes 151a, 161a with a conductive material.

[0088] (5) Patterning Next, the surface conductor layers 153, 163 are covered with a mask, and then the surface conductor layers 153, 163 are patterned by etching to form slits 153c and openings 153b in the surface conductor layer 153, and form slits 163c and openings 163b in the surface conductor layer 163 (see FIGS. 19 to 23). At this time, the signal lines 154, 164 remain and are formed so as to be separated from the surface conductor layers 153, 164, respectively. The above (4) and (5) are examples of subtractive processes, but MSAP, which uses copper foil as a seed layer, or semi-additive processes, which use electroless copper plating as a seed layer, can also be used. Patterning can be achieved by pattern plating using a mask that is the reverse of the above.

[0089] 3. Beneficial Effects Adjacent inner conductors 22 are short-circuited by via conductors 28, so that signal waves are efficiently propagated without leakage from signal line 154 to signal line 164. In addition, the advantageous effects of the first embodiment are also achieved in the second embodiment.

[0090] <<Third embodiment>> [1. Printed wiring board] The printed wiring board 200 will be described with reference to Figures 27 to 29. Figure 27 is a plan view of the printed wiring board 200. Figure 28 shows a cross section taken along line XXVIII-XXVIII in Figure 27. Figure 29 shows a cross section taken along line XXIX-XXIX in Figure 27. The components of the printed wiring board 200 of the third embodiment are given the same reference numerals as the corresponding components of the printed wiring board 100 of the second embodiment. Printed wiring board 200 of the third embodiment differs from printed wiring board 100 of the second embodiment in the following respects, and is the same as printed wiring board 100 of the second embodiment except for the following points.

[0091] In printed wiring board 100 of the second embodiment, all via conductors 152, 162 are so-called filled via conductors made of plating that fills holes 151a, 161a. In contrast, in the printed wiring board 200 of the third embodiment, the via conductors 152A and 162A of the via conductors 152 and 162 that overlap the via conductor 28 are conformal via conductors formed on the inner surfaces of the holes 151a and 161a. The via conductors 152A and 162A that overlap the via conductor 28 are integral with the via conductor 28, and these via conductors 152A, 28, and 162A are connected in the thickness direction to form a through-hole conductor. The via conductors 152B and 162B of the via conductors 152 and 162 that do not overlap the via conductor 28 are filled via conductors.

[0092] In printed wiring board 200 of the third embodiment, filled resin 229 in through-hole conductors consisting of via conductors 152A, 28, and 162A is covered with surface conductor layers 153 and 163. Note that filled resin 229 does not necessarily have to be formed. In this case, via conductor 152A opens in surface conductor layer 153, and via conductor 162A opens in surface conductor layer 163.

[0093] [2. Printed wiring board manufacturing method] A method for manufacturing printed wiring board 200 will be described with reference to Figures 30A to 35A, 37A, 30B to 32B, 36B, and 37B. The positions of the cross sections in Figures 30A to 35A and 37A are the same as the position of the cross section in Figure 28. The positions of the cross sections in Figures 30B to 32B, 36B, and 37B are the same as the position of the cross section in Figure 29.

[0094] (1) Processes similar to those of the first embodiment As in the manufacturing method of the first embodiment, the same steps as those described in the sections "(1) Preparation," "(2) Slot Formation," "(3) Plating," and "(4) Resin Filling" are performed (see FIGS. 6A to 9A and 6B to 9B).

[0095] (2) Plating 30A and 30B, plating is then performed on the laminate 1A, whereby plating also grows on the conductor layers 30, 40, thickening the conductor layers 30, 40. At this time, plating also grows on the surface of the filling resin 26, so that the filling resin 26 is covered with the conductor layers 30, 40.

[0096] (3) Port formation Next, the conductor layers 30, 40 are covered with a mask, and regions of the conductor layers 30, 40 corresponding to the internal dielectric 11 are removed by etching to form ports 31, 41 in the conductor layers 30, 40, respectively, as shown in Figures 31A and 31B. When forming the ports 31, 41, wiring patterns may be formed in regions of the conductor layers 30, 40 away from the ports 31, 41.

[0097] (4) Lamination of dielectric layers and surface conductor layers 32A and 32B, dielectric layers 151 and 161 are laminated on the conductor layers 30 and 40, respectively, and surface conductor layers 153 and 163 are formed on the dielectric layers 151 and 161, respectively, by, for example, electroless plating or vapor deposition. Alternatively, copper foil is laminated on the dielectric layers 151 and 161, respectively. Here, either the step of laminating the dielectric layers 151 and 161 on the conductor layers 30 and 40, respectively, or the step of laminating the surface conductor layers 153 and 163 on the dielectric layers 151 and 161, respectively, may be performed first, or they may be performed simultaneously.

[0098] (5) Formation of through holes Next, as shown in FIG. 33A , a plurality of through holes 228 are formed from the surface conductor layer 153 to the surface conductor layer 163. When viewed in the thickness direction, the through holes 228 are positioned so as to overlap the connecting portions 28A. Therefore, by forming the through holes 228, the connecting portions 28A are cut by the through holes 228, and the dielectric layer 10 is divided into the inner dielectric 11 and the outer dielectric 12. The portions of the through holes 228 that penetrate the dielectric layer 10 are holes 25, the portions that penetrate the dielectric layer 151 are holes 151a, and the portions that penetrate the dielectric layer 161 are holes 161a. The through holes 228 are formed using an etching method, a laser beam drilling method, a sandblasting drilling method, a liquid jet drilling method, or a mechanical drilling method. A tool used in the mechanical drilling method is, for example, a drill.

[0099] (6) Plating 34A , a plating process is performed on the laminate including the surface conductor layer 163, the dielectric layer 161, the conductor layer 40, the dielectric layer 10, the conductor layer 30, the dielectric layer 151, and the surface conductor layer 153. As a result, the via conductor 152A, the via conductor 28, and the via conductor 162A are integrally formed on the inner surface of the through hole 228. By such plating process, plating also grows on the surface conductor layers 153 and 163, making the surface conductor layers 153 and 163 thicker, and the via conductor 152A is electrically connected to the surface conductor layer 153, and the via conductor 162A is electrically connected to the surface conductor layer 163. Alternatively, this plating step may be omitted, and the via conductors 152A, 28, and 162A may be formed on the inner surface of the through hole 228 in the plating step (9) that is performed later.

[0100] (7) Resin filling 35A, resin is filled into the interior of via conductors 152A, 28, and 162A, and the resin is cured. This forms filled resin 229. This step may be omitted, and filling resin 229 may not be formed. If the plating step (6) is omitted, the formation of filled resin 229 is also omitted.

[0101] (8) Drilling 36B, a plurality of holes 151a are opened in the surface conductor layer 153 and the dielectric layer 151 from the surface conductor layer 153 to the conductor layer 30. When forming these holes 151a, these holes 151a are arranged at intervals along the outer circumferential surface 11a of the inner dielectric 11 and the inner circumferential surface 12a of the outer dielectric 12. The holes 151a are formed using an etching method or a laser beam drilling method. Similarly, a plurality of holes 161 a are opened in the surface conductor layer 163 and the dielectric layer 161 from the surface conductor layer 163 to the conductor layer 40 . The holes 151a and 161a formed in this step are not connected to the holes 25, that is, they are not part of the through-holes 228.

[0102] (9) Plating 37A and 37B, a plating process is performed on a laminate including the surface conductor layer 163, the dielectric layer 161, the conductor layer 40, the dielectric layer 10, the conductor layer 30, the dielectric layer 151, and the surface conductor layer 153. As a result, via conductors 152B, 162B are formed in the holes 151a, 161a that are not connected to the hole 25. By this plating process, a plating film is also formed on the surface conductor layers 153, 163, making the surface conductor layers 153, 163 thicker, and the filling resin 229 is covered by the surface conductor layers 153, 163. Furthermore, the via conductor 152B is electrically connected to the surface conductor layer 153, and the via conductor layer 163B is electrically connected to the surface conductor layer 163. This plating may be performed by filling plating, which fills the holes 151a and 161a with a conductive material.

[0103] (10) Patterning Next, the surface conductor layers 153, 163 are covered with a mask, and then the surface conductor layers 153, 163 are patterned by etching to form slits 153c and openings 153b in the surface conductor layer 153, and form slits 163c and openings 163b in the surface conductor layer 163. At this time, the signal lines 154, 164 remain and are formed so as to be separated from the surface conductor layers 153, 164, respectively. The above (9) and (10) are examples of subtractive methods, but MSAP, which uses copper foil as a seed layer, or semi-additive methods, which use electroless copper plating as a seed layer, can also be used. Patterning can be achieved by pattern plating using a mask that is the reverse of the above.

[0104] <<Additional Notes>> The specific details of the configurations, structures, positional relationships, shapes, etc. shown in the above embodiments can be changed as appropriate without departing from the spirit of the present disclosure. Furthermore, the configurations, structures, positional relationships, and shapes shown in the above embodiments can be combined as appropriate without departing from the spirit of the present disclosure.

[0105] In one embodiment, (1) a printed wiring board comprises a dielectric layer, a plurality of inner conductors, and a plurality of via conductors, the dielectric layer having a first surface and a second surface facing opposite each other and extending in a planar direction, an internal dielectric formed in the shape of a closed area extending in the planar direction, an external dielectric surrounding the internal dielectric outside the internal dielectric in the planar direction, the multiple inner conductors formed on the outer periphery of the internal dielectric and arranged at intervals in the circumferential direction of the outer periphery of the internal dielectric, the via conductors arranged at intervals in the circumferential direction between the outer periphery of the internal dielectric and the inner periphery of the external dielectric, and filling the spaces between adjacent inner conductors on the outer periphery of the internal dielectric and connected to the inner conductors.

[0106] (2) In the printed wiring board of (1) above, the outer periphery of the internal dielectric and the inner periphery of the external dielectric are rectangular, and the via conductors are arranged at the corners of the outer periphery of the internal dielectric and the outer periphery of the external dielectric.

[0107] (3) The printed wiring board of (1) or (2) above further comprises a plurality of outer conductors located on the inner periphery of the external dielectric and arranged at intervals in the circumferential direction on the inner periphery of the external dielectric, and the via conductors are connected to the outer conductors by filling the spaces between adjacent outer conductors on the inner periphery of the external dielectric.

[0108] (4) The printed wiring board of (3) above further comprises a plurality of filled resin portions positioned between the inner conductor and the outer conductor between the outer periphery of the inner dielectric and the inner periphery of the outer dielectric.

[0109] (5) In the printed wiring board of (4) above, the via conductor has a conductive portion that electrically connects the inner conductor and the outer conductor across the width from the outer periphery of the inner dielectric to the inner periphery of the outer dielectric.

[0110] (6) In any of the printed wiring boards (1) to (5) above, the inner conductor is formed on the outer periphery of the internal dielectric over the entire thickness of the dielectric layer from the first surface to the second surface.

[0111] (7) In the printed wiring board according to any one of (1) to (6) above, the inner conductor has a conductor protrusion that protrudes from the inner dielectric toward the outer dielectric and is connected to the via conductor.

[0112] (8) In the printed wiring board of (3) or (4) above, the outer conductor has a conductor protrusion that protrudes from the outer dielectric toward the inner dielectric and is connected to the via conductor.

[0113] (9) Any of the printed wiring boards (1) to (8) above further comprises a first conductor layer laminated on the first surface, grounded, and having a first port at a position overlapping the internal dielectric, and a second conductor layer laminated on the second surface, grounded, and having a second port at a position overlapping the internal dielectric, wherein the via conductor is connected to the first conductor layer and the second conductor layer, and the internal dielectric and the external dielectric have matching dielectric properties.

[0114] (10) In any of the printed wiring boards (1) to (9) above, the via conductor does not protrude beyond the outer periphery of the internal dielectric toward the center of the internal dielectric, and the shape of the closed area is rectangular.

[0115] (11) The printed wiring board of (9) above further comprises a build-up layer laminated on the first conductor layer, the build-up layer having a second dielectric layer laminated on the first conductor layer and a surface conductor layer laminated on the second dielectric layer, and the surface conductor layer has a signal line routed to a position overlapping the first port.

[0116] In one embodiment, (12) a method for manufacturing a printed wiring board includes the steps of: forming a dielectric layer having a first surface and a second surface extending in a planar direction and facing opposite to each other, penetrating the dielectric layer from the first surface to the second surface around a closed area such that the closed area extending in the planar direction is surrounded by a plurality of slots; forming a metal plating layer on the inner surface of the slot; filling resin inside the metal plating layer in the slot and hardening the resin; drilling holes in the dielectric layer between adjacent slots from the first surface to the second surface; and forming via conductors on the inner surface of the holes to electrically connect the via conductors to the metal plating layer. [Explanation of symbols]

[0117] 1,100,200 Printed wiring board 10 Dielectric Layer 10a 1st surface 10b 2nd surface 11 Inner dielectric 11a outer circumference 12 Outer dielectric 12a Inner circumference 21A Metal plating layer 22 Inner conductor 22b Conductor protrusion 24 outer conductor 24b Conductor protrusion 26 Filled Resin 28 Via conductor 28b,28d Conductive part 30 Conductor layer (first conductor layer) 40 Conductor layer (second conductor layer) 150 build-up layer 151 Dielectric layer (second dielectric layer) 153 Surface conductor layer 154 Signal Line

Claims

1. a dielectric layer, a plurality of inner conductors, and a plurality of via conductors; the dielectric layer has a first surface and a second surface facing opposite to each other and extending in a planar direction, an internal dielectric formed in the shape of a closed region extending in the planar direction, and an external dielectric surrounding the internal dielectric on the outside of the internal dielectric in the planar direction, the plurality of inner conductors are formed on an outer periphery of the inner dielectric and are arranged at intervals in a circumferential direction of the outer periphery of the inner dielectric, The via conductors are arranged at intervals in the circumferential direction between the outer periphery of the internal dielectric and the inner periphery of the external dielectric, and are connected to the internal conductors by filling the spaces between adjacent internal conductors on the outer periphery of the internal dielectric. Printed wiring board.

2. the outer periphery of the inner dielectric and the inner periphery of the outer dielectric are rectangular, The via conductors are disposed at corners of the outer periphery of the inner dielectric and the outer periphery of the outer dielectric. The printed wiring board according to claim 1 .

3. a plurality of outer conductors positioned on the inner periphery of the outer dielectric and arranged at intervals in the circumferential direction on the inner periphery of the outer dielectric; The via conductor fills the gap between adjacent ones of the outer conductors on the inner periphery of the outer dielectric and is connected to the outer conductor. The printed wiring board according to claim 1 or 2.

4. a plurality of filled resin portions positioned between the inner conductor and the outer conductor between the outer periphery of the inner dielectric and the inner periphery of the outer dielectric; The printed wiring board according to claim 3 .

5. The via conductor is a conductive portion that electrically connects the inner conductor and the outer conductor across the width direction from the outer periphery of the inner dielectric to the inner periphery of the outer dielectric; have The printed wiring board according to claim 4.

6. The inner conductor is formed on the outer periphery of the inner dielectric over the entire thickness of the dielectric layer from the first surface to the second surface. The printed wiring board according to claim 1 or 2.

7. The inner conductor is a conductor protrusion protruding from the inner dielectric toward the outer dielectric and connected to the via conductor; have The printed wiring board according to claim 1 or 2.

8. The outer conductor is a conductor protrusion protruding from the outer dielectric toward the inner dielectric and connected to the via conductor; have The printed wiring board according to claim 3 .

9. a first conductor layer laminated to the first surface, grounded, and having a first port at a position overlapping the inner dielectric; a second conductor layer laminated to the second surface, grounded, and having a second port at a position overlapping the internal dielectric; the via conductor is connected to the first conductor layer and the second conductor layer; The inner and outer dielectrics have the same dielectric properties. The printed wiring board according to claim 1 or 2.

10. the via conductor does not protrude beyond the outer periphery of the inner dielectric toward the center of the inner dielectric, The shape of the closed region is rectangular. The printed wiring board according to claim 1 or 2.

11. a build-up layer laminated on the first conductor layer; The build-up layer is a second dielectric layer laminated on the first conductor layer; a surface conductor layer laminated on the second dielectric layer, The surface conductor layer is a signal line that is wired to a position where it overlaps with the first port; have The printed wiring board according to claim 9.

12. a step of passing slots through a dielectric layer having a first surface and a second surface facing opposite to each other and extending in a planar direction, the slots extending in the planar direction from the first surface to the second surface around a periphery of the closed region so as to surround the closed region with the slots; forming a metal plating layer on the inner surface of the slot; filling a resin inside the metal plating layer in the slot and hardening the resin; drilling holes in the dielectric layer between adjacent slots from the first surface to the second surface; forming a via conductor on the inner surface of the hole and electrically connecting the via conductor to the metal plating layer; A method for manufacturing a printed wiring board, comprising:

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