Power supply circuits, gate driver circuits, motor driver circuits

Abstract

To provide a power supply circuit capable of coping with a wide range of input voltages.SOLUTION: A linear regulator 110 adjusts an intermediate voltage VREGOUT which occurs at an output node OUT such that an output voltage VOUT generated at an output terminal 104 approaches a first target voltage VOUT(REF1). A Dixon-type charge pump circuit 120 enters a disable state when the output voltage VOUT is higher than a threshold voltage VTH(CP) determined to be lower than the first target voltage VOUT(REF1), outputs a voltage VREGOUT at a first input node IN1 to the output node OUT in the disable state, enters an enable state when the output voltage VOUT is lower than the threshold voltage VTH(CP), and stabilizes the output voltage VOUT at the output terminal 104 to a second target voltage VOUT(REF2) determined to be lower than the first target voltage VOUT(REF1) in the enable state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power supply circuit. [Background technology]

[0002] Power supply circuits are used to supply appropriate power supply voltages to ICs (Integrated Circuits), circuit blocks within ICs, and various load circuits. Known power supply circuits include linear regulators, switching regulators such as buck converters and boost converters, and charge pump circuits, and are selected based on the relationship between input voltage and output voltage.

[0003] Specifically, when the target level of the output voltage is lower than the input voltage of the power supply voltage, a linear regulator or a step-down converter is used, whereas when the target level of the output voltage is higher than the input voltage of the power supply voltage, a charge pump circuit or a step-up converter is used. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-50243 Summary of the Invention [Problem to be solved by the invention]

[0005] Let's consider a power supply circuit (internal power supply circuit) built into some functional IC. The internal power supply circuit generates the power supply voltage for the circuit blocks within the same functional IC. In this case, the target level of the internal power supply circuit's output voltage is determined by the circuit block that serves as the load. Meanwhile, the input voltage of the internal power supply circuit is the power supply voltage supplied to the functional IC. Therefore, the magnitude relationship between the input voltage and output voltage of the internal power supply circuit is determined by the power supply voltage of the application circuit (platform) in which the functional IC is used.

[0006] If there is an internal power supply circuit that can operate in both application circuits where the target level of the output voltage is higher than the input voltage and application circuits where the target level of the output voltage is lower than the input voltage, the same functional IC can be used for multiple application circuits, making it easier to design multiple application circuits.

[0007] The present disclosure has been made in this situation, and one exemplary purpose of an embodiment thereof is to provide a power supply circuit that can accommodate a wide range of input voltages. [Means for solving the problem]

[0008] One aspect of the present disclosure relates to a power supply circuit. The power supply circuit includes: an input terminal receiving an input voltage; an output terminal to be connected to a load; an input node connected to the input terminal; and an output node. The linear regulator adjusts an intermediate voltage generated at the output node so that an output voltage generated at the output terminal approaches a first target voltage. The linear regulator also includes a Dickson-type charge pump circuit having a first input node receiving the intermediate voltage, a second input node receiving the input voltage, and an output node connected to the output terminal. The charge pump circuit is disabled when the output voltage is higher than a threshold voltage that is set lower than the first target voltage, and in the disabled state, outputs the voltage at the first input node to the output node. The charge pump circuit is enabled when the output voltage is lower than the threshold voltage, and in the enabled state, stabilizes the output voltage to a second target voltage that is set lower than the first target voltage.

[0009] Another embodiment of the present disclosure is also a power supply circuit including an input terminal receiving an input voltage, an output terminal, a first transistor having a source connected to the input terminal, an error amplifier that amplifies an error between a feedback voltage corresponding to an output voltage of the output terminal and a reference voltage and has an output connected to the gate of the first transistor, a flying capacitor, a driver circuit that applies a switching voltage to one end of the flying capacitor, the switching voltage having a high voltage corresponding to the input voltage and a ground voltage as a low voltage, a first rectifier element connected between the other end of the flying capacitor and the drain of the first transistor, a second rectifier element connected between the other end of the flying capacitor and the output terminal, and a controller that activates the driver circuit in an enable state and stops the driver circuit in a disable state.

[0010] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Effects of the Invention]

[0011] According to an aspect of the present disclosure, a power supply circuit capable of supporting a wide range of input voltages can be provided. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit diagram of a power supply circuit according to an embodiment. [Figure 2] FIG. 2 is an operational waveform diagram of the power supply circuit of FIG. [Figure 3] FIG. 3 is a circuit diagram of a power supply circuit according to a comparative technique. [Figure 4] FIG. 4 is a circuit diagram of the power supply circuit according to the first embodiment. [Figure 5] FIG. 5 is an operational waveform diagram of the power supply circuit of FIG. [Figure 6]FIG. 6 is a circuit diagram of a power supply circuit according to the second embodiment. [Figure 7] FIG. 7 is a circuit diagram of a power supply circuit according to a third embodiment. [Figure 8] FIG. 8 is a circuit diagram of a power supply circuit according to a fourth embodiment. [Figure 9] FIG. 9 is a block diagram of the switching circuit. [Figure 10] FIG. 10 is a block diagram of the motor driver. DETAILED DESCRIPTION OF THE INVENTION

[0013] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0014] A power supply circuit according to one embodiment includes: an input terminal for receiving an input voltage, an output terminal to be connected to a load, an input node connected to the input terminal, and an output node; a linear regulator for adjusting an intermediate voltage generated at the output node so that an output voltage generated at the output terminal approaches a first target voltage; and a Dickson charge pump circuit having a first input node for receiving the intermediate voltage, a second input node for receiving the input voltage, and an output node connected to the output terminal. The charge pump circuit is disabled when the output voltage is higher than a threshold voltage set lower than the first target voltage, and in the disabled state outputs the voltage at the first input node to the output node. When the output voltage is lower than the threshold voltage, the charge pump circuit is enabled, and in the enabled state stabilizes the output voltage to a second target voltage set lower than the first target voltage.

[0015] With this configuration, when the input voltage is sufficiently high, the charge pump circuit is disabled and the output voltage is stabilized at a first target voltage. When the input voltage drops and the linear regulator circuit can no longer maintain the output voltage at the first target voltage, causing the output voltage to fall below the threshold voltage, the charge pump circuit is enabled and the output voltage can be stabilized at a second target voltage set slightly lower than the first target voltage. Note that even when the input voltage drops, the linear regulator remains in operation and is in a full-on state, supplying an intermediate voltage close to the input voltage to the charge pump circuit. Because the linear regulator operates constantly, discontinuous changes in the output voltage due to switching between its modes can be prevented.

[0016] In one embodiment, the charge pump circuit may further include a first comparator having hysteresis that compares a monitored voltage corresponding to the output voltage with an upper threshold and a lower threshold corresponding to a second target voltage. In an enabled state, the charge pump circuit may alternate between an active period and a quiescent period according to the output of the first comparator. With this configuration, in the enabled state of the charge pump circuit, the output voltage can be stabilized within a voltage range determined by the upper threshold and the lower threshold.

[0017] In one embodiment, the charge pump circuit may include a flying capacitor, a driver circuit that, in an enabled state, alternately applies an input voltage and a ground voltage to a first end of the flying capacitor, a first rectifying element disposed between a first input node and a second end of the flying capacitor, and a second rectifying element disposed between the second end of the flying capacitor and an output node.

[0018] In one embodiment, the charge pump circuit may further include a second comparator that compares the output voltage with the voltage at the second end of the flying capacitor while the first end of the flying capacitor is low during a period when the charge pump circuit is enabled and asserts a stop signal when the output voltage is lower. The charge pump circuit may be disabled when the stop signal is asserted. If the capacity of the charge pump circuit is small compared to the load current, operating the charge pump circuit may result in a situation where the output voltage is lower than the intermediate voltage. This situation can be detected by the second comparator, and the charge pump circuit can be disabled in response to the stop signal generated by the second comparator, thereby preventing a drop in the output voltage.

[0019] In one embodiment, the first rectifying element may be a first synchronous rectifying transistor that switches in an enabled state and is on in a disabled state, and the second rectifying element may be a second synchronous rectifying transistor that switches complementarily to the first synchronous rectifying transistor in an enabled state and is on in a disabled state.

[0020] In one embodiment, the first rectifying element and the second rectifying element may be diodes.

[0021] In one embodiment, the charge pump circuit may further include a second comparator that compares the output voltage with the intermediate voltage and asserts a stop signal when the output voltage is lower. The charge pump circuit may be disabled when the stop signal is asserted. If the capacity of the charge pump circuit is small compared to the load current, operating the charge pump circuit may result in a situation where the output voltage is lower than the intermediate voltage. This situation can be detected by the second comparator, and the charge pump circuit can be disabled in response to the stop signal generated by the second comparator, thereby preventing a drop in the output voltage.

[0022] In one embodiment, the power supply circuit may further include a second comparator that compares the output voltage with a voltage based on the input voltage and asserts a stop signal when the output voltage is lower. The charge pump circuit may be disabled when the stop signal is asserted. If the capacity of the charge pump circuit is small compared to the load current, operating the charge pump circuit may result in a situation where the output voltage is lower than the intermediate voltage. This situation can be detected by the second comparator, and the charge pump circuit can be disabled in response to the stop signal generated by the second comparator, thereby preventing a drop in the output voltage.

[0023] In one embodiment, the linear regulator may include a first transistor having a source connected to an input node and a drain connected to an output node, a second transistor having a source connected to the input node and a gate and a drain connected to the gate of the first transistor, and an error amplifier receiving a feedback voltage according to the output voltage and a reference voltage, and having an output connected to the gate of the first transistor and the gate and drain of the second transistor.

[0024] In one embodiment, the power supply circuit may be integrated on a single semiconductor substrate. "Monopoly integration" includes cases where all of the circuit components are formed on a semiconductor substrate, or cases where the main circuit components are monopoly integrated, and some resistors, capacitors, etc., for adjusting circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniform.

[0025] A power supply circuit according to one embodiment includes an input terminal that receives an input voltage, an output terminal, a first transistor having a source connected to the input terminal, an error amplifier that amplifies the error between a feedback voltage corresponding to the output voltage of the output terminal and a reference voltage and has an output connected to the gate of the first transistor, a flying capacitor, a driver circuit that applies a switching voltage to one end of the flying capacitor, the switching voltage being a high voltage corresponding to the input voltage and a ground voltage being a low voltage, a first rectifier element connected between the other end of the flying capacitor and the drain of the first transistor, a second rectifier element connected between the other end of the flying capacitor and the output terminal, and a controller that activates the driver circuit in an enable state and stops the driver circuit in a disable state.

[0026] A gate driver circuit according to one embodiment drives an N-type high-side transistor. The gate driver circuit may include a switching terminal to which one end of the high-side transistor is connected, a pre-driver that drives the gate of the high-side transistor, a bootstrap terminal, any of the power supply circuits described above, a bootstrap rectifier element provided between the output terminal of the power supply circuit and the bootstrap terminal, and a pre-driver circuit that drives the pre-driver using the bootstrap voltage of the bootstrap terminal as a high voltage.

[0027] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0028] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0029] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0030] 1 is a circuit diagram of a power supply circuit 100 according to an embodiment. The power supply circuit 100 includes an input terminal 102 and an output terminal 104. The power supply circuit 100 receives an input voltage (power supply voltage) V CC and outputs a regulated output voltage V OUT For example, output voltage V OUT is about 12V, and the input voltage V CC can be between a first voltage greater than 12V (eg, 15V, 24V, 60V) and a second voltage less than 12V (eg, 6V).

[0031] The power supply circuit 100 includes a linear regulator 110 and a charge pump circuit 120. The linear regulator 110 is also called an LDO (Low Drop Output) regulator, and has an input node IN connected to an input terminal 102, an output node OUT, and a feedback node FB. The linear regulator 110 supplies an output voltage V 1 generated at an output terminal 104 to the feedback node FB. OUT Feedback voltage V according to FB feedback voltage V FB is the reference voltage V REF In other words, the output voltage V OUT is the first target voltage V OUT(REF1) The intermediate voltage V that appears at the output node OUT approaches REGOUT The power supply circuit 100 includes a voltage divider circuit 106 including resistors R11 and R12. FB is the output voltage V OUT is divided by resistors R11 and R12, and the first target voltage V OUT(REF1) is expressed by equation (1). V OUT(REF1) =V REF ×(R11+R12) / R12 …(1)

[0032] The charge pump circuit 120 is a Dickson type and includes a flying capacitor Cf, an output capacitor Co, a first input node IN1, a second input node IN2, and an output node OUT. The first input node IN1 is connected to the output node OUT of the linear regulator 110, and supplies an intermediate voltage V REGOUT The second input node IN2 is connected to the input terminal 102 and receives the input voltage V CC The output node OUT of the charge pump circuit 120 is connected to the output terminal 104.

[0033] The charge pump circuit 120 generates an output voltage V OUT The charge pump circuit 120 can be switched between an enabled state and a disabled state depending on the first target voltage V OUT(REF1) Lower threshold voltage V TH(CP)is set, and V OUT >V TH(CP) In the disabled state, the charge pump circuit 120 is through (conductive), and the intermediate voltage V REGOUT is output to the output node OUT as is. The output voltage V OUT is expressed by the following formula: V OUT =V REGOUT -ΔV CP ΔV CP is the voltage drop across the charge pump circuit 120 in the disabled state.

[0034] The charge pump circuit 120 is V OUT <V TH(CP) In the enabled state, the charge pump circuit 120 operates in synchronization with the clock signal CLK, and the voltage V of the first input node IN1 REGOUT The flying capacitor Cf is charged with the voltage V of the second input node IN2. CC When the charge pump circuit 120 is allowed to free-run, the output voltage V OUT is expressed by the following formula: V OUT =V CC +V REGOUT

[0035] The charge pump circuit 120 has an output regulation function, and in an enabled state, the output voltage V OUT The first target voltage V OUT(REF1) The second target voltage V is set lower OUT(REF2) The second target voltage V OUT(REF2) is the threshold voltage V TH(CP) can be defined as substantially equal to

[0036] For example, the first target voltage V OUT(REF1) When is 12.5V, the second target voltage V OUT(REF2) and threshold voltage VTH(CP) can be set to about 11.5V, which is 1V lower than that.

[0037] The above is the basic configuration of the power supply circuit 100. Next, the operation of the power supply circuit 100 will be described. Figure 2 is an operational waveform diagram of the power supply circuit 100 in Figure 1. The input voltage V CC is shown decreasing over time from a high voltage level to a low voltage level.

[0038] Between times t0 and t1, the input voltage V CC is the first target voltage V OUT(REF1) is higher than the output voltage V OUT is generated by the linear regulator 110 as a first target voltage V OUT(REF1) This state is called LDO mode.

[0039] Input voltage V CC is the first target voltage V OUT(REF1) When the voltage drops below 1 V, the linear regulator 110 reduces the output voltage V OUT the first target voltage V OUT(REF1) The output voltage V OUT is the input voltage V CC During this period from t1 to t2, the output transistor inside the linear regulator 110 is in a fully on state, and the intermediate voltage V REGOUT is the input voltage V CC The voltage level is slightly lower than V REGOUT =V CC -ΔV LDO ΔV LDO is the voltage drop of the linear regulator 110. OUT >V TH(CP) Therefore, the charge pump circuit 120 is disabled and the output voltage V OUT is expressed by the following formula: V OUT =V REGOUT -ΔV CP =V CC -ΔV LDO -ΔV CP This section from t1 to t2 is called a through mode.

[0040] At time t2, the output voltage V OUT is the threshold voltage V TH(CP) When the voltage drops to , the charge pump circuit 120 is enabled and the output voltage V OUT is the second target voltage V OUT(REF2) The period from time t2 onwards is called the charge pump (CP) mode.

[0041] This is the operation of the power supply circuit 100. The power supply circuit 100 operates in a wide range of input voltages V CC At this point, the output voltage V OUT within a given voltage range (V OUT(REF2) ~V OUT(REF1) ) can be maintained.

[0042] The advantages of the power supply circuit 100 of FIG. 1 become clear when compared with comparative techniques.

[0043] (Comparative Technology) 3 is a circuit diagram of a power supply circuit 100R according to the comparative technology. The power supply circuit 100R includes a linear regulator 110R and a charge pump circuit 120R, but the connection between them is different from that of the power supply circuit 100 shown in FIG. 1. That is, in the comparative technology, the linear regulator 110R and the charge pump circuit 120R are connected completely in parallel and operate complementarily. Specifically, a comparator 130 detects an input voltage V CC is the threshold voltage V TH Compared with V CC >V TH When this occurs, the switch SW1 connected to the output of the linear regulator 110R turns on, enabling the linear regulator 110R and outputting the output voltage V OUT , the target voltage V OUT(REF1) At this time, the charge pump circuit 120R is in a disabled state.

[0044] V CC <V THAt this time, the switch SW1 connected to the output of the linear regulator 110R is turned off, and the linear regulator 110R is in a disabled state. At this time, the charge pump circuit 120R is in an enabled state. In the enabled state, the charge pump circuit 120R generates an output voltage V OUT , the target voltage V OUT(REF2) In the comparative technology, V OUT(REF2) ≧V OUT(REF1) The target voltage is determined so that:

[0045] The above is the configuration of the power supply circuit 100R. In the power supply circuit 100R, the input voltage V CC and threshold voltage V TH The linear regulator 110R and the charge pump circuit 120R operate in a complementary manner depending on the comparison result. Therefore, there is a problem that the operation becomes discontinuous when switching.

[0046] The power supply circuit 100 according to the embodiment differs from the comparative technology in that the linear regulator 110 operates constantly. OUT(REF1) and V OUT(REF2) But V OUT(REF2) <V OUT(REF1) As a result, as shown in Figure 2, a through mode is inserted between the LDO mode and the CP mode, which allows for continuous transition.

[0047] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0048] Example 1 4 is a circuit diagram of a power supply circuit 100A according to a first embodiment. The linear regulator 110 includes an error amplifier 112 and an output stage 114. The output stage 114 includes a first transistor M21 and a second transistor M22. The source of the first transistor M21 is connected to an input node IN, and the drain is connected to an output node OUT. The source of the second transistor M22 is connected to the input node IN, and the gate and drain are connected to the gate of the first transistor M21. The error amplifier 112 outputs an output voltage V OUT Feedback voltage V according to FB and the reference voltage V REF The error amplifier 112 receives the feedback voltage V and has an output connected to the gate of the first transistor M21 and the gate and drain of the second transistor M22. FB and the reference voltage V REF The error is amplified and the gate voltage of the first transistor M21 is feedback-controlled. FB is generated by a voltage divider circuit 106 including resistors R11 to R13, V FB =V OUT ×R13 / (R11+R12+R13) The linear regulator 110 generates an output voltage V OUT is the first target voltage V OUT(REF1) is stabilized to V OUT(REF1) =(R11+R12+R13) / R13×V REF

[0049] The configuration of the linear regulator 110 is not limited to that shown in Fig. 4. For example, the second transistor M22 may be omitted.

[0050] The charge pump circuit 120A includes a flying capacitor Cf, a controller 122, a driver circuit 124, a first rectifying element 126, and a second rectifying element 128.

[0051] The controller 122 generates the clock signal CLK when the charge pump circuit 120A is in an enabled state.

[0052] The driver circuit 124 is connected to the second input node IN2 and receives the input voltage V CC The driver circuit 124 receives the input voltage V CC and the ground voltage (0 V) are applied alternately. The driver circuit 124 is, for example, an inverter, and includes transistors M31 and M32.

[0053] The first rectifier element 126 is connected between the first input node IN1 and the second terminal CPH of the flying capacitor Cf. The second rectifier element 128 is connected between the second terminal CPH of the flying capacitor Cf and the output node OUT. In the first embodiment, the first rectifier element 126 and the second rectifier element 128 are P-channel MOSFETs.

[0054] The gate of the first rectifier element 126 receives the inverted clock signal / CLK, and the gate of the second rectifier element 128 receives the clock signal CLK.

[0055] The free-running operation of the charge pump circuit 120A will now be described. The charge pump circuit 120A alternates between a high state φ1 of the clock signal CLK and a low state φ2 of the clock signal CLK.

[0056] When the clock signal CLK is in a high state φ1, the first rectifier element 126 is on, the output of the driver circuit 124 is low (0 V), and the second rectifier element 128 is off. In this state, the flying capacitor Cf is connected to the voltage V REGOUT It is charged by.

[0057] When the clock signal CLK is in the low state φ2, the first rectifier element 126 is off, and the output of the driver circuit 124 is high (V CC ), the second rectifying element 128 is off. In this state, the output capacitor Co connected to the output node OUT is V OUT =V CC +V REGOUT In the free-running state where the two states are repeated, the output terminal 104 is charged to an output voltage V OUT occurs. V OUT =V CC +V REGOUT

[0058] As described above, the charge pump circuit 120A has a regulation function, and does not free-run when enabled, and the output voltage V OUT to the second target voltage V OUT(REF2) For voltage regulation, the charge pump circuit 120A includes a first comparator COMP1.

[0059] The first comparator COMP1 is a hysteresis comparator that controls the output voltage V OUT The monitored voltage V MON The second target voltage V OUT(REF2) The upper threshold V THH and the lower threshold V THL Compare with the monitored voltage V MON teeth, V MON =V OUT ×(R12+R13) / (R11+R12+R13) The first comparator COMP1 is MON and the upper threshold V THH and the lower threshold V THL The enable signal EN is generated according to the relationship between the

[0060] Specifically, the monitored voltage V MON is the lower threshold V THL When the voltage V MON is the upper threshold V THH , the enable signal EN is negated (second level, for example, low).

[0061] When the enable signal EN is asserted, the controller 122 enters an operating period and generates the clock signals CLK and / CLK, and when the enable signal EN is negated, the controller 122 enters a stop period and stops generating the clock signals CLK and / CLK.

[0062] When the charge pump circuit 120A is enabled, the controller 122 preferably fixes the gate of the MOSFET that is the first rectifier element 126 and the gate of the MOSFET that is the second rectifier element 128 to low, putting the two MOSFETs in a fully on state. This reduces the voltage drop ΔV of the charge pump circuit 120A in the disabled state. CP can be reduced to reduce losses.

[0063] The above is the configuration of the power supply circuit 100A. Next, the operation of the power supply circuit 100A will be described.

[0064] 5 is an operational waveform diagram of the power supply circuit 100A of FIG. 4. The operation from time t0 to t2 is the same as that of FIG. 2. At time t2, the monitored voltage V MON is the lower threshold V THL When the output voltage V OUT The output voltage V OUT As the monitoring voltage V MON rises, and at time t3, the monitored voltage V MON is the upper threshold V THH When the load current exceeds 10 V, the enable signal EN is negated, the clock signal CLK stops, and the stop period begins. During the stop period, the output capacitor Co is discharged by the load current, and the output voltage V OUT decreases, and the monitored voltage V MON also decreases.

[0065] At time t4, the monitored voltage V MON is the lower threshold V THL When the voltage drops to , the enable signal EN is asserted again, and the operation period begins. After that, the same operation is repeated.

[0066] The above is the operation of the power supply circuit 100A. The enable signal EN is MON There are two thresholds V THH ,V THL The charge pump circuit 120A alternates between high and low states so that the output voltage V OUT is V THH × (R11 + R12 + R13) / (R12 + R13) as the upper limit, V THL The charge pump circuit 120A is stabilized within a voltage range with a lower limit of ×(R11+R12+R13) / (R12+R13). The state in which the enable signal EN alternates between high and low is the enable state of the charge pump circuit 120A.

[0067] Output voltage V OUT But V THL If the state where ×(R11+R12+R13) / (R12+R13) is exceeded continues, the enable signal EN is fixed to be negated. This state is the disabled state of the charge pump circuit 120A.

[0068] That is, the first comparator COMP1 has a function of switching between the enable state and the disable state of the charge pump circuit 120A, and a function of regulating the charge pump circuit 120A in the enable state. OUT <V THL × (R11 + R12 + R13) / (R12 + R13), so V THL × (R11+R12+R13) / (R12+R13) is the above-mentioned threshold voltage V TH(CP) It is considered to be equivalent to

[0069] Example 2 6 is a circuit diagram of a power supply circuit 100B according to Example 2. The difference from Example 1 is the configuration of a charge pump circuit 120B. The charge pump circuit 120B further includes a second comparator COMP2 in addition to the charge pump circuit 120A of FIG.

[0070] The second comparator COMP2 is active when the charge pump circuit 120B is enabled. The second comparator COMP2 is active when the first terminal CPL of the flying capacitor Cf is low and the output voltage V OUT is compared with the voltage at the second terminal CPH of the flying capacitor Cf. Then, the output voltage V OUT is lower, the stop signal STOP is asserted.

[0071] When the stop signal STOP is asserted, the controller 122 forcibly puts the charge pump circuit 120B into a disabled state.

[0072] The above is the operation of the power supply circuit 100B.

[0073] The second comparator COMP2 is active during the period φ1 when the clock signal CLK is high and the first rectifier element 126 is on. At this time, the voltage at the second end CPH of the flying capacitor Cf is equal to the intermediate voltage V REGOUT In other words, the second comparator COMP2 outputs the voltage V OUT and the intermediate voltage V REGOUT are compared.

[0074] If the capacity of the charge pump circuit 120B is small compared to the load current, the output voltage V OUT is the intermediate voltage V REGOUT In the power supply circuit 100B according to the embodiment, this situation can be detected by the second comparator COMP2. OUT <V REGOUT In this case, by disabling the charge pump circuit 120B, the intermediate voltage V REGOUT output voltage V OUT and a higher output voltage V OUT can be supplied to the load.

[0075] Example 3 Fig. 7 is a circuit diagram of a power supply circuit 100C according to a third embodiment. The difference from Fig. 4 is the configuration of a charge pump circuit 120C. In the charge pump circuit 120C, the first rectifier element 126 and the second rectifier element 128 are each formed of a diode.

[0076] Example 4 8 is a circuit diagram of a power supply circuit 100D according to a fourth embodiment. In the charge pump circuit 120D, a second comparator COMP2 outputs an intermediate voltage V REGOUT The voltage Vx corresponding to the output voltage V OUT The voltage Vx is compared with the intermediate voltage V REGOUT It can be itself, or the intermediate voltage V REGOUT 8, it is possible to realize the same function as in the third embodiment. Furthermore, voltage comparison is possible regardless of the states φ1 and φ2 of the charge pump circuit 120D.

[0077] Alternatively, the second comparator COMP2 operates based on the input voltage V CC The voltage Vy according to the output voltage V OUT The voltage Vy can be compared with the input voltage V CC It can be itself or the input voltage V CC Alternatively, the voltage may be reduced by a predetermined voltage step.

[0078] As mentioned above, the input voltage V CC When V decreases, REGOUT =V CC -ΔV LDO and the input voltage V CC and intermediate voltage V REGOUT are essentially equal. Therefore, the intermediate voltage V REGOUT Instead of the input voltage V IN , the output voltage V OUT By comparing with the above, it is possible to realize the same function as in the third embodiment.

[0079] (Variation) The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of the components and the processing steps. Such modifications will be described below.

[0080] (Variation 1) In the power supply circuits 100B and 100D of FIGS. 6 and 8, the rectifying elements 126 and 128 may be configured with diodes.

[0081] (Variation 2) The implementation of the linear regulator 110 with a regulation function is not limited to intermittent operation using a hysteresis comparator. For example, the regulation function may be implemented by incorporating a feedback loop using an error amplifier.

[0082] (Application) 9 is a block diagram of a switching circuit 200. The switching circuit 200 includes a high-side transistor 202, a low-side transistor 204, a gate driver circuit 300, and a bootstrap capacitor C BS The high-side transistor 202 and the low-side transistor 204 are N-channel transistors. The high-side transistor 202 and the low-side transistor 204 may be FETs such as Si, SiC, or GaN, or may be IGBTs or bipolar transistors.

[0083] The gate driver circuit 300 includes a power supply pin VCC, a bootstrap pin BS, a high-side gate pin HG, a low-side gate pin LG, a switching pin SW, a high-side pre-driver 310, a low-side pre-driver 320, a bootstrap rectifier element 302, and a power supply circuit 100.

[0084] A bootstrap capacitor, C, is connected between the BS and SW pins. BS is attached externally.

[0085] The HG pin is connected to the gate of the high-side transistor 202 , and the LG pin is connected to the gate of the low-side transistor 204 .

[0086] The output of the high-side pre-driver 310 is connected to the gate of the high-side transistor 202 via the HG pin, and the output of the low-side pre-driver 320 is connected to the gate of the low-side transistor 204 via the LG pin. The input terminal 102 of the power supply circuit 100 receives an input voltage V CC The rectifying element 302 is provided between the output terminal 104 of the power supply circuit 100 and the BS pin. BS is supplied to the upper terminal of the high-side pre-driver 310, and the lower terminal of the high-side pre-driver 310 is connected to the SW pin. The high-side pre-driver 310 supplies V to the gate of the high-side transistor 202 in response to the control signal HCTRL. BS High, V SW The gate voltage V HG supply.

[0087] The upper terminal of the low-side pre-driver 320 is connected to the output voltage V OUT The low-side pre-driver 320 supplies V to the gate of the low-side transistor 204 in response to a control signal LCTRL. OUT The gate voltage V is high and 0V is low. LG supply.

[0088] An example of a switching circuit is a motor driver circuit.

[0089] 10 is a block diagram of a motor driver circuit 400. The motor driver circuit 400 drives a three-phase motor 402. The motor driver circuit 400 includes a three-phase inverter 410 and a gate driver circuit 420. The three-phase inverter 410 includes three phase U, V, and W legs, and each phase leg includes a high-side transistor MH as an upper arm and a low-side transistor ML as a lower arm.

[0090] The gate driver circuit 420 includes a power supply circuit 100 and U-, V-, and W-phase gate driver circuits 430U, 430V, and 430W. The gate driver circuit 430 for each phase includes a rectifier element 302, a high-side pre-driver 310, and a low-side pre-driver 320.

[0091] The power supply circuit 100 is not limited to motor driver circuits, but can also be used in other applications that include switching circuits that include high-side and low-side transistors. For example, the power supply circuit 100 can be used in DC / DC converters. Furthermore, the power supply circuit 100 is not limited to switching circuits, and can be used in any type of IC.

[0092] Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims. The scope of the present invention is defined by the claims, and therefore, embodiments, examples, and modifications not described herein are also included in the scope of the present invention. [Explanation of symbols]

[0093] 100 Power circuit 102 Input terminal 104 Output terminal 110 Linear Regulator IN input node OUT output node FB Feedback Node 112 Error Amplifier 114 Output Stage 120 Charge pump circuit IN1 First input node IN2 Second input node Cf Flying Capacitor Co Output Capacitor COMP1 First comparator COMP2 Second comparator 122 Controller 124 Driver Circuit 126 First rectifier element 128 Second rectifier element 200 Switching Circuit 202 High-side transistor 204 Low-side transistor 300 Gate driver circuit 302 Rectifying element 310 High-side pre-driver 320 Low Side Pre-Driver 400 Motor driver circuit 410 Three-phase inverter 420 Gate driver circuit

Claims

1. an input terminal for receiving an input voltage; an output terminal to be connected to a load; a linear regulator having an input node connected to the input terminal and an output node, the linear regulator adjusting an intermediate voltage generated at the output node so that an output voltage generated at the output terminal approaches a first target voltage; a Dickson-type charge pump circuit having a first input node receiving the intermediate voltage, a second input node receiving the input voltage, and an output node connected to the output terminal; Equipped with the charge pump circuit is disabled when the output voltage is higher than a threshold voltage that is set lower than the first target voltage, and in the disabled state outputs the voltage of the first input node to the output node; the charge pump circuit is enabled when the output voltage is lower than the threshold voltage, and in the enabled state stabilizes the output voltage to a second target voltage that is set lower than the first target voltage.

2. the charge pump circuit includes a first comparator having hysteresis for comparing a monitored voltage corresponding to the output voltage with an upper threshold and a lower threshold corresponding to the second target voltage; 2. The power supply circuit according to claim 1, wherein said charge pump circuit, in said enabled state, alternates between an active period and a quiescent period in accordance with the output of said first comparator.

3. The charge pump circuit Flying capacitors, a driver circuit that, in the enabled state, alternately applies the input voltage and a ground voltage to a first end of the flying capacitor; a first rectifying element provided between the first input node and the second end of the flying capacitor; a second rectifying element provided between a second end of the flying capacitor and the output node; 3. The power supply circuit according to claim 1, comprising:

4. the charge pump circuit further includes a second comparator that compares the output voltage with a voltage at the second end of the flying capacitor during an interval in which the first end of the flying capacitor is low while the charge pump circuit is in the enabled state, and asserts a stop signal when the output voltage is lower than the voltage at the second end of the flying capacitor; 4. The power supply circuit according to claim 3, wherein said charge pump circuit is put into said disabled state when said stop signal is asserted.

5. the first rectifying element is a first synchronous rectifying transistor that switches in the enabled state and is in an on state in the disabled state; 5. The power supply circuit according to claim 3, wherein the second rectifying element is a second synchronous rectifying transistor that switches complementarily to the first synchronous rectifying transistor in the enable state and is in an on state in the disable state.

6. 5. The power supply circuit according to claim 3, wherein the first rectifying element and the second rectifying element are diodes.

7. The charge pump circuit further includes a second comparator that compares the output voltage with the intermediate voltage and asserts a stop signal when the output voltage is lower.

3. The power supply circuit according to claim 1, wherein said charge pump circuit is put into said disabled state when said stop signal is asserted.

8. the charge pump circuit further includes a second comparator that compares the output voltage with a voltage based on the input voltage and asserts a stop signal when the output voltage is lower; 3. The power supply circuit according to claim 1, wherein said charge pump circuit is put into said disabled state when said stop signal is asserted.

9. The linear regulator a first transistor having a source connected to the input node and a drain connected to the output node; a second transistor having a source connected to the input node and a gate and a drain connected to the gate of the first transistor; an error amplifier that receives a feedback voltage corresponding to the output voltage and a reference voltage, and has an output connected to the gate of the first transistor and the gate and drain of the second transistor; 9. The power supply circuit according to claim 1, comprising:

10. 10. The power supply circuit according to claim 1, which is integrated on a single semiconductor substrate.

11. an input terminal for receiving an input voltage; An output terminal; a first transistor having a source connected to the input terminal; an error amplifier that amplifies an error between a feedback voltage corresponding to an output voltage of the output terminal and a reference voltage, and has an output connected to a gate of the first transistor; Flying capacitors, a driver circuit that applies a switching voltage to one end of the flying capacitor, the switching voltage being a high voltage corresponding to the input voltage and a ground voltage being a low voltage; a first rectifying element connected between the other end of the flying capacitor and the drain of the first transistor; a second rectifying element connected between the other end of the flying capacitor and the output terminal; a controller that activates the driver circuit in an enable state and deactivates the driver circuit in a disable state; A power supply circuit comprising:

12. A gate driver circuit for driving an N-type high-side transistor, a switching terminal to which one end of the high-side transistor is connected; a pre-driver that drives a gate of the high-side transistor; A bootstrap terminal; a power supply circuit according to any one of claims 1 to 11; a bootstrap rectifying element provided between an output terminal of the power supply circuit and the bootstrap terminal; a pre-driver circuit that drives the pre-driver by setting a bootstrap voltage of the bootstrap terminal to a high voltage; A gate driver circuit comprising:

13. A motor driver circuit comprising the gate driver circuit of claim 12.

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