Reference voltage generating circuit and semiconductor integrated circuit

Abstract

This reference voltage generation circuit comprises: a resistor circuit (117) that is electrically connected between a first node and a second node and between the first node and a third node, and has variable resistors, the resistance values of which vary according to a first control signal; a differential amplification circuit (116) that has a pair of differential inputs, one of which is electrically connected to the second node and the other of which is electrically connected to the third node, and generates a reference voltage at an output node; a current source circuit (113 to 115) that is electrically connected between the second node and a fourth node and between the third node and the fourth node; and an adjustment circuit (301) that is electrically connected to the output node, compares at least two target voltages with the reference voltage, and thereby generates the first control signal.

Description

[Technical Field]

[0001] The present invention relates to a reference voltage generating circuit and a semiconductor integrated circuit. [Background technology]

[0002] Patent Document 1 describes a reference voltage generating circuit having two bipolar transistors with different current densities, an amplifier circuit that amplifies the difference between the base-emitter voltages of the two transistors, and a resistor to which the output of the amplifier circuit is applied. A voltage adder circuit adds the voltage generated in the resistor to the base-emitter voltage of one of the two transistors. An adjustment resistor is connected in series with the resistor, and its resistance value can be adjusted. A reference voltage adjustment unit adjusts the reference voltage extracted from one end or the midpoint of the adjustment resistor.

[0003] Patent Document 2 describes a bandgap reference voltage generator including forward-biased PN junction elements with different current densities. The bandgap reference voltage generator has first and second PN junction elements forward-biased with different current densities, a voltage divider connected to the first PN junction element, and a switch element for selecting the voltage division ratio. A voltage error amplifier inputs the divided voltage and the voltage of the second PN junction element and generates a thermally compensated output voltage.

[0004] Patent Document 3 describes a high-precision, low-power bandgap voltage reference circuit. The bandgap voltage reference circuit includes a high-power bandgap circuit, a low-power bandgap circuit, and a calibration circuit. The calibration circuit compares the bandgap voltage output by the high-power bandgap circuit with the bandgap voltage output by the low-power bandgap circuit, and outputs a calibration signal to the low-power bandgap circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-182113 [Patent Document 2] US Patent Application Publication No. 2014 / 0070777 [Patent Document 3] U.S. Patent No. 6,844,711 Summary of the Invention [Problem to be solved by the invention]

[0006] A reference voltage generation circuit generates a reference voltage. Reference voltage generation circuits generate errors in the reference voltage. To adjust for these errors, the reference voltage must be measured accurately. However, it is difficult to accurately measure the reference voltage and adjust it with high precision.

[0007] An object of the present invention is to enable the generated reference voltage to be adjusted with high precision. [Means for solving the problem]

[0008] The reference voltage generation circuit includes a resistor circuit electrically connected between a first node and a second node and between the first node and a third node, and having a variable resistor whose resistance value changes in response to a first control signal; a differential amplifier circuit having one of a differential input pair electrically connected to the second node and the other of the differential input pair electrically connected to the third node, and generating a reference voltage at an output node; a current source circuit electrically connected between the second node and a fourth node and between the third node and the fourth node; and an adjustment circuit electrically connected to the output node, and generating the first control signal by comparing the reference voltage with at least two target voltages. and a switch circuit that connects the output node to a reference voltage node for outputting the reference voltage in response to a second control signal, wherein the adjustment circuit generates the second control signal in response to a result of comparing the at least two target voltages with the reference voltage, and the switch circuit connects the reference voltage node to a ground potential node when disconnecting the output node from the reference voltage node. . [Effects of the Invention]

[0009] The generated reference voltage can be adjusted with high precision. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a reference voltage generating circuit according to a comparative example. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of the semiconductor integrated circuit according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing another configuration example of the semiconductor integrated circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a comparison result signal when the reference voltage is lower than the two target voltages. [Figure 5] FIG. 5 is a diagram showing a comparison result signal when the reference voltage is a voltage between two target voltages. [Figure 6] FIG. 6 is a diagram showing a comparison result signal when the reference voltage is higher than the two target voltages. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a variable resistor. [Figure 8] FIG. 8 is a flowchart for explaining the operation of the reference voltage generating circuit of FIG. [Figure 9] FIG. 9 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a switch circuit. [Figure 11] FIG. 11 is a flowchart for explaining the operation of the reference voltage generating circuit of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] (First embodiment) FIG. 1 is a diagram showing an example configuration of a reference voltage generating circuit 101 according to a comparative example. The reference voltage generating circuit 101 is a bandgap reference voltage generating circuit and includes a resistor circuit 117, a resistor 113, pnp bipolar transistors 114 and 115, and a differential amplifier circuit 116. The reference voltage generating circuit 101 is, for example, a circuit that constitutes part of a semiconductor chip, and includes terminals VDD, TRIM, VSS, and BGRO. The terminal VDD inputs a power supply voltage. The terminal TRIM inputs a trim code. The terminal VSS inputs a ground potential. The terminal BGRO outputs a reference voltage Vr.

[0012] The resistance circuit 117 has a variable resistor 111 and a variable resistor 112. The variable resistor 111 is connected between a node N21 and a node N22. The variable resistor 112 is connected between a node N21 and a node N23. The resistance values ​​of the variable resistors 111 and 112 are set to the same value.

[0013] The emitter of the pnp bipolar transistor 115 is connected to the node N22, and the base and collector are connected to the node of the terminal VSS. The node of the terminal VSS is a ground potential node. The pnp bipolar transistor 115 is diode-connected and connected between the node N22 and the node of the terminal VSS.

[0014] Resistor 113 is connected between node N23 and the emitter of pnp bipolar transistor 114. The base and collector of pnp bipolar transistor 114 are connected to the node of terminal VSS. Pnp bipolar transistor 114 is diode-connected. A series connection circuit of resistor 113 and pnp bipolar transistor 114 is connected between node N23 and terminal VSS.

[0015] The differential amplifier circuit 116 is connected to a node of a terminal VDD and a node of a terminal VSS. The node of the terminal VDD is a power supply voltage node. In the differential amplifier circuit 116, one + input node of the differential input pair is electrically connected to a node N22, and the other - input node of the differential input pair is electrically connected to a node N23, and the differential amplifier circuit 116 generates a reference voltage Vr at an output node. The output node of the differential amplifier circuit 116 is electrically connected to a node N21. The node N21 is electrically connected to a terminal BGRO.

[0016] The reference voltage generating circuit 101 can generate a reference voltage Vr that is independent of the power supply voltage and temperature. To improve the accuracy of the reference voltage Vr, the reference voltage Vr at the terminal BGRO is measured by a measuring instrument 102. Based on the measured reference voltage Vr, a trim code is input to the terminal TRIM so that the reference voltage Vr becomes a target voltage. The resistance values ​​of the variable resistors 111 and 112 are adjusted to a value corresponding to the trim code at the terminal TRIM. As a result, the reference voltage Vr is adjusted to the target voltage.

[0017] However, when the current of reference voltage generation circuit 101 is small, that is, when the driving capability of reference voltage generation circuit 101 is small, measuring device 102 becomes a load on reference voltage generation circuit 101. As a result, it is difficult for measuring device 102 to accurately measure reference voltage Vr generated by reference voltage generation circuit 101. This makes it difficult to adjust reference voltage Vr with high precision using a trim code. An embodiment for solving this problem will be described below.

[0018] 2 is a diagram showing an example of the configuration of a semiconductor integrated circuit 200 according to the first embodiment. The semiconductor integrated circuit 200 has a reference voltage generating circuit 201 and a subsequent circuit 206. The subsequent circuit 206 is connected to a terminal VREF of the reference voltage generating circuit 201. The reference voltage generating circuit 201 is obtained by adding an adjustment circuit 205 to the reference voltage generating circuit 101 of FIG. 1. The reference voltage generating circuit 201 is a circuit that constitutes, for example, a part of a semiconductor chip, and has a terminal VDE, a terminal VDD, a terminal VSS, and a terminal VREF.

[0019] The adjustment circuit 205 has resistors 202 and 203 and a comparison circuit 204. A power supply voltage is input to a terminal VDE. The node of the terminal VDE is a power supply voltage node, and is a node independent of the node of the terminal VDD. In other words, the power supply voltage of the terminal VDE is a stable power supply voltage that is hardly affected by noise from the power supply voltage of the terminal VDD that accompanies the operation of the reference voltage generation circuit 201.

[0020] The series circuit of the resistor 202 and the resistor 203 is connected between the terminal VDE and the terminal VSS. The target voltage V0 is the voltage at the interconnection point of the resistor 202 and the resistor 203.

[0021] The comparator circuit 204 is connected to the node of the terminal VDD and the node of the terminal VSS. The comparator circuit 204 compares the reference voltage Vr with the target voltage V0. The adjustment circuit 205 controls the resistance values ​​of the variable resistors 111 and 112 so that the reference voltage Vr is equal to the target voltage V0. When the reference voltage Vr is equal to the target voltage V0, the adjustment circuit 205 maintains the resistance values ​​of the variable resistors 111 and 112.

[0022] Furthermore, when the reference voltage Vr is lower than the target voltage V0, the adjustment circuit 205 increases the resistance values ​​of the variable resistors 111 and 112. As a result, the reference voltage Vr increases and approaches the target voltage V0.

[0023] Furthermore, when the reference voltage Vr is higher than the target voltage V0, the adjustment circuit 205 reduces the resistance values ​​of the variable resistors 111 and 112. As a result, the reference voltage Vr decreases and approaches the target voltage V0.

[0024] As described above, the adjustment circuit 205 can accurately measure the reference voltage Vr and adjust the reference voltage Vr with high precision so that the reference voltage Vr becomes the same as the target voltage V0.

[0025] The terminal VREF is connected to the node N21 and outputs the reference voltage Vr. The subsequent circuit 206 operates by receiving the reference voltage Vr from the terminal VREF of the reference voltage generating circuit 201.

[0026] The reference voltage generation circuit 201 can accurately perform trimming adjustment to improve the accuracy of the reference voltage Vr while reducing the amount of drive current flowing through the reference voltage generation circuit 201. Furthermore, the reference voltage generation circuit 201 does not need to be provided with a terminal BGRO for connecting the external measuring device 102 for trimming adjustment to the output node of the differential amplifier circuit 116, as shown in FIG. 1, and therefore the number of terminals of the reference voltage generation circuit 201 can be reduced. Furthermore, the semiconductor chip on which the reference voltage generation circuit 201 is provided does not need to be provided with pads for connecting to the external measuring device 102, and therefore the number of pads on the semiconductor chip can be reduced.

[0027] 3 is a diagram showing another example of the configuration of the semiconductor integrated circuit 200 according to the first embodiment. The semiconductor integrated circuit 200 has a reference voltage generating circuit 201 and a subsequent circuit 206. The subsequent circuit 206 is connected to the terminal VREF of the reference voltage generating circuit 201. The reference voltage generating circuit 201 in FIG. 3 is the same as the reference voltage generating circuit in FIG. 2 01, an adjustment circuit 301 is added instead of the adjustment circuit 205.

[0028] The reference voltage generating circuit 201 is a bandgap reference voltage generating circuit, and includes a resistor circuit 117, a resistor 113, pnp bipolar transistors 114 and 115, a differential amplifier circuit 116, and an adjustment circuit 301. The reference voltage generating circuit 201 is, for example, a circuit that constitutes a part of a semiconductor chip, and includes a terminal VDE, a terminal VDD, a terminal VSS, and a terminal VREF.

[0029] Terminals VDD and VDE input power supply voltages that are independent of each other. The node of terminal VDE is a power supply voltage node, and is a node independent of the node of terminal VDD. In other words, the power supply voltage of terminal VDE is a stable power supply voltage that is hardly affected by noise from the power supply voltage of terminal VDD that accompanies the operation of reference voltage generating circuit 201. Terminal VSS inputs ground potential. Terminal VREF outputs reference voltage Vr.

[0030] The resistance circuit 117 has a variable resistor 111 and a variable resistor 112. The variable resistor 111 is connected between a node N21 and a node N22. The variable resistor 112 is connected between a node N21 and a node N23. The resistance values ​​of the variable resistors 111 and 112 are set to the same value.

[0031] The emitter of the pnp bipolar transistor 115 is connected to the node N22, and the base and collector are connected to the node of the terminal VSS. The node of the terminal VSS is a ground potential node. The pnp bipolar transistor 115 is diode-connected and connected between the node N22 and the node of the terminal VSS.

[0032] Resistor 113 is connected between node N23 and the emitter of pnp bipolar transistor 114. The base and collector of pnp bipolar transistor 114 are connected to the node of terminal VSS. Pnp bipolar transistor 114 is diode-connected. A series connection circuit of resistor 113 and pnp bipolar transistor 114 is connected between node N23 and terminal VSS.

[0033] The differential amplifier circuit 116 is connected to a node of a terminal VDD and a node of a terminal VSS. The node of the terminal VDD is a power supply voltage node. In the differential amplifier circuit 116, one + input node of the differential input pair is electrically connected to a node N22, and the other - input node of the differential input pair is electrically connected to a node N23, and the differential amplifier circuit 116 generates a reference voltage Vr at an output node. The output node of the differential amplifier circuit 116 is connected to a node N21. The node N21 is connected to a terminal VREF. The reference voltage generation circuit 201 can generate a reference voltage Vr that is independent of the power supply voltage and temperature.

[0034] The adjustment circuit 301 includes resistors 302 to 304, comparison circuits 305 and 306, and a logic circuit 307. The series-connected circuit of the resistors 302 to 304 is connected between the terminal VDE and the terminal VSS, and generates target voltages V1 and V2 by resistively dividing the power supply voltage of the terminal VDE. The target voltage V1 is the voltage at the interconnection point of the resistors 303 and 304. The target voltage V2 is the voltage at the interconnection point of the resistors 302 and 303, and is higher than the target voltage V1.

[0035] The comparison circuit 306 compares the reference voltage Vr with the target voltage V1 and outputs a comparison result signal C1. The comparison circuit 305 compares the reference voltage Vr with the target voltage V2 and outputs a comparison result signal C2.

[0036] 4 is a diagram showing comparison result signals C1 and C2 when the reference voltage Vr is lower than the target voltages V1 and V2. When the reference voltage Vr is lower than the target voltage V1, the comparison circuit 306 outputs a comparison result signal C1 of 0 (low level). When the reference voltage Vr is lower than the target voltage V2, the comparison circuit 305 outputs a comparison result signal C2 of 0 (low level).

[0037] 5 is a diagram showing comparison result signals C1 and C2 when the reference voltage Vr is a voltage between the target voltages V1 and V2. When the reference voltage Vr is higher than the target voltage V1, the comparison circuit 306 outputs the comparison result signal C1 as 1 (high level). When the reference voltage Vr is lower than the target voltage V2, the comparison circuit 305 outputs the comparison result signal C2 as 0 (low level).

[0038] 6 is a diagram showing comparison result signals C1 and C2 when the reference voltage Vr is higher than the target voltages V1 and V2. When the reference voltage Vr is higher than the target voltage V1, the comparison circuit 306 outputs a comparison result signal C1 of 1 (high level). When the reference voltage Vr is higher than the target voltage V2, the comparison circuit 305 outputs a comparison result signal C2 of 1 (high level).

[0039] The logic circuit 307 outputs, for example, 3-bit trim codes T[0] to T[2] to the variable resistors 111 and 112 in response to the comparison result signals C1 and C2.

[0040] 7 is a diagram showing an example of the configuration of each of the variable resistors 111 and 112. The variable resistors 111 and 112 have the same configuration. The variable resistors 111 and 112 each include n-channel field effect transistors 701 to 703 and resistors 711 to 715.

[0041] Resistor 711 is connected between nodes N1 and N2. Resistor 712 is connected between nodes N2 and N3. Resistor 713 is connected between nodes N3 and N4. Resistor 714 is connected between nodes N4 and N5. Resistor 715 is connected between nodes N5 and N6.

[0042] In the case of the variable resistor 111, the node N1 is connected to the node N22 in Fig. 3, and the node N6 is connected to the node N21 in Fig. 3. In the case of the variable resistor 112, the node N1 is connected to the node N23 in Fig. 3, and the node N6 is connected to the node N21 in Fig. 3.

[0043] When the trim code T[0] is 1, the n-channel field effect transistor 701 connects the node N2 to the node N3, and when the trim code T[0] is 0, it disconnects the node N2 from the node N3.

[0044] The n-channel field effect transistor 702 connects the node N3 to the node N4 when the trim code T[1] is 1, and disconnects the node N2 from the node N4 when the trim code T[1] is 0.

[0045] When the trim code T[2] is 1, the n-channel field effect transistor 703 connects the node N4 to the node N5, and when the trim code T[2] is 0, it disconnects the node N4 from the node N5.

[0046] Fig. 8 is a flowchart for explaining the operation of the reference voltage generating circuit 201 of Fig. 3. In step S801, the logic circuit 307 proceeds to any of steps S802, S805, and S808 depending on the comparison result signals C1 and C2.

[0047] If the comparison result signals C1 and C2 are 0, the logic circuit 307 proceeds to step S802 because the reference voltage Vr is lower than the target voltages V1 and V2 as shown in FIG.

[0048] Also, if the comparison result signal C1 is 1 and the comparison result signal C2 is 0, the logic circuit 307 proceeds to step S805 because the reference voltage Vr is a voltage between the target voltage V1 and the target voltage V2, as shown in FIG.

[0049] If the comparison result signals C1 and C2 are 1, the logic circuit 307 proceeds to step S808 because the reference voltage Vr is higher than the target voltages V1 and V2, as shown in FIG.

[0050] In step S802, the logic circuit 307 decreases the trim codes T[0] to T[2] by one unit. Specifically, the logic circuit 307 decreases the total number of 1 bits in the trim codes T[0] to T[2] by one. For example, if the current trim codes T[0] to T[2] are 111, the logic circuit 307 changes the trim codes T[0] to T[2] to 110.

[0051] Next, in step S803, the resistance values ​​of the variable resistors 111 and 112 increase as the trim codes T[0] to T[2] decrease. For example, the resistance values ​​of the variable resistors 111 and 112 when the trim codes T[0] to T[2] are 110 are greater than the resistance values ​​of the variable resistors 111 and 112 when the trim codes T[0] to T[2] are 111. The resistance values ​​of the variable resistors 111 and 112 are the same.

[0052] Next, in step S804, the reference voltage Vr output by the differential amplifier circuit 116 increases and approaches the target voltages V1 and V2 as the resistance values ​​of the variable resistors 111 and 112 increase. After that, the processing of the reference voltage generation circuit 201 returns to step S801.

[0053] In step S805, the logic circuit 307 maintains the current trim codes T[0] to T[2].

[0054] Next, in step S806, the trim codes T[0] to T[2] are maintained, so the resistance values ​​of the variable resistors 111 and 112 are maintained. The resistance values ​​of the variable resistors 111 and 112 are the same.

[0055] Next, in step S807, the reference voltage Vr output by the differential amplifier circuit 116 is maintained when the resistance values ​​of the variable resistors 111 and 112 are maintained. After that, the processing of the reference voltage generation circuit 201 returns to step S801.

[0056] In step S808, the logic circuit 307 increases the trim codes T[0] to T[2] by 1. Specifically, the logic circuit 307 increases the total number of 1 bits in the trim codes T[0] to T[2] by 1. For example, if the current trim codes T[0] to T[2] are 000, the logic circuit 307 changes the trim codes T[0] to T[2] to 001.

[0057] Next, in step S809, as the trim codes T[0] to T[2] increase, the resistance values ​​of the variable resistors 111 and 112 decrease. For example, when the trim codes T[0] to T[2] are 001, the resistance values ​​of the variable resistors 111 and 112 are smaller than when the trim codes T[0] to T[2] are 000. The resistance values ​​of the variable resistors 111 and 112 are the same.

[0058] Next, in step S810, the reference voltage Vr output by the differential amplifier circuit 116 decreases and approaches the target voltages V1 and V2 as the resistance values ​​of the variable resistors 111 and 112 decrease. After that, the processing of the reference voltage generation circuit 201 returns to step S801.

[0059] 8, the reference voltage generation circuit 201 repeats the processing of the flowchart in Fig. 8, causing the reference voltage Vr to converge to a voltage between the target voltages V1 and V2. The processing of the flowchart in Fig. 8 is repeatedly performed while a power supply voltage is being supplied to the reference voltage generation circuit 201. Note that the processing of the flowchart in Fig. 8 may be performed when the reference voltage generation circuit 201 is shipped from the factory, or may be performed as initialization processing when the supply of a power supply voltage to the reference voltage generation circuit 201 begins.

[0060] The resistance circuit 117 is not limited to having the variable resistors 111 and 112. The resistance circuit 117 may be any circuit that is electrically connected between the node N21 and the node N22 and between the node N21 and the node N23 and has a variable resistor whose resistance value changes according to the trim code (control signal) T[0] to T2].

[0061] Furthermore, the resistor 113 and the pnp bipolar transistors 114 and 115 may share one current source, which may be a current source circuit electrically connected between the node N22 and the terminal VSS, and between the node N23 and the terminal VSS.

[0062] Also, although the example has been described with two target voltages V1 and V2, there may be three or more target voltages. Similarly, although the example has been described with two comparison circuits 305 and 306, there may be three or more comparison circuits. Similarly, although the example has been described with three-bit trim codes T[0] to T[2], the trim codes may be four or more bits.

[0063] The adjustment circuit 301 has a series-connected circuit of resistors 302 to 304 that generates at least two target voltages by resistively dividing the power supply voltage at the terminal VDE.

[0064] The adjustment circuit 301 is electrically connected to the output node of the differential amplifier circuit 116, and generates trim codes T[0] to T[2] by comparing at least two target voltages V1 and V2 with a reference voltage Vr.

[0065] As shown in FIG. 4, when the reference voltage Vr is lower than the target voltage V1 and the target voltage V2, the resistance circuit 117 increases the resistance value between the node N21 and the node N22 and the resistance value between the node N21 and the node N23.

[0066] As shown in FIG. 5, when the reference voltage Vr is a voltage between the target voltage V1 and the target voltage V2, the resistance circuit 117 maintains the resistance value between the node N21 and the node N22 and the resistance value between the node N21 and the node N23.

[0067] As shown in FIG. 6, when the reference voltage Vr is higher than the target voltage V1 and the target voltage V2, the resistance circuit 117 reduces the resistance between the node N21 and the node N22 and the resistance between the node N21 and the node N23.

[0068] In the resistance circuit 117, the resistance value between the node N21 and the node N22 is the same as the resistance value between the node N21 and the node N23.

[0069] The comparison circuit 305 and the comparison circuit 306 operate by receiving a power supply voltage from a node of the terminal VDD that is independent from the node of the power supply voltage of the terminal VDE. In other words, the power supply voltage of the terminal VDE is a stable power supply voltage that is hardly affected by noise of the power supply voltage of the terminal VDD that accompanies the operation of the reference voltage generation circuit 201.

[0070] The logic circuit 307 generates trim codes T[0] to T[2] in accordance with the comparison result signal (output signal) C1 of the comparison circuit 306 and the comparison result signal (output signal) C2 of the comparison circuit 305.

[0071] As described above, reference voltage generation circuit 201 can accurately perform trimming adjustment to improve the accuracy of reference voltage Vr while reducing the amount of drive current flowing through reference voltage generation circuit 201. Furthermore, reference voltage generation circuit 201 does not need to be provided with terminal BGRO for connecting external measuring device 102 for trimming adjustment to the output node of differential amplifier circuit 116, as shown in FIG. 1, thereby reducing the number of terminals of reference voltage generation circuit 201. Furthermore, it is not necessary to provide pads for connecting to external measuring device 102 on the semiconductor chip on which reference voltage generation circuit 201 is provided, thereby reducing the number of pads on the semiconductor chip.

[0072] (Second embodiment) The adjustment circuit 301 in FIG. 3 automatically adjusts the reference voltage Vr, and therefore there is a concern that the reference voltage Vr may be supplied to the subsequent circuit 206 even when the reference voltage Vr is not between the target voltages V1 and V2, causing the subsequent circuit 206 to malfunction. This problem arises as a result of the adjustment circuit 301 automatically adjusting the reference voltage Vr. In order for the adjustment circuit 301 to automatically adjust the reference voltage Vr, a mechanism is required to supply the reference voltage Vr to the subsequent circuit 206 after it is determined that the reference voltage Vr has become a voltage between the target voltages V1 and V2. A second embodiment for solving this problem will be described below.

[0073] Fig. 9 is a diagram showing an example of the configuration of a semiconductor integrated circuit 200 according to the second embodiment. The semiconductor integrated circuit 200 in Fig. 9 is obtained by adding a switch circuit 901 to the semiconductor integrated circuit 200 in Fig. 3. The differences between Fig. 9 and Fig. 3 will be described below.

[0074] The reference voltage generating circuit 201 includes a switch circuit 901. The switch circuit 901 is connected between a node N21 and a terminal VREF, and connects the node N21 to the terminal VREF in response to a control signal CTL. The terminal VREF is a reference voltage node for outputting a reference voltage. The adjustment circuit 301 generates the control signal CTL in response to a result of comparing at least two target voltages V1 and V2 with the reference voltage Vr.

[0075] Fig. 10 is a diagram showing an example of the configuration of the switch circuit 901 of Fig. 9. The switch circuit 901 includes an n-channel field effect transistor 1001, a p-channel field effect transistor 1002, an n-channel field effect transistor 1003, and an inverter 1004.

[0076] Node N11 is connected to node N21 in Fig. 9 and receives reference voltage Vr. Node N12 receives control signal CTL of logic circuit 307 in Fig. 9. Node N13 is connected to terminal VREF in Fig. 9. Inverter 1004 outputs the logically inverted signal of control signal CTL.

[0077] The n-channel field effect transistor 1001 has a source connected to node N11, a gate connected to node N12, and a drain connected to node N13. The p-channel field effect transistor 1002 has a source connected to node N11, a gate connected to the output node of the inverter 1004, and a drain connected to node N13. The n-channel field effect transistor 1003 has a drain connected to node N13, a gate connected to the output node of the inverter 1004, and a source connected to terminal VSS.

[0078] Fig. 11 is a flowchart for explaining the operation of reference voltage generating circuit 201 of Fig. 9. The flowchart of Fig. 11 is obtained by adding steps S1101 to S1103 to the flowchart of Fig. 8. Below, the differences between Fig. 11 and Fig. 8 will be described.

[0079] In step S801, the logic circuit 307 proceeds to one of steps S1101 to S1103 depending on the comparison result signals C1 and C2.

[0080] If the comparison result signals C1 and C2 are 0, the logic circuit 307 proceeds to step S1101 because the reference voltage Vr is lower than the target voltages V1 and V2 as shown in FIG.

[0081] Also, if the comparison result signal C1 is 1 and the comparison result signal C2 is 0, the logic circuit 307 proceeds to step S1102 because the reference voltage Vr is a voltage between the target voltage V1 and the target voltage V2, as shown in FIG.

[0082] If the comparison result signals C1 and C2 are 1, the logic circuit 307 proceeds to step S1103 because the reference voltage Vr is higher than the target voltages V1 and V2 as shown in FIG.

[0083] In step S1101, the logic circuit 307 outputs a control signal CTL of 0 to the switch circuit 901. Then, as shown in FIG. 10, the n-channel field effect transistor 1001 and the p-channel field effect transistor 1002 are turned off, and the n-channel field effect transistor 1003 is turned on. The node N11 (node ​​N21) is disconnected from the node N13 (terminal VREF). The node N13 (terminal VREF) is connected to the terminal VSS (ground potential node). The terminal VREF does not become the reference voltage Vr, but becomes the ground potential. The terminal VREF of the reference voltage generation circuit 201 does not supply the reference voltage Vr to the subsequent circuit 206. Thereafter, the processing of the reference voltage generation circuit 201 proceeds to steps S802 to S804 similar to FIG. 8.

[0084] In step S1102, the logic circuit 307 outputs a control signal CTL of 1 to the switch circuit 901. Then, as shown in FIG. 10, the n-channel field effect transistor 1001 and the p-channel field effect transistor 1002 are turned on, and the n-channel field effect transistor 1003 is turned off. The node N11 (node ​​N21) is connected to the node N13 (terminal VREF). The node N13 (terminal VREF) is disconnected from the terminal VSS (ground potential node). The terminal VREF becomes the reference voltage Vr. The terminal VREF of the reference voltage generation circuit 201 supplies the reference voltage Vr to the subsequent circuit 206. Thereafter, the processing of the reference voltage generation circuit 201 proceeds to steps S805 to S807 similar to FIG. 8.

[0085] In step S1103, the logic circuit 307 outputs a control signal CTL of 0 to the switch circuit 901. Then, as shown in FIG. 10, the n-channel field effect transistor 1001 and the p-channel field effect transistor 1002 are turned off, and the n-channel field effect transistor 1003 is turned on. The node N11 (node ​​N21) is disconnected from the node N13 (terminal VREF). The node N13 (terminal VREF) is connected to the terminal VSS (ground potential node). The terminal VREF does not become the reference voltage Vr, but becomes the ground potential. The terminal VREF of the reference voltage generation circuit 201 does not supply the reference voltage Vr to the subsequent circuit 206. Thereafter, the processing of the reference voltage generation circuit 201 proceeds to steps S808 to S810 similar to FIG. 8.

[0086] As described above, in step S1102, when the reference voltage Vr is a voltage between the target voltage V1 and the target voltage V2, the switch circuit 901 connects the node N21 to the terminal VREF.

[0087] In steps S1101 and S1103, the switch circuit 901 disconnects the node N21 from the terminal VREF when the reference voltage Vr is not a voltage between the target voltage V1 and the target voltage V2. When disconnecting the node N21 from the terminal VREF, the switch circuit 901 connects the terminal VREF to the terminal VSS (ground potential node).

[0088] According to this embodiment, when the reference voltage Vr is not between the target voltage V1 and the target voltage V2, the switch circuit 901 is turned off and does not supply the reference voltage Vr to the subsequent circuit 206. This makes it possible to prevent the subsequent circuit 206 from malfunctioning.

[0089] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Industrial Applicability]

[0090] The generated reference voltage can be adjusted with high precision.

Claims

1. a resistance circuit electrically connected between a first node and a second node and between the first node and a third node, the resistance circuit having a variable resistor whose resistance value changes in response to a first control signal; a differential amplifier circuit having one of a differential input pair electrically connected to the second node and the other of the differential input pair electrically connected to the third node, the differential amplifier circuit generating a reference voltage at an output node; a current source circuit electrically connected between the second node and a fourth node and between the third node and the fourth node; an adjustment circuit electrically connected to the output node, the adjustment circuit comparing at least two target voltages with the reference voltage to generate the first control signal; a switch circuit that connects the output node to a reference voltage node for outputting the reference voltage in response to a second control signal; the adjustment circuit generates the second control signal in response to a result of comparing the at least two target voltages with the reference voltage; The reference voltage generating circuit has a switch circuit that connects the reference voltage node to a ground potential node when disconnecting the output node from the reference voltage node.

2. the at least two target voltages include a first target voltage and a second target voltage; 2. The reference voltage generating circuit according to claim 1, wherein the switch circuit connects the output node to the reference voltage node when the reference voltage is a voltage between the first target voltage and the second target voltage, and disconnects the output node from the reference voltage node when the reference voltage is not a voltage between the first target voltage and the second target voltage.

3. The resistor circuit includes: a first variable resistor connected between the first node and the second node; 3. The reference voltage generating circuit according to claim 1, further comprising a second variable resistor connected between said first node and said third node.

4. the at least two target voltages include a first target voltage and a second target voltage; The resistor circuit includes: When the reference voltage is lower than the first target voltage and the second target voltage, a resistance value between the first node and the second node and a resistance value between the first node and the third node are increased; maintaining a resistance value between the first node and the second node and a resistance value between the first node and the third node when the reference voltage is a voltage between the first target voltage and the second target voltage; 4. The reference voltage generating circuit according to claim 1, wherein when the reference voltage is higher than the first target voltage and the second target voltage, the resistance value between the first node and the second node and the resistance value between the first node and the third node are reduced.

5. 5. The reference voltage generating circuit according to claim 1, wherein the resistance circuit has a resistance value between the first node and the second node and a resistance value between the first node and the third node that are the same as each other.

6. The current source circuit comprises: a first transistor connected between the second node and the fourth node; a first resistor and a second transistor connected between the third node and the fourth node; 6. The reference voltage generating circuit according to claim 1, wherein the first transistor and the second transistor are diode-connected.

7. 7. The reference voltage generating circuit according to claim 1, wherein the fourth node is a ground potential node.

8. 8. The reference voltage generating circuit according to claim 1, wherein the output node is electrically connected to the first node.

9. the at least two target voltages include a first target voltage and a second target voltage; The adjustment circuit a first comparison circuit that compares the reference voltage with the first target voltage; 9. The reference voltage generating circuit according to claim 1, further comprising a second comparison circuit that compares the reference voltage with the second target voltage.

10. 10. The reference voltage generating circuit according to claim 1, wherein the adjustment circuit comprises a resistor series connection circuit that generates the at least two target voltages by resistively dividing a first power supply voltage.

11. the adjustment circuit includes a resistor series connection circuit that generates the at least two target voltages by resistively dividing a first power supply voltage; 10. The reference voltage generating circuit according to claim 9, wherein the first comparison circuit and the second comparison circuit operate by receiving a second power supply voltage from a node independent of the node of the first power supply voltage.

12. 12. The reference voltage generating circuit according to claim 9, wherein the adjustment circuit has a logic circuit that generates the first control signal in response to the output signal of the first comparison circuit and the output signal of the second comparison circuit.

13. a reference voltage generating circuit; a first circuit connected to the reference voltage generating circuit; The reference voltage generating circuit comprises: a resistance circuit electrically connected between a first node and a second node and between the first node and a third node, the resistance circuit having a variable resistor whose resistance value changes in response to a first control signal; a differential amplifier circuit having one of a differential input pair electrically connected to the second node and the other of the differential input pair electrically connected to the third node, the differential amplifier circuit generating a reference voltage at an output node; a current source circuit electrically connected between the second node and a fourth node and between the third node and the fourth node; an adjustment circuit electrically connected to the output node, the adjustment circuit comparing at least two target voltages with the reference voltage to generate the first control signal; a switch circuit that connects the output node to a reference voltage node for outputting the reference voltage in response to a second control signal; the adjustment circuit generates the second control signal in response to a result of comparing the at least two target voltages with the reference voltage; the switch circuit connects the reference voltage node to a ground potential node when disconnecting the output node from the reference voltage node; The first circuit is a semiconductor integrated circuit that operates by receiving the reference voltage from the reference voltage generating circuit.

14. the at least two target voltages include a first target voltage and a second target voltage; 14. The semiconductor integrated circuit according to claim 13, wherein the switch circuit connects the output node to the reference voltage node when the reference voltage is a voltage between the first target voltage and the second target voltage, and disconnects the output node from the reference voltage node when the reference voltage is not a voltage between the first target voltage and the second target voltage.

15. the at least two target voltages include a first target voltage and a second target voltage; The resistor circuit includes: When the reference voltage is lower than the first target voltage and the second target voltage, a resistance value between the first node and the second node and a resistance value between the first node and the third node are increased; maintaining a resistance value between the first node and the second node and a resistance value between the first node and the third node when the reference voltage is a voltage between the first target voltage and the second target voltage; 15. The semiconductor integrated circuit according to claim 13, wherein when the reference voltage is higher than the first target voltage and the second target voltage, a resistance value between the first node and the second node and a resistance value between the first node and the third node are reduced.

16. the at least two target voltages include a first target voltage and a second target voltage; The adjustment circuit a first comparison circuit that compares the reference voltage with the first target voltage; 16. The semiconductor integrated circuit according to claim 13, further comprising a second comparison circuit that compares the reference voltage with the second target voltage.

17. the adjustment circuit includes a resistor series connection circuit that generates the at least two target voltages by resistively dividing a first power supply voltage; 17. The semiconductor integrated circuit according to claim 16, wherein the first comparison circuit and the second comparison circuit operate by receiving a supply of a second power supply voltage from a node independent of the node of the first power supply voltage.

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