Address fault detection in a flash memory system

Abstract

Various examples of memory systems with address fault detection systems are disclosed. The memory system includes a first memory array, a row decoder, and an address fault detection system including a second array, the row decoder decoding row addresses into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array. The second array includes digital bits and / or analog values ​​used to identify address faults.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 281,868, filed November 22, 2021, entitled "Address Fault Detection in a Flash Memory System," and U.S. Patent Application No. 17 / 588,198, filed January 28, 2022, entitled "Address Fault Detection in a Memory System."

[0002] (Technical field) Various mechanisms are disclosed for performing address fault detection in a memory system. [Background technology]

[0003] Nonvolatile memory cells are well known in the art. FIG. 1 shows a prior art nonvolatile split-gate memory cell 10 including five terminals. The memory cell 10 comprises a semiconductor substrate 12 of a first conductivity type, such as P-type. The substrate 12 has a surface in which a first region 14 (also known as a source line SL) of a second conductivity type, such as N-type, is formed. A second region 16 (also known as a drain line) of N-type is also formed in the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL20 is connected to the second region 16. A word line WL22 is positioned above and insulated from a first portion of the channel region 18. A word line 22 has little or no overlap with the second region 16. A floating gate FG24 is above another portion of the channel region 18. The floating gate 24 is insulated therefrom and adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap the first region 14 and provide coupling from the first region 14 to the floating gate 24. A coupling gate CG (also known as a control gate) 26 is above the floating gate 24 and insulated therefrom. An erase gate EG 28 is above the first region 14 and adjacent to and insulated from the floating gate 24 and the coupling gate 26. An upper corner of the floating gate 24 may face toward an inside corner of a T-shaped erase gate 28 to improve erase efficiency. The erase gate 28 is also insulated from the first region 14. The memory cell 10 is more particularly described in U.S. Pat. No. 7,868,375, the disclosure of which is incorporated herein by reference in its entirety.

[0004] One exemplary operation for erasing and programming a prior art nonvolatile memory cell 10 is as follows: The memory cell 10 is erased by the Fowler-Nordheim tunneling mechanism by applying a high voltage to the erase gate 28 and leaving the other terminals equal to 0 volts. Electrons tunnel from the floating gate 24 to the erase gate 28, causing the floating gate 24 to become positively charged and turning on the cell 10 in the read state. The resulting erased state of the cell is known as the "1" state.

[0005] The memory cell 10 is programmed by a source-side hot electron programming mechanism by applying a high voltage to the coupling gate 26, a high voltage to the source line 14, a medium voltage to the erase gate 28, and a programming current to the bit line 20. A portion of the electrons flowing through the gap between the word line 22 and the floating gate 24 gain enough energy to inject into the floating gate 24, causing it to become negatively charged and turning off the cell 10 in the read state. The resulting programmed state of the cell is known as the "0" state.

[0006] The memory cell 10 is read in current sensing mode as follows: a bias voltage is applied to the bit line 20, a bias voltage is applied to the word line 22, a bias voltage is applied to the coupling gate 26, a bias or zero voltage is applied to the erase gate 28, and ground (i.e., zero voltage) is applied to the source line 14. In the erased state, there is cell current flowing from the bit line 20 to the source line 14, and in the programmed state, there is little or no cell current flowing from the bit line 20 to the source line 14. Alternatively, the memory cell 10 can be read in reverse current sensing mode, in which the bit line 20 is grounded and a bias voltage is applied to the source line 24. In this mode, current flows in the reverse direction from the source line 14 to the bit line 20.

[0007] Alternatively, memory cell 10 can be read in a voltage sensing mode as follows: a bias current (to ground) is applied to bit line 20, a bias voltage is applied to word line 22, a bias voltage is applied to coupling gate 26, a bias voltage is applied to erase gate 28, and a bias voltage is applied to source line 14. In the erased state, there is a cell output voltage (significantly above 0V) on bit line 20, and in the programmed state, there is a small or near-zero output voltage on bit line 20. Alternatively, memory cell 10 can be read in a reverse voltage sensing mode, in which bit line 20 is biased to a bias voltage and a bias current (to ground) is applied to source line 14. In this mode, the output voltage of memory cell 10 is on source line 14 instead of bit line 20.

[0008] In the prior art, various combinations of positive or zero voltages are applied to the word lines 22, the coupling gates 26, and the floating gates 24 to perform read, program, and erase operations.

[0009] In response to a read, erase, or program command, logic circuitry 270 (not shown) causes various voltages to be applied to various portions of both selected and unselected memory cells 10 in a timely and least disturbing manner.

[0010] The voltages and currents applied to the selected and unselected memory cells 10 are as follows: As used below, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG). Table 1: Operation of Memory Cell 10 Using Positive Voltages for Reading, Erase, and Programming [Table 1]

[0011] In U.S. Patent No. 9,361,995, issued June 7, 2016 (incorporated by reference), negative voltages may be applied to word lines 22 and / or coupling gates 26 during read, program, and / or erase operations. In this example, voltages and currents are applied to selected and unselected memory cells 10 as follows: Table 2: Operation of Memory Cell 10 Using Negative Voltages for Reading and / or Programming [Table 2]

[0012] In another example of the above-mentioned patent, a negative voltage can be applied to the word line 22 when the memory cell 10 is unselected during read, erase, and program operations, and a negative voltage can be applied to the coupling gate 26 during an erase operation, such that the following voltages are applied: Table 3: Operation of Memory Cell 10 Using Negative Voltage for Erase [Table 3]

[0013] The CGINH signal listed above is an inhibit signal and is applied to the coupling gate 26 of unselected cells that share an erase gate 28 with the selected cell.

[0014] 2 shows an example of another prior art non-volatile split-gate memory cell 210. Similar to memory cell 10, memory cell 210 includes a substrate 12, a first region (source line) 14, a second region 16, a channel region 18, a bit line 20, a word line 22, a floating gate 24, and an erase gate 28. Unlike memory cell 10, memory cell 210 does not include a coupling gate, but only four terminals: the bit line 20, the word line 22, the erase gate 28, and the source line 14. This significantly reduces the complexity of the circuitry, such as decoder circuitry, required to operate an array of such memory cells.

[0015] The erase operation (erase through the erase gate) and read operation are similar to those in Figure 1, except that there is no control gate bias. The programming operation is also performed without a control gate bias, so the program voltage on the source line is higher to compensate for the lack of control gate bias.

[0016] Table 4 shows typical voltage ranges that can be applied to the four terminals to perform read, erase, and program operations. Table 4: Operation of memory cell 210 [Table 4]

[0017] 3 shows an example of another prior art non-volatile split-gate memory cell 310. Similar to memory cell 10, memory cell 310 includes a substrate 12, a first region (source line) 14, a second region 16, a channel region 18, a bit line 20, and a floating gate 24 and an erase gate 28. Unlike memory cell 10, memory cell 310 does not include a coupling gate or an erase gate. Additionally, word line 322 replaces word line 22 and, as shown, has a different physical shape than word line 22.

[0018] One exemplary operation for erasing and programming a prior art nonvolatile memory cell 310 is as follows: The cell 310 is erased through the Fowler-Nordheim tunneling mechanism by applying a high voltage to the word line 322 and 0 volts to the bit line and source line. Electrons tunnel from the floating gate 24 to the word line 322, causing the floating gate 24 to become positively charged and turning on the cell 310 in a read state. The resulting erased state of the cell is known as the "1" state. The cell 310 is programmed through a source-side hot electron programming mechanism by applying a high voltage to the source line 14, a small voltage to the word line 322, and a programming current to the bit line 320. A portion of the electrons flowing through the gap between the word line 322 and the floating gate 24 gain enough energy to inject into the floating gate 24, causing it to become negatively charged and turning off the cell 310 in a read state. The resulting programmed state of the cell is known as the "0" state.

[0019] Exemplary voltages that can be used for read, program, erase, and standby operations in memory cell 310 are shown in Table 5 below. Table 5: Operation of memory cell 310 [Table 5]

[0020] Various techniques for performing address fault detection in memory systems are also known in the prior art. Address faults sometimes occur due to material defects or due to radiation, such as solar flares, which can flip a "1" bit to a "0" bit in an address and vice versa. The result of an address fault is that the decoder may receive the intended address for an operation, but due to the fault, a bit in the decoder may be changed, causing the decoder to activate a word line corresponding to a different address, thereby accessing an incorrect row in the memory array. Another possible result is that the fault causes the decoder to activate a word line corresponding to the intended address and, in addition, a word line corresponding to another address different from the intended address. If not detected or corrected, the address fault will cause an erroneous read or write / program operation.

[0021] 4 illustrates a prior art memory system 400. The prior art memory system 400 includes a row decoder 410 and an array 420. The row decoder 410 receives an address X, where address is an address or portion of an address corresponding to a selected row in the array 420. The row decoder 410 decodes the address X and selects a word line corresponding to the selected row. In this simplified example, four word lines are shown: WL0 (corresponding to address 0000), WL1 (corresponding to address 0001), WL2 (corresponding to address 0010), and WL3 (corresponding to address 0011). The selected word line activates a row of memory cells in the array 420. Thus, for example, if address 0010 is received, the row decoder 410 activates WL2 (corresponding to address 0010).

[0022] Figure 5 shows a prior art memory system 400 similar to Figure 4. However, in this situation, an address fault has occurred. Row decoder 410 receives address 0010, but this time, instead of activating WL2 (corresponding to address 0010), row decoder 410 instead activates WL3 (corresponding to address 0011) due to a fault occurring in row decoder 410. If this fault is not detected or corrected, an erroneous read or program operation will occur.

[0023] Figure 6 shows a prior art memory system 400 similar to Figures 4 and 5. However, in this situation, a different type of address fault has occurred than that of Figure 4. Row decoder 410 receives address 0010, but this time, instead of activating only WL2 (corresponding to address 0010), row decoder 410 activates WL2 and WL3 (corresponding to addresses 0010 and 0011) due to a fault occurring in row decoder 410. If this fault is not detected or corrected, an erroneous read or program operation will occur.

[0024] FIG. 7 illustrates a prior art memory system 700. The memory system 700 includes a row decoder 410 and an array 420 similar to the memory systems of the previous figures. However, word lines such as WL0, WL1, WL2, and WL3 are also coupled to a ROM (read-only memory) 710. The ROM 710 performs a verify function. Each word line is coupled to a row of cells in the ROM 710. When a particular word line is activated, the corresponding row of cells in the ROM 710 is activated. By design, each word line corresponds to a row in the ROM 710, and each row in the ROM 710 stores a different value in its cells. In this example, each row in the ROM 710 stores the same value as the address corresponding to the word line associated with that row. Thus, WL0 corresponds to address 0000, and the value stored in the row in the ROM 710 attached to WL0 is also 0000.

[0025] 8, memory system 700 is again shown. Row decoder 410 receives address 0010, but due to a fault condition, word line WL3 (corresponding to address 0011) is selected instead of word line WL2 (corresponding to address 0010). This causes the incorrect row of memory cells to be selected in array 420. Because word line WL3 is activated, the row in ROM 710 corresponding to word line WL3 is also activated, and ROM 710 outputs the value 0011 stored in that row. Comparator 450 compares the address received by row decoder 410 (i.e., 0010) with the output of ROM 710 (i.e., 0011) and determines that the values ​​do not match. Comparator 450 can then output a value (e.g., "0") that is understood to mean that no match was found, indicating that an address failure has occurred.

[0026] While prior art memory system 700 can detect address faults in which the wrong word line is activated, prior art memory system 700 fails to detect faults in at least some situations in which multiple rows are selected rather than just one. Memory system 700 is again shown in FIG. 9. In this example, an address fault occurs in which the word line for the intended row (i.e., word line WL3 for address 0011) is activated and another word line (i.e., word line WL2 for address 0010) is activated. Word lines WL2 and WL3 are both activated, resulting in the contents of both rows of ROM 710 being output. Logically, ROM 710 is designed so that when two rows are activated, the output is the "OR" of the two rows. Thus, stored values ​​of 0010 and 0011 cause the output to be 0011. Comparator 450 compares the address received by row decoder 410 (i.e., 0011) with the output of ROM 710 (i.e., 0011). In this case, no fault is detected. It can therefore be seen that memory system 700 is not always effective at identifying this type of address fault where two rows are selected instead of one.

[0027] What is needed is an improved address fault detection system that can identify three types of address faults in a memory system: a first situation in which an incorrect word line is asserted; a second situation in which the correct word line is asserted but a second row is also erroneously asserted; and a third situation in which no word line is asserted. Summary of the Invention

[0028] Various examples of memory systems are disclosed that include an address fault detection system, the memory system including a first memory array, a row decoder, and a second array, the row decoder decoding row addresses onto word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array, the second array including digital bits and / or analog values ​​used to identify address faults.

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[0072] [Brief explanation of the drawings]

[0073] [Figure 1] 1 is a cross-sectional view of a prior art non-volatile memory cell to which the present invention is applicable; [Figure 2] 1 is a cross-sectional view of another prior art nonvolatile memory cell to which the present invention is applicable; [Figure 3] 1 is a cross-sectional view of another prior art nonvolatile memory cell to which the present invention is applicable; [Figure 4] 1 illustrates a prior art memory system. [Figure 5] 5 illustrates one type of address fault that can occur in the prior art memory system of FIG. [Figure 6] 5 illustrates another type of address fault that can occur in the prior art memory system of FIG. [Figure 7] 1 illustrates a prior art address fault detection system. [Figure 8] FIG. 7 shows a prior art address fault detection system and one type of address fault. [Figure 9] FIG. 7 shows a prior art address fault detection system and another type of address fault. [Figure 10] FIG. 4 is a layout diagram of a die including non-volatile memory cells of the type shown in FIGS. 1-3 and including an improved address fault detection system. [Figure 11] 1 illustrates an example of an address fault detection system. [Figure 12] 1 illustrates a prior art encoding scheme for verification data for an address. [Figure 13A]10 shows an example of an encoding scheme for verification data for an address. [Figure 13B] 10 illustrates another example of an encoding scheme for verification data for an address. [Figure 14] 10 illustrates another example of an encoding scheme for verification data for an address. [Figure 15] 2 illustrates another example of an address fault detection system. [Figure 16] 1 shows an example of an address failure detection circuit. [Figure 17A] 2 illustrates another example of an address fault detection system. [Figure 17B] 2 illustrates another example of an address fault detection system. [Figure 18] 10 illustrates another example of an encoding scheme for verification data for an address. [Figure 19] 2 illustrates another example of an address fault detection system. [Figure 20] 2 illustrates another example of an address fault detection system. [Figure 21] 2 illustrates another example of an address fault detection system. [Figure 22] 2 illustrates another example of an address fault detection system. [Figure 23] 1 illustrates an encoding scheme for an address fault detection system. [Figure 24A] 1 illustrates an encoding scheme for an address fault detection system. [Figure 24B] 1 illustrates an encoding scheme for an address fault detection system. [Figure 25A] 1 illustrates an encoding scheme for an address fault detection system. [Figure 25B] 1 illustrates an encoding scheme for an address fault detection system. [Figure 26] 1 illustrates an example of an address fault detection system. [Figure 27] 2 illustrates another example of an address fault detection system. [Figure 28] 2 illustrates another example of an address fault detection system. [Figure 29]2 illustrates another example of an address fault detection system. [Figure 30] 2 illustrates another example of an address fault detection system. [Figure 31] 2 illustrates another example of an address fault detection system. [Figure 32] 1 illustrates an example of a sensing circuit for use in an example address fault detection system. [Figure 33] 33 shows an example of a comparator used in the detection circuit of FIG. 32. [Figure 34] 1 illustrates another example of a sensing circuit for use in the example address fault detection system. [Figure 35] 1 illustrates another example of a sensing circuit for use in the example address fault detection system. [Figure 36] 1 shows a layout of a flash memory cell for use in the examples. [Figure 37] 1 shows a layout of a flash memory cell configured as a ROM cell for use in the examples. [Figure 38] 1 illustrates an example row decoder for use with the example address fault detection system. [Figure 39] 1 illustrates an example of an erase gate decoder for use with the example address fault detection system. [Figure 40] 1 illustrates an example of a source line decoder for use with an example address fault detection system. [Figure 41] 1 illustrates an example of a control gate decoder for use with an example address fault detection system. [Figure 42] 1 illustrates an example of high voltage level shifter use with an example address fault detection system. DETAILED DESCRIPTION OF THE INVENTION

[0074] 10 illustrates an example of a die memory system. Die 1000 includes memory arrays 1001, 1002, 1003, and 1004 for storing data, each memory array optionally utilizing memory cells 10 similar to FIG. 1, memory cells 210 similar to FIG. 2, memory cells 310 similar to FIG. 3, or other known types of memory cells; row decoder circuits 1005, 1006, 1007, and 1008 used to access and read or write rows in memory arrays 1001, 1002, 1003, and 1004, respectively; and column decoder circuits 1009, 1010, 1011, and 1012 used to access and read or write columns in memory arrays 1001, 1002, 1003, and 1004, respectively. and 1012, a sense circuit 1013 used to read data from memory arrays 1001 and 1003, a sense circuit 1014 used to read data from memory arrays 1002 and 1004, analog circuitry 1050, a control logic circuit 1051 for providing various control functions such as redundancy and built-in self-test, a high voltage circuit 1052 used to provide positive and negative high voltage supplies to the memory system, a charge pump circuit 1053 which provides increased voltages for erase and program operations of memory arrays 1001, 1002, 1003, and 1004, an interface circuit (ITFC) 1054 which provides interface pins for connecting to other macros on-chip, and high voltage decoder circuits 1018, 1019, 1020, and 1021 for use during read, erase, and program operations, as needed. Die 1000 further comprises address fault detection circuits 1022, 1023, 1024, and 1025, and array fault detection sense circuits 1026, 1027, 1028, and 1029, which are discussed in more detail below with respect to specific embodiments.

[0075] Figure 11 shows an example of a memory system with improved address fault detection capabilities. Memory system 1100 includes a row decoder 1110, an array 1120, a high voltage decoder 1140, a column decoder 1150, and a sense amplifier 1160, each of which corresponds to a component with a similar description in Figure 10. High voltage decoder 1140 provides the high voltages required for erase and program operations in array 1120.

[0076] Memory system 1100 further comprises an address fault detection system 1125, which comprises an address fault detection array 1130, a sense amplifier 1170, and a comparator 1180. Address fault detection array 1130 comprises a ROM array, flash array, or other non-volatile memory array that stores an encoded value for each possible address that may be received by row decoder 1110 and / or column decoder 1150.

[0077] Various encoding schemes are contemplated for generating verification data for each possible address. A prior art encoding scheme is shown in FIG. 12. In this example, a 4-bit address is shown, which is an address that can be received by row decoder 1110 and / or column decoder 1150. For simplicity, the row portion of the address is assumed to be 4 bits ranging from 0000 to 1111. Each of these possible addresses is associated with a word line, which here ranges from WL0 to WL15 (16 different row addresses and word lines). Each word line activates a row in address fault detection array 1130, and each row stores a value equal to the row address associated with that word line. Thus, address 0000 is associated with WL0, which in turn activates a row in address fault detection array 1130 that stores the value 0000.

[0078] 11, under the encoding scheme of FIG. 12, address X is received by row decoder 1110, which then activates word lines that access rows in array 1120 and rows in address fault detection array 1130. Sense amplifiers 1170 sense the value of each column in address fault detection array 1130 for which a word line is activated. The value in each column is the logical "OR" of the values ​​in that column for each activated row in address fault detection array 1130; that is, if multiple rows are activated, the value of the bit in the activated rows for that column is 1 if any of the bits in that column for the activated rows is 1. The value from each column is input to comparator 1180, which compares the received value with address X (or, in this example, the row address portion of address X). As previously mentioned, the output of comparator 1180 identifies a fault in the situation where the wrong row is activated because in that situation the comparator will output a value indicating that the two input values ​​are different. However, this scheme alone is not effective in all situations involving a fault where two rows are activated due to a fault, such as that described above in connection with FIG.

[0079] An improved encoding scheme for improving power savings is shown in FIG. 13A. Those skilled in the art will appreciate that storing and detecting a “1” value in the address fault detection array 1130 consumes more energy than a “0” value. In this encoding scheme, an additional bit is stored, here labeled “PB” (polarity bit). When PB is “0,” the encoded bit directly matches the associated address. When PB is “1,” the encoded bit is an inverted version of the associated address. In this example, whenever more than half of the bits in the address are “1,” a “1” value is used for PB, and the bit is stored inverted. For example, for address “1111,” a value of “0000” is stored in the address fault detection array 1130, and a “1” is stored in the PB bit for that value, indicating that each value is an inverted version of the corresponding address. By following this scheme, the memory system will consume less energy than if it were using the prior art scheme of FIG. 12 because fewer “1”s are stored overall.

[0080] Figure 13B shows another encoding scheme, which is similar to the encoding scheme of Figure 13A, but includes an additional column for multiple row detection (MRD), which can detect situations where multiple rows are erroneously activated, at the expense of additional power consumption compared to the encoding scheme of Figure 13A. The MRD column contains a "1" for each row. A detailed description of multiple row detection is included below.

[0081] Another improved encoding scheme is shown in FIG. 14. Here, each "0" in the address is encoded as "01" in the address fault detection array 1130, and each "1" in the address is encoded as "10" in the address fault detection array 1130. Thus, address "0000" is encoded as "01010101," and address "1111" is encoded as "10101010." Each bit Ax in the address is encoded as EAx and EBx. This means that the encoded value in the address fault detection circuit 1130 contains twice as many bits as the corresponding address. Since any two addresses always differ from each other by at least one bit, the sum of any two encoded values ​​corresponding to two addresses contains an "11" pattern in at least one bit pair (EAx and EBx). Therefore, detecting an "11" pattern in the sensed values ​​of the address fault detection array 1130 indicates that two addresses are activated, which is a fault condition. This is the type of fault condition that the prior art solution of Figure 12 is unable to detect, at least sometimes.

[0082] Figure 15 shows an example of a memory system having an improved address fault detection system for implementing the encoding scheme of Figure 14. Memory system 1500 includes the same components as memory system 1100, except that address fault detection circuit 1525 follows a different design than address fault detection circuit 1125. Here, address fault detection system 1525 includes address fault detection array 1130 and address fault detection circuit 1510. Address fault detection circuit 1510 receives outputs from each column in address fault detection array 1130 that has an activated word line, and the values ​​in any given column that has an activated word line are logically "ORed" to create the output for that column.

[0083] 16 further illustrates an example of address fault detection circuit 1510. In response to activation of a row containing bits EA[x] and EB[x] (where x=the number of encoded address bits in each row of address fault detection circuit 1210), each bit pair EA[x] and EB[x] is input to address fault detection circuit 1510. Address fault detection circuit 1510 includes, for each bit pair EA[x] and EB[x], a set of NAND gates 1601 and 1604, a NOR gate 1602, and an inverter 1603 configured as shown.

[0084] The output A[x] of the address fault detection circuit 1510 for the bit pair EA[x] and EB[x] is "0" if the input is "01" or "10" (where the first bit is EA[x] and the second bit is EB[x]), and "1" otherwise. A "1" indicates a fault condition (because a "11" or "00" pattern should not occur during normal operation based on the encoding scheme shown in FIG. 14, where EA[x] and EB[x] are always different bit values) and indicates that two rows have been activated instead of one, which is the only situation that would cause EAx and EBx to be "11," or that the received address has been changed or no row has been selected, which are the only situations that would cause EAx and EBx to be "00." Thus, the address fault detection system 1525 can detect the fault conditions of two rows being improperly activated or no row being selected.

[0085] 17A shows another example of a memory system having an improved address fault detection system. Memory system 1700, like the previous example, includes row decoder 1110, array 1120, and column decoder 1150. Memory system 1700 further includes address fault detection system 1725, which includes address fault detection array 1730, address fault detection array 1731, and address fault detection circuit 1710.

[0086] The column decoder 1150 is a set of multiplexers, often comprising hierarchical multiplexers. Referring to FIG. 17B, a portion of an example column decoder 1150 is shown. Each column in the array 1120 is coupled to a bit line. Here, four bit lines are shown, labeled BL0-BL3. A first layer of multiplexers selects a pair of adjacent bit lines to be activated. Portions of two such first layer multiplexers, namely, T0 and T1, are shown. A second layer of multiplexers selects a bit line from among a pair of adjacent bit lines. Here, each bit line has its own second layer multiplexer, partially shown, that receives signals labeled V0-V3. Thus, if BL0 is intended to be selected, T0 and V0 are activated; if BL1 is intended to be selected, T0 and V1 are activated; if BL2 is intended to be selected, T1 and V2 are activated; and if BL3 is intended to be selected, T1 and V3 are activated.

[0087] 17A and 17B, it can be seen that the column decoder 1150 is susceptible to faults in the same way as the row decoder 1110. In this example, an address X is input to the column decoder 1150, where address X comprises a row address portion and a column address portion. The column portion of address X includes a bit that indicates which multiplexer is activated (which in turn asserts a bit line). Each activation signal (V0, V1, V2, V3, ...) for the second tier of multiplexers in the column decoder 1150 is coupled to a row in the address fault detection array 1730, and each activation signal for the first tier of multiplexers in the column decoder 1150 is coupled to a row (T0, T1, ...) in the address fault detection array 1731. When a bit line is asserted, a row in address fault detection array 1730 is asserted, a row in address fault detection array 1731 is asserted, and values ​​are output by each of address fault detection array 1730 and address fault detection array 1731. These values ​​can be compared to the column portion of address X by address fault detection circuit 1710. If the values ​​are different, a fault has occurred and the wrong bit line has been asserted.

[0088] An exemplary encoding scheme for use in the example of FIG. 17A is shown in FIG. 18. Here, two hierarchies of multiplexers are used. The first hierarchy comprises multiplexers controlled by values ​​T[0]-[3] with column address bits AY[4] and AY[0]. The second hierarchy comprises multiplexers controlled by values ​​V[0]-V[7] with column address bits AY[2], AY[1], and AY[0]. It should be understood that additional hierarchies are possible. Address fault detection arrays 1330 and 1331 contain encoded values ​​for each multiplexer value, specifically, AYA[2], AYB[2], AYA[1], AYB[1], AYA[0], and AYB[0] for V[0]...V[7], and AYA[4], AYB[4], AYA[3], and AYB[3] for T[0]...T[3]. As in FIG. 14, each "0" in the column component of the address is coded as "01", and each "1" in the address is coded as "10".

[0089] Referring again to Figure 17A, the encoding scheme of Figure 18 can be used. Address fault detection circuit 1710 follows the same design as address fault detection circuit 1510 and outputs a "0" if a "11" or "00" pattern is detected in a bit pair of the encoded value stored in address fault detection array 1310 (because neither the "11" nor the "00" pattern should occur during normal operation based on the encoding scheme shown in Figure 18, where AYA[x] and AYB[x] are always different bit values). Thus, as a result of operation of address fault detection system 1725, memory system 1700 can detect a fault in the column component of an address.

[0090] Figures 19 and 20 show variations on the example already described. As can be seen, the functional blocks of the example can be arranged in different configurations.

[0091] Figure 19 shows a memory system 1900. Memory system 1900 is identical to memory system 1100 of Figure 11, except that a high voltage decoder 1140 is coupled between array 1120 and address fault detection array 1130. The system otherwise operates in the same manner as Figure 11.

[0092] Figure 20 shows a memory system 2000. Memory system 2000 is identical to memory system 1100 of Figure 11, except that a row decoder 1110 is coupled between array 1120 and address fault detection array 1130. The system otherwise operates in the same manner as the previous example.

[0093] 21 shows a memory system 2100, in which a row decoder 2103 operates with two arrays, array 2101 and array 2102. Array 2101 is coupled to a high voltage decoder 2104, a column decoder 2106, and a sense amplifier 2108. Array 2102 is coupled to a high voltage decoder 2105, a column decoder 2107, and a sense amplifier 2109. A single address fault detection system 2125 is used. Address fault detection system 2125 includes an address fault detection array 2110, a sense amplifier 2111, and a comparator 2112. Address fault detection array 2110 is coupled to sense amplifier 2111 and comparator 2112 and can operate similarly to the previous examples.

[0094] Figure 22 shows an example of a memory system having an improved address fault detection system. Memory system 2200 includes a row decoder 2210, an array 2220, a high-voltage decoder 2240, a column decoder 2250, and a sense amplifier 2260, each of which corresponds to components using similar descriptions in Figures 10, 11, 15, 17A, 19, 20, and 21. Memory system 2200 further includes an address fault detection system 2225, which includes an address fault detection array 2230, an analog multi-state sense amplifier 2270, and an analog comparator 2280. Address fault detection array 2230 includes a ROM array, flash array, or other non-volatile memory array that stores an encoded value for each possible address that can be received by row decoder 2210 and / or column decoder 2250.

[0095] Memory system 2200 utilizes the encoding scheme shown in FIG. 23. Address fault detection array 2230 contains an encoded value for each possible address that is identical to the associated address. In this example, a 4-bit address, [A3:A0], is shown, which is an address that can be received by row decoder 2210 and / or column decoder 2250. For simplicity, the row portion of the address is assumed to be 4 bits ranging from 0000 to 1111. Each of these possible addresses is associated with one word line, which here ranges from WL0 to WL15 (16 different row addresses and word lines). Each word line activates a row in address fault detection array 2230, and each row in address fault detection array 2230 stores a value equal to the row address associated with that word line. Thus, address 0000 is associated with WL0, which in turn activates a row in address fault detection array 2230 that stores the value 0000 in bit locations [EA3:EA0].

[0096] In FIG. 22 , multi-state sense amplifier 2270 can sense the analog level of each column corresponding to a three-bit or more (or more) value, e.g., it can sense a two-bit value in a column instead of a one-bit value. The current generated in each column represents the value of that column and is summed for each activated row in address fault detection array 1130; i.e., if multiple rows are activated, the values ​​of the bits in the multiple activated rows of that column are summed together. Multi-state sense amplifier 2270 optionally comprises a multi-state digital sense amplifier, a multi-state analog sense amplifier, or both. In the example illustrated in FIG. 23 , row 6 (ROM code pattern (0110)) and row 7 (code pattern 0111) are unintentionally shorted together, causing an error. Multi-state sense amplifier 2270 shows the output pattern as (0,2,2,1), which is essentially the value of row 6 added to the value of row 7. The failing address can be determined by subtracting the input address bits from the output pattern, here 0221-0110=0111.

[0097] 24A, 24B, 25A, and 25B illustrate additional encoding schemes that can be implemented in the address fault detection system 2225 of FIG.

[0098] FIG. 24A shows an example for encoding a ROM pattern for a 5-bit input address A[4:0]. Cells in the table that are blank should be understood to contain a "0." The encoded word pattern, as shown, is such that the number of "1"s in each codeword is less than half the number of bits in the encoded word. For example, in all 32 rows of encoded words ER[0:9], there are only three "1"s in any word. As shown for encoded word ER[0:9], the encoding pattern is such that there is only one "1" for the first four encoded bits ER[0:3], one "1" for the second four encoded bits ER[4:7], and one "1" for the last two encoded bits ER[8:9].

[0099] In another example shown in Figure 24B, the coded pattern is such that each word contains only one "1" in the first eight coded bits ER[0:7] and only one "1" in the next four bits ER[8-11]. Cells in the table that are blank should be understood to contain a "0". Thus, each of the 32 rows contains exactly two "1"s.

[0100] More generally, for an encoded word similar to Figure 24A or 24B, for K and / or L bit groups of an N-bit encoded word, there is only one "1" in the K and / or L bit groups, where K>2 and / or L>2. For example, for a 12-bit encoded word (N=12), there are three groups of 4 bits (K=4), and each 4-bit group contains only one "1". In another example, different combinations of K and / or L bit groups can be combined with each other, such as an 8-bit group (K=8) with a 4-bit (L=4) group.

[0101] FIG. 25A shows an encoding scheme using digital ROM cells and analog (multistate or multilevel) ROM cells (such as the memory cells of FIG. 1, 2, or 3). The encoded word in this example contains four digital bits ER[0-3] and four analog bits EAR[0:3] (for analog ROM cells, e.g., multistate or multilevel cells, meaning they store multiple levels per cell), corresponding to four digital columns ER[0:3] and four analog columns EAR[0:3]. A multistate sense amplifier 2270 is used on the analog columns to detect whether the cell current is 0.5×Ir or 1.0×Ir. The first four bits ER[0:3] follow the same pattern as FIG. 24A. Cells in the table that are blank should be understood to contain a "0." The first four encoded words have EAR[0] equal to 0.5×Ir (the ROM cell current), and the next four encoded words have EAR[0] equal to 1.0×Ir (the ROM cell current). This property is used to distinguish the first four coded words from the second four coded words. Columns EAR[1], EAR[2], and EAR[3] perform the same function for subsequent groups of eight rows.

[0102] Figure 25B shows an encoding scheme using only analog ROM cells. The encoded word in this example contains six analog ROM cells. A multi-state sense amplifier 2270 is used to read all columns.

[0103] FIG. 26 shows a memory system 2600. The memory system 2600 includes the array 1120, the address fault detection array 1130, and an analog comparator 2610. In this example, the address fault detection array 1130 includes a single column of nonvolatile memory or ROM cells, each storing a "1" value. The output of each of the nonvolatile memory or ROM cells is coupled in parallel to a single bit line. When a word line is asserted, the corresponding cell in that row outputs a "1," generating a current Ir. A typical value for Ir is 20 μA. If more than one word line is asserted (which occurs when a fault causes both an intended and an unintended word line to be asserted), two or more cells in the address fault detection array 1130 output a "1," and the total output current is n*Ir, where n is the number of activated word lines. The output is input to the analog comparator 2610. A reference current is also input to the analog comparator 2610. An exemplary reference current is 1.3Ir. If the input from the address fault detection array 1130 exceeds 1.3Ir, the output of the analog comparator 2610 is "1," indicating that two or more word lines are activated, which indicates a fault condition. If the input from the address fault detection array 1130 is less than 1.3Ir, the output is "0," indicating that one or zero word lines are activated, which indicates a non-fault condition. (It is possible that a zero word line condition is a fault; this example does not detect that condition.) It should be understood that other multiples other than 1.3 may be selected.

[0104] In some examples where the address fault detection array 1130 comprises flash memory cells, a "1" state in the cell is an erased state (having a cell current of Ir) and a "0" state in the cell is a programmed state (having a cell current of approximately 0 μA). In other examples where the address fault detection array 1130 comprises flash memory cells, a "1" in the cell is an erased state and a "0" state in the cell is a state where there is no bit line contact between the cell and the array column.

[0105] FIG. 27 shows memory system 2700. Memory system 2700 is similar to memory system 2600 of FIG. 26, except that memory system 2700 has two columns of cells in address fault detection array 1130. Memory system 2700 includes array 1120, address fault detection array 1130, and analog comparators 2710 and 2720. In this example, address fault detection array 1130 includes two columns of non-volatile memory or ROM cells, each storing a "1" value. The outputs of each of the non-volatile memory or ROM cells in each respective column are coupled in parallel to a single bit line. When a word line is asserted, the corresponding cells in that row each output a "1" corresponding to a current Ir. A typical value for Ir is 20 μA. If two or more word lines are asserted (this is a type of fault condition), two or more pairs of cells in the address fault detection array 1130 output a "1," and the total output current in each column is n*Ir, where n is the number of activated word lines. The outputs are input to analog comparators 2710 and 2720. Reference currents, such as 0.5Ir and 1.1Ir, are also input to analog comparators 2710 and 2720, respectively. If the input from the address fault detection array 1130 exceeds 1.1Ir, the output of comparator 2720 is a "1," indicating two or more word lines are activated, which indicates a fault condition. If the input from the address fault detection array 1130 is greater than 0.5Ir but less than 1.1Ir, the output of comparator 2710 is a "1," and the output of comparator 2720 is a "0," indicating exactly one word line is activated, which indicates a non-fault condition. If the input from the address fault detection array 1130 is less than 0.5Ir, the output of the comparator 2710 will be "0", representing that no word lines are activated, which indicates a fault condition. It will be appreciated that other multiples than 1.1 may be selected to determine whether a particular number of word lines (e.g., three) are in a fault condition.

[0106] Figure 28 shows a memory system 2800. Memory system 2800 includes array 1120, address fault detection array 1130, and analog comparator 2810. Memory system 2800 is the same as memory system 2600 of Figure 26, except that address fault detection array 1130 is controlled by its own control gate signal (CGAFD), erase gate signal (EGAFD), and source line gate signal (SLGAFD). As in Figure 26, array 1120 and address fault detection array 1130 share word lines. Thus, in this example, array 1120 and address fault detection array 1130 share word lines but use separate high-voltage control lines so that address fault detection array 1130 can be erased or programmed independently of array 1120.

[0107] 29 shows a memory system 2900. The memory system 2900 includes an array 1120 and an address fault detection array 1130. The address fault detection array 1130 includes one or more columns of non-volatile memory cells. Because the array 1120 and the address fault detection array 1130 share word lines and high voltage control lines (control gate, erase gate, and source line gate signals), cells in a particular row of the address fault detection array 1130 are erased when cells in that same row are erased in the array 1120. Therefore, appropriate values ​​must be programmed into each erased row in the address fault detection array 1130 by a controller or other device following the erase operation. A particular column in the address fault detection array 1130 contains validation bits encoded for the row portion and / or column of each possible address using the encoding scheme of Figure 12, Figure 13A, Figure 13B, Figure 14, Figure 18, Figure 23, Figure 24A, Figure 24B, Figure 25A, or Figure 25B or another encoding scheme.

[0108] FIG. 30 illustrates memory system 3000. Memory system 3000 includes array 1120 and address fault detection array 1130. Address fault detection array 1130 includes one or more columns of non-volatile memory cells. Memory system 3000 is identical to memory system 2900, except that memory system 3000 includes circuits 3010 and 3020 that pull one or more bit lines to ground during operation. This may be used, for example, to pull local source lines to ground due to multiple cells being locally turned on simultaneously in a ROM (address fault detection array 1130) pattern. It should be understood that memory system 3000 may include one such circuit for each column in address fault detection array 1130. A particular column in the address fault detection array 1130 contains validation bits encoded for the row portion and / or column of each possible address using the encoding scheme of Figure 12, Figure 13A, Figure 13B, Figure 14, Figure 18, Figure 23, Figure 24A, Figure 24B, Figure 25A, or Figure 25B or another encoding scheme.

[0109] FIG. 31 shows memory system 3100. Memory system 3100 includes array 1120, address fault detection array 1130, and analog comparator 3130. Address fault detection array 1130 includes one or more columns of non-volatile memory cells. Memory system 3100 is identical to memory system 3000, except that memory system 3100 includes polarity column 3110 and multi-row detection column 3120. Polarity column 3110 includes a single bit for each row to perform the function of the PB bit in FIG. 13A or 13B. Multi-row detection column 3120 includes a single cell for each row, and each single cell in multi-row detection column 3120 stores a "1." This column implements the functionality described above with respect to FIG. 26. Other columns in the address fault detection array 1130 contain validation bits encoded for the row portion and / or column of each possible address using the encoding scheme of Figure 12, Figure 13A, Figure 13B, Figure 14, Figure 18, Figure 23, Figure 24A, Figure 24B, Figure 25A, or Figure 25B or another encoding scheme.

[0110] In all of the examples described herein, if a fault is indicated, the memory system can take appropriate steps. For example, the memory system can ignore the results of any read operations affected by the fault and repeat the read operations. The memory system can also repeat any write operations affected by the fault. In situations where the array 1120 comprises flash memory cells, the memory system can first erase the relevant portion of the array before repeating the write (program) operation.

[0111] 32 shows an example of a detection circuit. Detection circuit 3200 includes bias transistors 3202 and 3204, current source (reference current) transistors 3201 and 3203, and analog comparator 3205. Bias transistor 3202 connects to a bit line (column) in address fault detection array 1130. Bias transistor 3203 connects to a dummy bit line, balancing capacitor, or reference current generator.

[0112] Different configurations can be selected by selecting appropriate transistors for current source transistors 3201 and 3203. In one configuration, the output of comparator 3205 indicates whether one word line is asserted. For example, current source (reference current) transistor 3201 can be selected or set to generate a current equal to 0.5*IR, where IR is the current drawn by a single cell when the word line is asserted. In this configuration, a "0" output from comparator 3205 indicates that no word lines are asserted, and a "1" output indicates that one word line is asserted.

[0113] In another configuration, the output of comparator 3205 indicates whether two or more word lines are asserted. Current source transistors 3201 and 3203 are selected or set to generate a current equal to 1.1*IR, where IR is the current drawn by a single cell when a word line is asserted. In this configuration, a "0" output from comparator 3205 indicates one or fewer word lines are asserted. The output of "1" is Indicates that two or more word lines are asserted.

[0114] Figure 33 shows additional details of the sensing circuit 3200. Bias switches 3301 and 3302 are also shown.

[0115] FIG. 34 shows another example of a detection circuit. The detection circuit 3400 includes bias transistors 3402 and 3404 and current mirror transistors 3401 and 3403. Transistors 3403 and 3404 constitute an output comparison stage 3410. The bias transistor 3402 is connected to a bit line (column) in the address fault detection array 1130. The bias transistor 3404 is connected to ground or another common potential. The mirror transistor 3403 mirrors the cell current (Ir) from the bit line in the address fault detection array 1130 through the mirror transistor 3401, which is compared to the reference current Iref from the bias transistor 3404. The bias transistor 3404 is modified (e.g., a trimable size) to implement different current comparison ratios (%*Ir). The output (Out) indicates whether a "1" or a "0" is output from the address fault detection array 1130 to that bit line. Specifically, when the cell current Ir > Iref (indicating a relatively high memory cell current and that a "0" is stored in the cell), Out becomes "1", and when the cell current Ir < Iref (indicating a relatively low memory cell current and that a "1" is stored in the cell), Out becomes "0". There may be multiple blocks of the output comparison stage 3410 for implementing different current comparison ratios simultaneously using multiple outputs indicating different current detection ratios. Further, the transistor 3403 may be modified (e.g., a trimable size) to implement different mirror ratios from the transistor 3401 to the transistor 3403.

[0116] FIG. 35 shows another example of a sensing circuit. Sensing circuit 3500 includes bias transistors 3504 and 3502, control transistors 3501 and 3503, and an inverter formed from transistors 3505 and 3506. Bias transistor 3504 connects to a bit line (column) in address fault detection array 1130. Bias transistor 3506 connects to ground. The output at AFD_OUT indicates whether a "1" or a "0" is being output from address fault detection array 1130 on that bit line. Control transistor 3503 serves to shut off the current in transistors 3502 and 3504 once sensing is complete (the inverter output switches from "0" to "1," meaning the gate of transistor 3503 is off). Bias transistor 3502 is used to set a reference current that is compared against the cell current (Ir) coupled to transistor 3504.

[0117] 36 shows the layout of a non-volatile memory cell 3600 that can be used in the address fault detection array 1130. The memory cell 3600 follows the architecture of the memory cell 10 of FIG.

[0118] Figure 37 shows the layout of a ROM cell 3700 that can be used in the address fault detection array 1130. The ROM memory cell 3700 follows the architecture of the memory cell 10 of Figure 1, but is modified to operate as a ROM cell; for example, the CG and EG gates can be removed from cell 3600.

[0119] 38 shows a row decoder 3800 for the eight word lines of a sector in a memory array (such as memory arrays 1001, 1002, 1003, and 1004). Row decoder 3800 could be used for row decoder 1110 in the example above. Row decoder 3800 includes a NAND gate 3801 that receives pre-decoded address signals, shown here as lines XPA, XPB, XPC, and XPD, which select a sector in the memory array. When XPA, XPB, XPC, and XPD are all "high," the output of NAND gate 3801 is "low" and that particular sector is selected.

[0120] The row decoder 3800 further comprises an inverter 3802, a decoder circuit 3810 for generating word line WL0, a decoder circuit 3820 for generating WL7, and additional decoder circuits (not shown) for generating word lines WL1, WL2, WL3, WL4, WL5 and WL6.

[0121] Decoder circuit 3810 includes PMOS transistors 3811, 3812, and 3814, and NMOS transistors 3813 and 3815, configured as shown. Decoder circuit 3810 receives the output of NAND gate 3801, the output of inverter 3802, and pre-decoded address signal XPZB0 from the previous stage of decoding. When this particular sector is selected and XPZB0 is low, WL0 is asserted. When XPZB0 is high, WL0 is not asserted.

[0122] Similarly, decoder circuit 3820 includes PMOS transistors 3821, 3822, and 3824 and NMOS transistors 3823 and 3825 configured as shown. Decoder circuit 3820 receives the output of NAND gate 3801, the output of inverter 3802, and pre-decoded address signal XPZB7. When this particular sector is selected and XPZB7 is low, WL7 is asserted. When XPZB7 is high, WL7 is not asserted.

[0123] It will be understood that the decoder circuits (not shown) for WL1, WL2 and WL3, WL4, WL5 and WL6 follow the same design as decoder circuits 3810 and 3820, except that they receive inputs XPZB1, XPZB2, XPZB3, XPZB4, XPZB5 and XPZB6, respectively, instead of XPZB0 or ​​XPZB7.

[0124] In a situation where this sector is selected and it is desired that WL0 be asserted, the output of NAND gate 3801 will be "low" and the output of the inverter will be "high." PMOS transistor 3811 is turned on, and the node between PMOS transistor 3812 and NMOS transistor 3813 receives the value of XPZB0, which is "low" when word line WL0 is asserted. This turns on PMOS transistor 3814, which pulls WL0 "high" to ZVDD, indicating an asserted state. In this case, XPZB7 is "high," representing that WL7 is not asserted, which pulls the node between PMOS transistor 3822 and NMOS transistor 3823 to the value of XPZB7 (which is "high"), which turns on NMOS transistor 3825, causing WL to be "low," indicating an unasserted state. In this way, when this sector is selected, one of word lines WL0...WL7 can be selected.

[0125] 39 shows an erase gate decoder 3900 as part of the high voltage decoders 1018-1021. The erase gate decoder 3900 includes an NMOS transistor 3901 and PMOS transistors 3902 and 3903, configured as shown. PMOS transistor 3903 is a current limiter with EGHV_BIAS as the current mirror bias level. When the erase gate signal (EG) is asserted, EN_HV_N is set low (e.g., 0V or 1.2V or 2.5V), which turns on PMOS transistor 3902 and turns off NMOS transistor 3901, which causes the erase gate (EG) to go high (i.e., =VEGSUP, e.g., 11.5V). When this erase gate signal (EG) is not asserted, EN_HV_N is set high, which turns off PMOS transistor 3902 and turns on NMOS transistor 3901, which causes the erase gate (EG) to go low (i.e., =VEGSUP_LOW level, e.g., 0V or 1.2V or 2.5V).

[0126] FIG. 40 shows a source line decoder 4000 as part of the high voltage decoders 1018-1021. The source line decoder 4000 comprises NMOS transistors 4001, 4002, 4003, and 4004 configured as shown. NMOS transistor 4001 pulls the source line (SL) low during a read operation in response to an active-high SLRD_EN signal. NMOS transistor 4002 pulls the source line (SL) low during a programming operation in response to an active-high SLP_EN signal. NMOS transistor 4003 performs a monitoring function via output VSLMON; i.e., NMOS transistor 4003 provides a voltage to SL that is detected at output VSLMON. NMOS transistor 4004 provides a voltage to the source line (SL) in response to an active-high EN_HV signal.

[0127] 41 shows a control gate decoder 4100 as part of the high voltage decoders 1018-1021. The control gate decoder 4100 includes an NMOS transistor 4101 and a PMOS transistor 4102. The NMOS transistor 4101 pulls down the control gate signal (CG) in response to an active high signal EN_HV_N. The PMOS transistor 4102 pulls up the control gate signal (CG) in response to an active low signal EN_HV_N.

[0128] 42 shows a latch voltage shifter 4200 as part of the high voltage decoders 1018-1021. In the illustrated configuration, the latch voltage shifter 4200 comprises a low voltage latch inverter 4209, NMOS transistors 4203, 4204, 4207, and 4208, and PMOS transistors 4201, 4202, 4205, and 4206. The latch voltage shifter 4200 receives the signal EN_SEC as an input and outputs EN_HV and EN_HV_N, which have a voltage swing greater than the voltage swing of EN_SEC.

Claims

1. 1. A memory system comprising: a memory array comprising a first set of memory cells arranged in rows and columns; a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, each possible row address corresponding to one word line in the plurality of word lines, each word line coupled to a row of cells in the first set of memory cells; an address fault detection array comprising a second set of memory cells arranged in rows and columns, each possible row address corresponding to an N-bit encoded word, N being an integer, each N-bit encoded word comprising: one or more K-bit groups, and each of the plurality of word lines is coupled to a row of cells in the second set of memory cells that includes an N-bit encoded word, such that the row of cells includes one or more L-bit groups; and an address fault detection array, wherein each of the K-bit groups and the L-bit groups contains only one "1" bit, K and L are integers, K≦N, L≦N, K>2, L>2, and the total number of bits in the one or more K-bit groups and the one or more L-bit groups is N, and the same K-bit group and L-bit group are applied to each of the N-bit encoded words.

2. 2. The memory system of claim 1, further comprising a comparator for identifying an address fault based on the row address and an output of the address fault detection array.

3. 3. The memory system of claim 2, wherein the comparator indicates a fault if no row is selected.

4. 3. The memory system of claim 2, wherein the comparator indicates a fault if more than one row of the memory array is selected.

5. The memory system of claim 2 , wherein the comparators include a digital bit comparator and an analog comparator.

6. 2. The memory system of claim 1, wherein each cell in said first set of memory cells is a split-gate flash memory cell.

7. 2. The memory system of claim 1, wherein each cell in said second set of memory cells is a split-gate flash memory cell.

8. 2. The memory system of claim 1, wherein each cell in said second set of memory cells is a read-only memory cell.

9. 2. The memory system of claim 1, wherein each cell in said first set of memory cells is an analog memory cell.

10. 10. The memory system of claim 1 further comprising a multi-state sense amplifier for sensing said memory array.

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