Structures with conductive features and methods of forming same - Patents.com

Abstract

An element is disclosed. The element includes a non-conductive structure with a non-conductive bonding surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back surface opposite the bonding surface. The average size of the grains at the bonding surface is smaller than the average size of the grains adjacent the bottom side of the cavity. The conductive pad may have a crystal structure with the grains oriented along 111 crystal planes. The element may be bonded to another element to form a bonded structure. The element and the other element may be bonded directly to each other without an intervening adhesive.

Description

[Technical Field]

[0001] The technical field relates to structures with features such as surface contact pads, and methods for forming such structures, as well as structures with conductive features having engineered metallic grains, and methods for forming such structures and direct bonding such features to conductive features on other devices.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 132,334, filed December 30, 2020, entitled "STRUCTURE WITH CONDUCTIVE FEATURE AND METHOD OF FORMING SAME," which is incorporated herein by reference in its entirety. [Background technology]

[0003] Semiconductor devices, such as integrated device dies or chips, may be mounted or stacked on other devices. For example, a semiconductor device may be mounted on a carrier, such as a package substrate, an interposer, a reconfigured wafer, or a device. As another example, a semiconductor device may be stacked on top of another semiconductor device, e.g., a first integrated device die may be stacked on top of a second integrated device die. Each of the semiconductor devices may have conductive pads that mechanically and electrically connect the semiconductor devices to one another. Improved methods of forming the conductive pads continue to be needed. Summary of the Invention

[0004] According to one aspect of the invention, there is provided a device comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; An element is provided having a conductive pad disposed within a cavity, the conductive pad having a joining surface and a back surface located opposite the joining surface, and wherein the average size of the grains of the conductive pad at the joining surface is smaller than the average thickness of the grains located adjacent a bottom side of the cavity.

[0005] According to another aspect of the present invention, there is provided a bonded structure, comprising: a first element, the first element comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; a conductive pad disposed within the cavity, the conductive pad having a joining surface and a back surface opposite the joining surface, the average size of the grains of the conductive pad at the joining surface being at least 20% greater than the average thickness of the grains located adjacent a bottom side of the cavity; a second element having a second conductive pad; A bonded structure is provided, characterized in that the conductive pad of the first element and the second conductive pad of the second element are bonded directly to one another along a bond interface without an intervening adhesive.

[0006] According to another aspect of the invention, there is provided a method of forming a device, comprising the steps of: providing a non-conductive structure having a first surface and a second surface opposite the first surface; forming a cavity in the non-conductive structure; providing a conductive material within the cavity and on a portion of the first surface of the non-conductive structure, the conductive material having a lower surface facing a bottom side of the cavity and an upper surface opposite the lower surface; cold working the upper surface of the conductive material to modify the crystalline structure of the conductive material, the cold working being performed at about -196°C to 50°C; A method is provided that includes removing at least a portion of the conductive material to form a conductive pad with a conductive bonding surface.

[0007] According to another aspect of the present invention, there is provided a method of forming a bonded structure, comprising the step of bonding the element to a second element having a second non-conductive structure and a second conductive pad.

[0008] According to another aspect of the invention, there is provided a device comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; A device is provided having a conductive pad disposed within the cavity, the conductive pad having a bonding surface and a back surface opposite the bonding surface, the conductive pad having a lower percentage of grains with 111 crystal planes at the bonding surface compared to adjacent the bottom side.

[0009] According to another aspect of the invention, there is provided a device comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; a conductive feature disposed within the cavity, the conductive feature having a joining surface and a back surface opposite the joining surface; An element is provided, characterized in that the average grain size within a portion of the conductive feature located near the bonding surface is less than 200 nanometers (nm).

[0010] According to another aspect of the present invention, there is provided a bonded structure, comprising: a first element, the first element comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; a conductive pad disposed within the cavity, the conductive pad having a joining surface and a back surface opposite the joining surface, the conductive pad including a crystalline structure in which crystal grains are oriented along a 111 crystallographic plane, and an average crystal grain size of the conductive pad located at the joining surface being larger than an average crystal grain size of the conductive pad located at the back surface; a second element having a second conductive pad; A bonded structure is provided in which the bonding surfaces of the first element and the second element are bonded directly to one another along a bonding interface without an intervening adhesive.

[0011] According to another aspect of the invention, there is provided a method of forming a device, comprising the steps of: providing a non-conductive structure having a first surface and a second surface opposite the first surface; forming a cavity in a first surface of the non-conductive structure; providing a conductive material within the cavity and over a first surface of the non-conductive structure; increasing the grain size of the conductive material by thermal annealing; forming lattice defects in the annealed conductive material; forming a planar joining surface having a non-conductive joining surface and a conductive joining surface; A method is provided in which the conductive interface is characterized by having lattice defects.

[0012] According to another aspect of the present invention, there is provided a bonded structure, comprising: a first element, the first element comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; a conductive pad disposed within the cavity, the conductive pad having a joining surface and a back surface opposite the joining surface, the conductive pad having a longitudinal columnar grain structure generally oriented parallel to the non-conductive joining surface; a second element having a second conductive pad; A bonded structure is provided, characterized in that the conductive pad of the first element and the second conductive pad of the second element are bonded directly to one another along a bond interface without an intervening adhesive.

[0013] According to another aspect of the present invention, there is provided a bonded structure, comprising: a first element, the first element comprising: a plate-like conductive structure embedded within a surface of a non-conductive material having a non-conductive joining surface, the conductive structure having a longitudinal columnar grain structure generally oriented parallel to the non-conductive joining surface; a second element having a flat bonding surface; A bonded structure is provided in which a bonding surface of a first element and a bonding surface of a second element are directly bonded to one another along a bonding interface without an intervening adhesive.

[0014] According to another aspect of the present invention, there is provided a bonded structure, comprising: a first element including a first conductive feature and a first non-conductive region; a second element including a second conductive feature bonded directly to the first conductive feature without an intervening adhesive and a second non-conductive region bonded to the first non-conductive region; A bonded structure is provided, wherein the first and second conductive features bonded to each other each include a grain having a length along a bond interface between the first element and the second element and a thickness perpendicular to the bond interface, and the grain has an average length that is at least 1.5 times the average thickness of the grain.

[0015] Specific embodiments will now be described with reference to the following drawings, which are provided by way of example and not by way of limitation of the invention. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic cross-sectional view of an element according to an embodiment. [Figures 2A-2D]FIG. 2A illustrates one step in a manufacturing process for forming the device shown in FIG. 1 according to one embodiment, and FIGS. 2B-2D illustrate other steps in the manufacturing process for forming the device shown in FIG. [Figures 2E-2F] 2E-2F illustrate different steps in the manufacturing process for forming the device shown in FIG. [Figure 2G-2I] 2G illustrates another step in the manufacturing process for forming the element shown in FIG. 1, FIG. 2H is a schematic cross-sectional view of the element in contact with another element, and FIG. 2I is a schematic cross-sectional view of the joining structure. [Figures 3A-3D] FIG. 3A illustrates a step in another manufacturing process for forming the device shown in FIG. 1 according to one embodiment, and FIGS. 3B-3D illustrate other steps in the manufacturing process for forming the device shown in FIG. 1. [Figure 3E-3G] 3E-3G illustrate different steps in the manufacturing process for forming the device shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present disclosure relates to methods for engineering metal grain structures for conductive pads in microelectronic devices. Such engineering may be advantageous for direct metal bonding, direct metal hybrid bonding. For example, two or more semiconductor devices (integrated device dies, wafers, etc.) may be stacked or bonded together to form a bonded structure. The conductive contact pads of one device may be electrically connected to corresponding conductive contact pads of another device. Any suitable number of devices may be stacked within the bonded structure. The methods and bond pad structures described herein may also be useful in other technological contexts.

[0018] In some embodiments, the elements are directly bonded to one another without adhesive. In various embodiments, a non-conductive (e.g., semiconductor or inorganic dielectric) material of a first element can be directly bonded to a corresponding non-conductive (e.g., semiconductor or inorganic dielectric) or dielectric field region of a second element without adhesive. In various embodiments, a conductive region (e.g., metal pad) of a first element can be directly bonded to a corresponding conductive region (e.g., metal pad) of a second element without adhesive. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of a first element can be directly bonded to a corresponding non-conductive material of a second element using adhesiveless bonding techniques, such as the direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of which are incorporated herein by reference for all purposes. In other applications, the bonded structure may directly bond the non-conductive material of a first element to the conductive material of a second element, such that the conductive material of the first element conforms intimately to the non-conductive material of the second element. Suitable dielectrics for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride; alternatively, such dielectrics may contain carbon, such as silicon carbide, silicon oxycarbonitride, silicon carbonitride, or diamond-like carbon. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content. Additional examples of hybrid direct bonding can be found throughout U.S. Pat. No. 11,056,390, which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0019] In various embodiments, direct bonds can be formed without an intervening adhesive. For example, the semiconductor or non-conductive bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma agent to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after or during activation (e.g., during a plasma process). Without being bound by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces, and the termination process can provide one or more additional chemical species at the bonding surfaces that improve the bonding energy during direct bonding. In some embodiments, activation and termination are performed in the same step, for example, using a plasma or wet etchant to both activate and terminate the surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the terminating chemical species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, one or more fluorine peaks can be generated near the layers and / or bonding interface. Thus, in a direct bond structure, the bond interface between the two dielectrics can comprise a very smooth interface with a high nitrogen content and / or fluorine peak at the bond surface. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0020] In various embodiments, conductive contact pads of a first component may also be directly bonded to corresponding conductive contact pads of a second component. For example, direct hybrid bonding techniques can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently directly bonded dielectric-to-dielectric surfaces that have been pretreated as described above. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonds and non-conductor-to-non-conductor hybrid bonds can be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference in its entirety for all purposes. The bond structures described herein may also be useful for direct metal bonding or other bonding techniques without non-conductive region bonding.

[0021] In some embodiments, inorganic dielectric bonding interfaces can be pretreated and directly bonded to one another without an intervening adhesive, as described above. Conductive contact pads (which may be surrounded by non-conductive field regions) can also be directly bonded to one another without an intervening adhesive. In some embodiments, each contact pad can be recessed below the outer surface (e.g., top surface) of the dielectric field region or non-conductive bonding region by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, and can be recessed by a range of 2 nm to 20 nm or a range of 4 nm to 10 nm. The non-conductive bonding regions can be directly bonded to one another without an adhesive, in some embodiments, at room temperature, after which the bonded structure can be annealed. During annealing, the contact pads can thermally expand relative to the non-conductive bonding region and contact each other, thereby forming a direct metal-to-metal bond. Beneficially, high density pads can be connected across a direct bond interface (e.g., at small or fine pitch for regular arrays) through the use of Direct Bond Interconnect (DBI®) hybrid bonding technology, commercially available from Xperi, Inc. of San Jose, Calif. In various embodiments, the contact pads may comprise copper or a copper alloy, although other suitable metals may be suitable.

[0022] Thus, in a direct bonding process, a first element can be directly bonded to a second element without an intervening adhesive. In some configurations, the first element can comprise a singulated element, such as a singulated integrated device die. In other configurations, the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can comprise a singulated element, such as a singulated integrated device die. In other configurations, the second element can comprise a carrier or substrate (e.g., a wafer).

[0023] As described herein, a first element and a second element can be directly bonded to each other without adhesive, which differs from a cladding process. Thus, the first and second elements may be comprised of non-cladded elements. Furthermore, unlike cladding layers, a directly bonded structure may include defect regions along the bond interface where nanovoids exist. Nanovoids may form due to activation of the bonding surfaces (e.g., exposure to plasma). As described above, the bond interface may include a concentration of material resulting from activation. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bond interface. In some embodiments, the bond interface may be comprised of a nitrogen-terminated inorganic non-conductive material, such as nitrogen-terminated silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride. Thus, the surface of the bonding layer may be comprised of silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, with the level of nitrogen present at the bonding interface representing the nitrogen termination of at least one of the elements prior to direct bonding. In some embodiments, nitrogen and nitrogen-related components may be absent at the bonding interface. As described herein, the direct bond comprises a covalent bond, which is stronger than a van der Waals bond. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness.

[0024] In various embodiments, the metal-to-metal joint between the contact pads may be bonded such that the copper grains grow into each other across the joint interface. In some embodiments, the copper may have grains oriented vertically along the 111 crystal plane to enhance copper diffusion across the joint interface. In some embodiments, the misorientation of the 111 crystal planes in the conductive material may be within ±30° of the normal as viewed from the surface of the conductive material. In some embodiments, the crystal misorientation may be within ±20° or within ±15° of the normal. The joint interface may extend substantially all the way to at least a portion of the bonding contact pad, such that there is substantially no gap between the non-conductive bonding regions at or near the bonding contact pad. In some embodiments, a barrier layer may be provided under the contact pad (which may comprise, for example, copper). However, in other embodiments, there may not be a barrier layer underneath the contact pads, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, the entire contents of which are incorporated by reference herein for all purposes.

[0025] The annealing temperature and duration for forming a direct metal-to-metal bond can affect the thermal budget consumption by the anneal. It may be desirable to reduce the annealing temperature and / or shorten the annealing time to minimize the thermal (energy) budget consumption. <111> Surface diffusion of atoms along 111 crystal planes can be three to four orders of magnitude faster than along 100 or 110 crystal planes. Additionally, metals (e.g., Cu) with grains oriented along 111 crystal planes can have higher surface mobility compared to conventional back-end-of-line (BEOL) copper. Furthermore, low-temperature direct metal-to-metal bonding can be achieved due to creep on the 111 crystal planes of Cu. Therefore, having 111 crystal planes at the bonding surface can be advantageous to shorten the annealing time and / or reduce the annealing temperature for direct bonding (e.g., direct hybrid bonding). The benefits of having 111 crystal planes can be particularly pronounced at low temperatures, since metal surface diffusion (e.g., Cu surface diffusion) also slows down as the annealing temperature decreases. Therefore, in various embodiments disclosed herein, the crystal structure can have grains oriented perpendicularly along 111 crystal planes to promote metal diffusion (e.g., copper diffusion) during direct bonding.

[0026] The metal layer may be formed by a process selected to plate a copper (Cu) layer having Cu in a 111 crystal orientation at or near the bonding surface of a conductive layer or bond pad. The Cu layer may be deposited from a non-superfilling or superfilling electroplating bath with a plating chemistry selected to optimize the effective filling of voids or buried cavities (e.g., vias, trenches) in the substrate, rather than to optimize the direct metal-to-metal bonding that occurs during, for example, direct hybrid bonding. Subsequent metal processing, as described below, can facilitate subsequent bonding, so that any desired plating chemistry can be used to optimize other considerations, such as the filling mentioned above. The microstructure (e.g., grain size or size) of the deposited or coated metal layer is typically less than 50 nm, and such microstructure must be stabilized, for example, by an annealing step (typically at temperatures below 300°C). After the plated metal stabilization step, the coated metal may be planarized by CMP to remove undesired material (excess plated metal, barrier layer, and / or portions of the non-conductive layer) and form a planar bond surface. The bond surface may include planar non-conductive portions surrounding well-dispersed planar conductive portions.

[0027] Various embodiments disclosed herein relate to forming devices having conductive pads with direct bond surfaces having a 111 crystal plane orientation regardless of plating chemistry. The direct bond surfaces may have a cold-worked surface containing nanocrystalline grains that are independent of the metallization method, such as electroplating, electroless, or physical vapor deposition (PVD), among others. Thus, various embodiments disclosed herein provide significant flexibility in designing plating processes and / or more efficient conductive material fill compared to conventional plating processes that are tuned to form a 111 crystal plane orientation. In some embodiments, conductive pads (e.g., plated Cu in damascene cavities) may be treated by a cold-working process at room temperature and / or below room temperature. In some embodiments, the surface of a coated conductive material, including the conductive pad, may be treated by peening, which impacts the conductive pad with a stream of particles, such as metal, glass, or ceramic. In some embodiments, the cold-working process may include, for example, cold-rolling the coated conductive material to reduce the grain size of the coated conductive material. A lubricating fluid with and / or without colloidal particles may be used in the cold rolling process. In some embodiments, the grain boundaries of the deformed grains in the conductive pad may include subgrains, high-angle grain boundaries, twins, massive dislocations, and / or dislocation networks. In some embodiments, nano-spaced nanotwinned grains and / or nanolaminates may be formed in the conductive pad.

[0028] In some embodiments, texture and grain size gradients within the conductive pad can be created by the cold working process. For example, relatively small grains and / or a low percentage of 111-oriented crystals can be achieved near the surface of the pad compared to deeper within the pad. A cold-worked coated conductive material or layer undergoes plastic deformation. A large portion of the mechanical energy expended in the deformation process may be converted to heat, while the remainder may be stored in the deformed structure, thereby creating lattice defects. Lattice defects may include fine grains, high-angle grain boundaries, mechanical twins and / or nanotwins, dislocations, vacancies, etc. In the deformed conductive layer (pad and trace), a significant contributor to the stored energy of the cold working process can be the energy associated with the creation of additional lattice defects relative to those in the undeformed portion of the annealed conductive layer. The deformation process can result in residual compressive stresses in the conductive pad. These residual compressive stresses may vary from the surface of the pad to the bottom of the pad. Depending on the energy imparted to the metal during the cold working process, the upper portion of the pad may have higher residual stresses compared to the lower portion of the pad.

[0029] Various embodiments disclosed herein enable relatively low-temperature annealing for direct metal-to-metal bonding independent of electroplating baths, electroplating processes, and / or other conductive layer coating or formation methods. In some embodiments, stored energy in a portion of the cold-worked conductive layer can contribute to enabling relatively low-temperature annealing. In some embodiments, the annealing temperature for bonding can be, for example, about 50°C to about 250°C, about 100°C to about 200°C, 125°C to about 170°C, or about 50°C to about 180°C. Depending on the annealing temperature(s), the annealing time can range from 45 minutes to 180 minutes. The annealing time may increase if the annealing temperature is lower. However, the embodiments disclosed herein can still consume a lower thermal (energy) budget relative to conventional structures, allowing the annealing duration to remain short despite the lower annealing temperature.

[0030] FIG. 1 is a schematic cross-sectional view of one embodiment of a device 1. Device 1 may include a semiconductor device before singulation, such as a semiconductor substrate or wafer, or a semiconductor device after singulation, such as an interposer, electronic component, integrated circuit (IC) die, or chip. Device 1 may include a substrate 10 (e.g., a bulk semiconductor material), a non-conductive layer (e.g., a dielectric layer 12, such as silicon oxide or other low-k material) on substrate 10, conductive pads 14 disposed within cavities 16 formed in dielectric layer 12, and a barrier layer 18 disposed between dielectric layer 12 and conductive pads 14. While a single dielectric layer 12 is shown for simplicity, those skilled in the art will understand that dielectric layer 12 and conductive pads 14 may comprise part of a back-end-of-line (BEOL) structure or a redistribution layer (RDL) structure on a back-end-of-line (BEOL) structure, which typically includes vias and trenches or traces (not shown). In some embodiments, the conductive pads or vias or traces may be made of a copper alloy, a nickel alloy, a gold alloy, or other metal alloy.

[0031] In some embodiments, the substrate 10 may comprise a semiconductor substrate or wafer. In some embodiments, the substrate 10 may comprise a glass substrate, a dielectric substrate, or a ceramic substrate.

[0032] The dielectric layer 12 may be comprised of a relatively low-k (e.g., k<4) dielectric. In some embodiments, the dielectric layer 12 may be comprised of an inorganic material. The dielectric layer 12 may have a lower surface 12a facing the substrate 10 and an upper surface 12b opposite the lower surface 12a. The upper surface 12b may constitute a bonding surface of the dielectric layer 12, and thus may include a high concentration of nitrogen and / or fluorine compared to the bulk material of the dielectric layer, for example, as described above. In some embodiments, the bonding surface at the upper surface may be formed by a barrier or etch stop layer (not shown) on the low-k dielectric layer 12. The dielectric layer 12 may have a cavity 16 extending at least partially through the thickness of the dielectric layer 12 from the upper surface 12b. The cavity 16 has a bottom 20 and sidewalls 22.

[0033] The conductive pad 14 has a lower surface 14a facing the bottom side 20 of the cavity and an upper surface 14b opposite the lower surface 14a. The upper surface 14b may form a bonding surface of the conductive pad 14. The conductive pad 14 may be comprised of a metal, such as copper (Cu). The conductive pad 14 may be comprised of copper with grains oriented along the 111 crystallographic plane. In some embodiments, the conductive pad 14 may be comprised of a cold worked or mechanically or optically deformed pad.

[0034] The size (grain size) of the grains 24 of the component 1 may vary in the deformed conductive pad 14. As used herein, the size of the grains 24 may refer to the largest dimension of the grains 24. In some embodiments, the grains 24 located at or near the upper surface 14b may be smaller on average than the grains 24 located at or near the lower surface 14a. In some embodiments, the grains may have a small grain region 26 located at or near the upper surface 14b of the conductive pad 14 and a large grain region 28 located at or near the lower surface 14a of the conductive pad 14. In some embodiments, the small grain region 26 may be arbitrarily selected to be a region of the conductive pad 14 extending from the upper surface 14b up to 1000 nm into the conductive pad 14 for shallow conductive pads 14, or up to 3000 nm for deeper conductive pads 14 (e.g., pads greater than 5000 nm thick), with the objective of comparing grain sizes above this level with grain sizes below this level. In some embodiments, the small grain region 26 located at or near the upper surface 14b may have an average grain size of about 10 nanometers (nm) to 200 nm, or about 30 nm to 200 nm. In some embodiments, the large grain region 28 located at or near the lower surface 14a may have an average grain size of about 0.5 microns (μm) to 5 μm. In some embodiments, the average grain size may vary depending on the width and depth of the conductive pad 14. In some embodiments, the average size of the grains 24 located at or near the lower surface 14 a may be at least five times the average size of the grains 24 located at or near the upper surface 14 b. For example, the average size of the grains 24 located at or near the lower surface 14 a of the deformed conductive pad 14 may be about 3-100 times, 10-100 times, 20-100 times, 30-100 times, 40-100 times, or 40-100 times the average size of the grains 24 located at or near the upper surface 14 b of the deformed conductive pad 14.In some embodiments, the grains 24 may have a gradient grain size across the depth of the conductive pad 14 as a result of a gradient of lattice defects from the upper surface 14b to the lower surface 14a. In some embodiments, the conductive pad 14 may be significantly harder at or near the upper surface 14b than at or near the lower surface 14a. In some embodiments, the average size of three consecutive grains 24 located at or near the lower surface 14a of the deformed conductive pad 14 may be about 3-100 times, 10-100 times, 20-100 times, 30-100 times, 40-100 times, or 40-100 times the average size of three consecutive grains 24 located at or near the upper surface 14b of the deformed conductive pad 14. Similarly, the average grain size of two consecutively adjacent grains 24 located at or near the upper surface 14b of the deformed conductive pad 14 may be at least half the average grain size of two consecutively adjacent grains in the interconnect layer located beneath the barrier layer 18 (not shown) of the deformed conductive pad 14. In some embodiments, at a high determined degree of deformation of the coated conductive layer, the grain sizes of three consecutively adjacent grains 24 located near the upper surface 14b of the conductive pad 14 and three consecutively adjacent grains 34 located near the lower surface 14a of the conductive pad 14 may be approximately the same and at least one-third the grain size at the corresponding locations of the undeformed conductive pad 14.

[0035] To release stored energy and promote grain recovery and growth in the deformed conductive pad 14 (deformed due to compressive stresses caused by mechanical or optical peening) during thermal annealing after cold working, such as during bonding of the conductive pad 14 to another conductive pad of another device, the recovered grains in the upper surface 14b region of the conductive pad 14 should be larger than the recovered grains in the underlying lower surface 14a region (see FIG. 2I). The grain size at the upper surface 14b should be larger than the grain size at the lower surface 14a to create a reverse gradient from the gradient immediately after the cold working process. Similarly, the grain size at the upper surface 14b should be larger than the grain size of an interconnect layer (not shown) underlying the barrier layer 18 of the deformed conductive pad 14.

[0036] In some embodiments, the upper surface 14b of the conductive pad 14 may be recessed below the upper surface 12b of the dielectric layer 12. For example, the upper surface 14b of the conductive pad 14 may be recessed below the upper surface 12b of the dielectric layer 12 by about 30 nm or less, about 20 nm or less, about 15 nm or less, or about 10 nm or less. For example, the upper surface 14b of the conductive pad 14 may be recessed below the upper surface 12b of the dielectric layer 12 by a range of 2 nm to 20 nm, or a range of 4 nm to 15 nm.

[0037] The barrier layer 18 may be, for example, a dielectric barrier layer such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, or the like. The barrier layer 18 may be a conductive barrier, a metal nitride (e.g., Ta, TiN, TaN, WN, and various combinations thereof). For example, the conductive barrier layer 18 may be deposited on the bottom side 20 and sidewalls 22 of the cavity 16. The non-conductive barrier layer 18 may be formed on the sidewalls 22 but not at the bottom side 20 of the cavity 16. In some embodiments, the non-conductive barrier layer 18 may be discontinuous on the bottom side 20 of the cavity 16. The barrier layer 18 may be interposed between the dielectric layer 12 and the conductive pad 14.

[0038] Figures 2A-2G illustrate initial stages in a manufacturing process for forming the device 1 shown in Figure 1 according to one embodiment. Figure 2H illustrates the device 1 in contact with another device (a second device 2), and Figure 21 illustrates a bonded structure 3 including the device 1 and the second device 2.

[0039] In FIG. 2A , a dielectric layer 12 is provided on a substrate 10. A cavity 16 is selectively formed in the dielectric layer 12, including an upper surface 12b. The cavity 16, shown with a bottom surface 20 and sidewall surfaces 22, may extend through at least a portion of the thickness of the dielectric layer 12. The cavity 16 may be formed by masking and etching or drilling. The cavity 16 may comprise a damascene cavity formed in a damascene process. The cavity 16 may be of the through substrate cavity (TSC) type, such as a through silicon via (TSV) type or a through glass via (TGV) type. In some embodiments, the cavity 16 may be formed to be in contact with a buried interconnect structure, such as a BEOL or RDL layer (not shown).

[0040] 2B, a barrier layer 18 may be provided on the upper surface 12b of the dielectric layer, the sidewalls 22 of the cavity 16, and the bottom surface 20 of the cavity 16. As mentioned above, the barrier layer 18 may be a non-conductive material formed on the upper surface 12b of the dielectric layer and the sidewalls 22 of the cavity 16, but not at the bottom surface 20 of the cavity 16. A seed layer 30 may be provided on these same surfaces and on the barrier layer 18. In some embodiments, one or more conductive vias or one or more traces (not shown) in contact with the barrier layer 18 may be provided below the bottom surface 20 of the cavity 16.

[0041] In FIG. 2C , a conductive material 32 may be disposed within the cavity 16 and on the upper surface 12b of the dielectric layer 12. In some embodiments, the conductive material may comprise a metal, such as copper (Cu), and may be disposed by, for example, plating or other known methods. In some embodiments, the conductive material 32 may comprise a copper alloy, a nickel alloy, a gold alloy, or other metal alloy. The conductive material 32 may have a lower surface 32a and an upper surface 32b. Advantageously, plating and additive processes may be optimized to effectively fill the cavity 16, which may be merely one of many vias and / or trenches across the substrate and may have a high aspect ratio. In some embodiments, the conductive material 32 may comprise an electroplated coating formed at or below room temperature. Room temperature may be defined, for example, as a temperature ranging from 20° C. to 35° C. The plated metal of conductive material 32 may have a grain size in the as-plated state ranging from 10 nm to 100 nm, or from 30 nm to 100 nm.

[0042] In FIG. 2D , the conductive material 32 may be annealed between room temperature and 250° C. In some embodiments, some electroplated copper films containing low interstitial (interstitial) and non-interstitial impurities may form large grains at room temperature due to a grain growth phenomenon at room temperature. The annealing process may stabilize the microstructure (e.g., grain size) of the grains 24 in the conductive material 32. The annealing process may form relatively large grains 24 in the conductive material 32. For relatively large pads exceeding 5 microns across, the grain size of the conductive material after annealing may range from approximately 0.3 microns to 3 microns. For conductive traces with widths less than 1 micron, the grain structure may exhibit a bamboo-shaped grain structure extending along the trace axis.

[0043] In FIG. 2E, the conductive material 32 may be subjected to a cold-working process. The cold-working process may be performed at room temperature and / or below room temperature. For example, the substrate temperature during the cold-working process may range from liquid nitrogen temperature, −196° C. (77 K), to about 30° C. or 50° C., or from 0° C. to about 25° C., and in one example, may be at about ambient cleanroom temperature. The conductive material 32 may be processed from the upper surface 32 b. In some embodiments, the conductive material 32 may be strain-hardened. For example, the conductive material 32 may be shot-peened, cold-rolled, or laser-peened to induce plastic deformation in the conductive material 32. As discussed above, shot-peening may involve bombardment with particles, such as metal, sand, glass, or ceramic. For example, mechanical peening may involve impacting the surface (e.g., upper surface 32b) of conductive material 32 with ceramic or steel shot. For example, the shot diameter may range from 0.1 mm to 2 mm, the shot velocity may be 1-5 meters per second, and the impact time may be 30-180 seconds. In some embodiments, substrate 10 may rotate at 10-60 rpm, preferably 15-45 rpm, during the peening operation. In some embodiments, element 1 may be stationary during the peening operation. Plastic deformation may induce compressive residual stresses in grains 24 at or below the surface of conductive material 32 and / or tensile stresses within or in the bulk of conductive material 32. After the cold working process, conductive material 32 may have stored energy from the compressive residual stresses. In some embodiments, the portion of the conductive material 32 located at or near the upper surface 32 b may have a higher stored energy from the cold working process than the lower surface 32 a. In some embodiments, the conductive material 32 may be uniformly deformed from the top surface 32 b to the bottom surface 32 a, including the portion of the conductive material 32 at the bottom of the cavity 16 located adjacent the barrier layer 18.The conductive material 32 may be severely deformed, making it difficult to distinguish individual metal grains, due to numerous stacking faults, such as mechanical twins, slips, vacancies, and / or dislocation networks, induced by the deformation process. As a result of structural defects and extremely small grain sizes (e.g., 5 nm to 30 nm), it may be difficult to index the individual grains 24 with respect to their orientation. Regardless of how one or more compressive forces are applied to the conductive material 32, the applied forces will degrade the substrate 1. Degradation of the device 1 may occur, for example, by applying excessive force, causing delamination of the barrier layer 18 or creating defects or cracks in the dielectric layer 12 and / or the substrate 10. Stored energy may contribute to achieving annealed bonding at relatively low temperatures (see FIG. 2I).

[0044] FIG. 2F shows the grains 24 after processing in FIG. 2E. The size of the grains 24 in the conductive material 32 can vary. In some embodiments, the grains 24 located at or near the upper surface 32b can be smaller than the grains 24 located at or near the lower surface 32a. In some embodiments, the average size of the grains 24 located at or near the upper surface 32b can be between about 10 nanometers (nm) and about 200 nm, or between about 50 nm and 200 nm. In some embodiments, the average size of the grains 24 located at or near the lower surface 32a or within the cavities can be between about 0.5 microns (μm) and 1 μm. In some embodiments, the average size of the grains 24 located at or near the lower surface 32a can be at least about five times the average size of the grains 24 located at or near the upper surface 32b. For example, the average size of the grains 24 located at or near the lower surface 32a may be about 10-100 times, 20-100 times, 30-100 times, 40-100 times, or 40-100 times the average size of the grains 24 located at or near the upper surface 32b. In some embodiments, the grains 24 may have a gradient grain size because the compressive residual stress in the conductive material varies from top to bottom. For example, the grain size of the grains 24 may gradually increase from the upper surface 32b to the lower surface 32a or within a conductive cavity or layer. In some embodiments, the conductive material 32 may be harder at or near the upper surface 32b than at or near the lower surface 32a. Compared to the deeper or bulk material near the lower surface 32a, the conductive material 32 near the upper surface 32b has a low percentage of grains 24 with vertically oriented 111 crystallographic planes and a relatively high percentage of 220 crystallographic planes ( <220> In some embodiments, particularly when laser peening is utilized on the conductive material 32, the cold work of the conductive layer may be deep enough so that the small grains located at the upper surface 32b are approximately the same as the grains located at the lower surface 32a or within the cavity.

[0045] In some applications, the conductive material 32 may comprise a portion of a through-substrate pad (not shown), such as a through-silicon via (TSV) or a through-glass via (TGV), in which case the portion of the conductive material 32 located at or near the upper surface 32b may exhibit lattice defects resulting from the cold working step.

[0046] In FIG. 2G, device 1 is prepared and prepared for direct bonding, for example, by advanced polishing and activation (e.g., nitrogen termination). At least a portion of conductive material 32 may be removed, for example, by polishing. Portions of barrier layer 18 and seed layer 30 may also be removed. The chemical mechanical planarization (CMP) slurry chemistry may be selected to stop on dielectric layer 12, but portions of dielectric layer 12 may also be removed to form a bonding interface. The bonding interface may include a highly polished surface of non-conductive layer 12b and upper surface 14b of the planar conductive material. In some embodiments, portions of the conductive material, barrier layer 18, seed layer 30, and dielectric layer 12 may be removed by polishing, for example, chemical mechanical polishing (CMP), in one or more stages involving one or more different slurry compositions to form a bonding interface. The upper surface 12b of the dielectric layer 12 may be polished to a high smoothness to prepare it for direct bonding, and then may be very lightly etched and / or activated, for example, by exposure to a nitrogen-containing plasma. The activated bonding surface may be cleaned with a suitable solvent, such as deionized (DI) water, to remove unwanted particles. The cleaned surface may be spin-dried to remove cleaning solvent residue prior to the bonding operation and subsequent annealing step.

[0047] In some embodiments, the highly polished bonding surface of the non-conductive material 12b and the upper surface 14b of the planar conductive material of the substrate 10 may be coated with a protective layer (not shown), typically an organic resist layer. The coated substrate may be mounted on a dicing frame for singulation. The singulation process may be performed by any known process, such as saw dicing, laser singulation, reactive ion etching (RIE), wet etching, or any suitable combination of these singulation steps. Regardless of the singulation step, the protective layer and singulation particles may be cleaned from the singulated die and dicing frame. The bonding surface of the cleaned die may be ashed to remove undesired organic residues and cleaned for direct bonding to another pre-treated bonding surface of another substrate. In some embodiments, the cleaned bonding surface of the singulated die may be activated by known methods and cleaned to remove undesired particles and materials, after which the activated bonding surface of the die may be directly bonded to another pre-treated bonding surface of the die's substrate. The bonded devices may be annealed to mechanically and electrically interconnect the opposing conductive pads of the bonded substrates (see FIG. 2I). In some embodiments, the second substrate containing the bonded singulated die may be further singulated to form a direct-bonded die stack.

[0048] The size of the grains 24 in the device 1 may vary. In some embodiments, the grains located at or near the upper surface 14b may be smaller on average than the grains 24 located at or near the lower surface 14a. In some embodiments, the grains may have a region of small grains located at or near the upper surface 14b of the conductive pad 14 and a region of large grains located at or near the lower surface 14a of the conductive pad. In some embodiments, the small grain region may be a region of the conductive pad 14 that is up to 1000 nm into the conductive pad 14 from the upper surface 14b, or up to 3000 nm for deeper pads. In some embodiments, the average size of the grains 24 in the small grain region located at or near the upper surface 14b may be between about 10 nanometers (nm) and 200 nm, or between about 30 nm and 200 nm. In some embodiments, the average size of the grains 24 in the large crystalline regions located at or near the lower surface 14a may be between about 0.2 microns (μm) and 1 μm, or between 0.2 μm and 0.5 μm. In some embodiments, the average size of the grains 24 located at or near the lower surface 14a may be at least five times the average size of the grains 24 located at or near the upper surface 14b. For example, the average size of the grains 24 located near the lower surface 14a may be between about 10 and 100 times, between about 20 and 100 times, between about 30 and 100 times, between about 40 and 100 times, or between about 40 and 100 times the average size of the grains 24 located at or near the upper surface 14b. In some embodiments, the grains 24 may have a gradient of grain size. For example, the grain size of the grains 24 may gradually increase from the upper surface 14b to the lower surface 14a. In some embodiments, the conductive pad 14 may be harder at or near the upper surface 14b than at or near the lower surface 14a. In some embodiments, the cold work of the conductive pad 14 may be deep enough so that the average size of the small grains located at or near the upper surface 14b is about the same as the average size of the grains located at or near the lower surface 14a or within the cavities.

[0049] In FIG. 2H, element 1 is placed in contact with second element 2. In some embodiments, the second element may be identical or entirely identical to element 1. In some embodiments, second element 2 may comprise a carrier, such as a package substrate, interposer, reconstituted wafer, or element. In some embodiments, second element 2 may also be prepared for direct bonding, as was element 1. The dashed line in FIG. 2H indicates a bond interface 56 between element 1 and second element 2. Second element 2 may include a second substrate 50, a second dielectric layer 52, and a second conductive pad 54. Conductive pad 54 may include grains 64. In some embodiments, when dielectric layer 12 and second dielectric layer 52 contact each other, dielectric layers 12 and 52 may bond to each other. In some embodiments, dielectric layer 12 and second dielectric layer 52 may be directly bonded to each other without an intervening adhesive. The dielectric layer 12 and the second dielectric layer 52 may be directly bonded at room temperature without external pressure. Although not shown in Figure 2H, the conductive pads 14, 54 may be recessed from the surfaces of the dielectric layers 12, 52, respectively, upon contact, so that a small gap exists between opposing conductive pads 14, 54 or other conductive elements at such surfaces.

[0050] In FIG. 2I, conductive pad 14 and second conductive pad 54 are bonded together. In some embodiments, conductive pad 14 and second conductive pad 54 may be bonded directly to each other without an intervening adhesive. The bonded structure may be annealed. Upon annealing, conductive pads 14, 54 may expand and contact each other, thereby forming a direct metal-to-metal bond. The dashed line in FIG. 2I indicates the bond interface 56 between element 1 and element 2.

[0051] As discussed above, prior to annealing, the crystalline structure of the conductive material 32 may have grains 24 containing a lower percentage of vertically oriented 111 crystal planes near the interface compared to the bottom regions of the conductive pads 14, 54. The conductive pad 14 after the cold working process of FIGS. 2G and 2H has stored energy within the cold worked conductive pad 14. The cold worked conductive pad 14 may contain very fine, misoriented grain sizes (large amounts of lattice defects, high-angle grain boundaries, twins, dislocations, vacancies, etc.) that indicate high creep within the pad 14. The combination of high creep and high grain stored energy allows for bridging of the recesses between the pads 14, 54 during a relatively low annealing temperature. Therefore, the conductive pads 14, 54 can be satisfactorily directly bonded to one another at relatively low temperatures and / or short annealing times. In some embodiments, the conductive pad 14 and the second conductive pad 54 may be annealed at a temperature of less than 250°C, less than 200°C, or less than 150°C, for example, between about 100°C and 250°C, between about 125°C and 200°C, or between about 125°C and 180°C.

[0052] After the conductive pad 14 and the second conductive pad 54 are annealed and bonded, the grain size may be changed compared to before bonding. In some embodiments, the size of the grains 24, 64 located at or near the bond interface 56 may be, on average, about 1.2 or 2 times the size of the grains 24 located at or near the lower surface 14a of the conductive pad 14. For example, the size of the grains 24, 64 located at or near the bond interface 56 may be, on average, about 2 to 10 times, 2 to 7 times, 2 to 5 times, 1.2 to 10 times, 1.2 to 7 times, or 1.2 to 5 times the size of the grains 24 located at or near the lower surface 14a of the conductive pad 14. In some embodiments, the grain size of the grains 24, 64 located at or near the bond interface 56 may be at least 20% to 50% larger than the grain size of the grains 24 located at or near the lower surface 14a of the conductive pad 14.

[0053] In some embodiments, the average size of the grains 24, 64 at the bond interface 56 is about 3-8 times, 3-6 times, 4-8 times, or 4-6 times the average size of the grains 24 located near the lower surface 14a of the conductive pad 14. In some embodiments, the grains 24, 64 located at or near the bond interface of the bonded conductive pad 14, 54 may have a higher percentage of 111 crystallographic planes and anneal twins than the percentage of grains 24 located at or near the lower surface 14a of the conductive pad 14. The stored energy in the surface grain structure facilitates greater grain growth and reorientation during the bonding anneal compared to portions located deeper in the pad structure that are less affected by the cold work process.

[0054] Figures 3A-3G illustrate steps in a manufacturing process for forming the element 1 shown in Figure 1 according to another embodiment. The process shown in Figures 3A-3G differs from the process shown in Figures 2A-2G in that the conductive material 32 is thinned prior to peening in the process shown in Figures 2A-2G. Components shown in Figures 3A-3G may be identical or generally similar to components shown in Figures 1-2I, and like reference numerals are used to indicate like parts.

[0055] In Figure 3A, a dielectric layer 12 is provided on a substrate 10. A cavity 16 is formed in the dielectric layer 12. The cavity 16 may extend through at least a portion of the thickness of the dielectric layer 12. The cavity 16 may be formed by selective etching or drilling. The cavity 16 may comprise a damascene cavity formed in a damascene process. In Figure 3A, an insulating or conductive barrier layer 18 may be provided on an upper surface 12b of the dielectric layer 12, on sidewalls 22 of the cavity 16, and on a bottom side 20 of the cavity 16. A seed layer 30 may be provided on the barrier layer 18 overlying the surfaces.

[0056] In FIG. 3B, a conductive material 32 may be disposed within the cavity 16 and on the upper surface 12b of the dielectric layer 12. In some embodiments, the conductive material may be comprised of a metal, such as copper (Cu). The conductive material 32 may have a lower surface 32a and an upper surface 32b. As shown in FIG. 3C, the conductive material 32 may be annealed. The annealing process may stabilize the microstructure (e.g., granular structure) of the grains 24 in the conductive material 32. The annealing process may form relatively large grains in the conductive material 32.

[0057] In Figure 3D, conductive material 32 may be thinned from upper surface 32b. In some embodiments, conductive material 32 may be thinned by polishing, such as chemical mechanical polishing (CMP). Figure 3D shows a portion of conductive material 32 disposed on upper surface 12b of dielectric layer 12. However, in some embodiments, conductive material 32 disposed on upper surface 12b of dielectric layer 12 may be completely removed to expose barrier layer 18. In other embodiments, barrier layer 18 on upper surface 12b of dielectric layer 12 may be completely removed to expose upper surface 12b of dielectric layer 12.

[0058] In FIG. 3E, the conductive material 32 may be processed by the cold working process described above with reference to FIG. 2E. The cold working process may be performed at room temperature and / or below room temperature. For example, the substrate temperature during the cold working process may range from liquid nitrogen temperature, −196° C. (77 K), to about 50° C., or from 0° C. to about 25° C., and in one example, may be at about ambient clean room temperature. The conductive material 32 may be processed from the upper surface 32 b. In some embodiments, the conductive material 32 may be processed by a strain hardening process. For example, the conductive material 32 may be processed by shot peening or laser peening to induce plastic deformation in the conductive material 32. As described above, shot peening may include bombardment with particles, such as metal, sand, glass, or ceramic. The plastic deformation can create compressive residual stresses in the grains 24 at or below the surface of the conductive material 32 and / or tensile stresses within or in the bulk of the conductive material 32. Regardless of how one or more compressive forces are applied to the conductive material 32 as described herein, the applied forces will degrade the substrate 1. Degradation of the device 1 may occur, for example, by applying excessive force that causes delamination of the barrier layer 18 relative to the surface of the substrate, or by creating defects or cracks in the dielectric layer 12 and / or the substrate 10.

[0059] FIG. 3F shows the grains 24 after processing of FIG. 3E. The size of the grains 24 in the conductive material 32 can vary. In some embodiments, the grains 24 located at or near the upper surface 32b can be smaller than the grains 24 located at or near the lower surface 32a. In some embodiments, the average size of the grains 24 located at or near the upper surface 32b can be between about 5 nanometers (nm) and about 200 nm, or between about 30 nm and 200 nm. Depending on the thickness of metal remaining on the field region (top surface of the dielectric layer 12), the average size of the grains 24 located at or near the lower surface 32a can be between about 0.5 microns (μm) and 3 μm or more. In some embodiments, the average size of the grains 24 at or near the lower surface 32a, or near the bottom of the conductive pad, can be at least about twice the average size of the grains 24 at or near the upper surface 32b. For example, the average size of the grains 24 at or near the lower surface 32a may be approximately 2-100 times, 20-100 times, 30-100 times, 40-100 times, or 40-100 times the average size of the grains 24 at or near the upper surface 32b. In some embodiments, the grains 24 may have a grain size gradient of 1. For example, the grain size of the grains 24 may gradually increase from the upper surface 32b to the lower surface 32a. In some embodiments, the conductive material 32 may be harder at or near the upper surface 32b than at or near the lower surface 32a. Due to plastic deformation, reduced grain size, increased lattice defects, and a reduced percentage of 111-oriented crystal planes remain at or near the upper surface 32b of the conductive pad 32. In some embodiments, due to the reduction in metal thickness left by the planarization shown in FIG. 3E, the plastic deformation may extend from the upper surface 32b of the conductive pad 32 to the lower surface 32a of the conductive pad 32.

[0060] In FIG. 3G, device 1 is formed. At least a portion of conductive material 32 may be removed. Portions of barrier layer 18 and seed layer 30 may also be removed, thereby forming a highly polished, planar bonding surface. A portion of dielectric layer 12 may also be removed. In some embodiments, the conductive material, barrier layer 18, seed layer 30, and portions of dielectric layer 12 may be removed in one or multiple steps by polishing, e.g., chemical-mechanical polishing (CMP), to form a highly polished bonding surface. The bonding surface includes a planar top surface of dielectric layer 12 and a planar polished surface of conductive pad 14. Upper surface 12b of dielectric layer 12 may be polished to a high smoothness and activated to prepare it for direct bonding.

[0061] As discussed above with reference to Figures 2H and 2I, the structure shown in Figure 3G may be directly hybrid bonded to another device that may or may not have been similarly processed. Also, as discussed above with reference to Figures 2H and 2I, the pre-processed bonding surfaces may first be protected with a protective layer, such as an organic resist layer, for intermediate singulation or other processing prior to bonding.

[0062] 2E and 3E, the conductive pad 14 has stored energy within it. The stored energy allows for a relatively low temperature anneal to bond the device (first device) 1 to another device (second device 2). The conductive pads 15, 14 may be sufficiently directly bonded to one another at a relatively low temperature and / or for a relatively short anneal duration. In some embodiments, the conductive pad 14 and the second conductive pad 54 may be annealed at a temperature below 250°C, below 200°C, or below 150°C, for example, between about 100°C and 250°C, or between about 125°C and 180°C.

[0063] After the conductive pad 14 and the second conductive pad 54 are annealed and bonded, the grain size may be altered compared to the grain size prior to bonding. In some embodiments, the size of the grains 24, 64 located at or near the bond interface 56 may be, on average, about 1.2 or 2 times the size of the grains 24 located at or near the lower surface 14a of the conductive pad 14. For example, the size of the grains 24, 64 located at or near the bond interface may be, on average, about 2 to 10 times, 2 to 7 times, 2 to 5 times, 1.2 to 10 times, 1.2 to 7 times, or 1.2 to 5 times the size of the grains 24, 64 located at or near the lower surface 14a of the conductive pad 14. In some embodiments, the grain size of the grains 24, 64 located at or near the bond interface may be at least 20% to 50% larger than the grain size of the grains 24, 64 located at or near the underside of the conductive pad 14, 54. Generally, the greater the stored energy from the applied compressive force, the larger the grain size of the bonded conductive pad after annealing.

[0064] In some embodiments, a third conductive material (not shown) may be provided in the cavity 16 in the conductive material 12 beneath the barrier layer 18 (see FIGS. 2B and 3A), as is typical in a multi-layer back-end or redistribution layer (RDL) in the device 1. After the bonding and annealing operations, as a result of the mechanical or thermal treatment of the conductive material 32 in the cavity 16, the average size of the grains 24 in the region of the conductive pad 32 in the cavity 16 may be at least about 20% larger than the average size of the grains 24 of the third conductive material located beneath the barrier layer 18, compared to the third conductive material subjected to only the thermal treatment. For example, the average size of the grains 24 in the conductive pad 32 may be about 1.2 to 20 times the average size of the grains 24 of the third conductive material beneath the barrier layer 18 or the next conductive pad (not shown) beneath the third conductive pad.

[0065] Referring back to FIG. 2I, in some embodiments, after annealing the mechanically or optically cold-worked conductive material, the annealed grains are elongated along a direction generally parallel to the dielectric interface or the conductive material interface. The horizontal dimension (length l) of the annealed conductive material grains 24 may be at least 20% greater than the vertical dimension (thickness t) of the same grain along a direction perpendicular to the dielectric interface or the conductive material interface. For example, the length of the conductive material grains generally parallel to the bond interface may be, on average, about 1.5 to 10 times greater than the thickness of the grains in a direction generally perpendicular to the bond interface. In some embodiments, the length of the columnar grains of the bonded element (e.g., bonded element 3 shown in FIG. 2I) may be at least 20% to 300% greater than the thickness of the columnar grains of the conductive material within the bonded element 3. In some embodiments, the aspect ratio of the grains (maximum longitudinal dimension (length l) of a grain / maximum vertical dimension (thickness t) of the same grain) may be greater than 1.2, greater than 1.5, or greater than 3.

[0066] In one aspect, a device is disclosed. The device may include a non-conductive structure having a non-conductive bonding surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a backside surface opposite the bonding surface. The average size of the grains of the conductive pad at the bonding surface is smaller than the average thickness of the grains located adjacent the bottom side of the cavity.

[0067] In one embodiment, the non-conductive structure includes a dielectric layer. The non-conductive bonding surfaces of the non-conductive structure may be pre-treated to allow direct bonding.

[0068] The conductive bonding surface of the conductive pad may be pre-treated to allow direct bonding.

[0069] The conductive pads preferably comprise copper (Cu) pads.

[0070] The conductive pad may have a lower percentage of grains with 111 crystal planes at the junction surface compared to adjacent the bottom side.

[0071] The conductive pad may have a higher percentage of grains with 220 crystal planes at the interface compared to adjacent the bottom side.

[0072] In one embodiment, the average size of the grains adjacent the bottom side of the cavity is at least three times the average size of the grains at the joining surface.

[0073] In one embodiment, the average size of the grains located adjacent the bottom side of the cavity is at least 20 times the average size of the grains located at the joining surface.

[0074] In one embodiment, the average size of the grains located adjacent the bottom side of the cavity is between 0.2 microns (μm) and 1 μm.

[0075] In one embodiment, the average size of the grains located at the interface is between 30 nanometers (nm) and 200 nm.

[0076] In one embodiment, the device further comprises a barrier layer disposed between the non-conductive structure and the conductive pad.

[0077] In one aspect, a bonded structure is disclosed. The bonded structure may include a first element, the first element including a non-conductive structure with a non-conductive bonding surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a backside surface opposite the bonding surface. The average size of the grains at the bonding interface is at least 20% larger than the average size of the grains located adjacent the bottom side of the cavity. The bonded structure may include a second element with a second conductive pad. The conductive pad of the first element and the second conductive pad of the second element are directly bonded to each other along the bonding interface without an intervening adhesive.

[0078] In one embodiment, the second element further comprises a second non-conductive structure with a second non-conductive bonding surface that is bonded directly to the non-conductive bonding surface of the first element without an intervening adhesive.

[0079] In one embodiment, the average size of the grains located at the bond interface is at least 50% larger than the average size of the grains located near the back surface.

[0080] In one embodiment, the average size of the grains located at the bond interface is at least twice the average size of the grains located adjacent the bottom side of the cavity.

[0081] The average size of the grains located at the bond interface is at least three times the average size of the grains located adjacent the bottom side of the cavity.

[0082] In one aspect, a method of forming a device is disclosed. The method may include providing a non-conductive structure having a first surface and a second surface opposite the first surface. The method may include forming a cavity within the non-conductive structure. The method may include providing a conductive material within the cavity and over a portion of the first surface of the non-conductive structure layer. The conductive material has a lower surface facing a bottom side of the cavity and an upper surface opposite the lower surface. The method may include cold working the upper surface of the conductive material to modify a crystal structure of the conductive material. The cold working is performed at a temperature between about -196°C and 50°C. The method may include removing at least a portion of the conductive material to form a conductive pad with a conductive bonding surface.

[0083] In one embodiment, the cold working comprises mechanical peening or laser peening.

[0084] In one embodiment, the cold working comprises bombarding the upper surface of the conductive material with metal, glass, or ceramic particles.

[0085] In one embodiment, the cold working includes reducing the percentage of 111 crystallographic planes in the conductive material.

[0086] Cold working includes inducing plastic deformation in the conductive material and reducing the grain size of the conductive material at least at the upper surface compared to the grain size before cold working.

[0087] In one embodiment, the cold working produces a smaller grain size at the upper surface of the conductive material than the grain size at the lower surface of the conductive material.

[0088] In one embodiment, the method further comprises annealing the conductive material to stabilize the grain size of the conductive material prior to cold working.

[0089] In one embodiment, the removing step includes removing at least a portion of the conductive material prior to cold working.

[0090] The method may further include preparing the conductive bonding surface of the conductive pad and the first surface of the non-conductive structure for direct bonding.

[0091] In one embodiment, the method further comprises providing a barrier layer between the non-conductive structure and the conductive material.

[0092] In one embodiment, a method of forming a bonded structure includes bonding the device to a second device comprising a second non-conductive structure and a second conductive pad.

[0093] The bonding step may include directly bonding the non-conductive structure and the second non-conductive structure to one another.

[0094] The bonding step may further include the step of annealing the conductive pad and the second conductive pad at a temperature of 50°C to 250°C.

[0095] The annealing step may include annealing the conductive pad and the second conductive pad at a temperature between 50°C and 150°C.

[0096] Annealing the conductive pad and the second conductive pad can increase the average grain size of the conductive material at the upper surface compared to the average grain size before annealing.

[0097] Annealing the conductive pad and the second conductive pad can cause the average grain size of the conductive material at the upper surface to be larger than the average grain size of the conductive material at the lower surface.

[0098] In one aspect, a device is disclosed. The device may include a non-conductive structure having a non-conductive bonding surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a backside surface opposite the bonding surface. The conductive pad has a lower percentage of grains with 111 crystallographic planes at the bonding surface compared to grains adjacent the bottom side.

[0099] In one aspect, an element is disclosed. The element may include a non-conductive structure having a non-conductive joining surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, and a conductive feature disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive feature has a joining surface and a backside surface opposite the joining surface. The average grain size within a portion of the conductive feature located near the joining surface is less than 200 nanometers (nm).

[0100] In one embodiment, the average grain size within the portion of the conductive feature located near the bonding surface is at least 50 nm.

[0101] In one aspect, a bonding structure is disclosed. The bonding structure may include a first element, the first element including a non-conductive structure with a non-conductive bonding surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back surface opposite the bonding surface. The conductive pad includes a crystalline structure in which the grains are oriented along the 111 crystallographic plane. The average grain size of the conductive pad located at the bonding surface is larger than the average grain size of the conductive pad located at the back surface. The bonding structure may include a second element with a second conductive pad. The conductive pad of the first element and the conductive pad of the second element are directly bonded to each other along a bonding interface without an intervening adhesive.

[0102] In one aspect, a method of forming a device is disclosed. The method may include providing a non-conductive structure having a first surface and a second surface opposite the first surface. The method may include forming a cavity in the first surface of the non-conductive structure. The method may include providing a conductive material in the cavity and over the first surface of the non-conductive structure. The method may include increasing the grain size of the conductive material by thermal annealing. The method may include forming lattice defects in the annealed conductive material. The method may include forming a planar joining surface comprising a non-conductive joining surface and a conductive joining surface. The conductive joining surface has lattice defects.

[0103] In one embodiment, the method further comprises providing a barrier layer between the non-conductive structure and the conductive material.

[0104] In one embodiment, the method further comprises singulating the devices on a dicing frame.

[0105] The method may further include providing a protective layer over the devices, and may further include cleaning the bonding surfaces of the singulated devices and protective layer particles resulting from singulation from the dicing frame.

[0106] The method may further include directly bonding the cleaned singulated elements to the pre-treated bonding surface of a second substrate to form a bonded structure.

[0107] The method may further include annealing the bonded structure at a temperature less than 200° C. to electrically bond the singulated elements to the second substrate.

[0108] In one embodiment, forming lattice defects comprises cold working the surface of the annealed conductive material.

[0109] In one aspect, a bonded structure is disclosed. The bonded structure may include a first element, the first element including a non-conductive structure with a non-conductive bonding surface, a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed within the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back surface opposite the bonding surface. The conductive pad has a longitudinal columnar grain structure generally oriented parallel to the non-conductive bonding surface. The bonded structure may include a second element with a second conductive pad. The conductive pad of the first element and the second conductive pad of the second element are directly bonded to each other along a bonding interface without an intervening adhesive.

[0110] In one aspect, a bonded structure is disclosed. The bonded structure may include a first element having a planar conductive structure embedded within a surface of a non-conductive material having a non-conductive bonding surface. The conductive structure has a longitudinal columnar grain structure generally oriented parallel to the non-conductive bonding surface. The bonded structure may include a second element having a planar bonding surface. The bonding surfaces of the first and second elements are directly bonded to each other along a bonding interface without an intervening adhesive.

[0111] In one aspect, a bonded structure is disclosed. The bonded structure may include a first element including a first conductive feature and a first non-conductive region, and a second element including a second conductive feature directly bonded to the first conductive feature without an intervening adhesive and a second non-conductive region bonded to the first non-conductive region. The bonded first and second conductive features include crystalline grains. Each of the crystalline grains has a length along a bonding interface between the first element and the second element and a thickness perpendicular to the bonding interface. The crystalline grains have an average length that is at least 1.5 times the average thickness of the crystalline grains.

[0112] Unless the context clearly requires otherwise, throughout the specification and claims, terms such as "comprise," "comprising," "include," and "including" are to be construed in an inclusive sense, i.e., "including, but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as used generally herein, means two or more elements that are directly connected to each other or that are connected to each other by one or more intermediate elements. Similarly, the term "coupled," as used generally herein, means two or more elements that are directly connected to each other or that are connected to each other by one or more intermediate elements. Additionally, as used herein, the terms "herein," "above," "below," and words of similar import refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being located "on" or "over" a second element, the first element may be directly located on or over the second element such that the first and second elements are in direct contact with each other, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first and second elements. Where the context permits, terms in the above Detailed Description using the singular or plural may also include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0113] Furthermore, conditional terms used in the specification, particularly "can" (often expressed as "preferably"), "could," "might," "may," "eg," "for example," and "such as," are generally intended to imply that certain embodiments include certain features, elements, and / or conditions, and that other embodiments do not include certain features, elements, and / or conditions, unless expressly specified otherwise or understood differently within the context in which they are used. Thus, such conditional terms are generally not intended to imply that a feature, element, and / or condition is present in any required way for one or more embodiments.

[0114] While certain embodiments have been described, these embodiments are provided by way of example only and do not limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, while blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention, as defined by the appended claims and their equivalents, is intended to cover such forms or modifications as fall within the scope and spirit of the invention.

Claims

1. An element, a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; a conductive pad disposed within the cavity, the conductive pad having a bonding surface and a back surface opposite the bonding surface, the bonding surface of the conductive pad being recessed relative to the non-conductive bonding surface, and an average size of the grains of the conductive pad at the bonding surface being smaller than an average thickness of the grains located adjacent the bottom side of the cavity.

2. 10. The device of claim 1, wherein the non-conductive structure includes a dielectric layer, and the non-conductive bonding surface of the non-conductive structure is pretreated to allow direct bonding.

3. The device of claim 2 , wherein the conductive pad is a copper (Cu) pad.

4. 4. The device of claim 3, wherein said conductive pad has a lower percentage of grains with 111 crystal planes at said junction surface compared to adjacent said bottom side.

5. 4. The device of claim 3, wherein said conductive pad has a higher percentage of grains with 220 crystal planes at said junction surface compared to adjacent said bottom side.

6. 2. The device of claim 1, wherein the average size of the grains adjacent the bottom side of the cavity is at least three times the average size of the grains at the joining surface.

7. 2. The device of claim 1, wherein the average size of the grains located adjacent the bottom side of the cavity is at least 20 times the average size of the grains located at the joining surface.

8. 2. The device of claim 1, wherein the average size of the grains located adjacent the bottom side of the cavity is between 0.2 microns (μm) and 1 μm.

9. 2. The device of claim 1, wherein the average size of the grains located at the interface is between 30 nanometers (nm) and 200 nm.

10. 2. The device of claim 1, further comprising a barrier layer disposed between said non-conductive structure and said conductive pad.

11. A bonded structure, A first element, the first element comprising: a non-conductive structure having a non-conductive joining surface; a cavity extending at least partially through a portion of the thickness of the non-conductive structure from the non-conductive joining surface, the cavity having a bottom side and a sidewall; a conductive pad disposed within the cavity, the conductive pad having a joining surface and a back surface opposite the joining surface, wherein an average size of grains of the conductive pad at the joining surface is different from an average thickness of the grains located adjacent the bottom side of the cavity; a second element having a second conductive pad; the conductive pad of the first element and the second conductive pad of the second element are directly bonded to one another along a bonding interface without any intervening adhesive; The second element comprises a second non-conductive bonding surface, the non-conductive bonding surface is directly bonded to the second non-conductive bonding surface, and at least one of the non-conductive bonding surface and the second non-conductive bonding surface comprises an activated bonding surface.

12. The bonded structure of claim 11 , wherein the second non-conductive bonding surface is bonded directly to the non-conductive bonding surface without an intervening adhesive.

13. The bonded structure of claim 11 , wherein the average size of the grains located at the bond interface is at least 50% larger than the average size of the grains located adjacent a bottom side of the cavity.

14. The bonded structure of claim 11 , wherein the average size of the grains located at the bond interface is at least twice the average size of the grains located adjacent the bottom side of the cavity.

15. The bonded structure of claim 14 , wherein the average size of the grains located at the bond interface is at least three times the average size of the grains located adjacent the bottom side of the cavity.

16. 1. A method of forming a device, the method comprising: providing a non-conductive structure having a first surface and a second surface opposite the first surface; forming a cavity in the non-conductive structure; providing a conductive material within the cavity and on a portion of the first surface of the non-conductive structure, the conductive material having a lower surface facing a bottom side of the cavity and an upper surface opposite the lower surface; cold working the upper surface of the conductive material to modify a crystal structure of the conductive material, the cold working being performed at about −196° C. to 50° C.; The method includes cold working the top side of the conductive material and then removing at least a portion of the conductive material to form a conductive pad with a conductive bonding surface.

17. The method of claim 16 , wherein the cold working comprises mechanical peening or laser peening.

18. The method of claim 16 , wherein the cold working comprises reducing the percentage of 111 crystallographic planes in the conductive material.

19. 20. The method of claim 18, wherein the cold working comprises inducing plastic deformation in the conductive material and reducing a grain size of the conductive material at least at the upper surface compared to the grain size before the cold working.

20. The method of claim 16 , wherein the cold working produces a smaller grain size at the upper surface of the conductive material compared to a grain size at the lower surface of the conductive material.

21. The method of claim 16 , further comprising annealing the conductive material to stabilize the grain size of the conductive material prior to cold working.

22. The method of claim 16 , further comprising preparing the conductive bonding surface of the conductive pad and the first surface of the non-conductive structure for direct bonding.

23. 20. A method of forming a bonded structure, said method comprising bonding the device of claim 16 to a second device comprising a second non-conductive structure and a second conductive pad.

24. The method of claim 23 , wherein the bonding step comprises directly bonding the non-conductive structure and the second non-conductive structure to one another.

25. 25. The method of claim 24, wherein said bonding step further comprises the step of annealing said conductive pad and said second conductive pad at a temperature between 50.degree. C. and 250.degree. C.

26. 24. The method of claim 23, wherein the conductive pad and the second conductive pad are annealed to increase an average grain size of the conductive material at the upper surface compared to the average grain size before the annealing.

27. The bonded structure of claim 11 , wherein an average grain size of the conductive pad at the bond surface differs from an average thickness of the grains located adjacent the bottom side of the cavity by at least 20%.

28. 28. The joint structure of claim 27, wherein the average size of the grains of the conductive pad at the joint surface is at least 20% greater than the average thickness of the grains located adjacent the bottom side of the cavity.

29. The bonded structure of claim 11 , wherein the activated bonding surface comprises a plasma activated bonding surface.

30. The bonded structure of claim 11 , wherein the activated bond surface comprises nitrogen, representing nitrogen termination.

31. The bonded structure of claim 11, wherein the activated bonding surface comprises a nitrogen-terminated inorganic non-conductive material.

32. The bonded structure of claim 11 , wherein the non-conductive bonding surface is directly covalently bonded to the second non-conductive bonding surface.

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