Array substrate, display panel and electronic device

Abstract

To provide an array substrate, a display panel, and an electronic apparatus.SOLUTION: Two driving units 11, 12 adjacent to each other in a first direction D1 are installed on an array substrate so as to share a first scanning wire 301 and a second scanning wire 302. Consequently, semiconductor wiring parts in these driving units can extend along a straight line and overlap the first scanning wire and the second scanning wire to form a first switching transistor and a second switching transistor, and a space occupied by the semiconductor wiring parts can thereby be reduced.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application bearing application number 202410008546.5, filed with the State Intellectual Property Office of China on January 2, 2024, and a Chinese patent application bearing application number 202410565972.9, filed with the State Intellectual Property Office of China on May 8, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] The present application relates to the field of display technology, and more particularly to array substrates, display panels and electronic devices. [Background technology]

[0003] Some display panels have a light-transmitting display area to realize under-screen camera or under-screen optical fingerprint recognition in the full screen. This not only fulfills the display function but also allows external light to pass through the light-transmitting display area and enter the optical collector below the display panel. However, as pixel density (PPI) increases, the wiring density on the array substrate of the display panel becomes higher, which reduces the light-transmitting area on the array substrate and affects the transmittance of the entire display panel. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides an array substrate, a display panel, and an electronic device to solve the above problems in the prior art. [Means for solving the problem]

[0005] The array substrate according to the present application includes a base, a first semiconductor layer located on one side of the base, and a first conductive layer located on a side of the first semiconductor layer away from the base. The first semiconductor layer includes a first semiconductor wiring portion and a second semiconductor wiring portion, and the first semiconductor wiring portion and the second semiconductor wiring portion extend in parallel along a first direction; the first conductive layer includes a first scanning wiring and a second scanning wiring, and the first scanning wiring and the second scanning wiring extend in parallel along a second direction, and the first direction and the second direction intersect. The array substrate includes a plurality of driving units, the driving units including a first driving unit and a second driving unit adjacent to each other in the first direction, the first driving unit being located on a side of the first scanning wiring that is farther from the second scanning wiring, and the second driving unit being located on a side of the second scanning wiring that is farther from the first scanning wiring. On the base, the orthogonal projection of the first semiconductor wiring portion at least partially overlaps with the orthogonal projection of the first scanning wiring and the orthogonal projection of the second scanning wiring, respectively, and the first switching transistor and the second switching transistor of the first driving unit are located at a position where the orthogonal projection of the first semiconductor wiring portion overlaps with the orthogonal projection of the first scanning wiring and the second scanning wiring. On the base, the orthogonal projection of the second semiconductor wiring portion at least partially overlaps with the orthogonal projection of the first scanning wiring and the orthogonal projection of the second scanning wiring, respectively, and the first switching transistor and the second switching transistor of the second driving unit are located at a position where the orthogonal projection of the second semiconductor wiring portion overlaps with the orthogonal projection of the first scanning wiring and the second scanning wiring.

[0006] In some possible embodiments, the first semiconductor layer further includes a third semiconductor wiring portion corresponding to the transistors other than the first and second switching transistors of the first driving unit in the first driving unit, and a fourth semiconductor wiring portion corresponding to the transistors other than the first and second switching transistors of the second driving unit in the second driving unit, the third semiconductor wiring portion and the fourth semiconductor wiring portion being disposed symmetrically with respect to an axis of symmetry extending along the second direction. Preferably, the orthogonal projection of the axis of symmetry on the base is located between the first scanning wiring and the second scanning wiring.

[0007] In some possible embodiments, the drive unit includes a drive transistor. The first semiconductor layer further includes a third semiconductor wiring portion corresponding to transistors other than the first switching transistor, the second switching transistor, and the drive transistor of the first drive unit in the first drive unit, and a fourth semiconductor wiring portion corresponding to transistors other than the first switching transistor, the second switching transistor, and the drive transistor of the second drive unit in the second drive unit. The third semiconductor wiring portion and the fourth semiconductor wiring portion are disposed symmetrically with respect to an axis of symmetry extending along the second direction. Preferably, the orthogonal projection of the axis of symmetry on the base is located between the first scanning wiring and the second scanning wiring. Preferably, the semiconductor wiring portion corresponding to the driving transistor is disposed asymmetrically with respect to an axis of symmetry extending along the second direction.

[0008] In some possible embodiments, the array substrate further includes first initialization wiring extending along the second direction, and an orthogonal projection of the first initialization wiring is located between an orthogonal projection of the first scan wiring and an orthogonal projection of the second scan wiring on the base. Preferably, the driving unit includes a driving transistor. The first driving unit and the second driving unit share the first initialization wiring, and the first initialization wiring is configured to provide a first initialization voltage to first electrodes of the driving transistor of the first driving unit and the driving transistor of the second driving unit.

[0009] In some possible embodiments, the first scanning wiring and the second scanning wiring synchronously transmit the same scanning signal, the first switching transistor and the second switching transistor are connected in series between the first electrode of the driving transistor and the first initialization wiring, and the first switching transistor and the second switching transistor are used to perform voltage initialization control on the first electrode of the driving transistor.

[0010] In some possible embodiments, the array substrate further includes a fifth conductive layer located on a side of the first conductive layer remote from the base, and the first initialization wiring is located on the fifth conductive layer. Preferably, the material of the first conductive layer comprises a metal. Preferably, the material of the fifth conductive layer comprises a metal.

[0011] In some possible embodiments, the fourth conductive layer includes a first connection wiring portion. The driving transistor of the first driving unit is located on the side of the first scanning wiring that is farther from the second scanning wiring, and the driving transistor of the second driving unit is located on the side of the second scanning wiring that is farther from the first scanning wiring. One end of the first semiconductor wiring portion close to the first scanning wiring is connected to the first electrode of the driving transistor of the first driving unit via the first connection wiring portion, and one end of the first semiconductor wiring portion close to the second scanning wiring is connected to the first initialization wiring via the first connection wiring portion. One end of the second semiconductor wiring portion close to the second scanning wiring is connected to a first electrode of a driving transistor of the second driving unit via the first connection wiring portion, and one end of the second semiconductor wiring portion close to the first scanning wiring is connected to the first initialization wiring via the first connection wiring portion.

[0012] In some possible embodiments, the array substrate further includes second initialization wiring extending along the second direction, and at the base, an orthogonal projection of the second initialization wiring is located between an orthogonal projection of the first scan wiring and an orthogonal projection of the second scan wiring. The driving unit further includes a pixel electrode connection point, the first driving unit and the second driving unit share the second initialization wiring, and the second initialization wiring is used to provide a second initialization voltage to the pixel electrode connection point between the first driving unit and the second driving unit.

[0013] In some possible embodiments, the array substrate further includes a third conductive layer and a fourth conductive layer located on a side of the first conductive layer away from the base, and the second initialization wiring includes a first portion located on the third conductive layer and a second portion located on the fourth conductive layer, and the first portion and the second portion are alternately arranged along the second direction. Preferably, at least one of the material of the third conductive layer or the material of the fourth conductive layer comprises a metal.

[0014] In some possible embodiments, the driving unit includes a third switching transistor connected between the pixel electrode connection point and the second initialization wiring, and the third switching transistor is used to perform voltage initialization control on the pixel electrode connection point.

[0015] In some possible embodiments, the array substrate includes a plurality of first driving unit groups, each of which includes one of the first driving units and one of the second driving units, and the first driving unit and the second driving unit in the same first driving unit group share the first scanning wiring and the second scanning wiring. Preferably, the array substrate further includes third initialization wiring, wherein an orthogonal projection of the third initialization wiring at the base is located between two adjacent first driving unit groups in the first direction, and the first driving unit and the second driving unit that belong to different first driving unit groups and are adjacent in the first direction share the third initialization wiring. Preferably, the driving unit includes a driving transistor, and the third initialization wiring is used to provide a third initialization voltage to the gate of the driving transistor.

[0016] In some possible embodiments, the array substrate further includes a fourth conductive layer and a fifth conductive layer located on sides of the first conductive layer remote from the base. The third initialization wiring includes a third portion located in at least one of the first conductive layer or the fourth conductive layer and a fourth portion located in the fifth conductive layer, the third portion and the fourth portion being alternately arranged along the second direction, and the fourth portion including a transparent openwork area.

[0017] In some possible embodiments, the driving unit includes a fourth switching transistor and a fifth switching transistor, which are connected between the gate of the driving transistor and the third initialization wiring, and which are used to perform voltage initialization control on the gate of the driving transistor.

[0018] In some possible embodiments, the array substrate further includes a plurality of fourth initialization wirings extending along the second direction. The array substrate includes a plurality of second driving unit groups, and each of the second driving unit groups includes two of the driving units adjacent to each other in the second direction. Two of the driving units in the same second driving unit group are installed symmetrically with respect to one of the fourth initialization wirings. In the second direction, there is a light leakage gap between the drive transistors of two adjacent drive units that belong to different second drive unit groups.

[0019] The present application further provides a display panel, which includes the array substrate according to the present application.

[0020] The present application further provides an electronic device, which includes the display panel according to the present application. [Effects of the Invention]

[0021] Compared with the prior art, the present application has the following technical effects:

[0022] The present application provides an array substrate, a display panel, and an electronic device, in which two adjacent driving units in a first direction on the array substrate are arranged to share a first scanning wiring and a second scanning wiring, so that the semiconductor wiring portions in these driving units extend along a straight line and overlap with the first scanning wiring and the second scanning wiring, respectively, to form a first switching transistor and a second switching transistor, thereby reducing the space occupied by the semiconductor wiring portions. [Brief explanation of the drawings]

[0023] In order to more clearly explain the technical solutions in the embodiments of the present application, the following briefly introduces the drawings that need to be used in the embodiments. Note that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without any creative work.

[0024] [Figure 1] 2 is a schematic diagram of the layer structure of the array substrate according to the present embodiment. FIG. [Figure 2] FIG. 2 is a first perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 3] FIG. 2 is a second perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 4] FIG. 10 is a third perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 5] FIG. 4 is a fourth perspective schematic view of layers in the array substrate according to the embodiment. [Figure 6] FIG. 2 is a schematic diagram of a circuit of a drive unit according to the present embodiment. [Figure 7] FIG. 5 is a fifth perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 8] FIG. 6 is a sixth perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 9] FIG. 7 is a seventh perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 10] FIG. 8 is an eighth perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 11] FIG. 9 is a ninth perspective schematic diagram of layers in the array substrate according to the embodiment. [Figure 12] FIG. 10 is a schematic perspective view of a layer in the array substrate according to the present embodiment. [Figure 13] FIG. 11 is an eleventh perspective schematic view of a layer in the array substrate according to the present embodiment. [Figure 14] FIG. 12 is a twelfth perspective schematic view of a layer in the array substrate according to the present embodiment. [Figure 15] FIG. 13 is a thirteenth perspective schematic diagram of a layer in the array substrate according to the present embodiment. [Figure 16] FIG. 14 is a 14th perspective schematic diagram of a layer in an array substrate according to the present embodiment. [Figure 17] FIG. 15 is a schematic perspective view of a layer in the array substrate according to the present embodiment. [Figure 18] FIG. 16 is a schematic perspective view of a layer in an array substrate according to the present embodiment. [Figure 19] FIG. 17 is a 17th perspective schematic diagram of a layer in the array substrate according to the present embodiment. [Figure 20] FIG. 18 is an 18th perspective schematic view of layers in the array substrate according to the present embodiment. [Figure 21] FIG. 19 is a 19th perspective schematic diagram of layers in the array substrate according to the present embodiment. [Figure 22] FIG. 20 is a twentieth perspective schematic view of a layer in the array substrate according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0025] In order to more clearly describe the objectives, technical solutions and advantages of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Needless to say, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. In general, the components according to the embodiments of the present application illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0026] Therefore, the detailed description of the embodiments of the present application provided in the drawings below is not intended to limit the scope of the application to be protected, but merely illustrates selected embodiments of the present application. All other embodiments that a person skilled in the art can obtain based on the embodiments of the present application without any creative effort fall within the scope of protection of the present application.

[0027] It should be noted that in the following drawings, like reference numerals and letters indicate like elements, so that once an element is defined in one drawing, it does not need to be further defined and interpreted in subsequent drawings.

[0028] In the description of this application, the orientations or positional relationships indicated by terms such as "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer" are orientations or positional relationships shown in the drawings or are orientations or positional relationships in which the product is always placed when in use, and are merely for the purpose of conveniently and simply describing this application. They do not indicate or imply that the device or part in question has a specific orientation, or is constructed or operated in a specific orientation, and should not be understood as a limitation on this application. Furthermore, terms such as "first," "second," and "third" are merely used for the purpose of distinction and description, and should not be understood as indicating or implying relative importance.

[0029] It should be noted that, if not inconsistent, different configurations in the embodiments of the present application may be combined with each other.

[0030] Referring to Figure 1, Figure 1 is a schematic cross-sectional view of an array substrate according to this embodiment, which may include a base 100, a first semiconductor layer 200 located on one side of the base 100, and a first conductive layer 300 located on the side of the first semiconductor layer 200 away from the base 100.

[0031] In this embodiment, a first insulating layer 101 may be further disposed between the first semiconductor layer 200 and the first conductive layer 300 .

[0032] 2, the first semiconductor layer 200 may include a plurality of semiconductor wiring portions. The plurality of semiconductor wiring portions may include a first semiconductor wiring portion 201 and a second semiconductor wiring portion 202. The first semiconductor wiring portion 201 and the second semiconductor wiring portion 202 extend in parallel along a first direction D1.

[0033] 3, the first conductive layer 300 may include a plurality of lines, such as a first scan line 301 and a second scan line 302. The first scan line 301 and the second scan line 302 extend in parallel along a second direction D2 and synchronously transmit the same scan signal. The first direction D1 and the second direction D2 intersect, for example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0034] Alternatively, in one example, the material of the first conductive layer 300 may include metal, and the first scan wiring 301 and the second scan wiring 302 may be metal wiring.

[0035] In other examples, the material of the first conductive layer 300 may include a non-metallic material, such as, for example, a metal oxide (eg, indium tin oxide), graphene, or a conductive semiconductor material.

[0036] In this embodiment, multiple layers on the array substrate can be combined with each other to form multiple thin film transistors (TFTs) at different positions. Multiple TFTs can be combined with each other to form multiple driving units. The driving units are configured to drive pixels to emit light. Here, one driving unit may include multiple different transistors.

[0037] Referring to FIG. 4, as shown in a rectangular dashed frame in FIG. 4, the plurality of driving units on the array substrate may include a first driving unit 11 and a second driving unit 12 adjacent to each other in the first direction D1.

[0038] In the first direction D1, the first driving unit 11 is located on the side of the first scanning wiring 301 that is farther from the second scanning wiring 302, and the second driving unit 12 is located on the side of the second scanning wiring 302 that is farther from the first scanning wiring 301.

[0039] For example, if the first scanning wiring 301 and the second scanning wiring 302 are regarded as one unit, the first driving unit 11 and the second driving unit 12 are located on both sides of the first scanning wiring 301 and the second scanning wiring 302 in the first direction D1.

[0040] 5, the orthogonal projection of the first semiconductor wiring portion 201 on the base 100 at least partially overlaps with the orthogonal projection of the first scanning wiring 301 on the base 100 and the orthogonal projection of the second scanning wiring 302 on the base 100. The first switching transistor T8-1 and the second switching transistor T8-2 in the first driving unit 11 are located at positions where the orthogonal projection of the first semiconductor wiring portion 201 overlaps with the orthogonal projections of the first scanning wiring 301 and the second scanning wiring 302.

[0041] The orthogonal projection of the second semiconductor wiring portion 202 on the base 100 at least partially overlaps with the orthogonal projection of the second scanning wiring 302 on the base 100 and the orthogonal projection of the first scanning wiring 301 on the base 100. The first switching transistor T8-1 and the second switching transistor T8-2 in the second drive unit 12 are located at positions where the orthogonal projection of the second semiconductor wiring portion 202 overlaps with the orthogonal projections of the first scanning wiring 301 and the second scanning wiring 302.

[0042] For example, the first semiconductor wiring portion 201 belongs to the first driving unit 11. The first semiconductor wiring portion 201 extending along the first direction D1 overlaps with the first scanning wiring 301 and the second scanning wiring 302 extending along the second direction D2, and corresponds to the first switching transistor T8-1 and the second switching transistor T8-2 of the first driving unit 11, respectively, at the overlapping position.

[0043] The second semiconductor wiring portion 202 belongs to the second driving unit 12. The second semiconductor wiring portion 202 extending along the first direction D1 overlaps with the first scanning wiring 301 and the second scanning wiring 302 extending along the second direction D2, and corresponds to the first switching transistor T8-1 and the second switching transistor T8-2 of the second driving unit 12, respectively, at the overlapping positions.

[0044] Based on the above design, in the array substrate of this embodiment, two scan lines (i.e., first scan line 301 and second scan line 302) transmitting the same signal are installed between the first driving unit 11 and the second driving unit 12 adjacent to each other in the first direction D1, and the first driving unit 11 and the second driving unit 12 share the first scan line 301 and the second scan line 302. As a result, for the first switching transistor T8-1 and the second switching transistor T8-2 that need to be arranged in series and require the same gate control signal, the semiconductor wiring portion extending along a straight line can be overlapped with the first scan line 301 and the second scan line 302, respectively, to form the transistors. Compared to the prior art where the semiconductor wiring portion is arranged in a U-shape to overlap the same scan line twice, the solution of the present application can save wiring space, which is advantageous for improving the light transmittance of the array substrate or the pixel density.

[0045] Optionally, referring again to FIG. 1, in some embodiments, the array substrate may further include a second conductive layer 400, a second semiconductor layer 500, a third conductive layer 600, a fourth conductive layer 700 and a fifth conductive layer 800 located on the side of the first conductive layer 300 away from the base 100.

[0046] Optionally, the array substrate may further include insulating layers located between adjacent layers, such as a first insulating layer 101 (e.g., a first gate insulating layer) located between the first semiconductor layer 200 and the first conductive layer 300, a second insulating layer 102 (e.g., a capacitor dielectric layer) located between the first conductive layer 300 and the second conductive layer 400, a third insulating layer 103 (e.g., a buffer layer) located between the second conductive layer 400 and the second semiconductor layer 500, a fourth insulating layer 104 (e.g., a second gate insulating layer) located between the second semiconductor layer 500 and the third conductive layer 600, a fifth insulating layer 105 (e.g., an interlayer insulating layer) located between the third conductive layer 600 and the fourth conductive layer 700, and a sixth insulating layer 106 (e.g., a first planarization layer) located between the fourth conductive layer 700 and the fifth conductive layer 800.

[0047] Optionally, in one example, the material of the second conductive layer 400 may include a metal, and / or the material of the third conductive layer 600 may include a metal, and / or the material of the fourth conductive layer 700 may include a metal, and / or the material of the fifth conductive layer 800 may include a metal.

[0048] In another example, the material of the second conductive layer 400 may include a non-metallic conductive material, and / or the material of the third conductive layer 600 may include a non-metallic conductive material, and / or the material of the fourth conductive layer 700 may include a non-metallic conductive material, and / or the material of the fifth conductive layer 800 may include a non-metallic conductive material. For example, the non-metallic conductive material may include a metal oxide (e.g., indium tin oxide), graphene, a conductive semiconductor material, etc.

[0049] Optionally, the array substrate may further include a sixth conductive layer located on the side of the fifth conductive layer 800 away from the base 100, and a seventh insulating layer 107 (e.g., a second planarization layer) located between the fifth conductive layer 800 and the sixth conductive layer.

[0050] In some possible embodiments, referring to Figure 2 or Figure 4, the first semiconductor layer 200 further includes a third semiconductor wiring portion 203A corresponding to other transistors in the first driving unit 11 other than the first switching transistor T8-1 and the second switching transistor T8-2 of the first driving unit 11, and a fourth semiconductor wiring portion 204A corresponding to other transistors in the second driving unit 12 other than the first switching transistor T8-1 and the second switching transistor T8-2 of the second driving unit 12.

[0051] The third semiconductor wiring portion 203A and the fourth semiconductor wiring portion 204A are arranged symmetrically with respect to an axis of symmetry extending along the second direction D2, and the orthogonal projection of the axis of symmetry on the base 100 is located between the first scanning wiring 301 and the second scanning wiring 302.

[0052] For example, in this embodiment, except for the first switching transistor T8-1 and the second switching transistor T8-2, the other transistors in the first driving unit 11 and the other transistors in the second driving unit 12 may be distributed symmetrically in the first direction D1, so that the first driving unit 11 and the second driving unit 12 can share other wiring extending along the second direction D2, thereby further saving wiring space and ensuring uniformity in the layout of the switching transistors to reduce the risk of display unevenness.

[0053] 7 or 8, the first semiconductor layer 200 further includes a third semiconductor wiring portion 203B corresponding to the other transistors in the first driving unit 11 except for the first switching transistor T8-1, the second switching transistor T8-2, and the driving transistor T1 of the first driving unit 11, and a fourth semiconductor wiring portion 204B corresponding to the other transistors in the second driving unit 12 except for the first switching transistor T8-1, the second switching transistor T8-2, and the driving transistor T1 of the second driving unit 12.

[0054] The third semiconductor wiring portion 203B and the fourth semiconductor wiring portion 204B are arranged symmetrically with respect to an axis of symmetry extending along the second direction D2, and the orthogonal projection of the axis of symmetry on the base 100 is located between the first scanning wiring 301 and the second scanning wiring 302.

[0055] For example, in this embodiment, except for the first switching transistor T8-1, the second switching transistor T8-2 and the driving transistor T1, the other transistors in the first driving unit 11 and the other transistors in the second driving unit 12 may be distributed symmetrically in the first direction D1.

[0056] On the other hand, the semiconductor wiring portions corresponding to the driving transistors T1 are disposed asymmetrically with respect to the axis of symmetry extending along the second direction D2, that is, the driving transistors T1 are distributed asymmetrically in the first direction D1.

[0057] This allows the first driving unit 11 and the second driving unit 12 to share other wiring extending along the second direction D2, thereby further saving wiring space and ensuring uniformity in the layout of the switching transistors to reduce the risk of display unevenness.

[0058] 9 and 10 , in some embodiments, the array substrate further includes first initialization wiring 801 extending along the second direction D2. On the base 100, the orthogonal projection of the first initialization wiring 801 is located between the orthogonal projection of the first scan wiring 301 and the orthogonal projection of the second scan wiring 302.

[0059] The driving unit includes a driving transistor T1, which includes a first electrode, a second electrode, and a gate. The first driving unit 11 and the second driving unit 12 share a first initialization wiring 801. The first initialization wiring 801 is configured to provide a first initialization voltage to the first electrodes of the driving transistor T1 of the first driving unit 11 and the driving transistor T1 of the second driving unit 12. The first electrode and the second electrode may each be one of the source and drain of the driving transistor T1.

[0060] 6 and 9, the driving unit according to this embodiment may use an 8T1C driving circuit, and the core member of the driving unit may include a driving transistor T1. The driving transistor T1 of the first driving unit 11 is located on the side of the first scan line 301 that is farther from the second scan line 302, and the driving transistor T1 of the second driving unit 12 is located on the side of the second scan line 302 that is farther from the first scan line 301.

[0061] During the display process, in order to enhance the display effect, it is necessary to initialize the first electrode voltage of the driving transistor T1 at a specific time point, so that a wiring (i.e., a first initialization wiring 801) transmitting the first initialization voltage Vref3 needs to be installed on the array substrate.

[0062] 9, in the first driving unit 11 and the second driving unit 12 according to this embodiment, the transistors other than the first switching transistor T8-1 and the second switching transistor T8-2 are generally arranged symmetrically in the first direction D1. Therefore, the first initialization wiring 801 can be arranged so that the orthogonal projection of the first initialization wiring 801 on the base 100 is located between the orthogonal projection of the first scan wiring 301 on the base 100 and the orthogonal projection of the second scan wiring 302 on the base 100. This allows the first driving unit 11 and the second driving unit 12 to share the first initialization wiring 801, thereby reducing the number of wirings and saving wiring space.

[0063] In some embodiments, referring again to Figures 6 and 9, the first switching transistor T8-1 and the second switching transistor T8-2 are connected in series between the first electrode of the driving transistor T1 and the first initialization wiring 801, and the first switching transistor T8-1 and the second switching transistor T8-2 are used to perform voltage initialization control on the first electrode of the driving transistor T1.

[0064] That is, the gate of the first switching transistor T8-1 and the gate of the second switching transistor T8-2 are formed by the first scanning wiring 301 and the second scanning wiring 302, respectively, and the first scanning signal ScanP2 transmitted synchronously by the first scanning wiring 301 and the second scanning wiring 302 simultaneously controls the first switching transistor T8-1 and the second switching transistor T8-2 to turn on or off the electrical connection between the first electrode of the driving transistor T1 and the first initialization wiring 801, thereby realizing voltage initialization control for the first electrode of the driving transistor T1.

[0065] Specifically, the first initialization wiring 801 may be located on the fifth conductive layer 800 .

[0066] Furthermore, referring to Figures 1 and 10, the drive transistor T1 of the first drive unit 11 is located on the side of the first scanning wiring 301 that is away from the second scanning wiring 302, and the drive transistor T1 of the second drive unit 12 is located on the side of the second scanning wiring 302 that is away from the first scanning wiring 301.

[0067] The fourth conductive layer 700 includes a first connection wiring portion 701, a second connection wiring portion 702, and a third connection wiring portion 703. One end of the first semiconductor wiring portion 201 close to the first scanning wiring 301 is connected to the first electrode of the driving transistor T1 of the first driving unit 11 via the first connection wiring portion 701, and one end of the first semiconductor wiring portion 201 close to the second scanning wiring 302 is connected to the first initialization wiring 801 via the second connection wiring portion 702.

[0068] One end of the second semiconductor wiring portion 202 close to the second scanning wiring 302 is connected to the first electrode of the driving transistor T1 of the second driving unit 12 via the third connection wiring portion 703, and one end of the second semiconductor wiring portion 202 close to the first scanning wiring 301 is connected to the first initialization wiring 801 via the second connection wiring portion 702.

[0069] In some possible embodiments, the array substrate further includes second initialization wiring 901 extending along the second direction D2. Referring to Fig. 11, on the base 100, the orthogonal projection of the second initialization wiring 901 is located between the orthogonal projection of the first scan wiring 301 and the orthogonal projection of the second scan wiring 302. For example, the second initialization wiring 901 and the first initialization wiring 801 may be located on different layers, and on the base 100, the orthogonal projection of the second initialization wiring 901 and the orthogonal projection of the first initialization wiring 801 may at least partially overlap.

[0070] 1, the driving unit includes a pixel electrode connection point 120, which is electrically connected to the anode of the light-emitting sub-pixel and is used to transmit a driving signal to the anode. The first driving unit 11 and the second driving unit 12 share a second initialization wiring 901, which is used to provide the second initialization voltage Vref2 shown in FIG. 6 to the pixel electrode connection point 120 of the first driving unit 11 and the pixel electrode connection point 120 of the second driving unit 12. That is, the second initialization wiring 901 is used to provide the second initialization voltage Vref2 to the anode.

[0071] Since the first driving unit 11 and the second driving unit 12 according to this embodiment are installed substantially symmetrically in the first direction D1, the second initialization wiring 901 can be installed so that the orthogonal projection of the second initialization wiring 901 on the base 100 is located between the orthogonal projection of the first scanning wiring 301 on the base 100 and the orthogonal projection of the second scanning wiring 302 on the base 100. This allows the first driving unit 11 and the second driving unit 12 to share the second initialization wiring 901, thereby reducing the number of wirings and saving wiring space.

[0072] 11 , in some embodiments, the second initialization wiring 901 includes a first portion 601 located on the third conductive layer 600 and a second portion 704 located on the fourth conductive layer 700. The first portion 601 and the second portion 704 are alternately arranged along the second direction D2 to avoid other wirings arranged on the same layer and extending along the first direction D1. The first portion 601 and the second portion 704 may be electrically connected to each other via through holes that penetrate a portion of an insulating layer of the array substrate.

[0073] In some embodiments, the driving unit includes a third switching transistor T7. Referring again to FIG. 6, the third switching transistor T7 is connected between the pixel electrode node 120 and the second initialization wiring 901 and is used to perform voltage initialization control for the pixel electrode node 120.

[0074] Specifically, the third switching transistor T7 of the first driving unit 11 may be formed by an overlap between the third semiconductor wiring portion 203 and the first scan wiring 301 in the first driving unit 11. The third switching transistor T7 of the second driving unit 12 may be formed by an overlap between the fourth semiconductor wiring portion 204 and the second scan wiring 302 in the second driving unit 12. A signal transmitted by the first scan wiring 301 or the second scan wiring 302 can control the third switching transistor T7 to turn on or off the electrical connection between the pixel electrode connection point 120 and the second initialization wiring 901, thereby realizing voltage initialization control for the pixel electrode connection point 120.

[0075] 12 or 13, in some embodiments, the array substrate includes a plurality of first driving unit groups 10, and each first driving unit group 10 includes one first driving unit 11 and one second driving unit 12. The first driving unit 11 and the second driving unit 12 in the same first driving unit group 10 share the first scanning wiring 301 and the second scanning wiring 302.

[0076] The array substrate further includes a third initialization wiring 902, and the orthogonal projection of the third initialization wiring 902 on the base 100 is located between two adjacent first driving unit groups 10 in the first direction D1. The first driving unit 11 and the second driving unit 12 that belong to different first driving unit groups 10 and are adjacent in the first direction D1 share the third initialization wiring 902. This reduces the number of wirings and saves wiring space. The third initialization wiring 902 is used to provide the third initialization voltage Vref1 shown in FIG. 6 to the gate of the driving transistor T1.

[0077] 12 or 13 , in some embodiments, the third initialization wiring 902 includes a third portion located on the first conductive layer 300 and / or the fourth conductive layer 700, and a fourth portion 802 located on the fifth conductive layer 800. The third portion and the fourth portion 802 are alternately arranged along the second direction D2, and the fourth portion 802 includes a transparent openwork region 30.

[0078] For example, the third portion includes the first extension 303 located on the first conductive layer 300 or the second extension 705 located on the fourth conductive layer 700 .

[0079] Alternatively, the third portion includes both the first extension portion 303 and the second extension portion 705, and the orthogonal projections of the first extension portion 303 and the second extension portion 705 on the base 100 at least partially overlap. This reduces the electrical resistance of the third portion, and further reduces the overall resistance of the third initialization wiring 902.

[0080] The third portion and the fourth portion 802 both extend along the second direction D2 and are arranged alternately to form the third initialization wiring 902. The third portion and the fourth portion 802 are electrically connected via through holes in the insulating layer between at least some of the metal layers.

[0081] Here, the fourth portion 802 extending in the fifth conductive layer 800 has an openwork area 30, and the orthogonal projection of the openwork area 30 on the base 100 does not at least partially overlap with the orthogonal projection of the wiring in other layers. In this way, the openwork area 30 forms a light-transmitting area, which can improve the light transmittance of the array substrate.

[0082] 6, in some embodiments, the driving unit includes a fourth switching transistor T3 and a fifth switching transistor T4, which are connected between the gate of the driving transistor T1 and the third initialization wiring 902, and are used to perform voltage initialization control on the gate of the driving transistor T1.

[0083] 14, the fourth switching transistor T3 may be formed by combining the third scanning line 603 in the third conductive layer 600 and the fifth semiconductor wiring portion 501 in the second semiconductor layer 500. The fifth switching transistor T4 may be formed by combining the fourth scanning line 604 in the third conductive layer 600 and the sixth semiconductor wiring portion 502 in the second semiconductor layer 500.

[0084] The second scanning signal ScanN2 transmitted by the third scanning line 603 and the third scanning signal ScanN1 transmitted by the fourth scanning line 604 can control the fourth switching transistor T3 and the fifth switching transistor T4 to turn on or off the electrical connection between the gate of the driving transistor T1 and the third initialization line 902, thereby realizing voltage initialization control for the gate of the driving transistor T1.

[0085] 6 and 15 , in some embodiments, the array substrate may include a first scan line 301 transmitting a first scan signal ScanP2, a second scan line 302 transmitting the first scan signal ScanP2, a third scan line 603 transmitting a second scan signal ScanN2, a fourth scan line 604 transmitting a third scan signal ScanN1, a fifth scan line 305 transmitting a fourth scan signal ScanP1, and an emission control line 306 transmitting an emission control signal EM. Here, the first scan line 301, the second scan line 302, the fifth scan line 305, and the emission control line 306 are located on a first conductive layer 300, and the third scan line 603 and the fourth scan line 604 are located on a third conductive layer 600.

[0086] The driving unit may include a driving transistor T1, an eighth switching transistor T2, a fourth switching transistor T3, a fifth switching transistor T4, a sixth switching transistor T5, a seventh switching transistor T6, a third switching transistor T7, a first switching transistor T8-1 and a second switching transistor T8-2.

[0087] Here, the driving transistor T1 is formed by combining the semiconductor wiring portion of the first semiconductor layer 200 and the gate electrode of the first conductive layer 300.

[0088] The eighth switching transistor T2 is formed by combining the fifth scanning wiring 305 and the semiconductor wiring portion of the first semiconductor layer 200, and the eighth switching transistor T2 performs data writing control on the capacitor Cst in the driving unit based on the fourth scanning signal ScanP1 transmitted by the fifth scanning wiring 305.

[0089] The fourth switching transistor T3 is formed by combining the third scanning line 603 of the third conductive layer 600 and the semiconductor wiring portion of the second semiconductor layer 500. The fourth switching transistor T3 is used to perform voltage compensation control on the driving transistor T1 based on the second scanning signal ScanN2 transmitted by the third scanning line 603.

[0090] The fifth switching transistor T4 is formed by combining the fourth scanning line 604 of the third conductive layer 600 and the semiconductor wiring portion of the second semiconductor layer 500. The fourth switching transistor T3 and the fifth switching transistor T4 are used to execute voltage initialization control on the gate of the driving transistor T1 based on the second scanning signal ScanN2 transmitted by the third scanning line 603 and the third scanning signal ScanN1 transmitted by the fourth scanning line 604, respectively.

[0091] The sixth switching transistor T5 and the seventh switching transistor T6 are formed by combining the light emission control wiring 306 of the first conductive layer 300 and the semiconductor wiring portion of the first semiconductor layer 200. The sixth switching transistor T5 and the seventh switching transistor T6 perform light emission enable control on the driving unit based on the light emission control signal EM transmitted by the light emission control wiring 306.

[0092] The third switching transistor T7 is formed by combining one of the first scanning line 301 and the second scanning line 302 with the semiconductor wiring portion of the first semiconductor layer 200. The third switching transistor T7 performs voltage initialization control on the pixel electrode connection point of the driving unit based on the first scanning signal ScanP2 transmitted by the first scanning line 301 or the second scanning line 302.

[0093] The first switching transistor T8-1 and the second switching transistor T8-2 are formed by combining the first scanning line 301 and the second scanning line 302 with the semiconductor wiring portion of the first semiconductor layer 200. The first switching transistor T8-1 and the second switching transistor T8-2 are used to perform voltage initialization control on the first electrode of the drive transistor T1 based on the first scanning signal ScanP2 transmitted by the first scanning line 301 and the second scanning line 302.

[0094] 16 , in some embodiments, the array substrate further includes a plurality of fourth initialization wirings 304 extending along the first direction D1. Optionally, the fourth initialization wirings 304 may be located on the fourth conductive layer 700, the fourth initialization wirings 304 and the second initialization wirings 901 may be electrically connected via through holes that penetrate at least one insulating layer, and the fourth initialization wirings 304 and the second initialization wirings 901 may be entangled to form a mesh structure.

[0095] The array substrate includes a plurality of second driving unit groups 20, each of which includes two driving units adjacent to each other in the second direction D2. The two driving units in the same second driving unit group 20 are arranged symmetrically with respect to one fourth initialization wiring 304.

[0096] 18 to 22, in addition to the above-mentioned wirings, each layer of the array substrate according to this embodiment may have more other wirings or wiring portions. Here, in the array substrate according to this embodiment, the first driving unit 11 and the second driving unit 12 adjacent to each other in the first direction D1 are arranged symmetrically in the first direction D1, so that the first driving unit 11 and the second driving unit 12 can share at least a part of the signal wiring or power wiring extending along the second direction D2, thereby saving wiring space on the array substrate.

[0097] Therefore, in some embodiments, the array substrate according to this embodiment may have a predetermined light leakage gap 40. For example, referring to FIG. 17, in the second direction D2, the light leakage gap 40 is located between the drive transistors T1 (e.g., shown by the elliptical dashed-line frame in FIG. 14) of two adjacent drive units belonging to different second drive unit groups 20. That is, on the base 100, the orthogonal projection of the light leakage gap 40 does not overlap with the orthogonal projection of the wiring on any layer. Therefore, the wiring on each layer does not block the transmission of light through the light leakage gap 40. In this way, the overall light transmittance of the array substrate can be improved, and the collection effect of the under-screen optical collection device installed under the display panel can be improved.

[0098] The present application further provides a display panel, which includes the array substrate according to the present application.

[0099] In some embodiments, the display panel further includes a light-emitting layer disposed on one side of the array substrate, which may include a pixel defining layer, a light-emitting material layer, a cathode layer, a sealing layer, and other layers, the details of which are omitted here.

[0100] In another embodiment, the display panel further includes a light-emitting layer located on one side of the array substrate. The light-emitting layer may include a plurality of layer structures, such as a pixel defining layer, an isolation structure, a light-emitting material layer, a cathode layer, and an encapsulation layer. Related technologies for isolation structures are described in PCT / CN2023 / 134518, Chinese Patent No. 202310759370.2, Chinese Patent No. 202310740412.8, Chinese Patent No. 202310707209.0, and Chinese Patent No. 202311346196.5, the contents of which are incorporated herein by reference, and will not be described further in this embodiment.

[0101] The present application further provides an electronic device, which includes the display panel of the present application, and may include devices with display capabilities, such as mobile phones, tablet computers, smart wearable devices, televisions, laptops, and displays.

[0102] As described above, the present application provides an array substrate, a display panel, and an electronic device, in which two adjacent driving units in a first direction on the array substrate are arranged to share a first scanning wiring and a second scanning wiring, so that the semiconductor wiring portions in these driving units extend along a straight line and overlap with the first scanning wiring and the second scanning wiring, respectively, to form a first switching transistor and a second switching transistor, thereby reducing the space occupied by the semiconductor wiring portions.

[0103] The technical configurations of the above embodiments can be combined in any manner, and in order to simplify the explanation, not all possible combinations of the technical configurations in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical configurations, it should be understood that they fall within the scope described in this specification.

[0104] The above examples merely illustrate some embodiments of the present application, and although the description is specific and detailed, it should not be understood as a limitation on the scope of the patent. It should be noted that a person skilled in the art may make some modifications and improvements without departing from the spirit of the present application, and all of these fall within the scope of protection of the present application. Therefore, the scope of protection of the present application should be governed by the appended claims. [Explanation of symbols]

[0105] 10 First drive unit group 11 First drive unit 12 Second drive unit 20 Second drive unit group 30 Openwork Area 40 Light leakage gap 100 base 101 First insulating layer 102 Second insulating layer 103 Third insulating layer 104 Fourth insulating layer 105 5th insulating layer 106 6th insulating layer 107 7th insulating layer 120 pixel electrode connection point 200 First semiconductor layer 201 First semiconductor wiring section 202 Second semiconductor wiring section 203 Third semiconductor wiring section 204 4th semiconductor wiring section 300 First conductive layer 301 First scanning wiring 302 Second scanning wiring 303 1st extension part 304 4th initialization wiring 305 5th scanning line 306 Light emission control wiring 400 Second conductive layer 500 Second semiconductor layer 501 5th Semiconductor Wiring Section 502 6th Semiconductor Wiring Section 600 Third conductive layer 601 Part 1 603 3rd scanning wiring 604 4th scanning wiring 700 4th conductive layer 701 First connection wiring section 702 Second connection wiring section 703 Third connection wiring section 704 Part 2 705 2nd extension part 800 5th conductive layer 801 1st initialization wiring 802 Part 4 901 2nd initialization wiring 902 3rd initialization wiring D1 1st direction D2 2nd direction T1 drive transistor T2 8th switching transistor T3 Fourth switching transistor T4 Fifth switching transistor T5 Sixth switching transistor T6 Seventh switching transistor T7 Third switching transistor T8-1 First switching transistor T8-2 Second switching transistor

Claims

1. An array substrate, a base; a first semiconductor layer located on one side of the base; and a first conductive layer located on a side of the first semiconductor layer away from the base, the first semiconductor layer includes a first semiconductor wiring portion and a second semiconductor wiring portion, the first semiconductor wiring portion and the second semiconductor wiring portion extending in parallel along a first direction; the first conductive layer includes first and second scanning wirings used to synchronously transmit the same scanning signal, the first and second scanning wirings extending in parallel along a second direction, and the first and second directions intersecting; the array substrate includes a plurality of driving units, each of which has a first electrode of a driving transistor transmitting a driving signal to an anode of a pixel through a pixel electrode connection point, thereby driving the pixel to emit light, the plurality of driving units including a first driving unit and a second driving unit adjacent to each other in the first direction; In the first direction, the first driving unit is located on a side of the first scanning wiring that is farther from the second scanning wiring, and the second driving unit is located on a side of the second scanning wiring that is farther from the first scanning wiring, on the base, an orthogonal projection of the first semiconductor wiring portion at least partially overlaps with an orthogonal projection of the first scanning wiring and an orthogonal projection of the second scanning wiring, respectively, and a first switching transistor and a second switching transistor of the first driving unit are located at positions where an orthogonal projection of the first semiconductor wiring portion overlaps with an orthogonal projection of the first scanning wiring and an orthogonal projection of the second scanning wiring; on the base, an orthogonal projection of the second semiconductor wiring portion at least partially overlaps with an orthogonal projection of the first scanning wiring and an orthogonal projection of the second scanning wiring, respectively, and a first switching transistor and a second switching transistor of the second driving unit are located at positions where an orthogonal projection of the second semiconductor wiring portion overlaps with an orthogonal projection of the first scanning wiring and an orthogonal projection of the second scanning wiring; the array substrate further includes a first initialization wiring, and the driving unit further includes a driving transistor, the first initialization wiring being used to provide a first initialization voltage to a first electrode of the driving transistor so as to perform voltage initialization on the driving transistor; the first switching transistor and the second switching transistor being connected in series between the first electrode of the driving transistor and the first initialization wiring, and being controlled to be turned on or off simultaneously, thereby turning on or off an electrical connection between the first electrode of the driving transistor and the first initialization wiring, and controlling the voltage initialization on the first electrode of the driving transistor; 1. An array substrate comprising:

2. the first semiconductor layer further includes a third semiconductor wiring portion corresponding to a third switching transistor in the first driving unit excluding the first switching transistor and the second switching transistor of the first driving unit, and a fourth semiconductor wiring portion corresponding to a third switching transistor in the second driving unit excluding the first switching transistor and the second switching transistor of the second driving unit, the third semiconductor wiring portion and the fourth semiconductor wiring portion are disposed symmetrically with respect to an axis of symmetry extending along the second direction, the array substrate further includes second initialization wiring, the second initialization wiring being used to provide a second initialization voltage to the pixel electrode connection point, and the third switching transistor being used to turn on or off an electrical connection between the pixel electrode connection point and the second initialization wiring based on signals transmitted by the first scanning wiring and the second scanning wiring, thereby controlling voltage initialization for the pixel electrode connection point; an orthogonal projection of the axis of symmetry at the base is located between the first scanning wiring and the second scanning wiring; 2. The array substrate according to claim 1.

3. the first semiconductor layer further includes: a third semiconductor wiring portion corresponding to a third switching transistor in the first driving unit excluding the first switching transistor, the second switching transistor, and the driving transistor of the first driving unit; and a fourth semiconductor wiring portion corresponding to a third switching transistor in the second driving unit excluding the first switching transistor, the second switching transistor, and the driving transistor of the second driving unit; the third semiconductor wiring portion and the fourth semiconductor wiring portion are disposed symmetrically with respect to an axis of symmetry extending along the second direction, the array substrate further includes second initialization wiring, the second initialization wiring being used to provide a second initialization voltage to the pixel electrode connection point so as to perform voltage initialization on the pixel electrode connection point, and the third switching transistor being used to turn on or off an electrical connection between the pixel electrode connection point and the second initialization wiring based on signals transmitted by the first scanning wiring and the second scanning wiring, thereby controlling the voltage initialization on the pixel electrode connection point; an orthogonal projection of the symmetry axis on the base is located between the first scanning wiring and the second scanning wiring; the semiconductor wiring portion corresponding to the driving transistor is disposed asymmetrically with respect to an axis of symmetry extending along the second direction; 2. The array substrate according to claim 1.

4. The first initialization wiring extends along the second direction, and at the base, an orthogonal projection of the first initialization wiring is located between an orthogonal projection of the first scanning wiring and an orthogonal projection of the second scanning wiring; the first driving unit and the second driving unit share the first initialization wiring; 2. The array substrate according to claim 1.

5. the first switching transistor and the second switching transistor are connected in series between the first electrode of the drive transistor and the first initialization wiring; 5. The array substrate according to claim 4.

6. the array substrate further includes a fifth conductive layer located on a side of the first conductive layer away from the base, the first initialization wiring being located on the fifth conductive layer; the material of the first conductive layer includes a metal; the material of the fifth conductive layer includes a metal; 5. The array substrate according to claim 4.

7. the array substrate further includes a fourth conductive layer located on a side of the first conductive layer away from the base, the fourth conductive layer including a first connection wiring portion; 5. The array substrate according to claim 4.

8. a driving transistor of the first driving unit is located on a side of the first scanning wiring that is distant from the second scanning wiring, and a driving transistor of the second driving unit is located on a side of the second scanning wiring that is distant from the first scanning wiring, one end of the first semiconductor wiring portion close to the first scanning wiring is connected to a first electrode of a driving transistor of the first driving unit via the first connection wiring portion, and one end of the first semiconductor wiring portion close to the second scanning wiring is connected to the first initialization wiring via the first connection wiring portion; one end of the second semiconductor wiring portion close to the second scanning wiring is connected to a first electrode of a driving transistor of the second driving unit via the first connection wiring portion, and one end of the second semiconductor wiring portion close to the first scanning wiring is connected to the first initialization wiring via the first connection wiring portion; 8. The array substrate according to claim 7.

9. the array substrate further includes second initialization wiring extending along the second direction, and an orthogonal projection of the second initialization wiring is located between an orthogonal projection of the first scan wiring and an orthogonal projection of the second scan wiring on the base; the first driving unit and the second driving unit share the second initialization wiring, and the second initialization wiring is used to provide a second initialization voltage to the pixel electrode connection point between the first driving unit and the second driving unit so as to perform voltage initialization on the pixel electrode connection point; 2. The array substrate according to claim 1.

10. the array substrate further includes a third conductive layer and a fourth conductive layer located on a side of the first conductive layer away from the base, the second initialization wiring includes a first portion located on the third conductive layer and a second portion located on the fourth conductive layer, the first portion and the second portion being alternately disposed along the second direction; a material of at least one of the third conductive layer or the fourth conductive layer includes a metal; 10. The array substrate according to claim 9.

11. the driving unit includes a third switching transistor connected between the pixel electrode connection point and the second initialization wiring, the third switching transistor being used to turn on or off an electrical connection between the pixel electrode connection point and the second initialization wiring to control a voltage initialization for the pixel electrode connection point; 10. The array substrate according to claim 9.

12. the array substrate includes a plurality of first driving unit groups, each of the first driving unit groups including one of the first driving units and one of the second driving units, the first driving unit and the second driving unit in the same first driving unit group sharing the first scanning wiring and the second scanning wiring; the array substrate further includes third initialization wiring, an orthogonal projection of the third initialization wiring at the base is located between two adjacent first driving unit groups in the first direction, and the first driving unit and the second driving unit, which belong to different first driving unit groups and are adjacent in the first direction, share the third initialization wiring; the driving unit includes a driving transistor, and the third initialization wiring is connected to a gate of the driving transistor via the first electrode and is used to provide a third initialization voltage to the gate of the driving transistor; 2. The array substrate according to claim 1.

13. the array substrate further includes a fourth conductive layer and a fifth conductive layer located on sides of the first conductive layer away from the base; the third initialization wiring includes a third portion located in at least one of the first conductive layer or the fourth conductive layer and a fourth portion located in the fifth conductive layer, the third portion and the fourth portion being alternately arranged along the second direction, and the fourth portion includes a light-transmitting openwork region; 13. The array substrate according to claim 12.

14. the driving unit includes a fourth switching transistor and a fifth switching transistor, the fourth switching transistor is connected between the gate of the driving transistor and the first electrode, and the fifth switching transistor is connected between the first electrode and the third initialization wiring, and the fourth switching transistor and the fifth switching transistor are used to turn on or off an electrical connection between the gate of the driving transistor and the third initialization wiring to control a voltage initialization for the gate of the driving transistor.

13. The array substrate according to claim 12.

15. the array substrate further includes a plurality of fourth initialization wirings extending along the second direction; the array substrate includes a plurality of second driving unit groups, each of the second driving unit groups including two of the driving units adjacent to each other in the second direction; two of the driving units in the same second driving unit group are installed symmetrically with respect to one of the fourth initialization wirings, In the second direction, there is a light leakage gap between the drive transistors of two adjacent drive units that belong to different second drive unit groups.

2. The array substrate according to claim 1.

16. A display panel comprising the array substrate according to any one of claims 1 to 15.

17. An electronic device comprising the display panel according to claim 16.

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