Semiconductor chip manufacturing method

Abstract

To prevent generation of a crack extending from a side face to the inside and an excessive distortion on the side face.SOLUTION: A one face 110a and the other face 110b are arranged along either one face among a {0001}c face, {0-100}m face, and a {11-20}a face. Among two opposing pairs of side faces 110c, one pair of side faces 110c are arranged along one face among the {0001}c face, the {0-100}m face, and the {11-20}a face, and along one face among the other face and remaining different two faces. Among the two opposing pairs of side faces 110c, the other pair of side faces 110c are arranged along one face 110a among the {0001}c face, the {0-100}m face, and the {11-20}a face, the other face 110b, and one face different from the one side face 110c. When a direction of a line normal to the side face 110c is a depth direction, the side face 110c is constituted while including an alteration layer 120 containing gallium oxide and gallium metal.SELECTED DRAWING: Figure 1I

Description

[Technical Field]

[0001] The present invention relates to a semiconductor chip having a chip structure substrate including gallium nitride (hereinafter also simply referred to as GaN). P's It relates to a manufacturing method. [Background technology]

[0002] Conventionally, a method for manufacturing semiconductor chips by dividing a processed wafer into chip units has been proposed (see, for example, Patent Document 1). Specifically, in this manufacturing method, a processed wafer containing gallium oxide is prepared, in which a plurality of chip formation regions are defined by dicing lines. Then, in this manufacturing method, a laser beam is irradiated along the dicing lines to form an altered layer, and then the dicing lines are cut with a dicing blade to divide the wafer into chip units, thereby manufacturing semiconductor chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-126838 Summary of the Invention [Problem to be solved by the invention]

[0004] The present inventors have been studying the manufacture of semiconductor chips using processed wafers containing GaN, which has advantages such as a wide band gap and a high electron saturation velocity, and have confirmed that when dividing such processed wafers into chips, cracks may occur extending from the side surfaces of the divided chips to the interior, or excessive distortion may occur on the side surfaces.

[0005] In view of the above, the present invention provides a semiconductor chip that can suppress the occurrence of cracks extending from the side surface to the inside and the occurrence of excessive strain on the side surface. P's The object is to provide a manufacturing method. [Means for solving the problem]

[0008] Claim 1 to achieve the above object is as follows: A method for manufacturing a semiconductor chip includes the steps of: preparing a processed wafer (10) having one surface (10a) and another surface (10b), comprising hexagonal gallium nitride, and having a plurality of chip formation areas (RA) partitioned by cutting lines (SL); and forming a chip altered layer (14) by separating nitrogen from gallium along the cutting lines by irradiating the processed wafer with laser light (L); After forming the deteriorated layer for chips, irradiating the other surface of the processed wafer with laser light (L) to form an deteriorated layer for wafer (15) along the surface direction of the processed wafer, dividing the recycled wafer (40) from the processed wafer at the deteriorated layer for wafer as a boundary, and using the divided surface of the processed wafer as the other surface of the processed wafer; By dividing the chip formation region at the chip alteration layer as a boundary, a chip configuration substrate is formed from the processed wafer, which has one surface (110a) formed by one surface of the processed wafer, another surface (110b) formed by the other surface of the processed wafer, and two pairs of opposing side surfaces (110c) that are surfaces along the cutting line and connect the one surface and the other surface, and by forming the chip configuration substrate, the one surface and the other surface are formed in the {0001}c plane, { 1 -100}m plane and one of the {11-20}a planes, and one of the two pairs of opposing sides is along the {0001}c plane, { 1 -100}m plane and one of the two remaining planes different from one plane and the other plane in the {11-20}a plane, and the other of the two pairs of opposing sides is the {0001}c plane, { 1 The chip-forming substrate has a surface along one of the {11-20}a-planes, one of the {11-20}a-planes, and the other of the {11-20}a-planes, which is different from one of the opposing side surfaces, and further, when the normal direction to the side surface is defined as the depth direction, an altered layer (120) containing gallium oxide and gallium metal is formed on the surface layer of the side surface in the depth direction. In forming the deteriorated layer for the chip and forming the deteriorated layer for the wafer, the deteriorated layer for the wafer is formed so as to intersect with the deteriorated layer for the chip. .

[0009] This allows the manufacture of semiconductor chips whose side surfaces are aligned along the plane that is easy to cleave. Therefore, when the semiconductor chips are separated from the processed wafer, it is possible to prevent cracks that extend inward from occurring on the side surfaces and to prevent excessive distortion on the side surfaces. Furthermore, the semiconductor chips have surface layers on the side surfaces that include altered layers containing gallium oxide. This also allows for improved insulation of the side surfaces.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0011] [Figure 1A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor chip according to the first embodiment. [Figure 1B] 1B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1A. [Figure 1C] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1B. [Figure 1D] 1D is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1C. [Figure 1E] 1D and 1E are cross-sectional views showing the manufacturing process of the semiconductor chip subsequent to FIG. [Figure 1F] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1E. [Figure 1G] 1F is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1F. [Figure 1H] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1G. [Figure 1I] 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1H. [Figure 1J] 1I. FIG. [Figure 2] FIG. 2 is a schematic diagram of a processed wafer. [Figure 3A] 10 is a schematic diagram illustrating a case where a deteriorated layer for a wafer is formed without forming a deteriorated layer for a chip. FIG. [Figure 3B]10 is a schematic diagram illustrating a case where a deteriorated layer for a chip is formed and then a deteriorated layer for a wafer is formed. FIG. [Figure 4] FIG. 2 is a schematic diagram of a chip configuration substrate. [Figure 5] FIG. 1 shows a spectrum obtained by X-ray photoelectron spectroscopy. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) The first embodiment will be described with reference to the drawings. A method for manufacturing a semiconductor chip 100 in which semiconductor elements are formed on a chip substrate 110 containing GaN will be described below. Note that, when indicating a crystal orientation, a bar (-) should normally be placed above the desired number, but due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification.

[0014] First, as shown in Fig. 1A, a bulk GaN wafer 1 having one surface 1a and the other surface 1b is prepared. For example, the GaN wafer 1 is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of 5 × 10 17 ~5×10 19 cm -3 The thickness of the GaN wafer 1 is arbitrary, but for example, a thickness of about 400 μm is prepared.

[0015] The GaN wafer 1 of this embodiment is formed of a hexagonal crystal, with one surface 1a and the other surface 1b being the {0001} c-plane. The GaN wafer 1 of this embodiment has one surface 1a being the (0001) Ga-plane and the other surface 1b being the (000-1) N-plane. After the manufacturing process of the semiconductor chip 100 described below is performed, this GaN wafer 1 is prepared by reusing a recycled wafer 40 shown in FIG. 1J, which will be described later. If necessary, a protective film made of an oxide film or the like may be formed on the other surface 1b of the GaN wafer 1.

[0016] Next, as shown in FIG. 1B, an epitaxial film 3 made of GaN having a thickness of about 10 to 60 μm is formed on one surface 1a of the GaN wafer 1 to prepare a processed wafer 10 in which a plurality of chip formation regions RA are partitioned by cutting lines SL. In this embodiment, the epitaxial film 3 is + type epitaxial layer 3a and n - The n-type epitaxial layer 3b is formed in this order from the GaN wafer 1 side. + The epitaxial layer 3a is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of 5×10 17 ~1×10 18 cm -3 It is said to be about. - The epitaxial layer 3b is doped with silicon or the like, and the impurity concentration is 1×10 17 ~4×10 17 cm -3 It is said to be about that level.

[0017] In addition, n - The epitaxial layer 3b is a portion on which the first surface side element components 11 such as the diffusion layer 12 described later are formed, and has a thickness of, for example, about 8 to 10 μm. + The n-type epitaxial layer 3a is a portion for ensuring the thickness of the semiconductor chip 100, which will be described later, and has a thickness of, for example, about 40 to 50 μm. + type epitaxial layer 3a and n - The thickness of the n-type epitaxial layer 3b can be arbitrarily determined, but in this case, the thickness of the n-type epitaxial layer 3b is set to ensure the thickness of the semiconductor chip 100.+ The n-type epitaxial layer 3a - It is thicker than the type epitaxial layer 3b.

[0018] Hereinafter, the surface of the processed wafer 10 facing the epitaxial film 3 will be referred to as one surface 10a of the processed wafer 10, and the surface of the processed wafer 10 facing the GaN wafer 1 will be referred to as the other surface 10b of the processed wafer 10. As described above, the GaN wafer 1 is constructed of a hexagonal crystal, the epitaxial film 3 is formed on the one surface 1a of the GaN wafer 1, and the other surface 10b of the processed wafer 10 is constructed of the other surface 1b of the GaN wafer 1. Therefore, the processed wafer 10 is constructed of a hexagonal crystal, and the one surface 10a and the other surface 10b are {0001}c-planes. Each chip formation region RA is constructed on the one surface 10a of the processed wafer 10.

[0019] 1C, a typical semiconductor manufacturing process is performed to form first-surface element components 11 of the semiconductor element, such as diffusion layers 12, gate electrodes 13, surface electrodes (not shown), wiring patterns, and passivation films, in each chip formation area RA. The semiconductor elements employed here may have a variety of configurations, including power devices such as high electron mobility transistors (HEMTs) and optical semiconductor elements such as light-emitting diodes. Thereafter, if necessary, a surface protection film made of resist or the like is formed on the first surface 10a of the processed wafer 10.

[0020] Next, as shown in FIG. 1D, a holding member 20 is placed on one surface 10a of the processed wafer 10. The holding member 20 may be, for example, a dicing tape having a base material 21 and an adhesive 22. The base material 21 is made of a material that is resistant to warping during the manufacturing process, such as glass, a silicon substrate, or ceramics. The adhesive 22 is made of a material whose adhesive strength can be changed, such as a material whose adhesive strength changes depending on temperature or light. In this case, the adhesive 22 may be made of, for example, an ultraviolet-curing resin, wax, or double-sided tape. However, the adhesive 22 is made of a material that maintains its adhesive strength even when forming the other-surface element component 60 shown in FIG. 1H, which will be described later.

[0021] Next, as shown in FIG. 1E, laser light L is irradiated from the other surface 10b of the processed wafer 10 to form chip-forming altered layers 14 along the cutting lines SL. In this embodiment, as shown in FIG. 2, the planar shape of each chip forming area RA surrounded by the cutting lines SL is rectangular. Also, in this embodiment, each chip forming area RA has a surface divided into chip units that is { 1 -100}m plane or {11-20}a plane. 1 The tip-forming altered layer 14 is adjusted to extend along the {-100}m plane or the {11-20}a plane. 1 The tip-forming affected layer 14 is formed so as to extend along the {-100}m plane or the {11-20}a plane. In other words, the tip-forming affected layer 14 is formed along a plane that is easy to cleave in the hexagonal crystal.

[0022] In this embodiment, this step involves preparing a laser device including a laser light source that oscillates laser light L, a dichroic mirror arranged to change the direction of the optical axis (i.e., optical path) of the laser light, a focusing lens (i.e., focusing optical system) for focusing the laser light, a displaceable stage, etc. When forming the chip-forming altered layer 14, the processed wafer 10 is placed on the stage, and the position of the stage, etc. is adjusted so that the focusing point of the laser light L is relatively scanned along the cutting line SL.

[0023] As a result, the thermal energy decomposes gallium and nitrogen to form a chip-forming altered layer 14 at the cutting line SL. More specifically, the application of the laser light L causes nitrogen to evaporate as a gas and gallium to precipitate, forming the chip-forming altered layer 14. Note that the chip-forming altered layer 14 is in a state where minute voids are formed due to the separation of nitrogen.

[0024] Furthermore, in this embodiment, when forming the chip-forming deteriorated layer 14, the stage or the like is moved appropriately, and the laser light L is irradiated so that the focal point moves to two or more different locations in the thickness direction of the processed wafer 10. In this case, the chip-forming deteriorated layers 14 are formed at different locations in the thickness direction of the processed wafer 10, and the chip-forming deteriorated layers 14 may be separated from each other or may be connected. Furthermore, when the focal point is moved to two or more different locations in the thickness direction of the processed wafer 10, the focal point is moved from one surface 10a side to the other surface 10b side of the processed wafer 10.

[0025] In this embodiment, the chip-deteriorated layer 14 is formed so that nitrogen generated by forming the wafer-deteriorated layer 15 shown in FIG. 1F can be released to the outside through pores in the chip-deteriorated layer 14. Although not particularly limited, in this embodiment, when forming the chip-deteriorated layer 14, a solid-state green laser with a wavelength of 532 nm is used as the laser light L. The laser light L is irradiated with a processing point output of 2 μJ, a pulse width of 500 ps, ​​and a processing speed of 500 mm / s. However, these conditions are merely examples, and the inventors have confirmed that the chip-deteriorated layer 14 can be appropriately formed even when the processing point output of the laser light L is lower or the pulse width is shorter. The inventors have also confirmed that the chip-deteriorated layer 14 can be appropriately formed even when the processing point output of the laser light L is higher or the pulse width is longer.

[0026] 1F, laser light L is applied from the other surface 10b of the processed wafer 10 to form a wafer-deteriorated layer 15 along the surface direction of the processed wafer 10 at a position at a predetermined depth D from the one surface 10a of the processed wafer 10. In this embodiment, the wafer-deteriorated layer 15 is formed using the laser device used to form the chip-deteriorated layer 14.

[0027] When forming the wafer-deteriorated layer 15, the position of a stage or the like is adjusted so that the focal point of the laser light L is scanned relatively along the surface direction of the processed wafer 10. As a result, the wafer-deteriorated layer 15 is formed along the surface direction of the processed wafer 10. Note that, like the chip-deteriorated layer 14, the wafer-deteriorated layer 15 is configured such that nitrogen evaporates as a gas and gallium is precipitated.

[0028] In this case, in this embodiment, the wafer-use damaged layer 15 is formed so as to intersect with the chip-use damaged layer 14 or pass directly below the chip-use damaged layer 14. This makes it possible to prevent large distortions from being applied to each chip formation region RA when the wafer-use damaged layer 15 is formed.

[0029] That is, if the chip-use damaged layer 14 is not formed, as shown in FIG. 3A, the nitrogen generated during the formation of the wafer-use damaged layer 15 is difficult to release to the outside, and the distortion of the processed wafer 10 due to the formation of the wafer-use damaged layer 15 is likely to increase. In contrast, in this embodiment, the chip-use damaged layer 14 is formed, and the wafer-use damaged layer 15 is formed so as to intersect with the chip-use damaged layer 14 or pass directly below the chip-use damaged layer 14. Therefore, as shown in FIG. 3B, the nitrogen generated during the formation of the wafer-use damaged layer 15 is easily released to the outside through the pores in the chip-use damaged layer 14. Therefore, the distortion of the processed wafer 10 due to the formation of the wafer-use damaged layer 15 can be suppressed, and the distortion applied to each chip formation region RA can be reduced.

[0030] Although not particularly limited, in this embodiment, when forming the wafer-deteriorated layer 15, a solid-state laser beam, a green laser beam with a wavelength of 532 nm, is used as the laser beam L. The laser beam L is irradiated with a processing point output of 0.1 to 0.3 μJ, a pulse width of 500 ps, ​​and a processing speed of 50 to 500 mm / s. However, these conditions are merely examples, and the inventors have confirmed that the wafer-deteriorated layer 15 can be appropriately formed even when the processing point output of the laser beam is lower or the pulse width is shorter. The inventors have also confirmed that the wafer-deteriorated layer 15 can be appropriately formed even when the processing point output of the laser beam L is higher or the pulse width is longer.

[0031] The predetermined depth D when forming the wafer affected layer 15 is set depending on the ease of handling and pressure resistance of the semiconductor chip 100, and is about 10 to 200 μm. In this case, the location where the wafer affected layer 15 is formed varies depending on the thickness of the epitaxial film 3, and is formed either inside the epitaxial film 3, at the boundary between the epitaxial film 3 and the GaN wafer 1, or inside the GaN wafer 1. Note that FIG. 1F shows an example in which the wafer affected layer 15 is formed at the boundary between the epitaxial film 3 and the GaN wafer 1.

[0032] However, as will be described later, at least a portion of the GaN wafer 1 in the processed wafer 10 is reused as a recycled wafer 40. For this reason, the wafer-use damaged layer 15 is preferably formed inside the epitaxial film 3 or at the boundary between the epitaxial film 3 and the GaN wafer 1. Furthermore, when the wafer-use damaged layer 15 is formed inside the GaN wafer 1, the wafer-use damaged layer 15 is preferably formed on the one surface 1a side of the GaN wafer 1.

[0033] When the wafer-use altered layer 15 is formed inside the epitaxial film 3, the wafer-use altered layer 15 is formed in the n-type semiconductor device. - The n-type epitaxial layer 3b is not +The portion of the processed wafer 10 on the other surface 10b side of the wafer-use altered layer 15 will be described below as a recycled wafer 40.

[0034] Next, as shown in FIG. 1G, an auxiliary member 50 is placed on the other surface 10b of the processed wafer 10. Similar to the holding member 20, the auxiliary member 50 may be, for example, a dicing tape having a base material 51 and an adhesive 52. The base material 51 may be, for example, glass, a silicon substrate, or ceramics. The adhesive 52 may be, for example, an ultraviolet-curing resin, wax, or double-sided tape. The holding member 20 and the auxiliary member 50 are then gripped to apply a tensile force or the like in the thickness direction of the processed wafer 10, and the recycled wafers 40 are separated from the processed wafer 10 using the wafer-degraded layer 15 as the boundary (i.e., the starting point of the separation).

[0035] In the following steps, the surface of the processed wafer 10 that has been separated into the recycled wafer 40 will be referred to as the other surface 10b of the processed wafer 10. Because the wafer-deteriorated layer 15 is formed along the surface direction of the processed wafer 10, the other surface 10b of the separated processed wafer 10 will be the {0001}c plane. In the following, the separated surface of the recycled wafer 40 will be referred to as the one surface 40a. In each of the figures from FIG. 1G onwards, the wafer-deteriorated layer 15 remaining on the other surface 10b of the processed wafer 10 and the one surface 40a of the recycled wafer 40 will be omitted as appropriate.

[0036] Thereafter, as shown in FIG. 1H, a typical semiconductor manufacturing process is performed to form a second surface side element component 60 of the semiconductor element, such as a metal film 61 that constitutes a back surface electrode, on the second surface 10b of the processed wafer 10.

[0037] Before the step of forming the other-side element component 60, a step of planarizing the other surface 10b of the processed wafer 10 by a CMP (short for chemical mechanical polishing) method or the like may be performed as needed. FIG. 1H shows a diagram of the other surface 10b of the processed wafer 10 after the planarization. After the step of forming the other-side element component 60 is performed, a heat treatment such as laser annealing may be performed as needed to establish ohmic contact between the metal film 61 and the other surface 10b of the processed wafer 10.

[0038] 1I, the holding member 20 is expanded to divide each chip formation area RA with the chip deterioration layer 14 as a boundary (i.e., the starting point of branching). This results in a semiconductor chip 100 having a chip configuration substrate 110 formed by the processed wafer 10, with one surface 110a formed by one surface 10a of the processed wafer 10, another surface 110b formed by the other surface 10b of the processed wafer 10, and side surfaces 110c formed by the cutting lines SL. In other words, the semiconductor chip 100 is formed by a rectangular parallelepiped chip configuration substrate 110 having one surface 110a, another surface 110b opposite to the one surface 110a, and two pairs of opposing side surfaces 110c connecting the one surface 110a and the other surface 110b.

[0039] As mentioned above, the cutting line SL is 1 Therefore, one of the two pairs of opposing side surfaces 110c of the chip configuration substrate 110 (i.e., the semiconductor chip 100) is aligned along the {-100}m plane or the {11-20}a plane. 1 4, the chip configuration substrate 110 has one surface 110a and the other surface 110b that are surfaces ... 1 The other of the two pairs of opposing side surfaces 110c is composed of a surface along the {11-20}a plane.

[0040] and,{ 1The {-100}m plane and the {11-20}a plane are planes that are perpendicular to the {0001}c plane, which forms one surface 10a of the processed wafer 10, and are planes that are easy to cleave. Therefore, when each chip formation region RA is divided along the chip-forming affected layer 14 as a boundary, it is possible to prevent cracks from extending inward from the side surface 110c and excessive distortion from occurring on the side surface 110c.

[0041] Thereafter, the adhesive strength of the adhesive 22 is weakened by heat treatment or light irradiation, and the semiconductor chip 100 is picked up. In this way, the semiconductor chip 100 is manufactured. Before dividing each chip formation area RA, if necessary, slits or the like may be formed in the metal film 61 at the boundaries of each chip formation area RA, so that the metal film 61 can be easily divided into each chip formation area RA. In this case, in the step of FIG. 1H, a metal mask may be prepared to cover the divided portions so that the metal film 61 is not formed in the divided portions.

[0042] Furthermore, since the semiconductor chip 100 manufactured as described above is divided at the chip-forming altered layer 14 as a boundary, the altered layer 120 formed by the chip-forming altered layer 14 remains on the side surface 110c, resulting in the formation of minute irregularities. Therefore, the manufacturing method of this embodiment manufactures a semiconductor chip 100 that is easy to handle.

[0043] Here, the inventors further investigated the state of the side surface 110c and obtained the following results. First, as described above, the side surface 110c of the semiconductor chip 100 is 1 The side surface 110c is defined as a {-100}m plane or a {11-20}a plane. The inventors then performed a depth profile analysis of the side surface 110c using X-ray photoelectron spectroscopy (hereinafter also referred to as XPS), and obtained the results shown in FIG.

[0044] 5 shows the results of analysis in the depth direction using sputter etching with argon ions in combination, with a sputter rate of 20 nm. Also, FIG. 5 shows the results of XPS analysis of the side surface 110c formed by the {11-20}a plane, with the normal direction to the side surface 110c taken as the depth direction (hereinafter simply referred to as the depth direction). However, according to the study by the present inventors, 1 It has been confirmed that similar results can be obtained when XPS is performed on the side surface 110c formed by the -100}m plane. In Fig. 5, c / s indicates the number of electron counts per second.

[0045] As shown in FIG. 5, the spectrum obtained when the sputtering cycle was 0 (referred to as the sputter cycle in FIG. 5) confirms the presence of a mixture of Ga2O3 (i.e., gallium oxide) and Ga metal, and the absence of GaN. More specifically, quantitative analysis of the results of the 0th sputtering cycle in FIG. 5 confirms that Ga2O3 is present in an amount of 90% or more and Ga metal is present in an amount of less than 10%. In other words, the analysis results for the 0th sputtering cycle are the analysis results of the outermost layer portion of the side surface 110c.

[0046] In the spectrum obtained when the sputtering number is one or more, only GaN is confirmed, and Ga2O3 and Ga metal are not confirmed.

[0047] From the above, it can be said that an altered layer 120 containing Ga2O3 and Ga metal is formed in the surface layer portion along the depth direction of each side surface 110c. Also, as mentioned above, FIG. 5 shows the results when the sputtering rate is 20 nm. Therefore, it can be said that the altered layer 120 exists only in a range of 20 nm or less along the depth direction from the side surface 110c. In other words, it can be said that the altered layer 120 exists only in a range of 20 nm or less from the side surface 110c in terms of the sputtering rate of sputter etching using argon ions. Note that, as mentioned above, minute irregularities are formed on the side surface 110c. Therefore, the range of 20 nm or less along the depth direction here can also be said to be a range with an average depth of 20 nm or less.

[0048] 1J, one surface 40a of the recycled wafer 40 configured as shown in FIG. 1G is subjected to CMP using a polishing device 70 or the like to flatten the surface 40a. The flattened recycled wafer 40 is then used as the GaN wafer 1, and the steps from FIG. 1A onward are repeated. This allows the GaN wafer 1 to be used multiple times to form semiconductor chips 100.

[0049] According to the present embodiment described above, the semiconductor chip 100 has one surface 110a and the other surface 110b formed as the {0001}c plane, and the side surface 110c formed as the { 1 The side surface 110c is aligned with the {-100}m plane or the {11-20}a plane. Therefore, when the processed wafer 10 is divided into each chip formation region RA, it is possible to prevent cracks from extending inward from occurring on the side surface 110c and to prevent excessive distortion from occurring on the side surface 110c.

[0050] The surface layer of the side surface 110c includes an altered layer 120 containing less than 10% Ga metal and 90% or more Ga2O3. In other words, the side surface 110c is mainly composed of gallium oxide. This improves the insulating properties of the side surface 110c.

[0051] (1) In this embodiment, the affected layer 120 is formed in a range of 20 nm or less along the depth direction from the side surface 110c, which allows most of the semiconductor chip 100 to be formed as an element region.

[0052] (2) In this embodiment, the chip formation areas RA are divided by expanding the holding member 20. Therefore, the manufacturing process can be simplified compared to, for example, dividing each chip formation area RA with a dicing blade or the like.

[0053] (3) In this embodiment, the chip-forming region 14 and the wafer-forming region 15 are formed so that they intersect. When the wafer-forming region 15 is formed, nitrogen generated during the formation of the wafer-forming region 15 is released through the chip-forming region 14. This reduces distortion in each chip-forming region RA, thereby preventing defects from occurring in the semiconductor chip 100.

[0054] (4) In this embodiment, recycled wafers 40 are separated from the processed wafer 10, and the recycled wafers 40 are reused as GaN wafers 1. This eliminates the need to prepare a new GaN wafer 1 each time a semiconductor chip 100 is manufactured, and allows for effective use of the GaN wafer 1. This allows for improved productivity of the semiconductor chips 100.

[0055] (5) In this embodiment, when thinning the processed wafer 10, the processed wafer 10 is thinned by irradiating it with laser light L to form a wafer-forming altered layer 15, and then dividing the recycled wafer 40 at the wafer-forming altered layer 15. This reduces the manufacturing time compared to thinning the processed wafer 10 by grinding from the other surface 10b using a CMP method or the like.

[0056] (6) In this embodiment, minute irregularities are formed on the side surface 110c of the semiconductor chip 100. This makes it easier to handle the semiconductor chip 100.

[0057] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0058] In each of the above embodiments, the first surface 110a, the second surface 110b, and the side surface 110c of the chip substrate 110 are the {0001}c plane, { 1 The specific plane configuration can be changed as appropriate as long as it is composed of either the {-100}m plane or the {11-20}a plane. 1 The side surface 110c may be configured as the {0001}c plane or the {11-20}a plane. Even when the side surface 110c is configured as the {0001}c plane, the inventors have confirmed that, according to their investigations, XPS results similar to those shown in FIG. 5 are obtained.

[0059] In the first embodiment, the processed wafer 10 may be composed of only a single crystal substrate. Alternatively, the processed wafer 10 may be ground from the other surface 10b before or after the step of Fig. 1E without undergoing the step of Fig. 1F, so that the thickness thereof is adjusted.

[0060] In the first embodiment, the epitaxial film 3 has an n - It may be composed of only the type epitaxial layer 3b.

[0061] 1B, an epitaxial film may also be formed on the other surface 1b of the GaN wafer 1. This makes it easier to leave a predetermined thickness or more as a recycled wafer 40 even when a wafer-use altered layer 15 is formed in the GaN wafer 1, thereby increasing the number of times the wafer can be reused.

[0062] In the first embodiment, the step of forming the chip-forming altered layer 14 shown in FIG. 1E may be performed before the step of arranging the holding member 20 shown in FIG. 1D. In this case, the laser light L may be irradiated from the one surface 10a of the processed wafer 10. However, when the laser light L is irradiated from the one surface 10a of the processed wafer 10, the position of the focal point of the laser light L may vary depending on the surface electrodes and wiring patterns formed on the one surface 10a. For this reason, it is preferable to irradiate the laser light from the other surface 10b of the processed wafer 10. [Explanation of symbols]

[0063] 110a one side 110b Other side 100c side 100 chip configuration board 120 Degenerated Layer

Claims

1. A method for manufacturing a semiconductor chip including a chip configuration substrate (110), comprising: A processed wafer (10) having one surface (10a) and another surface (10b), including hexagonal gallium nitride, and having a plurality of chip forming areas (RA) partitioned by cutting lines (SL) is prepared; Irradiating the processed wafer with laser light (L) to form a chip-forming altered layer (14) in which nitrogen is separated from gallium along the cutting line; After forming the chip deterioration layer, irradiating the other surface of the processed wafer with laser light (L) to form a wafer deterioration layer (15) along the surface direction of the processed wafer; Dividing the recycled wafer (40) from the processed wafer at the wafer deterioration layer as a boundary, and using the divided surface of the processed wafer as the other surface of the processed wafer; By dividing the chip formation region at the chip deterioration layer as a boundary, the chip configuration substrate is constructed from the processed wafer, having one surface (110a) formed from one surface of the processed wafer, another surface (110b) formed from the other surface of the processed wafer, and two pairs of opposing side surfaces (110c) that are surfaces along the cutting line and connect the one surface and the other surface, By configuring the chip configuration substrate, the one surface and the other surface are surfaces along any one of the {0001} c-plane, {1-100} m-plane, and {11-20} a-plane, one opposing side surface of the two pairs of opposing side surfaces is a surface along one of the remaining two surfaces in the {0001} c-plane, {1-100} m-plane, and {11-20} a-plane that are different from the one surface and the other surface, and the other opposing side surface of the two pairs of opposing side surfaces is a surface along a surface in the {0001} c-plane, {1-100} m-plane, and {11-20} a-plane that is different from the one surface and the other surface and the one opposing side surface, and further, when the normal direction to the side surfaces is defined as the depth direction, an altered layer (120) containing gallium oxide and gallium metal is formed on the surface layer portion of the side surfaces in the depth direction. A method for manufacturing a semiconductor chip, wherein forming the deteriorated layer for a chip and forming the deteriorated layer for a wafer form the deteriorated layer for a wafer so as to intersect with the deteriorated layer for a chip.

2. Before constructing the chip configuration substrate, a holding member (20) is arranged on one side of the processed wafer; 2. The method for manufacturing a semiconductor chip according to claim 1, wherein the chip formation region is divided at the chip-forming altered layer as a boundary by expanding the holding member in forming the chip formation substrate.

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