Diffusion break device and method of forming

Abstract

An apparatus with a diffusion break and a method for forming the same, comprising: a substrate, a first nanosheet device disposed on the substrate, and a second nanosheet device disposed on the substrate, the second nanosheet device adjacent to the first nanosheet device; a first gate disposed on the first nanosheet device, the first gate having a first width, and a second gate disposed on the second nanosheet device, the second gate having a second width, the first width and the second width being substantially identical; a diffusion break disposed between the first nanosheet device and the second nanosheet device, the diffusion break preventing the first nanosheet device from contacting the second nanosheet device, the diffusion break having a third width, the third width being greater than the first width and the second width.

Description

[Technical Field]

[0001] The present invention relates generally to the field of nanosheets, and more particularly to simultaneously forming diffusion breaks between devices formed on nanosheets. [Background technology]

[0002] When multiple devices are fabricated on a single substrate, they must be isolated from each other to prevent errors. Diffusion breaks separate adjacent devices from each other, but at the nanosheet size, forming diffusion breaks can lead to defect formation. Summary of the Invention

[0003] Additional aspects and / or advantages will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

[0004] An apparatus comprising: a substrate; a first nanosheet device disposed on the substrate; and a second nanosheet device disposed on the substrate, the second nanosheet device adjacent to the first nanosheet device, at least one first gate disposed on the first nanosheet device, the at least one first gate having a first width, at least one second gate disposed on the second nanosheet device, the at least one second gate having a second width, the first width and the second width being substantially identical, and a diffusion break disposed between the first nanosheet device and the second nanosheet device, the diffusion break preventing the first nanosheet device from contacting the second nanosheet device, the diffusion break having a third width, the third width being greater than the first width and the second width.

[0005] An apparatus comprising: a substrate; a first nanosheet device disposed on the substrate; a second nanosheet device disposed on the substrate, the second nanosheet device adjacent to the first nanosheet device; and a third nanosheet device disposed on the substrate, the third nanosheet device adjacent to the second nanosheet device; and at least one first gate disposed on the first nanosheet device, the at least one first gate having a first width. at least one second gate disposed on the second nanosheet device, the at least one second gate having a second width, the first width and the second width being substantially identical; at least one third gate disposed on the third nanosheet device, the at least one third gate having a third width, the third width and the second width being substantially identical; and a first diffusion break disposed between the first nanosheet device and the second nanosheet device, the first diffusion break being disposed between the first nanosheet device and the second nanosheet device. a first diffusion break that prevents the first nanosheet device from contacting the second nanosheet device, the first diffusion break having a fourth width, the fourth width being greater than the first width and the second width; and a second diffusion break disposed between the second nanosheet device and the third nanosheet device, the second diffusion break that prevents the second nanosheet device from contacting the third nanosheet device, the second diffusion break having a fifth width, the fifth width being greater than the second width and the third width.

[0006] The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1 is a top view of a nanosheet device according to one embodiment of the present invention. [Figure 1B] FIG. 2 is a top view of a FinFET device according to an embodiment of the present invention. [Figure 2] 1 is a cross-sectional view illustrating the structure of three gates of a device according to one embodiment of the present invention. [Figure 3] FIG. 1B is a cross-sectional view of isolating the active gate while exposing the wide gate according to one embodiment of the present invention. [Figure 4] 1A-1C are cross-sectional views illustrating the removal of gate material from the exposed gate according to one embodiment of the present invention. [Figure 5] 1A-1C are cross-sectional views of a device with respect to the formation of a diffusion break, according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view of a device having multiple diffusion breaks, according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] The following description of the accompanying drawings is provided to promote a comprehensive understanding of exemplary embodiments of the present invention, as defined by the claims and their equivalents. While various specific details are included to promote this understanding, they should be considered merely exemplary. Accordingly, those skilled in the art will recognize that various changes and modifications to the embodiments described herein may be made without departing from the scope and spirit of the present invention. Additionally, well-known functions and structures may be omitted for clarity and conciseness.

[0009] The terms and phrases used in the following description and claims are not limited to their bibliographical meanings, but are merely used to enable a clear and consistent understanding of the present invention. Therefore, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only and is not intended to limit the present invention, which is defined by the appended claims and their equivalents.

[0010] The singular forms "a," "an," and "the" are understood to include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces unless the context clearly dictates otherwise.

[0011] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, because the present invention may be embodied in many different forms, it should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Details of well-known features and techniques may be omitted herein to avoid unnecessarily obscuring the present embodiments.

[0012] References herein to "one embodiment," "an embodiment," "exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is believed to be within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0013] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods as oriented in the drawings. The terms "overlying," "atop," "on top," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, although an intervening element, such as an interfacial structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0014] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of illustration and description, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description will instead focus on salient features or elements of various embodiments of the present invention.

[0015] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments may be devised without departing from the scope of the present invention. Note that in the following description and in the drawings, various connections and relationships (e.g., above, below, adjacent, etc.) are defined between elements. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, coupling of entities may refer to either direct coupling or indirect coupling, and relationships between entities may be direct or indirect. As an example of an indirect relationship, the term "forming layer "A" on layer "B" herein includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," as long as the relevant properties and functionality of layer "A" and layer "B" are not substantially changed by the intermediate layers.

[0016] The following definitions and abbreviations are to be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or other variations thereof, are intended to include a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that comprises a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed, i.e., inherent in such composition, mixture, process, method, article, or device.

[0017] Furthermore, as used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include integers greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" may be understood to include integers greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "coupled" may include both an indirect and a direct "coupled."

[0018] As used herein, the term "about" modifying the amount of a component, ingredient, or reactant of the present invention utilized refers to variations in the numerically indicated amount that may occur due to typical measuring and liquid handling practices used, for example, to make concentrates or solutions. Additionally, variations may occur due to inadvertent errors during measuring practices, differences in the manufacture, source, or purity of components used in preparing a composition or practicing a method, and the like. The terms "about" or "substantially" are intended to include the degree of error associated with the measurement of a particular quantity based on equipment available at the time of filing. For example, ranges of ±8%, ±5%, or ±2% of a given value may be included. In another embodiment, the term "about" refers to within 5% of the reported numerical value. In another embodiment, the term "about" refers to within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0019] The various processes used to form microchips for integrated circuits (ICs) fall into four general categories: thin-film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition refers to the process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, atomic layer deposition (ALD). Removal / etching refers to any process that removes material from a wafer. Examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP). Semiconductor doping refers to modifying electrical properties, typically by doping the source or drain of a transistor, typically by diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Thin films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect or isolate electrical components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by applying a voltage.

[0020] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Multiple devices can be formed using the same nanosheet or group of fins in a FinFET device. To isolate the devices from each other, a single diffusion break must be formed between adjacent devices. However, forming a single diffusion break in a nanosheet or fin spanning multiple fins at the location that separates the devices is not a simple process. Multiple gates having the same dimensions are formed across the device. The single diffusion break is formed by replacing one of the formed gates with a dummy gate. The challenge of forming a dummy gate is targeting the replacement of the formed gate with the dummy gate. One solution is to form a dummy gate that can be replaced with a self-aligned process; for example, a wider opening is formed at the top of the gate when removing the gate to form the dummy gate. This process makes it easier to target the gate for processing, thereby enabling the gate to be replaced with the dummy gate. However, this process creates downstream processing problems because the wide top dummy gates protrude beyond the sides of the spacer material, creating a ledge that obstructs the deposition and removal of material between the gates. A method for creating dummy gates that avoid obstructions and save space on the substrate (i.e., do not require significant device separation) involves fabricating gates (that are to be replaced by dummy gates) that are located between adjacent devices wider than the adjacent gates. The wider gates allow for targeted placement of the gates that will be replaced by dummy gates.

[0021] FIG. 1A shows a top view of a nanosheet device 100 according to an embodiment of the present invention. The nanosheet device 100 includes a nanosheet 105, a first gate 110, a second gate 120, a dummy gate 115, a first device D1, and a second device D2. The dashed circle highlights the rounding of the edges of the nanosheet 105 that occurs during the fabrication process. The dummy gate 115 functions as a single diffusion break between the first device D1 and the second device D2. However, because the edges of the nanosheet 105 are rounded, the dummy gate 115 may not be a perfect single diffusion break.

[0022] FIG. 1B illustrates a top view of a FinFET device 102 according to an embodiment of the present invention. The FinFET device 102 includes a plurality of fins 135, a first gate 145, a second gate 160, a dummy gate 150, a first device D3, and a second device D4. The dummy gate 150 functions as a single diffusion break between the first device D3 and the second device D4. FIG. 1B further illustrates that the FinFET device 102 is not direct printed and therefore does not suffer from corner rounding issues.

[0023] FIG. 2 illustrates a cross-section of a nanosheet device 100 for forming a single diffusion break according to an embodiment of the present invention. The device includes a substrate 205, a source epitaxial layer 210, a dielectric layer 215, a first gate 235, a second gate 245, and a third gate 240. The substrate 205 may be selected from the group consisting of a silicon wafer, a sapphire wafer, an insulator, a metal layer, or any other type of suitable layer. The nanosheet device 100 may include the source epitaxial layer 210. The dielectric layer 215 is an interlayer dielectric (ILD) that may include any suitable dielectric material. FIG. 2 illustrates that a first device D1 includes a first gate 235, and a second device D2 utilizes a third gate 240. The two devices shown are for illustrative purposes only. Each of the first gate 235, second gate 245, and third gate 240 includes a spacer 225, a gate metal 220, and a cap 230. The cap 230 may be composed of SiN or another suitable material. The first gate 235 is formed with a width W1, the second gate 245 has a width W2, and the third gate 240 has a width W3. The width W1 of the first gate 235 is substantially equal to the width W3 of the third gate 240. However, the width W2 of the second gate is larger than the widths W1 and W3 of the first gate 235 and the third gate 240. By making the width W2 of the second gate 245 larger than the widths of the other gates, the second gate 245 can be easily replaced with a dummy gate to create a single diffusion break between the first device D1 and the second device D2.

[0024] FIG. 3 illustrates a cross section of a device after formation and patterning of an OPL layer 250 according to an embodiment of the present invention. The OPL layer 250 is formed over the dielectric layer 215 and the caps 230 of each of the gates 235, 245, and 240. The OPL layer 250 is patterned to expose the caps 230 of the second gate 245. The width W4 of the opening in the OPL layer 250 is large enough to expose the width W2 of the second gate 245. The width W4 shown in FIG. 3 is larger than the width W2 of the gate metal 220 of the second gate 245. It is critical that the width W4 be equal to or larger than the width W2 for subsequent fabrication processes described below. The width W2 of the second gate 245 is larger than the widths of the other gates, e.g., 2-20 nm larger than the widths of the other gates, making it easier to align the hole in the OPL layer 250 to the second gate 245. OPL layer 250 is composed of an optical planarization material, but can be any type of lithographic material.

[0025] FIG. 4 shows a cross section of a device after removal of the cap 230 and gate metal 220 disposed in the second gate 245 according to an embodiment of the present invention. The cap 230 and gate metal 220 of the second gate 245 are removed. The width W2 of the second gate 245 is wide enough to enable complete material removal. For example, the width W2 may be in the range of 10 to 50 nm, more preferably in the range of 18 to 38 nm. The width W2 is 2 to 20 nm wider than the width W1 or the width W3, more preferably, the width W2 is 2 to 10 nm wider than the width W1 or the width W3. If the width W2 of the second gate is too large, the area reduction effect of forming a single diffusion break is lost. FIG. 4 shows that the cap 230 and gate metal 220 of the second gate 245 have been selectively removed relative to the spacer 225 of the second gate 245.

[0026] FIG. 5 shows a cross section of a device after the formation of a single diffusion break, according to an embodiment of the present invention. The diffusion break is created by filling the second gate 245 with a filler material, such as SiN or another suitable material, that functions as a dummy gate / diffusion break. The second gate 245, i.e., diffusion break, allows for electrical isolation between the first device D1 and the second device D2, and by making the width W2 larger than the widths W1 and W3, it allows for easy formation of the diffusion break. The cap 230 forms the top of the second gate 245 (e.g., dummy gate / diffusion break), and the material of the cap 230 extends below the gate to the substrate 205. Furthermore, by having a wider second gate 245, i.e., dummy gate / diffusion break, the width of the gate is large enough to extend beyond the rounded edge of the nanosheet. Figure 5 shows an active gate for a first device (first gate 235) and an active gate for a second device (third gate 240). A single diffusion break (dummy gate, or second gate 245) separates the first and second devices.

[0027] FIG. 6 shows a cross section of a device with multiple diffusion breaks according to an embodiment of the present invention. When multiple devices are formed on the same substrate 205, for example, using the same nanosheet stack or fin as the basic structure of the devices, more than three devices are formed on the same substrate, and each device must be electrically isolated from the others. The multiple devices include a source epitaxial layer 210, a dielectric layer 215, a first gate 235, a second gate 245, a third gate 240, a fourth gate 252, a fifth gate 260, and a sixth gate 255. For example, the second gate 245 and the fifth gate 260 can be dummy gates or diffusion breaks between devices. Having multiple dummy gates / diffusion breaks allows multiple devices to be formed on the same substrate 205. Each dummy gate / diffusion break can have a width in the range of 10 to 50 nm, more preferably in the range of 18 to 38 nm. The width of the dummy gate is 2 to 20 nm wider than the width of the other gates (non-dummy gates), and more preferably, the width of the dummy gate is 2 to 10 nm wider than the width of the other gates (non-dummy gates). The dummy gate / diffusion break allows devices to be electrically isolated instead of spaced apart from each other, allowing separate devices to be formed close to each other. Therefore, the diffusion break / dummy gate reduces the area required to electrically deploy the devices.

[0028] As the number of dummy gates / diffusion breaks increases, the area reduction achieved by using them decreases. For example, if the width of the dummy gates / diffusion breaks is 10 nm greater than the width of the other gates (non-dummy gates), and two dummy gates / diffusion breaks are used to electrically isolate the device, the area reduction can exceed 40%. However, if the width of the dummy gates / diffusion breaks is 10 nm greater than the width of the other gates (non-dummy gates), and five dummy gates / diffusion breaks are used to electrically isolate the device, the area reduction decreases to just over 15%. In another example, if the width of the dummy gates / diffusion breaks is 2 nm greater than the width of the other gates (non-dummy gates), and two dummy gates / diffusion breaks are used to electrically isolate the device, the area reduction exceeds 45%. However, when five dummy gates / diffusion breaks are used to electrically isolate the device, the area reduction exceeds 19% when the width of the dummy gates / diffusion breaks is 2 nm greater than the width of the other gates (non-dummy gates). Therefore, the number of dummy gates / diffusion breaks and the gate width directly determine the area reduction achieved by using dummy gates / diffusion breaks. This may be better expressed as the number of active gates per diffusion break. The drawing shows two active gates per single diffusion break.

[0029] While the present invention has been shown and described with reference to certain exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and equivalents thereof.

[0030] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of one or more embodiments, practical applications or technical improvements over commercially available technology, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device, A substrate; a first nanosheet device disposed on the substrate; and a second nanosheet device disposed on the substrate, the second nanosheet device being adjacent to the first nanosheet device; and at least one first gate disposed on the first nanosheet device, the at least one first gate having a first width; at least one second gate disposed on the second nanosheet device, the at least one second gate having a second width, the first width and the second width being substantially the same; a single diffusion break disposed between the first nanosheet device and the second nanosheet device, the single diffusion break being formed by replacing a gate formed wider than other gates with a dummy gate, the dummy gate having a structure that extends beyond the curl of the nanosheet, the single diffusion break preventing the first nanosheet device from contacting the second nanosheet device, the single diffusion break having a third width, the third width being greater than the first width and the second width; Equipment comprising:

2. The apparatus of claim 1 , wherein the first nanosheet device is in direct contact with a first side of the single diffusion break and the second nanosheet device is in direct contact with a second side of the single diffusion break.

3. The device of claim 2 , wherein the first side of the single diffusion break is opposite the second side of the single diffusion break.

4. The apparatus of claim 1 , wherein the single diffusion break comprises a dummy gate.

5. The single diffusion break is a first spacer disposed adjacent to a first side of the single diffusion break; a second spacer disposed adjacent to a second side of the single diffusion break; a filler material disposed between the first spacer and the second spacer, the filler material being disposed on top of the first spacer and the second spacer; 5. The device of claim 4, comprising:

6. The device of claim 5 , wherein the filler material is SiN.

7. 2. The device of claim 1, wherein the third width is 2 to 20 nm greater than the first width, and the third width is 2 to 20 nm greater than the second width.

8. The device of claim 1 , wherein the third width is 2 to 10 nm greater than the first width, and the third width is 2 to 10 nm greater than the second width.

9. A device, A substrate; a first nanosheet device disposed on the substrate; and a second nanosheet device disposed on the substrate, the second nanosheet device being adjacent to the first nanosheet device; and a third nanosheet device disposed on the substrate, the third nanosheet device being adjacent to the second nanosheet device; and at least one first gate disposed on the first nanosheet device, the at least one first gate having a first width; at least one second gate disposed on the second nanosheet device, the at least one second gate having a second width, the first width and the second width being substantially the same; at least one third gate disposed on the third nanosheet device, the at least one third gate having a third width, the third width and the second width being substantially the same; a diffusion break disposed between the first nanosheet device and the second nanosheet device, the diffusion break being formed by replacing a gate formed wider than other gates with a dummy gate, the dummy gate having a structure that extends beyond the curl of the nanosheet, the diffusion break preventing the first nanosheet device from contacting the second nanosheet device, the diffusion break having a third width, the third width being greater than the first width and the second width; a second diffusion break disposed between the second nanosheet device and the third nanosheet device, the second diffusion break preventing the second nanosheet device from contacting the third nanosheet device, the second diffusion break having a fifth width, the fifth width being greater than the second width and the third width; and Equipment comprising:

10. The apparatus of claim 9 , wherein the first nanosheet device is in direct contact with a first side of the first diffusion break and the second nanosheet device is in direct contact with a second side of the first diffusion break.

11. The device of claim 10 , wherein the first side of the first diffusion break and the second side of the first diffusion break are separate sides of the first diffusion break.

12. The apparatus of claim 11 , wherein the second nanosheet device is in direct contact with a first side of the second diffusion break and the third nanosheet device is in direct contact with a second side of the second diffusion break.

13. 13. The device of claim 12, wherein the first side of the second diffusion break and the second side of the second diffusion break are separate sides of the second diffusion break.

14. 10. The apparatus of claim 9, wherein the first diffusion break and the second diffusion break are dummy gates.

15. The first diffusion break comprises: a first spacer disposed on a first side of the first diffusion break; a second spacer disposed on a second side of the first diffusion break; a filler material disposed between the first spacer and the second spacer, the filler material being disposed on top of the first spacer and the second spacer; and the second diffusion break comprises: a third spacer disposed adjacent to the first side of the second diffusion break; a fourth spacer disposed adjacent to the second side of the second diffusion break; a second filler disposed between the third spacer and the fourth spacer, the second filler disposed on top of the third spacer and the fourth spacer; 15. The device of claim 14, comprising:

16. The device of claim 15 , wherein the filler material is SiN.

17. 16. The device of claim 15, wherein the fourth width and the fifth width are 2 to 20 nm greater than the first width, the fourth width and the fifth width are 2 to 20 nm greater than the second width, and the fourth width and the fifth width are 2 to 20 nm greater than the third width.

18. 16. The device of claim 15, wherein the fourth width and the fifth width are 2 to 10 nm greater than the first width, the fourth width and the fifth width are 2 to 10 nm greater than the second width, and the fourth width and the fifth width are 2 to 10 nm greater than the third width.

19. 1. A method comprising: forming a first nanosheet device on a substrate; forming a second nanosheet device on the substrate, the second nanosheet device being adjacent to the first nanosheet device, and the first nanosheet device and the second nanosheet device being formed simultaneously; forming at least one first gate disposed on the first nanosheet device, the at least one first gate having a first width; forming at least one second gate disposed on the second nanosheet device, the at least one second gate having a second width, the first width and the second width being substantially the same; forming a diffusion break disposed between the first nanosheet device and the second nanosheet device, the diffusion break being formed by replacing a gate formed wider than other gates with a dummy gate, the dummy gate having a structure that extends beyond the curl of the nanosheet, the diffusion break preventing the first nanosheet device from contacting the second nanosheet device, the diffusion break having a third width, the third width being greater than the first width and the second width; A method comprising:

20. 20. The method of claim 19, wherein the third width is 2 to 10 nm greater than the first width, and the third width is 2 to 10 nm greater than the second width.

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