Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing a contact resistance.SOLUTION: A semiconductor device includes: a first conductivity-type drift layer 2; a second conductivity-type base layer 6 provided above the drift layer 2; a first conductivity-type first semiconductor region 7 selectively provided at a front surface side of the base layer 6; a second conductivity-type second semiconductor region 8 selectively provided at the front surface side of the base layer 6 and having impurity concentration higher than that of the base layer 6; a first electrode 13 being in contact with the first semiconductor region 7 and the second semiconductor region 8; a first trench portion 18 having a gate insulating film 9 and a gate electrode 10 and being extended in a first direction; and a second trench portion 19 having a conductive layer 15 and at least a part of the conductive layer 15 being in contact with the second semiconductor region 8. The second semiconductor region 8 includes a second region connecting first regions located at both sides of the second trench portion 19 in a second direction orthogonal to the first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) for power semiconductor elements to reduce the on-resistance of the elements. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface allows for a higher cell density per unit area than a planar structure in which the channel is formed parallel to the substrate surface, and therefore allows for an increased current density per unit area, which is advantageous from a cost perspective.

[0003] The trench gate structure is a three-dimensional structure in which a MOS gate (an insulated gate made of metal-oxide-semiconductor) is embedded in a trench formed in a semiconductor substrate made of silicon carbide (hereinafter referred to as the silicon carbide substrate), and the portion along the trench sidewall is used as a channel (inversion layer).For this reason, when comparing devices with the same on-resistance (Ron), the trench gate structure can overwhelmingly reduce the device area (chip area) compared to a planar gate structure in which a MOS gate is provided as a flat plate on a silicon carbide substrate, making it a promising device structure for the future.

[0004] In a trench MOSFET, there is a structure in which a trench for a Schottky diode (SBD: Schottky Barrier Diode) is formed between adjacent gate trenches, and a Schottky junction is formed on the side surface of the trench. Fig. 20 is a cross-sectional view taken along line A-A' in Fig. 22 showing the configuration of a conventional trench silicon carbide semiconductor device. Fig. 21 is a cross-sectional view taken along line B-B' in Fig. 22 showing the configuration of a conventional trench silicon carbide semiconductor device. Fig. 22 is a top view showing the configuration of a conventional trench silicon carbide semiconductor device.

[0005] As shown in FIGS. 20 and 21, a conventional trench-type silicon carbide semiconductor device has n + The front surface of the silicon carbide substrate 1 is provided with a trench-type MOS gate (insulated gate made of metal-oxide-semiconductor) structure and a contact trench 19 in which a trench-type SBD is embedded. + The silicon carbide substrate 1 has an n-type drain layer. + On a silicon carbide substrate 1, - n-type drift layer 2 - The mold layer is epitaxially grown. + The front surface (n - On the surface of the n-type drift layer 2, an n-type high concentration region 5, a p-type base layer 6, and an n-type + Type source region 7, p + A MOS gate structure consisting of a contact region 8, a gate insulating film 9 and a gate electrode 10 is provided.

[0006] In order to reduce the electric field applied to the gate insulating film 9 at the bottom of the gate trench 18 and the contact trench 19, + The mesa portion has a contact trench 19 formed therein, the contact trench 19 having a depth approximately equal to that of the gate trench 18. A Schottky electrode is buried in the contact trench 19, forming a Schottky junction with the n-type high concentration region 5.

[0007] n + The n-type source region 7 is selectively provided inside the p-type base layer 6 between the adjacent gate trench 18 and contact trench 19. As shown in FIG. + The source region 7 is provided so as to be in contact with the gate trench 18 , and a part of the source region 7 extends toward the contact trench 19 and is connected to the contact trench 19 .

[0008] p + The contact region 8 is an n + The n-type source region 7 is provided on the surface of the p-type base layer 6 where the n-type source region 7 is not provided. + Type source region 7 and p +The contact region 8 is exposed to a contact hole that penetrates the interlayer insulating film 11 in the depth direction. A source electrode 13 is provided as a front surface electrode so as to be embedded in the contact hole and the contact trench 19. + type contact region 8 and n + The n-type source region 7 is in contact with the n-type source region 7. + The back surface (n - A drain electrode 14 is provided as a back surface electrode on the surface opposite to the drift layer 2.

[0009] In the case of an SBD built into a trench MOSFET with this structure, the drift region can be shared with the MOSFET, so the chip area can be smaller than the combined chip area of ​​the external SBD and MOSFET. Also, in the case of an external SBD, the VF (forward voltage) of the SBD is the difference between the p-type base layer 6 of the MOSFET and the n-type base layer 7. - When the voltage exceeds the built-in voltage of the body diode formed between the gate electrode and the gate drift layer 2, the body diode turns on, and the bipolar operation of the body diode causes the characteristics to change over time (aging degradation), reducing reliability.

[0010] On the other hand, with an internal SBD, even if the voltage at the drain of the MOSFET, which corresponds to the cathode of an external SBD, exceeds the built-in voltage of the body diode, the potential difference near the pn junction that makes up the body diode is low because the voltage is maintained in the drift region, making it difficult for current to flow through the body diode. As a result, current does not flow through the body diode even up to a large current, making it less susceptible to degradation due to bipolar operation.

[0011] Also known is a semiconductor device in which a plurality of trenches are formed in a stripe pattern on the upper surface of a substrate, a first contact hole has an opening shape with a first width extending parallel to the trenches, a second contact hole has an opening shape with a second width wider than the first width, and an electrode layer makes Schottky contact with a pillar region within the second contact hole (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 2017-054928 Summary of the Invention [Problem to be solved by the invention]

[0013] In the conventional trench-type silicon carbide semiconductor device, the gate trench 18 is + The n-type source region 7 is formed after the n-type source region 7 is formed. Therefore, as the cell pitch becomes finer, for example, the mask position when forming the gate trench 18 may be shifted. + In some cases, it may not be possible to ensure the area for the type source region 7. As described above, the tolerance for the mask formation position is small, and therefore it has been difficult to reduce the cell pitch in conventional trench type silicon carbide semiconductor devices.

[0014] An object of the present invention is to provide a semiconductor device that can ensure the area of ​​a source region or a contact region. [Means for solving the problem]

[0015] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: It comprises a semiconductor substrate and a plurality of MOS gate structures provided in parallel on the front surface side of the semiconductor substrate. The MOS gate structures each include an N-type semiconductor region and an N-type + a P-type source region, a P-type base region disposed between the semiconductor region and the source region in the depth direction, and a P-type base region extending in a stripe shape in a first direction. , does not extend in a second direction perpendicular to the first direction A first unit in which a Schottky barrier diode is formed between a first MOS gate structure and a second MOS gate structure adjacent to each other among the plurality of MOS gate structures, and a source region or a P region between the first MOS gate structure and the second MOS gate structure adjacent to each other + an extension portion that is a contact region of the Schottky barrier diode, the extension portion extending in front of a region sandwiched between the Schottky barrier diodes in the first direction; Record number and a second unit extending in two directions. [Effects of the Invention]

[0016] The semiconductor device according to the present invention has the effect of ensuring the area of ​​the source region or contact region. [Brief explanation of the drawings]

[0017] [Figure 1] 4 is a cross-sectional view taken along line AA' of FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 2] 4 is a cross-sectional view taken along line BB' of FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 3] 1 is a top view showing a configuration of a silicon carbide semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view (part 1) showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 5] 10 is a cross-sectional view (part 2) illustrating a state during manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 6] 10 is a cross-sectional view (part 3) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 7] 10 is a cross-sectional view (part 4) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 8] 5 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 5). FIG. [Figure 9] FIG. 6 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 6). [Figure 10] 13 is a cross-sectional view taken along line AA' of FIG. 12 showing a configuration of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 11] 13 is a cross-sectional view taken along line BB' of FIG. 12 showing the configuration of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 12]FIG. 10 is a top view showing a configuration of a silicon carbide semiconductor device according to a second embodiment. [Figure 13] 17 is a cross-sectional view taken along line AA' of FIG. 16 showing the configuration of a silicon carbide semiconductor device according to a third embodiment. FIG. [Figure 14] 17 is a cross-sectional view taken along line BB' of FIG. 16 showing the configuration of a silicon carbide semiconductor device according to a third embodiment. FIG. [Figure 15] 17 is a cross-sectional view taken along the line CC' of FIG. 16 showing the configuration of a silicon carbide semiconductor device according to a third embodiment. FIG. [Figure 16] FIG. 10 is a top view showing a configuration of a silicon carbide semiconductor device according to a third embodiment. [Figure 17] 20 is a cross-sectional view taken along line AA' of FIG. 19 showing a configuration of a silicon carbide semiconductor device according to a fourth embodiment. FIG. [Figure 18] FIG. 20 is a cross-sectional view taken along the line BB' of FIG. 19 showing the configuration of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 19] FIG. 10 is a top view showing a configuration of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 20] FIG. 23 is a cross-sectional view taken along the line AA' of FIG. 22 showing the configuration of a conventional trench-type silicon carbide semiconductor device. [Figure 21] FIG. 23 is a cross-sectional view taken along the line BB' of FIG. 22 showing the configuration of a conventional trench-type silicon carbide semiconductor device. [Figure 22] FIG. 1 is a top view showing a configuration of a conventional trench-type silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0018] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. The same n or p symbol, including + and -, indicates similar concentrations, but does not necessarily mean that the concentrations are the same. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. In this specification, in the Miller index notation, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0019] (Embodiment 1) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the first embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. FIG. 1 is a cross-sectional view taken along line A-A' in FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line B-B' in FIG. 3 showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a top view showing the configuration of the silicon carbide semiconductor device according to the first embodiment.

[0020] The semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is a trench-type SiC-MOSFET provided on the front surface side of a semiconductor substrate (semiconductor chip) with a gate trench (first trench) 18 and a contact trench (second trench) 19. The gate trench 18 is a trench in which a gate electrode 10 is buried via a gate insulating film 9. The contact trench 19 is a trench in which an SBD having a Schottky junction formed by a Schottky electrode 15 (described later) is buried.

[0021] Specifically, as shown in FIGS. 1 and 2, the silicon carbide semiconductor device according to the first embodiment has n +A first main surface (front surface) of a silicon carbide substrate (semiconductor substrate of a first conductivity type) 1, for example, a (0001) surface (Si surface), is provided with an n - A first conductivity type drift layer (first semiconductor layer) 2 is deposited on the semiconductor substrate.

[0022] n + The silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). - The n-type drift layer 2 + The n-type drift layer is a low-concentration n-type drift layer that is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 1. - n-type drift layer 2 + An n-type heavily doped region 5 is formed on the surface opposite to the silicon carbide substrate 1 side. + Lower n than silicon carbide substrate 1 - The n-type high-concentration region 5 is a high-concentration n-type drift layer that is doped with, for example, nitrogen, at a higher impurity concentration than the n-type drift layer 2. The n-type high-concentration region 5 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + A silicon carbide substrate 1 and an n - The p-type drift layer 2 and a p-type base layer (second semiconductor layer of the second conductivity type) 6 described later are collectively referred to as a silicon carbide semiconductor substrate.

[0023] Also, n + A back electrode (second electrode) 14 is provided on a second main surface (back surface, that is, the back surface of the silicon carbide semiconductor base) of the silicon carbide substrate 1. The back electrode 14 constitutes a drain electrode.

[0024] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the gate trench 18 and the contact trench 19 are formed on the n-type +The gate insulating film 9 extends from the surface opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor base) through the p-type base layer 6 to reach the n-type high concentration region 5. A gate insulating film 9 is formed along the inner wall of the gate trench 18, on the bottom and side walls of the gate trench 18, and a gate electrode 10 is formed inside the gate insulating film 9 within the gate trench 18. The gate insulating film 9 allows the gate electrode 10 to - The gate electrode 10 is insulated from the p-type drift layer 2 and the p-type base layer 6. A part of the gate electrode 10 may protrude from above the gate trench 18 (on the source electrode pad 14 side) toward the source electrode pad 14.

[0025] n - n-type drift layer 2 + The surface layer on the side opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor base) contains p + A mold base region 3 is optionally provided. + The base region 3 is formed under the gate trench 18 and the contact trench 19. + The width of the base region 3 is wider than the width of the gate trench 18 and the contact trench 19. + The p-type base region 3 is doped with, for example, aluminum. + The p-type base region 3 is provided apart from the p-type base layer 6 .

[0026] n - A p-type base layer 6 is provided on the first main surface side of the base of the n-type drift layer 2. Inside the p-type base layer 6, an n-type + type source region (first semiconductor region of the first conductivity type) 7 and p + A contact region (second semiconductor region of the second conductivity type) 8 is selectively provided. + The n-type source region 7 is in contact with the gate trench 18. + Type source region 7 and p + The mold contact regions 8 abut each other.

[0027] The gate trenches 18 are arranged in a planar layout of parallel stripes extending in the depth direction (X-X' direction). Furthermore, the contact trenches 19 are arranged between adjacent gate trenches 18 in a planar layout of stripes extending in the X-X' direction, parallel to the gate trenches 18 and spaced apart from the gate trenches 18. For example, when contact trenches 19 are arranged in all mesa portions, the gate trenches 18 and the contact trenches 19 are arranged alternately and spaced apart from each other in the A-A' direction perpendicular to the X-X' direction. The contact trenches 19 extend from the first main surface side of the silicon carbide semiconductor substrate through the p-type base layer 6 to reach the n-type high concentration region 5. The depth of the contact trenches 19 is approximately the same as the depth of the gate trenches 18.

[0028] As shown in Fig. 3, the contact trenches 19 are provided discontinuously. Therefore, there are portions in the X-X' direction where the contact trenches 19 are not provided. The A-A' cross section in Fig. 1 is a cross section of a portion where the contact trenches 19 are provided, and the B-B' cross section in Fig. 2 is a cross section of a portion where the contact trenches 19 are not provided.

[0029] The portion in the X-X' direction where the contact trench 19 is not provided is n + A part of the source region 7 extends toward the contact trench 19. Therefore, the region sandwiched between the contact trenches 19 in the XX' direction contains n + Type source region 7 and p + The n-type contact region 8 is provided in the gate trench 18. By adopting such a structure, the n-type contact region 8 in the portion in contact with the gate trench 18 + The n-type source region 7a extends + The n-type source region 7b is connected to the n-type source region 7b, and the n-type source region 7b is connected to the n-type source region 7b. + The n-type source regions 7a are connected to each other. + Even if the area of ​​the source region 7 becomes large and the mask position is shifted when forming the gate trench 18, +This allows for the formation of the source region 7. This increases the tolerance for the position at which the mask is formed, making it possible to miniaturize the trench-type silicon carbide semiconductor device.

[0030] Although only one trench MOS structure is shown in FIG. 1, many more trench MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0031] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the gate trench 18. The source electrode (first electrode) 13 is connected to the n-type semiconductor layer 11 via a contact hole opened in the interlayer insulating film 11. + Type source region 7 and p + The source electrode 13 is in contact with the contact region 8. The source electrode 13 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 13. A barrier metal, such as a single layer or multilayer of Ti or TiN, may be provided between the source electrode 13 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 13 to the gate electrode 10 side.

[0032] A Schottky electrode 15 made of, for example, Ti silicide (TiSi) is provided along the front surface of the silicon carbide semiconductor substrate and the inner wall of the contact trench 19. The Schottky electrode 15 may be configured by stacking electrodes made of different materials. The Schottky electrode 15 functions as a front surface electrode together with the source electrode 13. The Schottky electrode 15 is p-type and extends from the front surface of the silicon carbide semiconductor substrate to the side wall of the contact trench 19. + It contacts the mold contact region 8.

[0033] The Schottky electrode 15 is formed on the entire surface of the contact trench 19 from the bottom to the corner. +The Schottky electrode 15 is in contact with the n-type high concentration region 5 on the sidewall of the contact trench 19, and forms a Schottky junction with the n-type high concentration region 5. This forms a Schottky barrier diode consisting of the Schottky electrode 15 in the contact trench 19 and the n-type high concentration region 5. The Schottky electrode 15 is also in contact with the n-type high concentration region 5. - The electrode material may be, for example, polysilicon, which forms a heterojunction between the n-type drift layer 2 and the n-type high concentration region 5. If the n-type high concentration region 5 is not provided, the n-type - A Schottky junction is formed between the n-type drift layer 2 and the conductive layer 15 in the contact trench 19. - A Schottky barrier diode is formed by the semiconductor layer and the semiconductor drift layer 2.

[0034] (Method for Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment) Next, a description will be given of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 4 to 9 are cross-sectional views schematically showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0035] First, n-type silicon carbide + A silicon carbide substrate 1 is prepared. + On the first main surface of the silicon carbide substrate 1, an n-type impurity, for example, a silicon carbide n-type impurity, is doped. - The structure of the semiconductor layer 2 is then epitaxially grown. The structure up to this point is shown in FIG.

[0036] Next, n - On the surface of the n-type drift layer 2, a lower n-type heavily doped region 5a, which is a part of the n-type heavily doped region 5, is formed by doping n-type impurities such as nitrogen. Next, an ion implantation mask having predetermined openings is formed on the surface of the lower n-type heavily doped region 5a using photolithography, for example, an oxide film. Then, p-type impurities such as aluminum are implanted into the openings in the oxide film, forming p + The mold base region 3 is formed. The state up to this point is shown in FIG.

[0037] Next, a portion of the ion implantation mask is removed, and an upper n-type heavily doped region 5b made of silicon carbide is formed on the surface of the lower n-type heavily doped region 5a while doping with n-type impurities, such as nitrogen atoms. This upper n-type heavily doped region 5b and the lower n-type heavily doped region 5a are formed so that they are at least partially in contact with each other, forming the n-type heavily doped region 5. However, this n-type heavily doped region 5 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in Figure 6.

[0038] Next, a p-type base layer 6 doped with p-type impurities such as aluminum is formed on the surface of the n-type high concentration region 5. Next, the p-type base layer 6 and the exposed n - An ion implantation mask having predetermined openings is formed on the surface of the p-type drift layer 2 by photolithography, using, for example, an oxide film. N-type impurities such as phosphorus (P) are ion-implanted into the openings, forming n-type impurities in a portion of the surface of the p-type base layer 6. + Forming the n-type source region 7. + The impurity concentration of the n-type source region 7 is set to be higher than the impurity concentration of the n-type high concentration region 5. + The ion implantation mask used to form the p-type source region 7 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner. P-type impurities such as aluminum are ion-implanted into a portion of the surface of the p-type base layer 6, forming p + A contact region 8 is provided. + The impurity concentration of the p-type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6. In the following description of the manufacturing method, only the cross section of the portion where the contact trench 19 is provided, which corresponds to the A-A' cross section in Figure 1, will be shown. The state up to this point is shown in Figure 7.

[0039] Next, heat treatment (annealing) is carried out in an inert gas atmosphere at about 1700°C, and p + Type base region 3, n + Type source region 7, p +An activation process is performed on the mold contact region 8. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be performed by performing a heat treatment after each ion implantation.

[0040] Next, a trench forming mask having predetermined openings is formed on the surface of the p-type base layer 6 by photolithography, using, for example, an oxide film. Next, gate trenches 18 and contact trenches 19 are formed by dry etching, penetrating the p-type base layer 6 and reaching the n-type high concentration region 5. At this time, the mask is formed so that the contact trenches 19 are formed intermittently. The bottoms of the gate trenches 18 and contact trenches 19 are connected to the p-type high concentration region 5 formed in the n-type high concentration region 5. + This may extend to the mold base region 3. The trench mask is then removed, as shown in FIG.

[0041] Next, annealing is performed to round the corners of the bottoms and openings of the gate trench 18 and the contact trench 19. Before annealing, isotropic etching may be performed to remove damage to the gate trench 18 and the contact trench 19.

[0042] Next, n + Type source region 7 and p + A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the gate trench 18. This gate insulating film 9 may be formed by thermal oxidation using heat treatment at a temperature of about 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a deposition method using a chemical reaction such as high temperature oxidation (HTO).

[0043] Next, a field oxide film 17 is formed by sacrificial oxidation and CVD (Chemical Vapor Deposition). The field oxide film 17 is patterned by photolithography and etching, and the contact trench 19 is filled with the field oxide film 17.

[0044] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the gate trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the gate trench 18 to form the gate electrode 10.

[0045] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9, the gate electrode 10, the gate trench 18, and the field oxide film 17, forming an interlayer insulating film 11. The interlayer insulating film 11 is patterned by photolithography. + Type source region 7 and p + A contact hole is formed to expose the mold contact region 8. Then, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11. Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) is formed to cover the interlayer insulating film 11. Then, the barrier metal in the contact hole portion is removed.

[0046] Next, a conductive film such as nickel (Ni) that will become source electrode 13 is provided in the contact hole and on interlayer insulating film 11. This conductive film is patterned by photolithography, leaving source electrode 13 only in the contact hole.

[0047] Next, a back electrode (not shown) made of nickel or the like is provided on the second main surface of the n-type silicon carbide semiconductor substrate 1. After that, a heat treatment is performed in an inert gas atmosphere at about 1000° C. to form the n + Type source region 7, p + A source electrode 13 and a back surface electrode 14 are formed to form ohmic junctions with the contact region 8 and the n-type silicon carbide semiconductor substrate 1. The state up to this point is shown in FIG.

[0048] Next, the interlayer insulating film 11 on the contact trench 19 and the field oxide film 17 inside the contact trench 19 are removed, and one of Ti, W (tungsten), Ni, and Mo (molybdenum) is deposited as a Schottky metal. After this, patterning is performed to remove the Schottky metal from areas other than the active area. Next, annealing is performed at 400°C to 600°C to form a Schottky electrode 15 along the bottom and sidewalls of the contact trench 19.

[0049] Next, n + An aluminum film having a thickness of about 5 μm is deposited on the first main surface of the silicon carbide semiconductor substrate 1 by sputtering, and the aluminum is removed by photolithography so as to cover the source electrode 13 and the interlayer insulating film 11 in the active portion, thereby forming a source electrode pad.

[0050] Next, a drain electrode pad (not shown) is formed by sequentially stacking, for example, titanium (Ti), nickel, and gold (Au) on the surface of the back surface electrode 14. In this manner, the silicon carbide semiconductor device shown in FIGS.

[0051] As described above, in the silicon carbide semiconductor device according to the first embodiment, the contact trenches are provided discontinuously, and the n-type contact trenches are formed at the portions where the contact trenches are in contact with the adjacent gate trenches. + The n-type source regions are connected together. + Even if the area of ​​the source region becomes larger and the mask position is shifted when forming the gate trench, + This increases the tolerance for the position at which the mask is formed, making it possible to miniaturize trench-type silicon carbide semiconductor devices.

[0052] (Embodiment 2) Next, a structure of a silicon carbide semiconductor device according to the second embodiment will be described. Fig. 10 is a cross-sectional view taken along line A-A' in Fig. 12 showing the configuration of the silicon carbide semiconductor device according to the second embodiment. Fig. 11 is a cross-sectional view taken along line B-B' in Fig. 12 showing the configuration of the silicon carbide semiconductor device according to the second embodiment. Fig. 12 is a top view showing the configuration of the silicon carbide semiconductor device according to the second embodiment.

[0053] The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that p-type base layer 6 is partially provided and isolated from contact trench 19 .

[0054] 12, in the second embodiment, as in the first embodiment, the contact trenches 19 are provided discontinuously in the regions sandwiched between the gate trenches 18. As shown in Fig. 10, where the contact trenches 19 are provided, the p-type base layer 6 is partially provided to isolate the contact trenches 19. Furthermore, as shown in Fig. 11, the p-type base layer 6 is provided continuously where no contact trenches 19 are provided.

[0055] By isolating the p-type base layer 6 from the contact trench 19, the area where the contact trench 19 is in contact with the n-type high concentration region 5 increases. Specifically, the area where the contact trench 19 is in contact with the region A, which was previously in contact with the p-type base layer 6, increases. A Schottky junction is also formed in this area, and the Schottky junction area can be increased.

[0056] In addition, since the contact trenches 19 are provided discontinuously, even if the p-type base layer 6 is isolated from the contact trenches 19, the n + Therefore, the n-type source region 7 and the n-type heavily doped region 5 are not short-circuited.

[0057] Next, a method for manufacturing a silicon carbide semiconductor device according to the second embodiment will be described. First, similarly to the first embodiment, steps up to the step of forming the n-type heavily doped region 5 are performed (see FIG. 6). Next, an ion implantation mask having a predetermined opening is formed on the surface of the n-type heavily doped region 5 by photolithography, for example, using an oxide film. At this time, the mask is formed so that the p-type base layer 6 is isolated from the contact trench 19. Then, p-type impurities such as aluminum are implanted into the opening in the oxide film to form the p-type base layer 6. Thereafter, the n-type impurity layer 6 of the first embodiment is implanted by photolithography. + By performing the steps from the step of forming type source region 7 onwards, the silicon carbide semiconductor device shown in FIGS. 10 and 11 is completed.

[0058] The p-type base layer 6 can also be formed by epitaxial growth. For example, the p-type base layer 6 can be formed by doping a p-type impurity such as aluminum on the surface of the n-type high concentration region 5, and then partially converting a portion of the p-type base layer 6 to n-type by partial ion implantation of an n-type impurity such as nitrogen, thereby forming a p-type base layer 6 isolated from the contact trench 19.

[0059] As described above, in the silicon carbide semiconductor device according to the second embodiment, the p-type base layer is partially provided to isolate it from the contact trench. This increases the area where the contact trench contacts the n-type heavily doped region. As a result, a Schottky junction is formed in this area as well, thereby increasing the Schottky junction area.

[0060] (Embodiment 3) Next, a structure of a silicon carbide semiconductor device according to a third embodiment will be described. Fig. 13 is a cross-sectional view taken along line A-A' in Fig. 16 showing the configuration of the silicon carbide semiconductor device according to the third embodiment. Fig. 14 is a cross-sectional view taken along line B-B' in Fig. 16 showing the configuration of the silicon carbide semiconductor device according to the third embodiment. Fig. 15 is a cross-sectional view taken along line C-C' in Fig. 16 showing the configuration of the silicon carbide semiconductor device according to the third embodiment. Fig. 16 is a top view showing the configuration of the silicon carbide semiconductor device according to the third embodiment.

[0061] The silicon carbide semiconductor device according to the third embodiment differs from the silicon carbide semiconductor device according to the second embodiment in that contact trenches 19 are divided into smaller trenches than those in the second embodiment. As shown in FIG. 16, the region sandwiched between contact trenches 19 has n + Type source region 7 and p + a region where the p-type contact region 8 is provided; + and a region where only the mold contact region 8 is provided.

[0062] For example, the region S1 in FIG. 16 is a region sandwiched between contact trenches 19. + Type source region 7 and p + The region S2 is a region where the contact region 8 is provided, and the region S2 is a region sandwiched between the contact trenches 19. + 14 shows a region where only the n-type contact region 8 is provided. + Type source region 7 and p + 15 is a cross section of a region where a p-type contact region is provided, and FIG. 15 shows a region sandwiched by contact trenches 19. + 1 is a cross section of a region where only the n-type contact region 8 is provided. + Type source region 7 and p + a region where the p-type contact region 8 is provided; + It is preferable that the regions where only the mold contact region 8 is provided are provided alternately.

[0063] By doing this, p + Even if the area of ​​the contact region 8 becomes large and the mask position for forming the gate trench 18 is shifted, + Therefore, the tolerance for the mask formation position is greater than in the first and second embodiments, and the trench-type silicon carbide semiconductor device can be miniaturized more than in the first and second embodiments. + The increased size of the mold contact region 8 also reduces the contact resistance.

[0064] The silicon carbide semiconductor device according to the third embodiment is fabricated by the method for fabricating a silicon carbide semiconductor device according to the second embodiment, wherein contact trench 19 is further subdivided to form n + Type source region 7 and p + This can be achieved by changing the position where the mold contact region 8 is formed.

[0065] As described above, according to the silicon carbide semiconductor device of the third embodiment, the contact trenches are further divided, and the regions sandwiched between the contact trenches are provided with n + Type source region and p + A region provided with a p-type contact region + A region where only the p-type contact region is provided can be provided. + Even if the area of ​​the contact region becomes larger and the mask position is shifted when forming the gate trench, + Therefore, the tolerance for the mask formation position is increased, and trench-type silicon carbide semiconductor devices can be further miniaturized.

[0066] (Fourth embodiment) Next, a structure of a silicon carbide semiconductor device according to the fourth embodiment will be described. Fig. 17 is a cross-sectional view taken along line A-A' in Fig. 19 showing the configuration of the silicon carbide semiconductor device according to the fourth embodiment. Fig. 18 is a cross-sectional view taken along line B-B' in Fig. 19 showing the configuration of the silicon carbide semiconductor device according to the fourth embodiment. Fig. 19 is a top view showing the configuration of the silicon carbide semiconductor device according to the fourth embodiment.

[0067] The silicon carbide semiconductor device according to the fourth embodiment differs from the silicon carbide semiconductor device according to the second embodiment in that the silicon carbide semiconductor device according to the fourth embodiment has n-type base layer 6 on the surface thereof. + 19, the n-type source region 16 has a lower impurity concentration than the n-type source region 7. + The n-type source region 7 is in contact with the gate trench 18. + The n-type source region 7a and the n-type source region 10 are provided in the region sandwiched between the contact trench 19. + and n-type source region 7c.+ Type source region 7a and n + An n-type source region 16 is provided between the n-type source region 7c and the n-type source region 7d.

[0068] By providing the n-type source region 16 in this way, the source follower effect and back gate effect can reduce the current during a short circuit with a small increase in on-resistance. + This is because the temperature characteristic is greater than that of the source region 7, and therefore when a large current flows during a short circuit, the resistance increases, thereby limiting the current.

[0069] The silicon carbide semiconductor device according to the fourth embodiment is the same as the method for manufacturing a silicon carbide semiconductor device according to the second embodiment, except that n + Type source region 7 and p + The step of forming the contact region 8 (see FIG. 7) is + Type source region 7, p + The semiconductor device can be manufactured by forming the n-type contact region 8 and the n-type source region 16.

[0070] As described above, according to the silicon carbide semiconductor device of the fourth embodiment, the n + The n-type source region and the n-type source region are provided in the region sandwiched between the contact trenches. + An n-type source region is provided between the n-type source region. This increases the resistance when a large current flows during a short circuit, limiting the current. Therefore, the current during a short circuit can be reduced with only a small increase in on-resistance.

[0071] In the above-described embodiments, silicon carbide is used as the wide bandgap semiconductor, but similar effects can be obtained when a wide bandgap semiconductor other than silicon carbide, such as gallium nitride (GaN), is used. Also, in the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is equally valid when the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0072] As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for semiconductor devices with a trench gate structure. [Explanation of symbols]

[0073] 1n + Silicon carbide substrate 2n - Mold drift layer 3 p + Type-based domain 5 n-type high concentration region 5a Lower n-type high concentration region 5b Upper n-type high concentration region 6 p-type base layer 7n + Type Source Area 8 p + Mold contact area 9 Gate insulating film 10 gate electrode 11 Interlayer insulating film 13 Source electrode 14 Drain electrode 15 Schottky electrode 16 n-type source region 17 Field oxide 18 Gate Trench 19 Contact trench

Claims

1. a semiconductor substrate; a plurality of MOS gate structures provided in parallel on the front surface side of the semiconductor substrate; Equipped with The MOS gate structure includes an N-type semiconductor region and an N + a P-type source region, a P-type base region disposed between the semiconductor region and the source region in a depth direction, a gate electrode extending in a stripe shape in a first direction but not extending in a second direction perpendicular to the first direction, and a gate insulating film, a first unit in which a Schottky barrier diode is formed between adjacent first and second MOS gate structures among the plurality of MOS gate structures; The source region or P is formed between the first MOS gate structure and the second MOS gate structure adjacent to each other. + a second unit having an extension portion that is a contact region of the Schottky barrier diode, the extension portion extending in the second direction through a region sandwiched between the Schottky barrier diodes in the first direction; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the extending portion connects the source region of the first MOS gate structure and the source region of the second MOS gate structure.

3. an interlayer insulating film provided on the front surface side of the semiconductor substrate; a conductive electrode in contact with the first unit and the second unit through a contact hole provided in the interlayer insulating film; 3. The semiconductor device according to claim 1, further comprising:

4. 4. The semiconductor device according to claim 3, wherein the extending portion is in contact with the conductive electrode.

5. 5. The semiconductor device according to claim 3, wherein the conductive electrode has a barrier metal containing Ti.

6. 6. The semiconductor device according to claim 3, wherein the conductive electrode includes any one of Ti, W (tungsten), Ni, and Mo (molybdenum), and has a Schottky electrode in contact with the first unit.

7. 7. The semiconductor device according to claim 1, wherein the first units are provided intermittently in the first direction.

8. a contact trench in which the conductive electrode is embedded is provided between the first MOS gate structure and the second MOS gate structure adjacent to each other; 7. The semiconductor device according to claim 3, wherein the contact trenches are provided discontinuously in the first direction.

9. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a trench-type SiC-MOSFET.

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