How to convert numbers

Abstract

A vector pack instruction and a vector unpack instruction are described with respect to a method of format conversion of numeric values. An instruction is executed to perform a conversion between one decimal format and another decimal format, the one decimal format or the other decimal format being a zoned decimal format. The executing includes obtaining values ​​from at least one register specified using the instruction. At least a portion of the values ​​are converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written to a single register specified using the instruction.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to improving such processing. [Background technology]

[0002] Applications executing within computing environments provide many of the operations used by a wide variety of technologies, including, but not limited to, design, manufacturing, medical technology, automotive technology, computer processing, etc. These applications, written in programming languages ​​such as COBOL, represent numerical values ​​in a particular format and often require conversion from one format to another, for example, to perform calculations or present data, or both.

[0003] One format used to represent numbers is packed decimal format, which can be signed or unsigned. In packed decimal format, each byte contains two 4-bit decimal digits (D). In signed packed decimal format, the rightmost byte to the right of the 4-bit decimal digits contains a 4-bit sign (S).

[0004] Another format used to represent numeric values ​​is the zoned decimal format, which can be unsigned or signed. In the unsigned zoned decimal format, each byte contains two fields: a zone field in the leftmost four-bit positions and a decimal digit in the rightmost four-bit positions. The signed zoned decimal format (also called the embedded signed zoned decimal format) is similar to the unsigned zoned decimal format, except that the zone field in the rightmost byte contains a 4-bit sign. A separate signed zoned decimal format also exists, in which the sign is encoded as a separate byte and the numeric portion of the value is in unsigned zoned decimal format.

[0005] An embedded signed zoned decimal data item, for example in COBOL, can range from 1 to 31 bytes to encode 1 to 31 decimal digits. A separate signed zoned decimal data item can range from 2 to 32 bytes to encode 1 to 31 decimal digits and a 1-byte sign code. Due to the large and variable size of zoned decimal data, zoned decimal data is currently supported only as a storage operand. Before operating on the zoned decimal data, for example to perform a calculation, the zoned decimal data is converted to another format, such as packed decimal or decimal floating point. The result of the calculation is then converted back to a zoned decimal storage operand. These conversions to and from memory are time-consuming, affecting the performance of the computing environment and the availability of computer resources. Summary of the Invention

[0006] Shortcomings of the prior art are overcome and additional advantages are achieved by providing a computer program product for facilitating processing within a computing environment. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method includes executing the instructions to perform a conversion between one decimal format and another decimal format. The one decimal format or another decimal format is a zoned decimal format. The execution includes obtaining a value from at least one register specified using the instructions, converting at least a portion of the value from the one decimal format to another decimal format different from the one decimal format to provide a converted result, and writing a result obtained from the converted result to a single register specified using the instructions.

[0007] By performing at least the transform and write operations using a single instruction, performance is improved and resource utilization is reduced. By performing at least the transform and write operations using a single designed instruction, certain tasks, such as the transform and write operations, can be performed much more efficiently than using a software paradigm. The transform and write operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0008] The use of registers, such as hardware vector registers, to convert between zoned decimal format and another format, to operate on data, or to use data, for example, with SIMD (single instruction, multiple data) instructions, is performed using the registers directly. For example, input and output are provided in registers. This is more efficient than using memory to obtain input or store output, or both. Operations are performed faster, reducing execution time and improving processor or overall system performance. Additionally, by using registers in zoned decimal format, some operations, such as numeric editing and / or string manipulation of zoned decimal data items, for example, using the COBOL INSPECT statement, can be performed more efficiently by operating directly on the data in registers in zoned decimal format.

[0009] Additionally, writing to a single register is beneficial for data dependencies and out-of-order execution: writing to one register instead of multiple registers reduces contention per instruction execution.

[0010] In one example, one decimal format is a zoned decimal format and the other decimal format is a packed decimal format.

[0011] In one example, obtaining the value includes obtaining a first value from a first vector register specified using at least one field of the instruction, obtaining a second value from a second vector register specified using at least one field of the instruction, and concatenating the first value and the second value to obtain the value.

[0012] In one example, writing includes determining the number of digits of the converted result to be written as a result, selecting the determined number of digits of the converted result to be written as a result, and writing the selected determined number of digits to a single register, thereby providing flexibility.

[0013] In one example, determining the number of digits involves checking a control specified using the instruction. Further, in one example, the single register is a single vector register. This control allows for flexibility and ease in using the instruction.

[0014] As another example, one decimal number format is a packed decimal number format and the other decimal number format is a zoned decimal number format. In one example, converting at least a portion of the value includes converting selected digits of the value to obtain a converted result. The selected digits include, for example, the leftmost 15 digits of the value. As a further example, the selected digits include the rightmost 16 digits of the value, and converting includes converting the sign of the value.

[0015] In one example, writing includes writing the transformed result to a selected portion of a single register, where the single register is a vector register.

[0016] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0017] Additional features and advantages are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0018] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, together with objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0019] [Figure 1A] FIG. 1 illustrates an example computing environment for incorporating and using one or more aspects of the present invention. [Figure 1B] 1B illustrates further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2A] FIG. 2 illustrates an example of a zoned decimal number format in accordance with one or more aspects of the present invention. [Figure 2B] FIG. 2 illustrates an example of a signed packed decimal number format in accordance with one or more aspects of the present invention. [Figure 3A] FIG. 10 illustrates an example format for a Vector Pack Zoned Register instruction in accordance with one or more aspects of the present invention. [Figure 3B] FIG. 10 illustrates an example of further details of a mask field of a vector pack zone register instruction in accordance with one or more aspects of the present invention. [Figure 3C] FIG. 10 illustrates an example of further details of the immediate fields of a vector pack zone register instruction in accordance with one or more aspects of the present invention. [Figure 4] FIG. 1 illustrates an example of processing associated with executing a vector pack zone register instruction in accordance with one or more aspects of the present invention. [Figure 5A]FIG. 2 illustrates an example format for a Vector Unpack Zoned High instruction in accordance with one or more aspects of the present invention. [Figure 5B] FIG. 10 illustrates an example of further details of the mask field of the vector unpack zone high instruction in accordance with one or more aspects of the present invention. [Figure 5C] FIG. 2 illustrates an example format for a Vector Unpack Zoned Low instruction in accordance with one or more aspects of the present invention. [Figure 5D] FIG. 10 illustrates an example of further details of the mask field of a vector unpack zone low instruction in accordance with one or more aspects of the present invention. [Figure 6] FIG. 2 illustrates an example of processing associated with executing a vector unpack zone high instruction or a vector unpack zone low instruction in accordance with one or more aspects of the present invention. [Figure 7A] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 7B] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 8A] FIG. 1 illustrates another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 8B] FIG. 8B illustrates an example of further details of the memory of FIG. 8A in accordance with one or more aspects of the present invention. [Figure 8C] 8B illustrates another example of further details of the memory of FIG. 8A in accordance with one or more aspects of the present invention. [Figure 9A] FIG. 1 illustrates yet another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 9B]9B illustrates further details of the memory of FIG. 9A in accordance with one or more aspects of the present invention. [Figure 10] FIG. 1 illustrates one embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 11] FIG. 2 illustrates an example of an abstract model layer in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] In accordance with one or more aspects of the present invention, capabilities are provided to facilitate processing within a computing environment. As one example, a single instruction (e.g., a single designed hardware machine instruction at a hardware / software interface) is provided to perform a pack operation or an unpack operation. For example, a vector pack zone register instruction is provided to perform a pack operation, and a vector unpack zone high instruction and a vector unpack zone low instruction are provided to perform an unpack operation. Each instruction is part of the instruction set architecture (ISA) of a general-purpose processor, dispatched by a program on a processor such as a general-purpose processor (in another example, each instruction may be part of a special-purpose processor, such as a coprocessor configured for a specific function).

[0021] As part of the execution of a vector pack zoned register instruction, a packing operation is performed where zoned decimal numbers are represented in packed decimal format. Various operations are used to perform the packing operation, such as concatenation, conversion, register write, validity check, or condition code setting, or a combination thereof. Each of these operations is performed as part of executing a single instruction, improving system performance and reducing system resource usage. Additionally, in one example, hardware registers (e.g., vector registers) specified with the instruction for both the source and target data are used in the packing operation, allowing the instruction to operate on and / or use the data directly in the register. This saves time, improves system performance, and reduces system resource usage.

[0022] In a further aspect, as part of the execution of a vector unpack zone high instruction or a vector unpack zone low instruction, an unpack operation is performed in which a packed decimal number is represented as one or more zoned decimal numbers. To perform the unpack operation, various operations are used, such as, for example, conversion, register write, or validity check, or a combination thereof. Each of these operations is performed as part of executing a single instruction, improving system performance and reducing system resource usage. Furthermore, in one example, hardware registers (e.g., vector registers) specified with the instruction for both the source data and the target data are used in the unpack operation, allowing the instruction to operate on and / or use the data directly in the registers. This saves time, improves system performance, and reduces system resource usage.

[0023] In one aspect, each instruction uses a single output vector register to hold packed or unpacked data, which is beneficial for data dependencies and out-of-order execution. By writing to one register instead of multiple registers, contention per instruction execution is reduced.

[0024] One embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 1A. As an example, the computing environment is based on the z / Architecture® hardware architecture provided by International Business Machines Corporation (Armonk, New York). One embodiment of the z / Architecture hardware architecture is described in the publication “z / Architecture Principles of Operation,” IBM Publication No. SA22-7832-12, Thirteenth Edition, September 2019, which is incorporated herein by reference in its entirety. However, the z / Architecture hardware architecture is only one exemplary architecture, and other architectures or types of computing environments of International Business Machines Corporation or other entities or both may include and / or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0025] 1A, computing environment 100 includes a computer system 102, shown, for example, in the form of a general-purpose computing device. Computer system 102 may include, but is not limited to, one or more processors or processing units 104 (e.g., central processing units (CPUs)), memory 106 (e.g., also referred to as system memory, main memory, primary storage, central storage, or storage), and one or more input / output (I / O) interfaces 108, coupled together via one or more buses or other connections 110 or both.

[0026] Bus 110 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example only, Industry Standard Architecture (ISA), MicroChannel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI).

[0027] The memory 106 may include a cache 112, such as a shared cache, which may be coupled to a local cache 114 of the processor 104, for example. Additionally, the memory 106 may include one or more programs or applications 116 and at least one operating system 118. An exemplary operating system includes the z / OS® operating system offered by International Business Machines Corporation (Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and / or other entities may also be used. The memory 106 may include one or more computer-readable program instructions 120, which may be configured to perform functions of embodiments of aspects of the present invention.

[0028] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, for example, via the I / O interface 108. The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0029] The computer system 102 may communicate, for example, via the I / O interface 108, with a network interface 132 that enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0030] Computer system 102 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, computer system 102 may include and / or be coupled to non-removable, non-volatile magnetic media (typically referred to as a "hard drive"), a magnetic disk drive for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or an optical disk drive for reading from or writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used with computer system 102, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0031] Computer system 102 may operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0032] In one example, a processor (e.g., processor 104) includes multiple functional components used to execute instructions. As shown in FIG. 1B , these functional components include, for example, an instruction fetch component 150 for fetching instructions to be executed, an instruction decode unit 152 for decoding the fetched instructions and obtaining operands for the decoded instructions, one or more instruction execution components 154 for executing the decoded instructions, a memory access component 156 for accessing memory to execute the instructions, if necessary, and a writeback component 158 ​​for providing results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in instruction processing. Additionally, one or more of the components may include or be able to access at least a portion of one or more other components used in performing pack and unpack operations of, for example, a vector pack zone register instruction, a vector unpack zone high instruction, or a vector unpack zone low instruction, or combinations thereof (or other processes that may employ one or more aspects of the present invention) in accordance with one or more aspects of the present invention and as described herein. The one or more other components may include, for example, pack component / unpack component (or one or more other components) 170.

[0033] The packing and unpacking operations described herein involve conversion between one decimal format, such as zoned decimal format, and another decimal format, such as signed packed decimal format. Examples of these formats are described with reference to Figures 2A-2B.

[0034] Referring to FIG. 2A, an example of a zoned decimal number format is shown. In one example, a zoned decimal number includes 32 digits (e.g., 256 bits), with each digit stored in a byte. For example, byte 200 of a zoned decimal number includes a zone portion (e.g., the leftmost four bits) 202 and a digit portion (e.g., the rightmost four bits) 204. The digit portion 204 includes a code representing the decimal digit. A decimal number in zoned format may be part of a larger character set that includes alphabetic characters and special characters. The zone portion of the low-order byte 206 (e.g., the rightmost byte of a decimal operand) may include the sign 208 of the decimal digit.

[0035] 2B, an example of a signed packed decimal number format is shown. In one example, a signed packed decimal number is 128 bits long, and each byte 220 of storage (except for the rightmost byte, the low byte) may contain two decimal digits 222. The low byte may contain, for example, a digit in the leftmost portion 224 of the byte and a sign (positive or negative) in the rightmost portion 226 of the byte.

[0036] In accordance with one or more aspects of the present invention, various instructions are used to perform packing and unpacking operations on zoned decimal and packed decimal values. For example, an instruction referred to herein as a vector pack zone register instruction is provided to perform the packing operation. As part of executing the instruction, multiple operations are used to perform the packing operation, including, for example, a concatenation operation, a conversion operation, a write to register operation, a validity check operation, and / or a condition code setting operation.

[0037] One embodiment of a vector pack zone register instruction used to perform a pack operation, for example, including a concatenation operation, a conversion operation, a write to register operation, a validity check operation, or a condition code setting operation, or a combination thereof, is described with reference to FIGS. 3A-3C. The instruction, in one example, is executed using a general-purpose processor (e.g., processor 104). In the description herein, specific locations of fields, specific fields, or specific sizes, or combinations thereof, are indicated (e.g., specific bytes and / or bits). However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, while setting bits to specific values ​​(e.g., 1 or 0) may be specified, this is merely an example. Bits may be set to different values, such as opposite or different values, in other examples. Many variations are possible.

[0038] In one example, the vector pack zone register instruction has a VRI-f format that indicates a vector register and immediate operation along with an extended operation code (opcode). The vector pack zone register instruction is part of, for example, a vector function that provides fixed-size vectors containing, for example, 1 to 16 elements. Each vector contains data that is operated on by the vector instructions defined in this function. In one embodiment, when a vector consists of multiple elements, each element is processed in parallel with the other elements. In one example, instruction completion does not occur until processing of all elements is complete. In other embodiments, elements are processed partially in parallel, sequentially, or both.

[0039] In one embodiment, there are 32 vector registers, and other types of registers can be mapped to the vector register quadrants. For example, a register file, which is an array of processor registers within a central processing unit (e.g., processor 104), may contain 32 vector registers, each 128 bits in length. Sixteen floating-point registers, each 64 bits in length, can overlap the vector registers. Thus, as an example, if floating-point register 2 is modified, vector register 2 is also modified. Other mappings of other types of registers are possible.

[0040] For example, vector data may appear in storage in the same left-to-right order as other data formats: bits of the data format numbered 0-7 form the byte in the leftmost (lowest numbered) byte position in storage, bits 8-15 form the byte in the next consecutive position, etc. In yet another example, vector data may appear in storage in a different order, such as right-to-left.

[0041] As shown in FIG. 3A , in one example, a vector pack zone register instruction 300 includes multiple fields, which may have subscript numbers associated with them. The subscript numbers associated with a field of the instruction indicate the operand to which the field applies. For example, the subscript number 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The length of a register operand is one register, e.g., 128 bits.

[0042] In one embodiment, the vector pack zoned register instruction 300 includes operation code (opcode) fields 302a, 302b (e.g., bits 0-7 and 40-47) indicating a pack operation where the input data is, e.g., a zoned decimal number and the output is, e.g., a signed packed decimal number; a first vector register (V1) field 304 (e.g., bits 8-11) used to specify a first vector register; a second vector register (V2) field 306 (e.g., bits 12-15) used to specify a second vector register; a third vector register (V3) field 308 (e.g., bits 16-19) used to specify a third vector register; a mask (M5) field 310 (e.g., bits 24-27); an immediate (I4) field 312 (e.g., bits 28-35); and a register extension bit (RXB) field 314 (e.g., bits 36-39), each of which is described below. In one embodiment, each field is separate and independent of one another, but in other embodiments, two or more fields may be combined. More information regarding these fields is described below.

[0043] In one embodiment, the vector register (V1) field 304 is used to indicate a vector register that stores a first operand. The first operand is the result obtained from a pack operation, which may include, for example, concatenating a second operand located in a vector register specified using the V2 field 306 and a third operand located in a vector register specified using the V3 field 308 to form, for example, a 32-byte zoned decimal number including 32 digits and a sign, and converting this zoned decimal number to, for example, a signed packed decimal format including, for example, 31 digits and a sign.

[0044] In one example, each of the vector register fields 304, 306, and 308 is used in conjunction with the RXB field 314 to specify a vector register. For example, the RXB field 314 contains the most significant bit of the operand specified by the vector register. Bits of the register specification not specified by the instruction are reserved and are set to 0. The most significant bit is, for example, concatenated to the left of the 4-bit register specification of the vector register field to create a 5-bit vector register specification.

[0045] In one example, the RXB field includes four bits (eg, bits 0-3), each defined as follows: 0 - The most significant bit of the instruction's first vector register specification (e.g., bits 8 through 11). 1 - The most significant bit of the instruction's second vector register specification (e.g., bits 12-15), if present. 2 - The most significant bit of the instruction's third vector register specification (e.g., bits 16-19), if present. 3 - The most significant bit of the instruction's fourth vector register specification (e.g., bits 32-35), if present. Each bit is set to 0 or 1 depending on the register number, e.g., by an assembler. For example, for registers 0-15, the bit is set to 0, for registers 16-31, the bit is set to 1, etc.

[0046] In one embodiment, each RXB bit is an extension bit for a particular position in an instruction containing one or more vector registers. For example, bit 0 of RXB is the extension bit for positions 8-11, assigned to, for example, V1, and so on. Specifically, for vector registers, registers containing operands are specified using a 4-bit field in the register field, for example, with the corresponding register extension bit (RXB) added as the most significant bit. For example, if the 4-bit field is 0110 and the extension bit is 0, then the 5-bit field 00110 indicates register number 6. In a further embodiment, the RXB field includes additional bits, so that two or more bits per vector or position are used as extensions.

[0047] In one example, a mask field (e.g., M5 310) of an instruction is used in controlling one or more aspects of the execution of the instruction as described herein. In one example, referring to FIG. 3B, the M5 field 310 includes, for example:

[0048] No Sign Validation (NSV) 320: If this control (e.g., bit 0) is 0 and the No Validation (NV) control (e.g., bit 1) (described below) is 0, the sign code of the source vector (e.g., the concatenation of the second and third operands) is checked for validity to determine if a general operand data exception exists. If this control (e.g., bit 0) is 1 or the No Validation control is 1, only the sign code of the source vector is checked for validity to set the condition code.

[0049] No Validation (NV) 322: If this control (e.g., bit 1) is 0, the validity of the digits of the source vector is checked for general operand data exceptions, and if the No Sign Validation control is 0, the validity of the sign code of the source vector is also checked. If this control (e.g., bit 1) is 1, only the validity of the digits and sign code of the source vector is used to set the condition code, and no general operand data exceptions are reported.

[0050] Force Operand 1 Positive (P1) 324: If this control (e.g., bit 2) is 1, the sign of the result placed in the first operand is forced to be positive, e.g., a sign code of 1111 is used. If this control (e.g., bit 2) is 0, the sign of the result placed in the first operand maintains the sign code from the source vector.

[0051] Condition Code Set (CS) 326: If this control (e.g., bit 3) is 0, the condition code is not set and remains unchanged. If this control (e.g., bit 3) is 1, the condition code is set as specified below.

[0052] If the condition code setting control is 1, the condition codes are set as follows:

[0053] 0 The result is equal to 0, all digits and signs are significant, and there is no overflow.

[0054] 1 The result is not equal to 0, the sign is negative, all digits and signs are significant, and there is no overflow.

[0055] 2 The result is not equal to 0, the sign is positive, all digits and signs are significant, and there is no overflow.

[0056] 3 Overflow or invalid digits or invalid sign.

[0057] Below are summarized example combinations of no validation field, no sign validation field, and set condition code field, as well as whether the sign of the digit is checked for general data exceptions (this check is independent of a force operand 1 positive value) and whether the condition code is set based on validity.

[0058] NV NSV CS General Data Exceptions Checking the sign of General Data Exceptions Checking digits for Condition Code Settings

[0059] 0 0 0 Yes Yes No

[0060] 0 0 1 Yes Yes Yes

[0061] 0 1 0 No Yes No

[0062] 0 1 1 No Yes Yes

[0063] 1 0 0 No No No

[0064] 1 0 1 No No Yes

[0065] 1 1 0 No No No

[0066] 1 1 1 No No Yes

[0067] In one example, if novalidation or nosignvalidation is equal to 1, the sign code is not checked for validity, and if the forceoperand1positive is equal to 0, an invalid sign code in the source operand is propagated to the result.

[0068] In one example, the instruction also uses an immediate field (e.g., I4312). As an example, referring to Figure 3C, the immediate field 312 may include, for example:

[0069] Instruction Overflow Mask (IOM) 330: This control (e.g., bit 0) is the instruction overflow mask. If the instruction overflow mask is 1, or if the decimal overflow mask (e.g., in a control register such as the program status word) is 0, the decimal overflow exception is suppressed.

[0070] Result Digits Count (RDC) 332: Bits 3 through 7 contain an unsigned binary number that specifies the number of rightmost digits of the source vector to place in the first operand. If the magnitude of the source vector is larger than the largest decimal number that can be represented using the specified number of digits, a decimal overflow occurs, and a program interrupt for decimal overflow occurs if the decimal overflow mask is 1 and the instruction overflow mask is 0. If the result digits field is 0, a specification exception is reported.

[0071] In one example, bits 1-2 are reserved and will contain 0; otherwise, a specification exception is recognized.

[0072] In execution of one embodiment of the vector pack zoned register instruction, a source vector (also referred to as a concatenated value) is formed from the concatenation of a second operand located in a vector register specified using the V2 field 306 followed by a third operand located in a vector register specified using the V3 field 308 to form, for example, a 32-byte zoned decimal number containing 32 digits and a sign. The source vector is converted to a converted result, for example, a signed packed decimal format containing, for example, 31 digits and a sign. The result obtained from the converted result is placed in the location of the first operand (e.g., the vector register specified using the V1 field 304).

[0073] In one example, all digit codes of the source vector are checked for validity to determine if a general operand data exception exists unless, for example, the no validation control is 1. For example, the sign code of the source vector is checked for validity to determine if a general operand data exception exists unless, for example, the no sign validation control is 1 and the no validation control is 1. In one example, the validity of the zone digits is not checked and the source vector contains only one sign digit, for example, located in the zone field of the rightmost byte.

[0074] The condition code setting control is independent of the general operand data exception control; for example, if equal to 1, all digits and sign codes of the source vector are checked for validity to determine the condition code setting.

[0075] The determination of general operand data exceptions takes precedence over the detection of decimal overflow, in one example, prior to the detection of decimal overflow.

[0076] If the result length control specifies fewer than 31 digits, zeros are placed in the remaining leftmost digits of the first operand. If the leftmost digit of the source vector is non-zero, or leading zero digits are excluded, and the result length field specifies fewer digits than the number of digits in the source vector, decimal overflow occurs. If the decimal overflow mask is, for example, 0, or the instruction overflow mask field in the fourth operand is, for example, 1, decimal overflow is suppressed.

[0077] Further details of one embodiment of a process based on execution of a vector pack zone register instruction in accordance with one or more aspects of the present invention are described with reference to FIG. 4. In one example, a processor, such as general processor 104, is used to execute the instruction. As an example, hardware of the processor is used to execute the instruction. The hardware may be within or coupled to the processor for receiving instructions from the processor, which may, for example, retrieve, decode, and configure the instructions for execution on the hardware. Other variations are possible.

[0078] 4, in one embodiment, an instruction, such as a vector packed zone register instruction, is first obtained (e.g., fetched, received, provided, etc.) (400) and executed (410). This execution includes, for example, obtaining a second operand and a third operand of the instruction (412), which are concatenated to provide a concatenated value (also referred to as a source vector) (414). The second operand may, for example, be a zoned decimal number (e.g., 16 digits and, optionally, a sign that is not used in the concatenation) obtained from a location (e.g., a vector register) specified by the instruction (e.g., using V2 field 306), and the third operand may, for example, be another zoned decimal number (e.g., 16 digits and a sign) obtained from a location (e.g., a vector register) specified by the instruction (e.g., using V3 field 308). This concatenation, e.g., the second operand followed by the third operand, provides a source vector, e.g., of 32 digits and a sign, also referred to herein as the concatenated value.

[0079] The concatenated value, which is in one format, such as zoned decimal format, is converted to another format, such as signed packed decimal format, to provide a converted result (416). In one example, the signed packed decimal format includes 31 digits and a sign. To perform the conversion, the digits of the zoned decimal number are placed in nibbles (two nibbles equal a byte) of the packed decimal format. For example, the rightmost digit of the concatenated value is placed in the rightmost byte of the signed packed decimal format (in the left nibble, since the sign of the concatenated value is placed in the right nibble). The next two rightmost digits of the concatenated value are placed in the next rightmost byte of the signed packed decimal number, and so on. Because the signed packed decimal format includes 31 digits and a sign, the leftmost digit of the concatenated zoned decimal number is not placed in the signed packed decimal format. If the leftmost digit of the source vector (e.g., the 32nd digit) is nonzero, a decimal overflow occurs. Additionally, as described herein, if the RDC field specifies fewer digits than the number of digits in the source vector when leading zeros are excluded, decimal overflow occurs. For example, if a 32-byte / digit input source vector contains 29 leading zeros (F0...F0 F1 F2 F3) and RDC=2 (or 1 or less), overflow occurs; if a 32-byte / digit input source vector contains 30 leading zeros (F0...F0 F0 F2 F3) and RDC=2 (or 3 or greater), overflow does not occur; and if a 32-byte / digit input source vector contains a non-zero leftmost zero digit, overflow occurs regardless of the value of RDC. For example, decimal overflow is suppressed if the decimal overflow mask is 0 or the instruction overflow mask field in the fourth operand is 1.

[0080] The result obtained from the converted result is placed in a selected location (418), such as the location of the first operand (e.g., a register specified using V1 of the instruction). In one example, this placement is based on one or more controls specified by the instruction. For example, the result digits field specifies the number of right-most digits of the source vector (or the converted result, since the right-most digit of the source vector is the same as the right-most digit of the converted result; e.g., if RDC=5, the right-most 5 digits of the converted result are the same as the right-most 5 digits of the source vector) to be placed in the first operand (e.g., starting from the left nibble of the right-most byte). If the magnitude of the source vector is larger than the maximum decimal number that can be represented using the specified digits, a decimal overflow occurs, and if the decimal overflow mask is 1 and the instruction overflow mask is 0, a program interrupt for decimal overflow occurs. If the result digits field is 0, a specification exception is reported. Additionally, if the result length control specifies fewer than 31 digits, zeros are placed in the remaining leftmost digits of the first operand. If the leftmost digit of the source vector is non-zero, or leading zeros are excluded, and the result length field specifies fewer digits than the number of digits in the source vector, decimal overflow occurs. If the decimal overflow mask is, for example, 0, or the instruction overflow mask field in the fourth operand is, for example, 1, decimal overflow is suppressed.

[0081] Placing the result in the first operand involves providing a sign selected based on a control of the instruction (e.g., force operand 1 positive, control 324). If control 324 is 1, the sign of the result placed in the first operand (e.g., in the rightmost nibble) is forced to positive, and a sign code of 1111 is used. If control 324 is 0, the sign of the result placed in the first operand maintains the sign code from the source vector.

[0082] Optionally, one or more validity checks are performed (420) as specified by one or more controls of the instruction. For example, the validity check is determined based on the no validation control 322 and / or the no sign validation control 320, if any, e.g., in the M5 field of the instruction. As an example, unless the no validation control is 1, the validity of the code of a digit of the source vector is checked to determine whether a general operand data exception exists (e.g., checking that the digit is within the inclusive range of 0 to 9). For example, unless the no sign validation control is 1 and the no validation control is also 1, the validity of the sign code of the source vector is checked to determine whether a general operand data exception exists (e.g., checking that the sign code is within the inclusive range of 0xA to 0xF hexadecimal). In one example, the validity of the zone digit is not checked, and the source vector includes only one sign digit, e.g., located in the zone field of the rightmost byte.

[0083] Additionally, in one example, a condition code is optionally set (422) in response to one or more controls specified by the instruction, such as condition code setting control 326. In one example, the condition code setting control is independent of the general operand data exception control, and if equal to 1, for example, all digits and sign codes of the source vector are checked for validity to determine the condition code setting.

[0084] Although various fields and registers of the vector pack zone register instruction have been described, one or more aspects of the present invention may use other more or fewer fields and / or registers, other sized fields and / or registers, or combinations thereof. Many variations are possible. For example, implicit registers may be used in place of explicitly specified registers and / or fields of the instruction, or explicitly specified registers and / or fields may be used in place of implicit registers and / or fields, or combinations thereof. Other variations are also possible.

[0085] As described herein, in one aspect, a single instruction (e.g., a single engineered machine instruction at a hardware / software interface (e.g., a vector pack zone register instruction)) is provided to perform the pack operation. For example, the instruction is a hardware instruction defined in an instruction set architecture (ISA) that directly performs the pack operation, including, for example, concatenation, conversion, register write, validity check, or condition code setting, or a combination thereof. Processing is faster and more efficient than a program that executes the pack operation and the employed operations. Program complexity associated with the pack operation is reduced. Furthermore, performance of the operation (and therefore the processor) is improved. Execution of the hardware instruction reduces execution time and improves performance.

[0086] By using a single instruction to perform, for example, a pack operation, rather than multiple instructions (e.g., used to perform various operations of the pack operation on larger data sizes and / or to perform multiple pack operations), performance is improved by not requiring multiple passes through a hardware / software interface. Furthermore, by performing an operation as part of a single instruction, the operation does not require updating registers in the processor's register file (i.e., the array of processor registers used to store data between memory and functional units) before completing the operation, and remains within the processing unit performing the operation. This improves execution time and reduces processor resource usage.

[0087] Additionally, the use of a single instruction that is register-to-register (inputs are provided by registers and outputs are written to a single register) improves performance by, for example, not requiring inputs to be read from memory or outputs to be written to memory. Register-to-register instructions, along with other instructions that also operate on registers, also promote more efficient operation because memory does not need to be referenced to obtain input / output values.

[0088] In another aspect, vector unpack zone instructions are provided, each of which uses only one vector register write. By way of example, the vector unpack zone instructions include a vector unpack zone high instruction and a vector unpack zone low instruction, each of which is used to unpack a value in one format (e.g., a signed packed decimal format) to provide a value in another format (e.g., a zoned decimal format) in accordance with an aspect of the present invention. Each instruction performs an unpacking operation in which a signed packed decimal number is represented as one or more zoned decimal numbers. To perform the unpacking operation, various operations are used, such as, for example, a conversion, a register write, or a validity check, or a combination thereof. Each of these operations is performed as part of executing a single instruction, improving system performance, and reducing system resource usage. Further details regarding each instruction are provided below.

[0089] One embodiment of a vector unpack zone high instruction used to perform an unpack operation is described with reference to FIGS. 5A-5B. The instruction, in one example, is executed using a general-purpose processor (e.g., processor 104). In the description herein, a particular location of a field, a particular field, or a particular size, or combinations thereof (e.g., particular bytes and / or bits), is indicated. However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, while setting a bit to a particular value (e.g., 1 or 0) may be specified, this is merely an example. The bit may be set to a different value, such as the opposite value or another value, in other examples. Many variations are possible.

[0090] In one example, the vector unpack zone high instruction has a VRR-k format that indicates vector registers and register operations along with an extended operation code (opcode). This instruction is part of, for example, a vector function, as described herein.

[0091] As shown in FIG. 5A , in one example, a vector unpack zone high instruction 500 includes multiple fields, which may have subscript numbers associated with them. The subscript numbers associated with a field of the instruction indicate the operand to which the field applies. For example, the subscript number 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The length of the register operand is one register, e.g., 128 bits.

[0092] In one embodiment, the vector unpack zone-high instruction 500 includes operation code (opcode) fields 502a, 502b (e.g., bits 0-7 and 40-47) indicating an unpack operation in which the input data is, for example, a signed packed decimal number and the output is, for example, a zoned decimal number; a first vector register (V1) field 504 (e.g., bits 8-11) used to specify a first vector register; a second vector register (V2) field 506 (e.g., bits 12-15) used to specify a second vector register; a mask (M3) field 508 (e.g., bits 24-27); and a register extension bits (RXB) field 510 (e.g., bits 36-39), each of which is described below. In one embodiment, each field is separate and independent of one another, although in other embodiments, two or more fields may be combined. More information regarding these fields is described below.

[0093] In one embodiment, the vector register (V1) field 504 is used to indicate a vector register that stores a first operand (e.g., a result), and the vector register (V2) field 506 is used to indicate a vector register that stores a second operand that is an input to the instruction. The second operand may be, for example, in signed packed decimal format, including, for example, 31 digits and a sign. In one example, each of the vector register fields 504, 506 is used in conjunction with the RXB field 510 to specify a vector register.

[0094] In one example, a mask field (e.g., M3 508) of an instruction is used to control one or more aspects of the execution of the instruction as described herein. In one example, referring to Figure 5B, the M3 field 508 may include, for example:

[0095] No Sign Validation (NSV) 520: If this control (e.g., bit 0) is 0 and the No Validation (NV) control (described below) is 0, the sign code of the second operand is checked for validity to determine if a general operand data exception exists. If this control (e.g., bit 0) is 1 or the No Validation control is 1, the sign code of the second operand is not checked for validity.

[0096] No Validation (NV) 522: If this control (e.g., bit 1) is 0, the digits of the second operand are checked for validity, and if the No Sign Validation control is also 0, the sign code of the second operand is also checked for validity. If this control (e.g., bit 1) is 1, the digits and sign code of the second operand are not checked for validity.

[0097] In one example, bits 2-3 are reserved and will contain 0; otherwise, a specification exception is recognized.

[0098] In execution of one embodiment of the vector unpack zone high instruction, selected digits (e.g., the leftmost 15 digits) of a second operand in one format, such as a signed packed decimal format containing 31 digits and a sign, are converted to a converted result in another format, such as a zoned decimal format, and placed in a selected location (e.g., the rightmost 15 bytes of the first operand), with the most significant digit set, for example, to 0.

[0099] In one example, a zone bit containing the binary encoding of 1111 is supplied to every byte, and no sign digit is expanded in the result. In one embodiment, if the no validation control is 0, all 31 digits of the second operand are checked to be valid codes, and if the no sign validation control is 0, the sign is also checked.

[0100] Further details of one embodiment of a process based on execution of a vector unpack zone high instruction in accordance with one or more aspects of the present invention are described with reference to FIG. 6. In one example, a processor, such as general processor 104, is used to execute the instruction. As an example, hardware of the processor is used to execute the instruction. The hardware may be within or coupled to the processor for receiving instructions from the processor, which may, for example, retrieve, decode, and configure the instructions for execution on the hardware. Other variations are possible.

[0101] Referring to FIG. 6, in one embodiment, an instruction, such as a vector unpack zone high instruction, is first obtained (e.g., fetched, received, provided, etc.) (600) and executed (610). For example, this execution includes obtaining (612) a second operand of the instruction, e.g., in a signed packed decimal format including 31 digits and a sign. A selected portion of the second operand (e.g., the leftmost 15 digits) is converted (614) into a converted result (e.g., in zoned format). To perform the conversion, as an example, the leftmost 15 digits are placed into 15 bytes in zoned format. For example, each digit is written to the rightmost nibble of each byte in zoned format. A result obtained from the converted result is placed (616) into a selected location (e.g., the location of the first operand, such as a register specified using the V1 field of the instruction). As an example, the converted result is placed in the rightmost 15 bytes of the first operand, with the most significant digit (e.g., the leftmost digit) set to 0. Again, each digit is written in the rightmost nibble of each byte in zoned format. Additionally, in one example, a zone bit containing the binary encoding of 1111 is supplied to every byte (e.g., the leftmost nibble of each byte), and the sign digit is not expanded in the result.

[0102] In one example, for example, if the no validation control is 0, the 31 digits of the second operand are checked to be a valid code (e.g., within the inclusive range of 0 to 9), and if the no sign validation control is 0, the sign is also checked (e.g., within the inclusive range of 0xA to 0xF hexadecimal digits) (618).

[0103] Although various fields and registers of the vector unpack zone high instruction have been described, one or more aspects of the present invention may use other more or fewer fields and / or registers, or other sized fields and / or registers, or combinations thereof. Many variations are possible. For example, implicit registers may be used in place of the instruction's explicitly specified registers and / or fields, or explicitly specified registers and / or fields may be used in place of the implicit registers and / or fields, or combinations thereof. Other variations are also possible.

[0104] As described herein, in one aspect, a single instruction (e.g., a single engineered machine instruction at a hardware / software interface (e.g., a vector unpack zone high instruction)) is provided to unpack signed packed decimal numbers. For example, this instruction is a hardware instruction defined in an instruction set architecture (ISA) that directly performs the unpack operation, which may include, for example, a conversion, a write to a register, or a validity check, or a combination thereof. The processing is faster and more efficient than a program that performs the unpack operation and the employed operation. The program complexity associated with the unpack operation is reduced. Furthermore, the performance of the operation (and therefore the processor) is improved. Execution of the hardware instruction reduces execution time and improves performance.

[0105] By performing, for example, an unpack operation using a single instruction rather than multiple instructions (e.g., used to perform various operations of the unpack operation on larger data sizes and / or to perform multiple unpack operations), performance is improved by not requiring multiple passes through the hardware / software interface. Furthermore, by performing the operation as part of a single instruction, the operation does not require updating registers in the processor's register file (i.e., the array of processor registers used to store data between memory and functional units) before completing the operation, and remains within the processing unit performing the operation. This improves execution time and reduces processor resource usage.

[0106] Additionally, performance is improved by using a single instruction across registers.

[0107] One embodiment of a vector unpack zone row instruction used to perform an unpack operation is described with reference to FIGS. 5C-5D. The instruction, in one example, is executed using a general-purpose processor (e.g., processor 104). In the description herein, a particular location of a field, a particular field, or a particular size, or combinations thereof, is indicated (e.g., a particular byte or bit, or both). However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, while setting a bit to a particular value (e.g., 1 or 0) may be specified, this is merely an example. The bit may be set to a different value, such as the opposite value or another value, in other examples. Many variations are possible.

[0108] In one example, the vector unpack zone low instruction has a VRR-k format that indicates vector registers and register operations along with an extended operation code (opcode). This instruction is part of, for example, a vector function, as described herein.

[0109] As shown in FIG. 5C , in one example, a vector unpack zone low instruction 550 includes multiple fields, which may have subscript numbers associated with them. The subscript numbers associated with a field of the instruction indicate the operand to which the field applies. For example, the subscript number 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The length of the register operand is one register, e.g., 128 bits.

[0110] In one embodiment, the vector unpack zone low instruction 550 includes operation code (opcode) fields 552a, 552b (e.g., bits 0-7 and 40-47) indicating an unpack operation in which the input data is, for example, a signed packed decimal number and the output is, for example, a zoned decimal number; a first vector register (V1) field 554 (e.g., bits 8-11) used to specify a first vector register; a second vector register (V2) field 556 (e.g., bits 12-15) used to specify a second vector register; a mask (M3) field 558 (e.g., bits 24-27); and a register extension bits (RXB) field 560 (e.g., bits 36-39), each of which is described below. In one embodiment, each field is separate and independent of one another, although in other embodiments, two or more fields may be combined. More information regarding these fields is described below.

[0111] In one embodiment, the vector register (V1) field 554 is used to indicate a vector register that stores a first operand (e.g., a result), and the vector register (V2) field 556 is used to indicate a vector register that stores a second operand that is an input to the instruction. The second operand may be, for example, in signed packed decimal format, including, for example, 31 digits and a sign. In one example, each of the vector register fields 554, 556 is used in conjunction with the RXB field 560 to specify a vector register.

[0112] In one example, a mask field (e.g., M3 558) of an instruction is used to control one or more aspects of the execution of the instruction as described herein. In one example, referring to Figure 5D, the M3 field 558 includes, for example:

[0113] No Sign Validation (NSV) 570: If this control (e.g., bit 0) is 0 and the No Validation (NV) control (described below) is 0, the sign code of the second operand is checked for validity to determine if a general operand data exception exists. If this control (e.g., bit 0) is 1 or the No Validation control is 1, the sign code of the second operand is not checked for validity.

[0114] No Validation (NV) 572: If this control (e.g., bit 1) is 0, the digits of the second operand are checked for validity, and if the No Sign Validation control is 0, the sign code of the second operand is also checked for validity. If this control (e.g., bit 1) is 1, the digits and sign code of the second operand are not checked for validity.

[0115] Force Operand 1 Positive (P1) 574: If this control (e.g., bit 2) is 1, the sign of the result placed in the first operand is forced to positive and a sign code of 1111 is used. If this control (e.g., bit 2) is 0, the sign of the result placed in the first operand maintains the sign code from the second operand. In one example, this field applies when no general operand data exceptions exist.

[0116] In one example, bit 3 is reserved and will contain a 0; otherwise, a specification exception is recognized.

[0117] In one example, if novalidation or nosignvalidation is equal to 1, the validity of the sign code is not checked, and if the force operand is 1 positive and control is 0, an invalid sign code in the source operand is propagated to the result.

[0118] In execution of one embodiment of the vector unpack zone low instruction, selected digits (e.g., the rightmost 16 digits) of a second operand in one format, such as a signed packed decimal format containing 31 digits and a sign, are converted to a converted result in another format, such as a zoned decimal format, and placed in the position of the first operand.

[0119] In one example, zone bits containing the binary encoding of 1111 are supplied to all bytes except the rightmost byte, whose zone receives the sign of the first operand. If the no validation control is 0, all 31 digits of the second operand are checked to be valid codes; if the no sign validation control is 0, the sign is also checked.

[0120] Further details of one embodiment of a process based on execution of a vector unpack zone low instruction in accordance with one or more aspects of the present invention are described with reference to FIG. 6. In one example, a processor, such as general processor 104, is used to execute the instructions. As an example, hardware of the processor is used to execute the instructions. The hardware may be within or coupled to the processor for receiving instructions from the processor, which may, for example, retrieve, decode, and set the instructions for execution on the hardware. Other variations are possible.

[0121] Referring to FIG. 6, in one embodiment, an instruction, such as a vector unpack zone low instruction, is first obtained (e.g., fetched, received, provided, etc.) (600) and executed (610). For example, this execution includes obtaining (612) a second operand of the instruction, e.g., in a signed packed decimal format including 31 digits and a sign. A selected portion of the second operand (e.g., the rightmost 16 digits and the sign) is converted (614) into a converted result (e.g., in zoned format). To perform the conversion, as an example, the rightmost 16 digits and the sign are arranged into 16 bytes in zoned format. For example, each digit is written in the rightmost nibble of each byte in zoned format, and the sign is placed in the left nibble of the rightmost byte. A result obtained from the converted result is placed (616) into a selected location (e.g., the location of the first operand, such as a register specified using the V1 field of the instruction). For example, the converted result is written to the vector register specified using V1, and each digit of the converted result is written to the rightmost nibble of each byte. Additionally, in one example, a zone bit containing the binary encoding of 1111 is supplied to all bytes (e.g., the leftmost nibble of each byte) except the rightmost byte, whose zone receives the sign of the first operand.

[0122] In one example, for example, if the no validation control is 0, the 31 digits of the second operand are checked to be a valid code, and if the no sign validation control is 0, the sign is also checked (618).

[0123] Although various fields and registers of the vector unpack zone low instruction have been described, one or more aspects of the present invention may use other more or fewer fields and / or registers, or other sized fields and / or registers, or combinations thereof. Many variations are possible. For example, implicit registers may be used in place of the instruction's explicitly specified registers and / or fields, or explicitly specified registers and / or fields may be used in place of the implicit registers and / or fields, or combinations thereof. Other variations are also possible.

[0124] As described herein, in one aspect, a single instruction (e.g., a single engineered machine instruction at a hardware / software interface (e.g., a vector unpack zone low instruction)) is provided to unpack signed packed decimal numbers. For example, this instruction is a hardware instruction defined in an instruction set architecture (ISA) that directly performs the unpack operation, which may include, for example, a conversion, a write to a register, or a validity check, or a combination thereof. The processing is faster and more efficient than a program that performs the unpack operation and the employed operation. The program complexity associated with the unpack operation is reduced. Furthermore, the performance of the operation (and therefore the processor) is improved. Execution of the hardware instruction reduces execution time and improves performance.

[0125] In one embodiment, the Vector Unpack Zone High and Vector Unpack Zone Low instructions may be used together to unpack a signed packed decimal operand in a vector register into a zoned decimal operand in two vector registers containing unsigned high and signed low data. Either or both instructions may check the validity of the digit and sign codes of the signed packed decimal source.

[0126] One or more aspects of the present invention are closely related to computer technology and facilitate processing in computers and improve their performance. Using a single designed machine instruction to perform packing or unpacking operations improves performance in a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. Data and / or instructions can be used in many technical fields, such as computer processing, medical processing, design, automotive technology, and manufacturing. By achieving optimization in data packing / unpacking, these technical fields are improved by reducing execution time.

[0127] Further details of one embodiment that facilitates processing within a computing environment as it relates to one or more aspects of the present invention are described with reference to FIGS. 7A-7B.

[0128] 7A , in one embodiment, instructions for performing a conversion between one decimal number format and another decimal number format are executed (700). The one decimal number format or the other decimal number format is a zoned decimal number format (702). The execution includes obtaining a value from at least one register specified using the instruction (704), converting at least a portion of the value from the one decimal number format to another decimal number format different from the one decimal number format and providing a converted result (706), and writing a result obtained from the converted result to a single register specified using the instruction (708).

[0129] As an example, one decimal format is a zoned decimal format and the other decimal format is a packed decimal format (710).

[0130] In one example, obtaining the value includes obtaining a first value from a first vector register specified using at least one field of the instruction (712), obtaining a second value from a second vector register specified using at least one field of the instruction (714), and concatenating the first value and the second value to obtain the value (716).

[0131] Referring to FIG. 7B, in one example, writing includes determining the number of digits of the converted result to be written as a result (720), selecting the determined number of digits of the converted result to be written as a result (722), and writing the selected determined number of digits to a single register (724).

[0132] In one example, determining the number of digits includes checking a control specified using the instruction 726. Further, in one example, the single register is a single vector register 728.

[0133] As another example, one decimal format is a packed decimal format and the other decimal format is a zoned decimal format (730). In one example, converting at least a portion of the value includes converting selected digits of the value to obtain a converted result (732), where the selected digits include, for example, the leftmost 15 digits of the value (734). As a further example, the selected digits include the rightmost 16 digits of the value (736), and converting includes converting the sign of the value (738).

[0134] In one example, writing includes writing the transformed result to a selected portion of a single register, where the single register is a vector register (740).

[0135] By performing packing and unpacking operations using a single instruction, performance is improved and resource utilization is reduced. By performing packing (e.g., concatenation, conversion, writing, validity checking, and / or condition code setting) and unpacking (e.g., conversion, writing, and / or validity checking) operations using a single designed instruction, a particular task, such as a packing or unpacking operation, can be performed much more efficiently than using a software paradigm. The packing or unpacking operation is performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0136] Other variations and embodiments are possible.

[0137] Aspects of the present invention may be employed by many types of computing environments. Another example of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 8A. As an example, the computing environment of FIG. 8A is based on the z / Architecture® hardware architecture offered by International Business Machines Corporation (Armonk, New York). However, the z / Architecture hardware architecture is only one exemplary architecture. Additionally, computing environments may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other architectures from International Business Machines Corporation, or architectures from other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0138] In one example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, such as, for example, memory 12 (also called system memory, main memory, primary storage, central storage, or storage) coupled to one or more processors (also called central processing units (CPUs)) 13 and an input / output (I / O) subsystem 14.

[0139] I / O subsystem 14 may be part of or separate from the central electronics complex. I / O subsystem 14 directs the flow of information between main memory 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronics complex.

[0140] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 may store one or more programs 18, one or more computer-readable program instructions 19, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0141] Central electronics complex 11 can include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronics complex 11 can include and / or be coupled to non-removable, non-volatile magnetic media (typically referred to as "hard drives"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from and writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components can be used in conjunction with central electronics complex 11, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0142] Additionally, central electronics complex 11 can operate in numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with central electronics complex 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0143] In one or more embodiments, central electronics complex 11 provides support for logical partitioning and / or virtualization. In one embodiment, as shown in FIG. 8B , memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of hypervisor 21 is the Processor Resource / System Manager (PR / SM™) offered by International Business Machines Corporation (Armonk, New York). As used herein, firmware includes, for example, processor microcode. Firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, firmware includes proprietary code that controls operating system access to the system's hardware, typically provided as microcode containing trusted software or microcode specific to the underlying hardware. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0144] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23, such as the z / OS® operating system provided by International Business Machines Corporation (Armonk, New York), or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire system, but in fact, only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems provided by International Business Machines Corporation, other companies, or both, may be used in accordance with one or more aspects of the present invention.

[0145] The memory 12 is coupled to a CPU 13 (FIG. 8A), which is a physical processor resource that is assigned to the logical partition. For example, a logical partition 20 includes one or more logical processors, each of which represents all or a portion of the physical processor resource 13 that is dynamically assigned to the logical partition.

[0146] In yet another embodiment, the central electronics complex provides support for virtual machines (which may or may not support logical partitioning). As shown in FIG. 8C, memory 12 of central electronics complex 11 includes, for example, one or more virtual machines 26, a virtual machine manager (e.g., hypervisor 27) that manages the virtual machines, and processor firmware 28. One example of hypervisor 27 is the z / VM® hypervisor offered by International Business Machines Corporation (Armonk, New York). A hypervisor may be referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0147] The central electronics complex's virtual machine support allows multiple virtual machines 26 to be run, each running a different program 29 and a guest operating system 30, such as the Linux® operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and run different programs. An operating system or application program running within a virtual machine appears to have access to the entire system, but in fact only a portion of it is available. While z / VM and Linux are provided as examples, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation (an exclusive licensee of Linus Torvalds, owner of the trademark worldwide).

[0148] Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 9A. In this example, computing environment 36 includes a native central processing unit (CPU) 37, memory 38, and one or more input / output devices and / or interfaces 39, coupled together, for example, via one or more buses 40 or other connections. By way of example, computing environment 36 may include a PowerPC® processor offered by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel® Itanium® II processor offered by Hewlett-Packard Company (Palo Alto, California), or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard Company, Intel Corporation, Oracle Corporation, or other companies, or combinations thereof. PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0149] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular point in time.

[0150] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one particular example, central processing unit executes emulator code 42 stored in memory 38. This code enables a computing environment configured with one architecture to emulate another architecture. For example, emulator code 42 enables machines based on architectures other than the z / Architecture hardware architecture (e.g., PowerPC processors, HP Superdome servers, etc.) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0151] Further details related to emulator code 42 are described with reference to FIG. 9B . Guest instructions 43 stored in memory 38 include software instructions (e.g., interrelated to machine instructions) developed to execute on an architecture other than that of native CPU 37. For example, guest instructions 43 are designed to execute on a processor based on the z / Architecture hardware architecture, but are instead emulated on native CPU 37, which may be, for example, an Intel Itanium II processor. In one example, emulator code 42 includes an instruction fetch routine 44 for retrieving one or more guest instructions 43 from memory 38 and, optionally, providing local buffering of the retrieved instructions. Emulator code 42 also includes an instruction conversion routine 45 for determining the type of the retrieved guest instruction and for converting the guest instruction into one or more corresponding native instructions 46. This conversion includes, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform this function.

[0152] Additionally, emulator code 42 includes an emulation control routine 47 for causing execution of native instructions. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more already-fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine to emulate the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include reading data from memory 38 into registers, storing data from registers back to memory, or performing any type of arithmetic or logical operation as determined by a translation routine.

[0153] For example, each routine is implemented in software that is stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or any combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or by using locations in memory 38. In embodiments, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0154] In accordance with an aspect of the present invention, the emulated instructions include the vector pack zone register instructions, vector unpack zone high instructions, and vector unpack zone low instructions described herein.

[0155] The computing environments described above are only examples of computing environments that may be used. Other environments may be used, including, but not limited to, non-partitioned, partitioned, cloud, or emulated environments, or combinations thereof, and embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are only examples.

[0156] Each computing environment can be configured to include one or more aspects of the present invention.

[0157] One or more aspects may relate to cloud computing.

[0158] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings presented herein is not limited to cloud computing environments. Embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0159] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with a service provider. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0160] The features are as follows:

[0161] On-demand self-service: Cloud customers can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without the need for human interaction with the service provider.

[0162] Wide network access: Cloud capabilities are available over the network and can be accessed using standard mechanisms, facilitating usage by heterogeneous thin- or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0163] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated according to demand. There is a sense of location independence; consumers typically have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction, they may be able to specify a location (e.g., country, state, or data center).

[0164] Rapid Elasticity: Cloud capacity can be quickly and elastically provisioned, in some cases automatically, to scale out quickly, and quickly released to scale in quickly. Capacity available for provisioning often appears to consumers as unlimited, available for purchase in any quantity at any time.

[0165] Metered Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an abstraction level appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0166] The service model is as follows:

[0167] SaaS (Software as a Service): The consumer is provided with the ability to use the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application features, except for the possibility of setting limited user-specific application configuration settings.

[0168] PaaS (Platform as a Service): The ability offered to a consumer is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0169] Infrastructure as a Service (IaaS): The capability provided to a consumer is the provisioning of processing, storage, network, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0170] The deployment model is as follows:

[0171] Private Cloud: This cloud infrastructure is operated solely for the organization, can be managed by the organization or a third party, and can reside on-premise or off-premise.

[0172] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by these organizations or a third party and can reside on-premises or off-premises.

[0173] Public Cloud: This cloud infrastructure is available for use by the general public or large industry organizations and is owned by an organization that sells cloud services.

[0174] Hybrid cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct but are joined together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0175] A cloud computing environment is a service-oriented environment that emphasizes statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0176] Referring now to FIG. 10 , an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N) can communicate. The nodes 52 may communicate with each other. The nodes 52 may be physically or virtually grouped in one or more networks (not shown), such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as previously described herein. This enables the cloud computing environment 50 to provide an infrastructure, platform, and / or SaaS that does not require cloud consumers to maintain resources on their local computing devices. The types of computing devices 54A-N shown in FIG. 10 are intended to be illustrative only, and it is understood that computing node 52 and cloud computing environment 50 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0177] Referring now to Figure 11, a set of functional abstraction layers provided by cloud computing environment 50 (Figure 10) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 11 are intended to be illustrative only, and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0178] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0179] The virtualization layer 70 comprises an abstraction layer capable of providing virtual entities such as virtual servers 71 , virtual storage 72 , virtual networks including virtual private networks 73 , virtual applications and operating systems 74 , and virtual clients 75 .

[0180] By way of example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources used to execute tasks within the cloud computing environment; Metering and pricing 82 tracks costs as resources are utilized within the cloud computing environment and sends bills or invoices for the utilization of those resources; by way of example, those resources may include application software licenses; Security verifies the identity of cloud users and tasks and protects data and other resources; User portal 83 provides users and system administrators with access to the cloud computing environment; Service level management 84 allocates and manages cloud computing resources to meet required service levels; and Service Level Agreement (SLA) planning and execution 85 proactively prepares and procures cloud computing resources in accordance with SLAs in anticipation of future demand.

[0181] The Workload Layer 90 shows examples of functionality available in a cloud computing environment. Examples of workloads and functionality provided by this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and vector pack and vector unpack processing 96.

[0182] Aspects of the invention may be systems, methods, and / or computer program products, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to perform aspects of the invention.

[0183] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0184] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof) that may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0185] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0186] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, are implemented by computer-readable program instructions.

[0187] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to create a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for performing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0188] Computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0189] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may actually be realized as a single step, executed concurrently, executed substantially concurrently in a partially or fully overlapping manner in time, or executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, are implemented by a special-purpose hardware-based system that performs the specified function or operation or executes a combination of special-purpose hardware and computer instructions.

[0190] Additionally, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that offers management of a customer's environment. For example, a service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example, under a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0191] In one aspect, an application may be deployed to perform one or more embodiments. As one example, deploying an application includes providing a computer infrastructure that functions to perform one or more embodiments.

[0192] As a further aspect, a computing infrastructure may be deployed that includes integrating computer readable code into a computing system, where the code in combination with the computing system is capable of executing one or more embodiments.

[0193] In yet another aspect, a process for integrating a computing infrastructure may be provided, comprising integrating computer-readable code into a computer system comprising a computer-readable medium, the computer-readable medium including one or more embodiments, the code in combination with the computer system being capable of executing one or more embodiments.

[0194] Although various embodiments have been described above, they are merely examples. For example, computing environments of other architectures may be used to incorporate one or more aspects and / or to use one or more aspects. Furthermore, various instructions or operations may be used. Furthermore, various types of registers and / or different registers may be used. Furthermore, other formats used to represent numeric values ​​may be employed. By way of example, aspects of the present invention may be used with numeric portions in separate signed zoned decimal format, unsigned packed decimal format, or other formats, or combinations thereof. Many variations are possible.

[0195] Various embodiments are described herein. Furthermore, many variations are possible without departing from the spirit of the embodiments of the present invention. It should be noted that each embodiment or feature described herein and variations thereof can be combined with any other embodiment or feature unless specifically inconsistent.

[0196] Additionally, other types of computing environments may be beneficial and may be used. By way of example, a data processing system may be used that includes at least two processors coupled directly or indirectly via a system bus to memory elements suitable for storing and / or executing program code. These memory elements may include, for example, local memory used during the actual execution of the program code, bulk storage, and cache memory for temporarily storing at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0197] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the types of network adapters available.

[0198] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0199] Corresponding structures, materials, acts, and equivalents of all means or steps and functional elements within the scope of the claims below are intended to include any structure, material, or act for performing a function in combination with other claimed elements, if any, when specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain various aspects and practical applications, and to enable others skilled in the art to appreciate various embodiments with various modifications as may be suited to the particular use contemplated.

Claims

1. 1. A computer program stored on a computer-readable recording medium for facilitating processing in a computing environment, the computer program comprising: executing instructions to convert between a source decimal format and a destination decimal format, wherein the source decimal format or the destination decimal format is a zoned decimal format; obtaining a value from at least one register specified using said instruction; converting at least a portion of the value from the source decimal format to the destination decimal format and providing a converted result; and writing a result obtained from said transformed result into a selected portion of a single vector register specified using said instruction.

2. 2. The computer program product of claim 1, wherein the source decimal format is the zoned decimal format and the destination decimal format is a packed decimal format.

3. 2. The computer program product of claim 1, wherein the source decimal format is a packed decimal format and the destination decimal format is the zoned decimal format.

4. said obtaining said value Obtaining a first value from a first vector register specified using at least one field of the instruction; Obtaining a second value from a second vector register specified using at least one field of the instruction; and and concatenating the first value and the second value, maintaining digit boundaries, to obtain the value.

5. The writing determining the number of digits of the converted result to be written as the result based on a field of an instruction; selecting the determined number of digits of the converted result to be written as the result; and writing the selected determined number of digits into a selected portion of the single vector register.

6. 6. The computer program product of claim 5, wherein said determining said number of digits comprises checking a control specified using said instruction, and wherein said single register is a single vector register.

7. 7. The computer program product of claim 6, wherein said transforming at least a portion of said value comprises transforming selected digits of said value to obtain said transformed result.

8. 8. The computer program product of claim 7, wherein the selected digits include the leftmost 15 digits of the value.

9. 8. The computer program product of claim 7, wherein the selected digits include the rightmost 16 digits of the value, and wherein the converting further comprises converting the sign of the value.

10. 1. A computer system for facilitating processing within a computing environment, said computer system comprising: Memory and a processor in communication with the memory, the computer system configured to perform a method, the method comprising: Executing instructions to convert between a source decimal format and a destination decimal format, wherein the source decimal format or the destination decimal format is a zoned decimal format, Obtaining a value from at least one vector register specified using said instruction; converting at least a portion of the value from the source decimal format to the destination decimal format and providing a converted result; and writing a result obtained from said transformed result to a selected portion of a single vector register specified using said instruction.

11. 11. The computer system of claim 10, wherein the source decimal format is the zoned decimal format and the destination decimal format is a packed decimal format.

12. 11. The computer system of claim 10, wherein the source decimal format is a packed decimal format and the destination decimal format is the zoned decimal format.

13. said obtaining said value Obtaining a first value from a first vector register specified using at least one field of the instruction; Obtaining a second value from a second vector register specified using at least one field of the instruction; and and concatenating the first value and the second value, maintaining digit boundaries, to obtain the value.

14. The writing determining the number of digits of the converted result to be written as the result based on a field of an instruction; selecting the determined number of digits of the converted result to be written as the result; and writing the selected determined number of digits to a selected portion of the single vector register.

15. 1. A method for facilitating processing in a computing environment by processing information in a computer, said method comprising: executing instructions to convert between a source decimal format and a destination decimal format, wherein the source decimal format or the destination decimal format is a zoned decimal format, and the executing obtaining a value from at least one register specified using said instruction; converting at least a portion of the value from the source decimal format to the destination decimal format and providing a converted result; and writing a result obtained from said transformed result to a selected portion of a single vector register specified using said instruction.

16. 16. The method of claim 15, wherein the source decimal format is the zoned decimal format and the destination decimal format is a packed decimal format.

17. 16. The method of claim 15, wherein the source decimal format is a packed decimal format and the destination decimal format is the zoned decimal format.

18. said obtaining said value Obtaining a first value from a first vector register specified using at least one field of the instruction; Obtaining a second value from a second vector register specified using at least one field of the instruction; and and concatenating the first value and the second value, maintaining digit boundaries, to obtain the value.

19. The writing determining the number of digits of the converted result to be written as the result based on a field of an instruction; selecting the determined number of digits of the converted result to be written as the result; and writing the selected determined number of digits to a selected portion of the single vector register.

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