Systems and devices for nanopore single-molecule sequencing

Abstract

An integrated circuit for controlling a sensor chip capable of detecting various substances includes a plurality of amplifier clusters, a plurality of analog multiplexers, and at least one analog-to-digital converter connected to the plurality of analog multiplexers and configured to generate digital code values ​​representing electrical signals. Each amplifier cluster includes four amplifiers, each having a first input connected to a sensor of the sensor chip and a second input connected to a programmable voltage reference. Each analog multiplexer is connected to one of the amplifier clusters and configured to selectively pass the electrical signals to the at least one analog-to-digital converter.

Description

[Technical Field]

[0001] The present invention relates generally to analytical instruments, and more particularly to systems and integrated devices for high throughput biochemical analysis and methods of operating the same. [Background technology]

[0002] High-throughput analysis of chemical and / or biochemical species is an important tool in the fields of diagnostics and therapeutics. Sensor chips can be designed to detect specific sequences, analyze gene expression patterns, identify specific allelic variants, determine the copy number of DNA sequences, and identify protein (e.g., transcription factor and other regulatory molecule) attachment sites on a genome-wide scale. In a specific example, the advent of the Human Genome Project necessitated improved methods for sequencing nucleic acids such as DNA (deoxyribonucleic acid) and RNA (ribonucleic acid). The determination of the complete sequence of the 3,000,000,000 bases of the haploid human genome provided the foundation for identifying the genetic basis of many diseases.

[0003] High-throughput analyses such as massively parallel DNA sequencing often utilize flow cells that contain an array of chemical and / or biological species available for analysis. Flow cells are often fabricated in microfluidic housings that are integrated with biological chips, such as silicon-based sensor chips, to form microfluidic devices.

[0004] Characterization of single molecules using nanopore membranes requires the detection and measurement of extremely small ionic currents flowing through the nanopore. The magnitude of the ionic currents through nanopores is on the order of tens to hundreds of picoamperes (pA). Detecting such weak changes in current through a nanopore is extremely difficult. Summary of the Invention

[0005] An embodiment of the present invention provides an integrated circuit for controlling a sensor chip capable of detecting various substances. The integrated circuit includes a plurality of amplifier clusters, a plurality of analog multiplexers, and at least one analog-to-digital converter connected to the plurality of analog multiplexers and configured to generate digital code values ​​representing electrical signals. Each amplifier cluster includes four amplifiers, each having a first input connected to a sensor of the sensor chip and a second input connected to a programmable voltage reference. Each analog multiplexer is connected to one of the amplifier clusters and configured to selectively pass the electrical signals to the at least one analog-to-digital converter.

[0006] In one embodiment, the integrated circuit further includes a digital-to-analog converter configured to generate the programmable voltage reference in response to a digital input signal.

[0007] In one embodiment, each amplifier cluster includes four amplifiers and each analog multiplexer includes four inputs, each input connected to the output of an amplifier in the amplifier cluster.

[0008] In one embodiment, the integrated circuit further includes a correlated double sampling and low pass filtering circuit coupled to the plurality of analog multiplexers and configured to reduce noise, offset voltage, and drift of the integrated circuit.

[0009] In one embodiment, the integrated circuit further includes a timing control circuit configured to provide control signals to the plurality of amplifier clusters, the plurality of first analog multiplexers, and the at least one ADC.

[0010] In one embodiment, the plurality of amplifier clusters, the plurality of first analog multiplexers, and the at least one ADC are powered by separate voltage supplies that are physically and electrically isolated from each other.

[0011] In one embodiment, the integrated circuit further includes a self-calibration and test circuit configured to calibrate the plurality of amplifier clusters and analyze a plurality of data flows from the amplifier clusters to the at least one ADC.

[0012] In one embodiment, the integrated circuit further includes a plurality of second analog multiplexers disposed between the plurality of first analog multiplexers and the at least one ADC and configured to sequentially provide the selectively passing electrical signals to the at least one ADC.

[0013] According to one embodiment, a nanopore flow cell system is provided. The nanopore flow cell system includes a sensor chip having a plurality of sensors, an integrated circuit (IC) configured to receive electrical signals from the sensors of the sensor chip and output digital code values ​​representing the electrical signals, and an interface device connected to the integrated circuit and configured to process the digital code values ​​received from the IC and provide control signals to the IC according to the processed digital code values. The IC includes a plurality of amplifier clusters (each of the plurality of amplifier clusters includes a plurality of amplifiers, each amplifier having a first input connected to a sensor of the sensor chip and a second input connected to a programmable voltage reference), a plurality of analog multiplexers (each of the plurality of analog multiplexers is connected to one of the plurality of amplifier clusters and configured to selectively pass the electrical signals), and at least one analog-to-digital converter (ADC) connected to the plurality of analog multiplexers and configured to generate digital code values ​​representing the electrical signals.

[0014] In one embodiment, the integrated circuit is a complementary metal oxide semiconductor (CMOS) application specific integrated circuit (ASIC) and the interface device is a field programmable gate array (FPGA).

[0015] In one embodiment, the nanopore flow cell system further includes a substrate disposed between the integrated circuit and the sensor chip, the integrated circuit connected to the sensor chip via a plurality of through-silicon vias extending into the substrate.

[0016] In one embodiment, the integrated circuit connects to an interface device via a four-wire serial peripheral interface (SPI) and a low-voltage differential signaling (LVDS) port.

[0017] In one embodiment, the programmable voltage reference is configured to provide a bias voltage to the sensor chip for one of DNA strain unblocking, nanopore membrane characterization, or protein insertion.

[0018] In one embodiment, the interface device is configured to perform an arithmetic operation on the digital code values ​​received from the IC, and transmit a control signal to the IC according to the result of the arithmetic operation.

[0019] In one embodiment, the sensor chip is disposed on a sensor substrate and the integrated circuit is disposed on a second substrate, with the sensor chip and the integrated circuit being connected together by a set of pogo pins.

[0020] An embodiment of the present disclosure further provides a method of operating an integrated circuit (IC) configured to control a sensor chip, the method comprising the steps of receiving, by the IC, an electrical signal from the sensor chip; The method includes amplifying the received electrical signal using an amplifier having a first input connected to the sensor chip and a second input connected to a programmable voltage reference; converting the amplified electrical signal by an analog-to-digital converter (ADC) into a digital code value representative of the amplified electrical signal; outputting the digital code value to an interface device; and varying the programmable voltage reference in response to a control signal received by the interface device.

[0021] In one embodiment, the method further includes multiplexing the amplified electrical signals through a multi-stage analog multiplexer before converting the amplified electrical signals into digital code values.

[0022] An embodiment of the present invention further provides a method of operating a flow cell analysis system, the method including the steps of providing a sensor chip including an array of sensors, providing an integrated circuit including a plurality of amplifiers, each amplifier configured to condition an electrical signal of one of the sensors, selectively passing a portion of the conditioned electrical signal, converting the portion of the conditioned electrical signal to a digital code representative of the portion of the conditioned electrical signal, outputting the digital code to an external device using a high-speed serial interface, analyzing the digital code by the external device to obtain an analysis result, and applying a programmable voltage reference to the sensor chip in response to the analysis result.

[0023] Numerous advantages are achieved by the present invention over known techniques. For example, embodiments of the present invention provide systems, devices, and methods that utilize a flow cell that includes a sensor chip, a CMOS application-specific integrated circuit (ASIC), and a field-programmable gate array (FPGA). The flow cell is mounted on a first substrate, and the CMOS ASIC and FPGA are mounted on a second substrate. The flow cell can be connected to the CMOS ASIC chip by a set of pogo pins when the first and second substrates are mated. The flow cell is disposable, but the CMOS ASIC and FPGA are reusable. These and other embodiments of the present invention, along with their many advantages and features, are described in more detail in the following text and accompanying figures. [Brief explanation of the drawings]

[0024] The accompanying drawings form a part of this disclosure and illustrate exemplary embodiments of the invention, and together with the description, serve to explain the principles of the invention.

[0025] [Figure 1A] FIG. 1 is a simplified block diagram illustrating a nanopore analysis system according to one embodiment of the present disclosure. [Figure 1B] FIG. 1 is a simplified cross-sectional view illustrating a nanopore flow cell system according to one embodiment of the present disclosure. [Figure 1C] FIG. 10 is a simplified cross-sectional view showing a nanopore flow cell device according to another embodiment of the present disclosure. [Figure 2A] FIG. 10 is a top view of a sensor chip according to another embodiment of the present disclosure. [Figure 2B] 2B is a magnified portion of the sensor chip of FIG. 2A. [Figure 2C] FIG. 1 is a simplified cross-sectional view showing a portion of a sensor chip including wells and electrodes according to an embodiment of the present disclosure. [Figure 3A] 3 is a flowchart illustrating a method 300A for preparing a nanopore flow cell system according to one embodiment of the present disclosure. [Figure 3B] 1 is a graph of current showing a nanopore being blocked and then unblocked according to an embodiment of the present disclosure. [Figure 3C] FIG. 3C is a simplified block diagram illustrating a blocked state of a molecular strand within a nanopore when the ASIC applies a bias voltage V to attract the molecular strand to the nanopore, blocking the nanopore corresponding to state B in FIG. 3B. [Figure 3D] FIG. 3C is a simplified block diagram illustrating the ASIC applying a reverse bias voltage to unblock the nanopore, corresponding to state C in FIG. 3B. [Figure 4] FIG. 1 is a simplified block diagram illustrating the architecture of a multi-sensor integrated chip for a nanopore flow cell system according to various embodiments of the present disclosure. [Figure 5] FIG. 1 is a schematic block diagram illustrating a two-stage amplifier 50 according to an embodiment of the present disclosure. [Figure 6] FIG. 1 is a timing diagram illustrating an exemplary readout cycle of a nanopore based on a correlated double sampling process according to an embodiment of the present disclosure. [Figure 7]1 is a simplified flowchart illustrating a DNA unblocking process according to an embodiment of the present disclosure. [Figure 8] 1 is a simplified flowchart illustrating a film characteristic evaluation process according to an embodiment of the present disclosure. [Figure 9] 1 is a simplified flowchart illustrating a protein insertion process according to an embodiment of the present disclosure. [Figure 10] 1 is a simplified flowchart illustrating a short circuit prevention process according to an embodiment of the present disclosure. [Figure 11] 1 is a simplified flowchart illustrating a method of operation of a flow cell analysis system according to one embodiment of the present disclosure. [Figure 12] 1 is a simplified flowchart illustrating a method of operation of an integrated circuit according to one embodiment of the present disclosure configured to control a sensor chip having multiple sensor elements. DETAILED DESCRIPTION OF THE INVENTION

[0026] 1A is a simplified block diagram illustrating a nanopore flow cell analysis system 100A according to one embodiment of the present disclosure. The nanopore flow cell analysis system 100A includes, but is not limited to, a sensor chip 11, an ASIC (application-specific integrated circuit) chip 12, and an FPGA (field-programmable gate array) 13. The sensor chip 11, the ASIC 12, and the FPGA 13 are communicatively connected to each other, thereby preparing the sensor chip 11 to measure data about a target sample (e.g., a biological or biochemical sample) using nanopores and sensor elements integrated in the sensor chip 11. The FPGA 13 is further connected to a computing device PC (e.g., a personal computer, PDA, laptop, etc.) for storing measurement data and providing a user interface. The nanopore flow cell analysis system 100A can prepare or control the operating conditions of the sensor chip 11 and ASIC 12 and can perform "housekeeping functions" such as DNA sequencing, membrane property measurement and control, protein insertion, control of fluid flow to and from the sensor chip 11, unblocking blocked nanopores, constantly checking for short circuits and other fault conditions and reading the sensor chip junction temperature, channel blocking, and self-calibration via a PC or user-initiated testing.

[0027] In one embodiment, the sensor chip 11 includes an array of sensor elements arranged within the array of nanopores, each sensor element configured to output an electrical signal in response to a physical condition of the nanopore. In one embodiment, the sensor chip 11 may include a plurality of field-effect transistors (FETs), each capable of outputting an electrical signal indicative of a change in the impedance or characteristics of the FET in response to a biochemical substance. The ASIC 12 includes a plurality of amplifiers, each configured to amplify the electrical signal provided by one of the sensor elements, and a plurality of multiplexers configured to selectively pass the amplified electrical signals of the sensor elements to a plurality of signal paths, where the number of signal paths is less than the number of sensor elements or amplifiers. The ASIC 12 further includes one or more analog-to-digital converters configured to receive the amplified electrical signals on the signal paths and convert selected amplified electrical signals into digital codes or digital words representing the selected amplified electrical signals, and a controller configured to control the multiplexers to select or pass electrical signals of sensor elements having acceptable performance to the plurality of signal paths. The ASIC 12 further includes a high-speed link configured to output digital code to the FPGA 13 and an interface port configured to receive control data and instructions from the FPGA 13. The FPGA 13 receives the digital code from the ASIC 12, processes the digital code, and provides instructions to the ASIC 12 based on the received digital code. The FPGA 13 may provide the results of the digital code processing to a PC for analysis and display. The FPGA 13 may receive temperature information from a temperature sensor embedded in the sensor chip 11 and provide one or more feedback signals to the sensor chip via the ASIC 12. The nanopore flow cell analysis system 100A can operate autonomously and / or in an interactive mode with a user via a PC. These and other features of the nanopore flow cell analysis system 100A are described in further detail below.

[0028] FIG. 1B is a simplified cross-sectional view illustrating a nanopore flow cell (NFC) device 100B according to one embodiment of the present disclosure. Referring to FIG. 1B, the NFC device 100B includes a substrate 110, a sensor chip 120 attached to the substrate 110 by an attachment adhesive layer 113, and a microfluidic housing 130 covering the sensor chip 120 and PCB 110. The microfluidic housing 130 is attached to the sensor chip 120 using a first adhesive layer 141 to form a flow cell, and the microfluidic housing is attached to the PCB 110 using a second adhesive layer 142 to provide mechanical support. The sensor chip 120 has a front surface (also referred to as a top surface) 121 and a back surface (or bottom surface) 122. In one embodiment, the substrate 110 may be a printed circuit board (PCB), and the sensor chip 120 may be capable of biological analysis. It will be understood that the substrate 110 described herein is not limited to a PCB, and other substrates may be used, such as semiconductor (eg, silicon) substrates, glass substrates, ceramic substrates, etc.

[0029] The microfluidic housing 130 has an inlet 131, an outlet 132, and a first cavity 133. The microfluidic housing 130 can have an inner sidewall 135 adjacent to the cavity 133. The inner sidewall 135 is attached to the sensor chip 120 using a first adhesive layer 141 to form a flow cell 140 having an airtight seal. As used herein, a hermetic seal refers to an airtight and liquid-tight seal that precludes the passage of air, gas, and liquid. The flow cell 140 includes a channel formed by the cavity 133 between the microfluidic housing 130, the inner sidewall 135 of the microfluidic housing, and the sensor chip 120. In an exemplary application, a biological sample 137 can be introduced into the cavity 133 through the inlet 131 of the flow cell 140, and a sensor element (also referred to as a sensor) in the sensor chip 120 can determine the characteristics of the biological sample 137. The biological sample 137 may then be transferred from the cavity 133 to a waste container 139 and then removed therefrom through the outlet 132 of the flow cell 140 .

[0030] The first adhesive layer 141 forms an airtight and liquid-tight seal between the microfluidic housing 130 and the sensor chip 120. Furthermore, the first adhesive layer 141 is compatible with materials used in the flow cell. Meanwhile, the second adhesive layer 142 is configured to provide mechanical strength to the joint between the microfluidic housing 130 and the PCB 110. In some examples, the second adhesive layer 142 is thicker than the first adhesive layer 141. A distance 144 between the bottom surface of the outer sidewall 136 of the microfluidic housing and the PCB 110 is greater than a distance 145 between the bottom surface of the inner sidewall 135 of the microfluidic housing and the sensor chip 120.

[0031] In some embodiments, to bond the microfluidic housing 130 to the sensor chip 120 and PCB 110, first and second adhesive layers are formed, and then the microfluidic housing 130 is picked up and placed in contact with the sensor chip 120 and PCB 110. In some embodiments, the NFC device 100B is designed so that the first adhesive layer is in a solid form and has a well-defined thickness. On the other hand, the second adhesive layer is sufficiently thick and in a liquid state before curing, so that the bondline thickness of the second adhesive layer is self-adjustable. In other words, the second adhesive layer can fill the space required by the structure of the microfluidic device. The structure of the microfluidic device can be affected by the thickness of the first adhesive layer, the thickness of the sensor, the thickness of the die attach adhesive, the unevenness of the PCB surface, the step of the wire bond cavity in the microfluidic device, etc. Here, the bondline thickness refers to the thickness of the adhesive layer between the bottom surface of the device structure above the adhesive layer and the top surface of the device structure below the adhesive layer. Depending on the context, the term "bondline thickness" can refer to the pre-cure bondline thickness or the post-cure bondline thickness of the adhesive layer.

[0032] 1B , the NFC device 100B further includes a CMOS application-specific integrated circuit (ASIC) device 150 attached to the backside of the PCB 110 (the side opposite the front side on which the sensor chip 120 is attached). In one embodiment, the CMOS ASIC device 150 is attached to the PCB 110 by a second adhesive layer 151. The CMOS ASIC device 150 is connected to the sensor chip 120 via a plurality of through-silicon vias (TSVs) 160. In one embodiment, a heat sink 170 is attached to the CMOS ASIC device 150 by clips or adhesive (glue) for heat dissipation. In one embodiment, the FPGA 180 may be assembled on or attached to the PCB 110 and connected to the ASIC device 150 via metal traces on and in the substrate (PCB) 110.

[0033] FIG. 1C is a simplified cross-sectional view illustrating a nanopore flow cell (NFC) device 100C according to one embodiment of the present disclosure. Referring to FIG. 1C, the NFC device 100C includes a sensor substrate 110a, a sensor chip 120 attached to the sensor substrate 110a by an attachment adhesive layer 113, and a microfluidic housing 130 overlying the biological chip 120 and the sensor substrate 110a. The sensor chip 120 includes multiple sensors (sensor elements) arranged in an array of nanopores, each configured to generate an electrical signal in response to a condition of the nanopore. The microfluidic housing 130 is attached to the biological chip 120 using a first adhesive layer 141 to form a flow cell, and the microfluidic housing is attached to the sensor substrate 110a using a second adhesive layer 142 to provide mechanical support. In one embodiment, the sensor substrate 110a may be a printed circuit board (PCB), and the sensor chip 120 may be capable of biological analysis. It will be understood that the substrates described herein are not limited to PCBs, and other substrates, such as semiconductor (e.g., silicon) substrates, glass substrates, ceramic substrates, etc., can also be used. The microfluidic housing 130 has an inlet 131, an outlet 132, and a first cavity 133. The microfluidic housing 130 can have an inner sidewall 135 adjacent to the cavity 133, and the inner sidewall 135 is attached to the biochip 120 using a first adhesive layer 141 to form a flow cell 140 with an airtight seal. The flow cell 140 includes a channel formed by the cavity 133 between the microfluidic housing 130, the inner sidewall 135 of the microfluidic housing, and the biochip 120. The flow cell 140 has an inlet 131 and an outlet 132. A biosample 137 may be introduced into the cavity 133 through the inlet 131. A sensor element (also referred to as a sensor) in the sensor chip 120 can then determine the characteristics of the biosample 137. The biological sample 137 may then be transferred from the cavity 133 to a waste container 139 and then removed therefrom through the outlet 132. The flow cell structure of the NFC device 100C is similar to that of the NFC device 100B and, for purposes of brevity, will not be further described here.

[0034] The NFC device 100C further includes a plurality of pads 161 disposed on a second surface (or bottom surface) of the sensor substrate 110a opposite to the first surface (or top surface) on which the sensor chip 120 is mounted. The pads 161 are connected to the sensors of the sensor chip 120 via a plurality of through silicon vias (TSVs) 160.

[0035] The NFC device 100C further includes a second substrate 110b having a first surface 111 and a second surface 112 opposite the first surface, and a set of pogo pins 162 attached to the first surface 111 and configured to contact pads 161 when the sensor substrate 110a and the second substrate 110b are brought together. The NFC device 100C further includes a CMOS ASIC chip 150 mounted on the second surface 112 of the second substrate 110b. The NFC device 100C further includes an FPGA 180 mounted on the second surface 112 of the second substrate 110b and connected to the CMOS ASIC chip 150. In one embodiment, the flow cell mounted on the sensor substrate 110a is single-use and disposable, while the second substrate 110b having the CMOS ASIC chip and FPGA mounted thereon is reusable.

[0036] FIG. 2A is a top view illustrating a sensor chip 200 according to one embodiment of the present disclosure. The sensor chip 200 may include an array of sensors 210 to enable simultaneous measurement of multiple samples (biological or biochemical substances) disposed on its surface. The number of available sensors depends on the sensor density and the dimensions of the array or sensor chip. While one sensor chip is shown, it should be noted that those skilled in the art will understand that multiple sensor chips can be used in parallel to significantly increase overall throughput or reduce noise at a slower readout rate. In one embodiment, multiple sensors are disposed on a substrate, each having a circular sample well configured to hold a biological sample. The multiple sensors are separated from one another by mesa structures.

[0037]

[0003] Figure 2B is an enlarged portion of the sensor chip of Figure 2A. Referring to Figure 2B, the sensor, including the well and the electrode, supplies an electrical signal to the CMOS ASIC chip through a through-silicon via (TSV). In one embodiment, the TSV has a diameter of 50 μm or less, and the pitch between two TSVs is approximately 210 μm.

[0038] FIG. 2C is a simplified cross-sectional view illustrating a portion of a sensor chip including a well and an electrode according to one embodiment of the present disclosure. Referring to FIG. 2C, the sensor includes a sensor layer and a mesa structure on top of the sensor layer that surrounds the sensor layer. A dielectric is disposed between the substrate and the sensor layer. The dielectric layer may include silicon dioxide (SiO2). A stack of metal layers is disposed at the bottom of the sensor well and within the dielectric layer and is configured to provide an electrical signal output by the sensor to another device (e.g., an ASIC) via a through-silicon via (TSV). In one embodiment, the well has a thickness of approximately 90 μm, the mesa structure surrounding the well has a thickness of approximately 30 μm, and the dielectric layer has a thickness of approximately 1.5 μm. In one embodiment, the stack of metal layers may include a platinum (Pt) layer having a thickness of 300 nm and a titanium (Ti) layer having a thickness of 100 nm.

[0039] FIG. 3A is a flowchart illustrating a method 300A for preparing a nanopore flow cell system according to one embodiment of the present disclosure. Referring to FIG. 3A, the method begins in block 301 with the preparation of a nanopore flow cell (NFC), for example, by providing a nanopore flow cell analysis system 100A, such as that shown in FIG. 1A. For example, the system 100A may include a sensor chip 11, an ASIC 12, and an FPGA 13. In block 302, a membrane is formed on the sensor chip. In 303, the membrane is characterized. Membrane characterization may include determining whether the membrane is in good working condition by passing a current through the membrane. When the current is equal to or less than a predetermined value, the membrane is determined to be in good working condition. When the current exceeds a predetermined value, the membrane is determined to be broken. In block 304, a voltage is applied to the membrane to deform the membrane and allow protein (nanopore) insertion. In block 305, a motor molecule and a library conjugate are loaded into the protein (nanopore). In block 306, ADP is added to drive the motor molecules. In block 307, the sequence of the motor molecules is determined as they pass through the protein (nanopore). Sequencing may be based on changes in current as the motor molecules pass through the nanopore. In block 308, the method determines whether the current exceeds a predetermined current level. If the current is equal to or less than the predetermined current level (Yes in block 308), the method determines that the nanopore is blocked and causes the ASIC to apply a reverse voltage to the blocked nanopore to unblock the nanopore, i.e., to extrude the molecule (DNA) through the blocked nanopore. Once the nanopore is unblocked in block 309, the method repeats blocks 305, 306, 307, and 308 for molecular (DNA) sequencing. If the method determines that the nanopore is not blocked (No at block 308), the method performs self-calibration at block 310 and then proceeds to match the best sensor to the channel for DNA sequencing at block 311.

[0040] FIG. 3B is a graph of current indicating a blocked and then unblocked nanopore according to one embodiment of the present disclosure. As shown in FIG. 3B, the x-axis represents time and the y-axis represents current I in pA, which may be in one of three states: State A, State B, and State C. State A shows an example of current when a molecule passes through an unblocked nanopore. In the example shown, the current is approximately 100 pA when a molecule passes through an unblocked nanopore. State B shows an example of current when the nanopore is blocked by a molecule. In the example shown, the current is well below 100 pA. When this state is detected, the method includes the ASIC chip reversing the voltage applied to the nanopore, expelling the molecule from the blocked nanopore. When the nanopore is unblocked, the current may increase to a high current level, e.g., 200 pA, indicating an unblocked nanopore state (State C).

[0041] Figure 3C is a simplified block diagram showing a blocked state of molecular tether 33 in the nanopore when the ASIC applies a bias voltage V to attract molecular tether 33 to the nanopore, blocking the nanopore corresponding to state B in Figure 3B. Figure 3D is a simplified block diagram showing the ASIC applying a reverse bias voltage -V to unblock the nanopore corresponding to state C in Figure 3B.

[0042] FIG. 4 is a simplified block diagram illustrating a multi-sensor integrated chip architecture 400 for a nanopore flow cell (NFC) system according to various embodiments of the present disclosure. Referring to FIG. 4 , the architecture 400 may be configured to include multiple amplifier clusters 410, each of which may include multiple amplifiers configured to amplify signals received from multiple sensors (sensor 1, ..., sensor 4096). In one example, the received signals are associated with data signals associated with the sensor chip 120 via through-silicon vias 160. The architecture 400 includes multiple analog multiplexers 420, each connected to the output of an amplifier and configured to select one of the amplified signals of the sensors. The selected signals are multiplexed by multiplexers 440 to provide signal 441 to a set of analog-to-digital converters (ADCs) 450. The ADCs 450 convert the selected signals into digital data 451 representing the analog signals 441. It should be noted that the multiplexer 440 may include multiple multiplexer stages, but for clarity, only one of the multiple multiplexer stages 440 is shown. In one embodiment, the architecture 400 may include a correlated double sampling (CDS) and low-pass filtering (LPF) circuit 430 disposed between the analog multiplexer (4:1 MUX) 420 and the multiplexer (MUX) 440. The correlated double sampling and low-pass filtering (CDS+LPF) circuit 430 is configured to remove noise during a sensor reset operation and an amplifier offset voltage. The architecture 400 further includes a low-voltage differential signaling (LVDS) interface 460 for transmitting a differential data clock signal 461, a differential data signal 462, and a differential frame signal 463 to an external field-programmable gate array (FPGA).The architecture 400 includes a built-in self-calibration and test (Icalibration) circuit 470 configured to provide a reference signal to the amplifier for calibration, and a timing and control signal generator 480 that generates timing clocks and control signals for driving the amplifier 410, multiplexers 420 and 440, CDS and LPF circuit (CDS+LPF) 430, ADC 450, and LVDS interface 460. The architecture 400 includes a serial peripheral interface (SPI) port 481 configured to receive control data and / or software commands provided by a user or an external device such as a PC or FPGA. Those skilled in the art will appreciate that other bus ports may be used, such as an I2C port, a parallel port, a general-purpose input / output (GPIO) port, a universal serial bus (USB), a short-range wireless port, a WiFi port, etc. Architecture 400 further includes advanced functional blocks 490, such as functionality for applying a reference voltage V0 (491) to an amplifier, functionality for unblocking a DNA strand in the nanopore 492, functionality for nanopore membrane characterization 493, functionality for preventing channel shorting, functionality for protein insertion 494, etc. In some embodiments, all of the above-listed blocks, devices and / or circuits 410-490 of architecture 400 are integrated into an integrated chip, such as a CMOS integrated circuit.

[0043] In some embodiments, architecture 400 also includes providing different voltage supplies to different functional blocks. Signal amplification, multiplexing, analog-to-digital conversion, timing control, and high-speed interface operations can adversely affect the voltage supplies, thereby affecting the performance of the integrated circuit. For example, amplifiers, multiplexers, and analog-to-digital converters powered by a noisy voltage supply will read noisy signals. Some embodiments provide different voltage supplies to different functional blocks. For example, the amplifier cluster is provided with voltage supply V1, the 4:1 multiplexer is provided with voltage supply V2, the CDS and low-pass filter circuit 430 is provided with voltage supply V3, the one or more stages of multiplexer 440 are provided with voltage supply V4, the ADC 450 is provided with voltage supply V5, the LVDS serializer interface 460 is provided with voltage supply V6, the calibration and built-in self-test circuit 470 is provided with voltage supply V7, the timing control signal generator (or circuit) 480 is provided with voltage supply V8, and the advanced function block 490 is provided with voltage supply V9. Voltage supplies V1-V9 may have the same or different nominal voltages and are physically and electrically isolated from one another (e.g., by one or more dielectric layers). In one embodiment, some of voltage supplies V1-V9 may be shared by other components (not shown), such as phase-locked loops (PLLs), other input / output ports to the FPGA, etc. In one embodiment, voltage supplies V1-V9 may be low-dropout (LDO) regulators. In one embodiment, the LDO regulators are integrated with the integrated circuit (CMOS ASIC).

[0044] In one embodiment, the amplifiers in amplifier cluster 410 are differential amplifiers with a first input connected to the sensor signal and a second input connected to a reference voltage provided by an advanced function block 490 having various advanced functions such as a reference voltage V0 (491), a DNA unblocking function 492, a membrane characterization function 493, and a protein insertion function 494. In some embodiments, advanced function block 490 may include other functions such as housekeeping functions. Examples of housekeeping functions are short circuit checking and prevention, junction temperature verification, channel blocking, self-tests, and / or user-initiated tests. Of course, one skilled in the art will recognize that many other additional functions are possible.

[0045] The inventors observed that the probability that a sensor in a flow cell's sensor chip would capture a single biological substance, such as a nanopore protein or a motor protein, in a given period of time was approximately 33%, i.e., the sensor occupancy rate was approximately one-third based on a Poisson distribution model. Experimental results indicated that approximately one-third of all sensors provided meaningful data. The inventors determined that an adequate amount of data could be collected from the flow cell by reading out four sensors at a time, and proposed reading out four sensors at a time. Therefore, according to the present disclosure, each amplifier cluster includes four differential amplifiers. It is understood that the number of sensors may be any integer. In the example shown in FIG. 4, 4096 sensors are used. However, it is understood that this number is arbitrarily chosen to illustrate an exemplary embodiment and is not limiting.

[0046] FIG. 5 is a schematic block diagram illustrating a two-stage amplifier 50 according to one embodiment of the present disclosure. As shown in FIG. 5, the two-stage amplifier 50 includes a first differential amplifier or op-amp U1A having a first input 51 configured to receive a sensor data signal Iin1, a second input 52 for receiving a reference signal REF, and an output 53 connected back to the first input 51 through a first resistor R1. The two-stage amplifier 50 also includes a second differential amplifier or op-amp U2A having a first input 54 configured to receive the reference signal REF through a resistor R5, a second input 55 for receiving an amplified signal 57 from the differential amplifier U1A through a resistor R3, and an output 56 connected back to the first input 54 through a resistor R2. The second input 55 of the second differential amplifier U2A is connected to ground through a resistor R4. It should be noted that while the resistors are shown as discrete resistors, one skilled in the art would understand that other resistor configurations may be used without limiting the scope of the present disclosure. For example, each resistor may include multiple resistors switched in series and / or parallel, or the resistors may be implemented as metal-oxide-semiconductor field-effect transistors configured as variable resistors. In one embodiment, the two-stage amplifier 50 may be implemented as a transimpedance amplifier (TIA) with a feedback resistor that is adjustable to maintain the gain of the amplifier. The two-stage amplifier 50 has two gain stages, with the gain of the first stage being greater than the gain of the second stage.

[0047] In one embodiment, the reference voltage REF is generated by an on-chip digital-to-analog converter (DAC) that converts N-bit data received from an external device (e.g., FPGA) into an analog signal, where N is a positive integer. In one embodiment, the reference voltage REF is provided to the sensor (nanopore) of the sensor chip via an output.

[0048] FIG. 6 is a timing diagram illustrating an exemplary readout cycle of a nanopore based on a correlated double sampling (CDS) process according to one embodiment of the present disclosure. Referring to FIG. 6, during an initial stage when no biological or biochemical material is loaded into the nanopore of the flow cell, the sensor element associated with the nanopore outputs a maximum voltage Vmax. Alternatively, the unloaded nanopore of the flow cell may be precharged to the maximum voltage by the ASIC. This maximum voltage is sampled by the CDS of the CDS+LPF circuit 430 to obtain a first sampling result 610. The first sampling result 610 represents the noise and offset voltages of the sensor element, amplifier, and multiplexer. After that, a biological material is loaded into the nanopore, and the electrical signal of the nanopore of the sensor chip is then provided to the integrated circuit (ASIC) for signal measurement. The CDS+LPF circuit 430 samples the electrical signal to obtain a second sampling result 620. The difference between the first sampling result and the second sampling result represents the effective electrical signal value of the loaded nanopore, free of noise and offset values. In one embodiment, the sensor chip includes a CMOS image sensor. In other words, the pixels of the CMOS image sensor are the sensor elements. During a reset stage when the flow cell is clean, i.e., when no biological material is loaded into the flow cell, the pixels are reset to a reset voltage and can be converted into pixel signals. The initial electrical signals of the pixels are sampled by the CDS+LPF circuit 430 to obtain multiple first sampling results. Subsequently, biological material is loaded into the flow cell through the inlet, and the biological material is absorbed into the nanopore, causing changes in the electrical signals of the pixels of the CMOS image sensor. The electrical signals of the pixels are amplified or adjusted by an amplifier, optionally passed through a multiplexer, and then sampled by the correlated double sampling circuit. In one embodiment, the effective voltage value of the pixel is the difference between the first sampled value and the second sampled value. The effective voltage value is then low-pass filtered by the CDS+LPF circuit 430 to reduce uncorrelated noise. In some embodiments, the correlated double sampling is performed after the nanopore is loaded.

[0049] FIG. 7 is a simplified flowchart illustrating a DNA unblocking process 700 according to one embodiment of the present disclosure. Referring to FIG. 7, the DNA unblocking process includes a normal operation and an unblocking operation. In normal operation, DNA insertion is initiated and the DNA current is calibrated. This uses an algorithm similar to normal sequencing, except that the input can be from a built-in self-test (BIST) block or from known DNA provided by the user. In block 701, a set of operating parameters is input and stored. In block 702, user-provided or pre-programmable data is provided via the output of the ASIC to an analog-to-digital converter (DAC), which provides a corresponding voltage reference to the sensor chip. In block 703, a voltage ramp is generated and verified. The sensor's electrical signal is then measured by the DAC, which sends the measurement data to the FPGA in block 704. In block 705, the FPGA determines whether the nanopore is blocked. If the FPGA determines that the nanopore is blocked (Yes at block 705), the DNA unblocking process 700 proceeds to program the ASIC with the set of unblocking parameters (Block 706), initiate unblocking by applying a new voltage reference to the nanopore (Block 707), and observe the sensor (nanopore) electrical signal at Block 708. If the FPGA determines that an unblocked spike has been detected (Yes at block 709), the process repeats the above operations for the next nanopore (sensor) at Block 710. If the FPGA determines that an unblocked spike has not been detected (No at block 709), the DNA unblocking process 700 returns to Block 706 and repeats the above process until the FPGA detects an unblocked spike.

[0050] FIG. 8 is a simplified flowchart illustrating a film characterization process 800 according to one embodiment of the present disclosure. The film characterization process 800 begins film formation in block 801 by inputting a set of parameters into the ASIC. In one embodiment, a ramp Vref may be 0 V to ±500 mV for a period ranging from 1 ms to 10 seconds. In block 802, the DAC outputs a voltage reference to the sensor. The sensor's electrical signal is read and then measured in block 803. In block 804, the film characterization process 800 determines whether the electrical signal is within expected limits (or predetermined ranges). If the film characterization process 800 determines that the electrical signal is within the expected or predetermined ranges (Yes in block 804), the FPGA proceeds to calculate the film's capacitance value and proceeds to the next sensor (pixel). In one embodiment, the film's capacitance value is in the range of 1 pF to 400 pF. If the electrical signal is not within the expected range but the cutoff current is reached, the FPGA determines that the membrane is damaged and sets a flag indicating a damaged membrane. If the electrical signal is not within the expected range and the cutoff current is not reached, the process 800 returns to block 802.

[0051] FIG. 9 is a simplified flowchart illustrating a protein insertion process 900 according to one embodiment of the present disclosure. The nanopore insertion process 900 begins in block 901 by inputting a set of parameters into the ASIC. In one embodiment, the voltage reference Vref is 0 V to ±500 mV for a period ranging from 1 ms to 10 seconds. In block 902, the DAC outputs the voltage reference to the sensor. In block 903, the DAC continues to output a ramping voltage. The sensor's electrical signal is read and then measured in block 904. In block 905, the FPGA determines that a peak insertion current is present (Yes in block 905), the FPGA notes that the nanopore has successfully inserted into the membrane's electrical signal, shuts off the transmembrane voltage, and moves on to the next nanopore. If the presence of a peak insertion current is not detected (No in block 905), the protein insertion process continues with the voltage ramp in block 903.

[0052] 10 is a simplified flowchart illustrating a short circuit prevention process 1000 according to one embodiment of the present disclosure. The short circuit prevention process 1000 is used to protect the system or prevent the system from entering a short circuit condition by constantly checking for short circuit current. The short circuit prevention process 1000 cuts off the shorted channel by providing a resistor to set a 0V bias voltage across a pixel to cut off the pixel.

[0053] Referring to FIG. 10 , the short circuit prevention process 1000 begins in block 1001 by inputting a set of parameters into an ASIC. In block 1001, a generator is provided for generating a set of electrical signal patterns for a transistor amplifier (TIA). The electrical signal waveform may be a sine wave, a linear or nonlinear ramp, a sawtooth pattern, a square wave, or other waveform. The electrical signal pattern is applied as a stimulus to a sensor (sensor element or pixel) associated with the amplifier (block 1002), and the sensor's output signal is conditioned (amplified) by the amplifier and provided to an ADC to obtain a measurement (block 1003). The measurement is sent to an FPGA. The FPGA determines whether the measurement meets an expected value (block 1004). If the FPGA determines that the measurement meets the expected value, it instructs the ASIC to apply a stimulus to the next sensor (block 1006), and the process repeats. If the FPGA determines that the measurement does not meet the expected value, it sets an error flag (block 1005) and transitions to block 1006.

[0054] FIG. 11 is a simplified flowchart illustrating a method 1100 of operating a flow cell analysis system according to one embodiment of the present disclosure. Referring to FIG. 11 , in block 1101, a sensor device is provided. The sensor device may include an array of sensor elements, each configured to output an electrical signal in response to a physical condition. For example, the sensor elements may be associated with a nanopore having a biological sample and output an electrical signal in response to the biological sample. In one embodiment, the sensor device may include a CMOS image sensor, and the sensor elements are pixels. In block 1103, the method 1100 includes providing an integrated circuit coupled to the sensor device, the integrated circuit including multiple amplifier clusters coupled to the sensor elements and configured to amplify or condition the electrical signal by a gain factor greater than a single value. In block 1105, the method 1100 further includes selectively passing amplified electrical signals equal to or greater than a predetermined value. The selected electrical signals are provided to multiple analog-to-digital converters (ADCs) via multiple multiplexer stages. The selected electrical signals are then digitally converted to respective digital codes representing the selected electrical signals. The digital code is then output to an external device (e.g., FPGA 13 shown in FIG. 1A) via a low-voltage differential signaling (LVDS) interface. In one embodiment, before providing the selected electrical signal to the ADC, method 1100 includes subjecting the selected electrical signal to a correlated double sampling and filtering operation to reduce noise and offset of the sensor element and amplifier. In some embodiments, the timing control signal generator autonomously performs the amplification, selection, correlated double sampling and filtering, signal conversion, and data storage operations. In other embodiments, these operations may be performed by a user or by a software program stored on a PC via a wired or wireless communication link (e.g., SPI, USB, WiFi, etc.).

[0055] 11 , method 1100 further includes analyzing the digital code by an external device at block 1111. In one embodiment, the external device analyzes the digital code to obtain genetic information. In another embodiment, the external device analyzes the digital code to obtain an analysis result and determines a corrective action for the sensor device depending on the analysis result. The analysis and corrective action may include several functions, such as DNA unblocking, membrane characterization, protein insertion, short circuit protection, etc., as described in the above sections. Based on the analysis result, the external device may take a corrective action at block 1113, such as changing a programmable voltage reference to the sensor device via an integrated circuit (e.g., a CMOS ASIC chip).

[0056] FIG. 12 is a simplified flowchart illustrating a method 1200 according to one embodiment of the present disclosure for operating an integrated circuit configured to control a sensor chip having multiple sensor elements based on instructions received from an external device. Referring to FIG. 12, the method 1200 includes, at block 1201, receiving, by an integrated circuit, an electrical signal provided by the sensor element, the integrated circuit, which may be the CMOS ASIC device of FIG. 4, and including multiple differential amplifiers, each including a first input configured to receive the electrical signal of the sensor element and a second input connected to a bias voltage source (programmable voltage reference) and configured to apply a bias voltage to the sensor element. At block 1203, the method 1400 includes amplifying the received electrical signal by a programmable or variable factor. At block 1205, the method 1200 also includes selectively passing the scaled (amplified) signal through multiple signal paths using multiple multiplexers, where the number of signal paths is less than the number of differential amplifiers. The selected scaled signal is then converted to a digital code by one or more analog-to-digital converters at block 1207 and stored in data storage. At block 1209, method 1200 includes reading or outputting the digital code to an external device via a high-speed interface. In one embodiment, the high-speed interface includes a low-voltage differential signaling (LVDS) driver for driving a differential signal through a load. At block 1211, method 1200 further includes adjusting a bias voltage and applying the bias voltage to the sensor chip.

[0057] The scope of the embodiments disclosed herein is not limited by the specific embodiments described herein. Various modifications of the embodiments of the present invention, in addition to those described herein, will be apparent to those skilled in the art from the foregoing description and accompanying drawings. Furthermore, while some of the embodiments of the present invention have been described in the context of specific implementations in particular environments for particular purposes, those skilled in the art will recognize that their usefulness is not limited thereto, and that embodiments of the present invention may be beneficially implemented in any number of environments for any number of purposes.

Claims

1. An integrated circuit for processing a sensor signal output from a sensor chip capable of detecting various substances, The integrated circuit comprises: a plurality of amplifier clusters; a plurality of first analog multiplexers; at least one analog-to-digital converter (ADC) coupled to the plurality of first analog multiplexers and configured to generate digital code values ​​representative of the electrical signals; each of the plurality of amplifier clusters comprises a plurality of amplifiers; each amplifier having a first input for receiving the sensor signal output from a sensor of the sensor chip, a second input connected to a programmable voltage reference, and an output for outputting an electrical signal; each of the plurality of first analog multiplexers is connected to one amplifier cluster of the plurality of amplifier clusters and is configured to selectively pass one of the electrical signals output from the plurality of amplifiers in the one amplifier cluster; The programmable voltage reference Controllable to provide bias voltages to the sensor chip for each of DNA strain unblocking, nanopore membrane characterization, and protein insertion; or The sensor chip can be controlled so that a bias voltage is supplied to attract the molecular chain to the nanopore, and a reverse bias voltage is supplied to push the molecular chain out of the nanopore. At least one of Integrated circuit.

2. The integrated circuit of claim 1 , wherein each amplifier in an amplifier cluster includes two stages of amplification.

3. The integrated circuit of claim 1 further comprising a digital-to-analog converter configured to generate the programmable voltage reference in response to a digital input signal.

4. 2. The integrated circuit of claim 1, wherein the number of amplifiers in an amplifier cluster is four, and each of the first analog multiplexers has four inputs, each input connected to an output of an amplifier in the amplifier cluster.

5. 10. The integrated circuit of claim 1, further comprising: a correlated double sampling and low pass filtering circuit coupled to the plurality of first analog multiplexers and configured to reduce noise, offset voltage, and drift of the integrated circuit.

6. The integrated circuit of claim 1 , further comprising a timing control circuit configured to provide control signals to the plurality of amplifier clusters, the plurality of first analog multiplexers, and the at least one ADC.

7. 2. The integrated circuit of claim 1, wherein the plurality of amplifier clusters, the plurality of first analog multiplexers, and the at least one ADC are powered by separate voltage supplies that are physically and electrically isolated from one another.

8. 2. The integrated circuit of claim 1, further comprising: a plurality of second analog multiplexers disposed between the plurality of first analog multiplexers and the at least one ADC, the second analog multiplexers configured to sequentially provide selectively passed electrical signals to the at least one ADC.

Images