Processing method for power semiconductor modules

Abstract

A method for treating a power semiconductor module comprising at least one semiconductor element including a metal oxide semiconductor element and / or a metal insulator semiconductor element, the method comprising the steps of: a. determining a first value V corresponding to an initial health state of a gate oxide of the module; soh,0 and b. obtaining a second value V corresponding to the current state of health of the gate oxide of the module. soh,X and c. obtaining the on-state gate voltage V CC or the off-state gate voltage V EE and the turn-on delay time t ON or turn-off delay time t OFF and the first value V soh,0 and a second value V soh,X and d. estimating the estimated delay time t ON Or t OFF During this time, the estimated gate voltage V CC Or V EE and generating at least one control signal configured to apply the at least one control signal to the module.

Description

[Technical Field]

[0001] The present disclosure relates to the field of monitoring, limiting, inhibiting and / or reducing intrinsic degradation of power semiconductors during operation. [Background technology]

[0002] The quality of the gate oxide of a power semiconductor module during operation is known to be a critical parameter relating to the reliability of such devices.

[0003] Especially for SiC MOSFETs, the thin gate oxide (GOX) film appears to be a key reliability issue, as SiC MOSFET devices have failure probabilities up to four orders of magnitude higher than Si MOSFETs.

[0004] Reducing the positive gate-source voltage can improve device reliability. A negative bias is commonly used to avoid device self-turn-on during the switching on of series-connected devices. However, because power semiconductors have idle times, applying a negative bias for several hours reduces the threshold voltage. This change is important during the first few seconds when the converter starts switching again. Furthermore, gate overvoltage occurs during the gate switching time, which also contributes to a shift in the threshold voltage.

[0005] Known solutions to improve substrate defect density and theoretically improve reliability include limiting the gate oxide field in block mode and on-state, avoiding voltage spikes, and passivating the SiC / SiO2 interface. However, known solutions to maintain gate oxide quality have various adverse effects in some operating states of power semiconductor modules. Summary of the Invention

[0006] The present disclosure improves this situation.

[0007] 1. A method for treating a power semiconductor module including at least one semiconductor element including a metal oxide semiconductor element and / or a metal insulator semiconductor element, comprising: a. A first value V corresponding to the initial healthy state of the gate oxide of the module soh,0 and b. A second value V corresponding to the current state of health of the gate oxide of the module soh,X and c. On-state gate voltage V CC or the off-state gate voltage V EE and the first value V obtained soh,0 and a second value V soh,X Turn-on as a function of t ON Delay time or turn-off time t OFF and estimating the delay time of d. Estimated delay time t ON or t OFF During this time, the estimated gate voltage V CC or V EE and generating at least one control signal configured to apply the signal to the module. A method is proposed.

[0008] In another aspect, a power semiconductor module is proposed, comprising a single metal oxide semiconductor device, a set of metal oxide semiconductor devices, a single metal insulator semiconductor device, or a set of metal insulator semiconductor devices, the module being configured to perform the above method.

[0009] In another aspect, computer software is proposed comprising instructions which, when the software is executed by a processor, perform a method as defined herein. In another aspect, a computer-readable non-transitory recording medium having stored thereon software for performing a method as defined herein, when the software is executed by a processor.

[0010] The following features may optionally be implemented separately or in combination with each other: the method may further comprise the following preliminary operations: At least one semiconductor element Zero or negative gate voltage V EE and turn-off delay time t OFF or switching from an on state to an off state according to a control logic signal involving Positive gate voltage V CC and turn-on delay time t ON and switching from an off state to an on state according to a control logic signal involving:

[0011] Applied gate voltage V CC or V EE The sign of depends on the on / off state of at least one semiconductor element.

[0012] The first value obtained, V soh,0 and the obtained second value V soh,X Turn-on delay time t as a function of ON or turn-off delay time t OFF The criteria for estimating are the following: The second value obtained, V soh,X The first value V is obtained soh,0 If it is greater than , the turn-off delay time t OFF is the turn-off delay time t OFF and The second value obtained, V soh,X The first value V is obtained soh,0 If it is smaller than the turn-off delay time t OFF is the turn-off delay time t OFF a decrease relative to its previous value; Includes.

[0013] The first value obtained, V soh,0 and the obtained second value V soh,X On-state gate voltage V as a function of CC or the off-state gate voltage VEE The criteria for estimating are the following: The second value obtained, V soh,X The first value V is obtained soh,0 If the on-state gate voltage V CC is the on-state gate voltage V CC is increased relative to the previous value of V, and the increase is soh,0 and the second value V obtained soh,X be proportional to or equal to the difference between Includes.

[0014] The first value obtained, V soh,0 and the obtained second value V soh,X On-state gate voltage V as a function of CC or the off-state gate voltage V EE The criteria for estimating are the following: The second value obtained, V soh,X The first value V is obtained soh,0 If the off-state gate voltage V EE is the off-state gate voltage V EE is decreased relative to its previous value; The second value obtained, V soh,X The first value V is obtained soh,0 If the off-state gate voltage V EE is the off-state gate voltage V EE is increased relative to its previous value, The second value obtained, V soh,X The first value V is obtained soh,0 If the off-state gate voltage V is equal to EE is the off-state gate voltage V EE remains equal to its previous value, and Includes.

[0015] The first value obtained, V soh,0 and the obtained second value V soh,X On-state gate voltage V as a function of CC or the off-state gate voltage V EE The criteria for estimating are the following: The second value obtained, V soh,X The first value V is obtained soh,0 If the off-state gate voltage V EE is the off-state gate voltage V EE is decreased relative to its previous value; The second value obtained, V soh,X The first value V is obtained soh,0 If the on-state gate voltage V CC is the on-state gate voltage V CC is increased relative to its previous value, The second value obtained, V soh,X The first value V is obtained soh,0 If the on-state gate voltage V is equal to CC and the off-state gate voltage V EE are reinitialized to their default values, and Includes.

[0016] The method comprises the following operations: When reverse conduction of the semiconductor device is detected, the estimated gate voltage V CC or V EE generating at least one control signal configured to apply to the module; Further includes:

[0017] At least two second values ​​V soh,X and V soh,X+1 is obtained during module operation, and the on-state gate voltage V CC or the off-state gate voltage V EE the first value V obtained soh,0 and the second value V obtained soh,X and V soh,X+1 The criteria to estimate as a function of and are: The time derivative dV of the second value obtained soh,X When / dt is positive, the on-state gate voltage V CC is the on-state gate voltage V CC and / or the off-state gate voltage V EEis the off-state gate voltage V EE is decreased relative to its previous value; The time derivative dV of the second value obtained soh,X When / dt is negative, the on-state gate voltage V CC is the on-state gate voltage V CC and / or the off-state gate voltage V EE is the off-state gate voltage V EE is increased relative to its previous value, Includes.

[0018] Turn-on delay time t ON or turn-off delay time t OFF The basis for estimating is the on-state gate voltage V CC and / or the off-state gate voltage V EE It depends even more on

[0019] Other features, details and advantages are set forth in the following detailed description and figures. [Brief explanation of the drawings]

[0020] [Figure 1A] Schematic diagram of a physical phenomenon. [Figure 1B] Schematic diagram of a physical phenomenon. [Figure 2] 1 is a schematic diagram of the evolution of an index during operation of a power semiconductor device; [Figure 3] FIG. 1 is a diagram illustrating an example of a circuit having a semiconductor element. [Figure 4] FIG. 10 shows superimposed gate driver switching waveforms for various situations. [Figure 5] FIG. 2 illustrates a circuit portion according to one embodiment. [Figure 6] 1 is a graph of several values ​​over time in one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] {Major problem to be solved} Bias temperature instability (BTI) is a reliability issue for insulated gate power modules such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and high electron mobility transistors (HEMTs). In SiC power semiconductor devices, this phenomenon is much more problematic (approximately 10 times) during device operation than in Si power semiconductor devices because the band offset between the gate oxide and the power semiconductor is reduced and carbon atoms degrade the atomically smooth Si / SiO2 interface. Charge trapping is also a reliability concern for GaN HEMT devices due to the complexity of the gate stack structure.

[0022] Charge trapping can be a persistent or transient phenomenon and the main consequences of this reliability problem are: i / "Increased on-state resistance RDS(on)" During operation of the power semiconductor element, this can lead to excessive power dissipation and overheating of the device / module, which can have a devastating effect on the integrity of the material. ii / "Body diode threshold voltage" During operation of a power semiconductor, this can lead to excessive power dissipation and overheating of the device. iii / "Off-state blocking leakage current IDSS(off)" causes additional losses in the device and may even lead to catastrophic failure. iv / "Shoot-through current" The on-time delay and off-time delay are varied. The initial dead time of the power semiconductors may not be sufficient to safely switch the series device, potentially resulting in a catastrophic short-circuit failure.

[0023] In each of the above problems, the extra loss caused by degradation increases the temperature of the power semiconductor, accelerating degradation.

[0024] Identifying gate oxide degradation under on-line operation of power semiconductors is an important parameter for assessing the reliability of such devices from the standpoint of testing and safety assessment (including standards) as well as delivery / maintenance of power conversion equipment.

[0025] {theory} Flat band voltage V fb is the voltage that generates a flat energy band in the semiconductor when applied to a semiconductor element, and is determined by the following equation (1):

number

[0026] Φ MS is the work function difference between the gate metal material and the semiconductor material. C ox is the capacitance of the oxide film. Q ox is the total effective charge in the oxide. The last term in equation (1) is due to the charge density in the oxide.

[0027] Note that the flat-band voltage is affected by the presence of charge at the oxide-semiconductor interface. Charges present at this interface are sensitive to the electric field formed on the channel. A positive gate voltage generates a positive electric field, causing negative charge to accumulate in the oxide, and therefore the flat-band voltage increases according to equation (1). Conversely, a negative gate voltage generates a negative electric field, causing positive charge to accumulate in the oxide, and therefore the flat-band voltage decreases according to equation (1). This phenomenon is called bias temperature instability, or BTI. In the case of a positive electric field, it is called positive temperature bias instability (PBTI). In the case of a negative electric field, it is called negative temperature bias instability (NBTI).

[0028] Figures 1A and 1B are based on figures published in the paper by X. Zhong et al., "Bias Temperature Instability of Silicon Carbide Power MOSFET Under AC Gate Stresses," IEEE Transactions on Power Electronics, vol. 37, no. 2, pp. 1998-2008, Feb. 2022, doi: 10.1109 / TPEL.2021.3105272. Figures 1A and 1B illustrate the phenomenon described above. Figure 1A illustrates the effect of the gate-source voltage VGS corresponds to the situation where the gate-source voltage V GS corresponds to the situation where is less than 0V.

[0029] Despite efforts to avoid charge trapping in the oxide during design, charge is trapped in the gate oxide due to positive or negative electric fields during operation of power semiconductor devices. This phenomenon is largely unavoidable in the case of SiC or GaN semiconductor materials, where more interface states and fixed oxide charges appear after high electric fields are applied. The trapped charge increases significantly with high switching frequencies and / or high device temperatures.

[0030] One of the main consequences of gate oxide degradation is the threshold voltage V th This is the fluctuation of the temperature, and is described as the following equations (2) and (3).

number

[0031] N a is the acceptor concentration in the substrate. s is the dielectric constant of the semiconductor. k is the Boltzmann constant. T is the temperature. ni is the intrinsic carrier concentration. C ox is the capacity of the oxide.

[0032] The doping of the gate layer and substrate and the oxide thickness are not affected by the bias voltage, so the threshold voltage V th The significant change in is related to the change in oxide charge and therefore the flat band voltage V fb can be monitored solely by measuring

number

[0033] Gate oxide changes can be either temporary or permanent. Temporary changes are related to high frequencies, such as switching frequencies, in the range of tens to hundreds of kHz. Permanent changes are related to durations measured in hours / days. Exacerbating factors are long off-state periods, such as module idle times, or long on-state periods, such as in solid-state power controller applications (solid-state relays). Both modes have the following effects: - Gate voltage V g to main voltage V CE , V DS , and the main current I C , I D The transfer characteristics to the power semiconductor elements are changed, which affects the conduction losses. -The threshold voltage is changed, which affects the switching time.

[0034] As a result of gate oxide degradation, in Figures 2, 3 and 4 the switching time increases with the threshold voltage V th It can be seen that the gate voltage V g is the voltage source 32(V driv ) and a gate resistor 33 (Rg). The graph in Figure 4 shows a comparison of the switching waveforms for the same semiconductor device 31 depending on the situation: - the index "New" corresponds to the new state (nominal state) of the semiconductor element 31; - index "PermPos" corresponds to the case where gate oxide degradation is permanent and positive; - the index "PermNeg" corresponds to the case where the gate oxide degradation is permanent and negative; The index "Trans" corresponds to the case of transient gate oxide degradation.

[0035] Figure 2 shows the evolution of some indices during operation (within a few days) when the gate is driven with a standard pattern. Index 21 corresponds to a permanent change, index 22 to a temporary change: - positive gate bias ΔVsohP; - negative gate bias ΔVsohN; -Temporary healthy state change ΔVsoh=ΔVsohP-ΔVsohN. The solid lines correspond to the index "PermPos" in FIG. 4, while the dotted lines and the indexes with a "prime" (') correspond to "PermNeg" in FIG.

[0036] The defaults that occur at turn-on are as follows: - threshold voltage V th A drop in will cause turn-on to occur earlier than desired.,In half-bridge configurations where series power semiconductor elements,operate in complementary states, shoot-through currents can occur; - threshold voltage V th An increase in τ causes turn-on to occur later than desired, resulting in body diode conduction and increasing overall system losses.

[0037] The defaults that occur in the turn-off state are as follows: - threshold voltage V th An increase in τ causes turn-off to occur earlier than desired, resulting in body diode conduction and increasing total system losses; - threshold voltage V th A decrease in V causes turn-off to occur later than desired. In a half-bridge configuration where series power semiconductor devices are operated in complementary fashion, shoot-through currents can occur.

[0038] From a system safety perspective, turn-on anticipation and turn-off delays can cause serious damage to the device if large shoot-through currents occur.

[0039] The objective here is to eliminate or at least reduce the effects of gate oxide degradation by acting on the control gate driver voltage that provides the gate voltage that controls the power semiconductor device, and further, the dedicated gate voltage is controlled in such a way that it also reduces and / or eliminates gate oxide degradation.

[0040] {Description of the embodiment} 5 and 6. In the following, a power semiconductor module 1 is an assembly comprising at least one metal oxide semiconductor (MOS) or metal insulator semiconductor (MIS) element. Even if the module 1 comprises multiple MOS elements, they will be considered as a single element in the following, since there is a common gate G, a common source S, and a common drain D. For this reason, in the following, the single gate, single source, and single drain will be used without distinguishing between embodiments with single or multiple MOS elements. The term "power" is used in its general sense in the technical field of energy conversion (power electronics).

[0041] The purpose of the following method is to measure the output characteristic V DS and I D The goal is to adapt the gate control voltages and switching timings to reduce or neutralize charge trapping effects while maintaining as much as possible the required capacitance. The proposed method can be used not only in operational conditions, typically on a test bench, but also when the modules are integrated and interconnected in their operational and industrial environments.

[0042] The module 1 comprises at least one semiconductor element 11 (here a transistor) and a control circuit section 12. The control circuit section 12 includes: - means for detecting the health of the gate oxide, here for example a detection module 2; means for comparing the current state of health of the gate oxide with an initial state of health, here for example a calculation module 3; -Turn on t ON Delay time for turn-off t OFF delay time, on-state voltage VCC , and the off-state voltage V EE means for determining, here for example a calculation module 3; - means for converting the control signal CTRL into the required gate signal, here for example the actuation module 4; means for driving the gate, here for example a gate driver control voltage source 5;

[0043] By way of example only, the computation module 3 may comprise a digital or analog controller. The actuation module 4 may comprise a programmable delay generator, such as the trade reference "AD9500", or the delay may be generated by an FPGA. The gate driver control voltage source 5 may be a variable voltage source, such as a linear gain controlled amplifier. The gate driver voltage source may be a push-pull voltage source, a totem pole voltage source, or a class B amplifier.

[0044] The method includes the following acts. a. A first value V corresponding to the initial healthy state of the gate oxide of module 1 soh,0 To obtain; b. A second value V corresponding to the current state of health of the gate oxide of module 1 soh,X To obtain; c. The first value V obtained soh,0 and a second value V soh,X as a function of gate voltage V CC or V EE and delay time t ON or t OFF and to presume; d. Delay time t ON or t OFF During this time, the gate voltage V CC or V EE generating at least one control signal CTRL configured to apply to the module 1;

[0045] Healthy state (initial healthy state V soh,0 and / or current health status V soh,X) can be acquired by the detection module 2. For example, a fast Measure-Stress-Measure (MSM) technique can be performed to determine the current health state of the gate oxide. The measurement is performed immediately after the stress. For example, it is proposed that: 1. Threshold voltage V th Measurement of; The Kelvin source voltage generated by the time differential di / dt of the current during the turn-on / off switching time of the semiconductor element 11 is used to calculate V soh The gate-source voltage V is taken as GS Measurement of is triggered; 2. Turn-on / off delay measurement: The Kelvin source voltage generated by the time differential di / dt of the current during the turn-on / off switching time of the semiconductor element 11 is used to calculate V soh A timer is triggered that is converted to

[0046] Such an MSM technique is advantageous because it requires only a gate connection, although other techniques for obtaining the state of health may be used in various embodiments.

[0047] Typical on-state voltage V CC is about 15V (typically between 10V and 20V), and the voltage during the typical off state, V EE is approximately -5V (typically between -20V and 0V).

[0048] In the embodiment shown in FIG. 5, the calculation module 3 calculates the current health state V soh,X from the detection module 2. The calculation module 3 is configured to calculate the received current health state V soh,X the initial healthy state V soh,0The gate driver voltage source 5 is configured to control the gate of the semiconductor element 11 between an ON state and an OFF state according to an external control signal CTRL modified by the actuation module 4. The transition instants between the alternating OFF and ON states within a switching period are determined by the external control signal CTRL and are determined by a delay t imposed by the calculation module 3. ON and t OFF and amplitude V CC and V EE As a result, the applied gate driver voltage is varied in time and amplitude. As an example, the amplitude variation is between 0V and 5V, and the time is between 0ns and 500ns (see Figure 6).

[0049] In some embodiments, the method further comprises the following preliminary acts: at least one metal oxide semiconductor element (11), *Zero or negative gate voltage V EE and turn-off delay time t OFF switching from an ON state to an OFF state in accordance with a CTRL logic signal with *Positive gate voltage V CC and turn-on delay time t ON and switching from an OFF state to an ON state according to a CTRL logic signal.

[0050] In some embodiments, part of the method includes, after generating the control signal CTRL for a previous loop, the method generating a second value V soh,X+1 Starting from the second acquisition of V, the sequence of operations b to d is repeated at least once as a current loop. In these examples, the first value V soh,0 is not re-obtained a second time, but is reused for each loop. In the following, the indices "X" and "X+1" are used to designate the current iteration and the subsequent iteration, respectively.

[0051] In the following, the first value obtained, V soh,0 and a second value V soh,Xas a function of (operation c) and / or successive values ​​V soh,X and V soh,X+1 As a function of gate voltage V CC or V EE and delay time t ON or t OFF We present several different examples of how to estimate σ and σ. An embodiment may include a combination of features obtained from such examples.

[0052] {Example A} Gate oxide health V soh The sequence of operations including obtaining the ON state can be performed only once in a switching period (a sequence of ON states and OFF states). In various embodiments, the sequence of operations can be performed twice in a switching period: a first sequence of operations for the ON state and a second sequence of operations for the OFF state.

[0053] Advantageously, the on-switching and off-switching times can be adapted according to the permanent healthy state of the gate oxide. In this case, the on-healthy state V sohP and off healthy state V sohN are defined for the on and off states, respectively. Advantageously, the on- and off-switching times are adapted according to the permanent and temporary health states of the gate oxide.

[0054] In some embodiments, the gate oxide healthy state V soh is taken at a fixed time delay after the turn-off of the semiconductor device 11. sohP can be taken just before or just after turn-off, for example within 10 μs before / after turn-off.

[0055] In some embodiments, the off-health state V sohN is taken just before turn-on, for example within 10 μs before turn-on. Alternatively, the off-healthy state V sohNcan be acquired continuously (within an estimation interval of 10 μs) during the off-time. The last value acquired before turn-on is retained. In addition, an external signal can be sohN You can control when the value should be obtained.

[0056] The initial healthy state V of the semiconductor element 11 soh,0 may be obtained during the first operating time of module 1, e.g., two hours. In various embodiments, the initial state of health may be obtained during commissioning of each semiconductor device. Alternatively, the initial state of health may be pre-programmed based on measurements on a representative batch of power semiconductor devices, such as nominal values.

[0057] {Example B} In some embodiments, it is possible to optimize the switching instants of the semiconductor device 11 in response to gate oxide degradation. To this end, the healthy state voltage V of the gate oxide during operation (over its lifetime) of the module 1 can be optimized to avoid shoot-through currents and excessive losses due to body diode conduction. soh The delay time of the switching sequence can be adjusted when the gate oxide degradation occurs. Advantageously, the switching time is adapted to the gate oxide degradation, which reduces the design margin and improves the module efficiency.

[0058] To do so, it is possible to change the times of the rising and falling edges of the signals controlling the semiconductor element 11, for example: -V soh,X >V soh,0 If , the delay t ON is decreased and the delay t OFF is increased; -V soh,X <V soh,0 If , the delay t ON is increased and the delay t OFF is reduced.

[0059] In the initial state, t ON and tOFF are the initial values ​​t ON,0 and t OFF,0 , for example, 300ns and 200ns.

[0060] The healthy state of the gate oxide is the threshold voltage V th If it corresponds to t, the applicable ON Delay and t OFF The delay can be calculated according to (5) and (6), or (5) and (7).

number

[0061] Rg is the total external and internal gate resistance, and Ciss is the input gate capacitance, which can be approximated by the oxide capacitance. When that is combined with the example where the healthy state is obtained twice in the switching period, V sohP,X is the turn-on delay t ON is used to find V sohN,X is the turn-off delay t OFF is used to find the

[0062] The healthy state is the flat band voltage V fb In this case, equations (2) and (3) are soh Used in place of variables.

[0063] In this system, the delay t ON and / or t OFF cannot be negative. Therefore, t ON,0 and t OFF,0 is the maximum change in the delay time of a semiconductor device, taking into account the maximum degradation of the gate oxide health of the semiconductor device during operation. In this case, the initial delay t OFF,0 is calculated as a function of the minimum gate oxide health value and the initial delay t ON,0 is t OFFto the maximum value of the turn-on and turn-off delays of non-degraded devices plus a security margin, "dead time," which integrates conventional turn-on and turn-off delays of non-degraded devices, as shown in equation (8).

number

[0064] {Example C} In some embodiments, it is possible to maintain a constant conduction loss in a semiconductor device in response to gate oxide degradation. To this end, a positive gate voltage V CC If the gate oxide health state shifts during semiconductor device operation, the time is adjusted to avoid overheating of the semiconductor device. Advantageously, the initial positive gate voltage V CC,0 can be designed to be lower than the nominal value to avoid rapid degradation of the gate oxide. In other words, the positive gate voltage V CC The increase is done in a gradual / iterative manner to avoid overvoltage and the corresponding unnecessary heating.

[0065] for example: -V soh,X+1 >V soh,X If the positive gate voltage V CC,X+1 its previous value V CC,X Increase relative to

[0066] To avoid causing more damage to the gate oxide by applying a larger positive voltage, this condition / rule may only be effective when the semiconductor device is under stress higher than a certain percentage (e.g., 60%) of the initial maximum stress design. "Stress" in this context may be, for example, the primary collector / drain current or junction temperature.

[0067] For example, the increment value is equal to the change in the difference between the initial health state and the current health state.

number

[0068] {Example D} In some embodiments, applying a reverse gate voltage bias during operation of a power semiconductor module can reduce (but not necessarily prevent or repair) gate oxide degradation. Advantageously, applying a gate voltage different from conventional operation can reduce trapped gate charge without interfering with normal operation. Thus, any charge buildup that would lead to degradation of the power semiconductor operating mode is slowed down before any potentially catastrophic irreversible failure.

[0069] for example: -V soh,X >V soh,0 If , a lower voltage (V EE,X <V EE,0 ) is applied; -V soh,X <V soh,0 If the EE,X >V EE,0 ) is applied; -V soh,X =V soh,0 If the EE,X =V EE,0 ) is applied.

[0070] Negative gate bias (V EE By decreasing the gate bias voltage, more holes are trapped in the gate oxide and the positive bias instability is compensated for by the negative bias instability, which slows down the rate of degradation. Conversely, by increasing the negative gate bias on the semiconductor device, fewer holes are trapped in the gate oxide and the negative bias instability is reduced.

[0071] In the first example, V EE,X =V EE,0 +V soh,0 -V soh,X is. V EE =-5V;V soh,0=3V;V soh,X If V = 4V, EE,X =-6V. V EE =-5V;V soh,0 =3V;V soh,X If V = 2V, EE,X =-4V.

[0072] In the second example, V EE,X =V EE,0 +k(V soh,0 -V soh,X ), where k is a predetermined coefficient, for example 0.05.

[0073] {Example E} In some embodiments, by varying the negative and / or positive gate voltage bias during operation of the semiconductor module, it is possible to prevent (not just reduce, but not necessarily repair) further degradation of the gate oxide of the semiconductor device. Advantageously, applying a gate voltage different from conventional operation can slow down gate charge trapping, thus preventing any charge accumulation that would lead to degradation of the power semiconductor operating mode before any potentially catastrophic irreversible failure.

[0074] for example: -dV soh,X If / dt>0, a lower voltage V EE,X and / or a lower voltage V during the on-state CC,X Applying; -dV soh,X If / dt<0, a higher voltage V EE,X and / or apply a higher voltage V during the on-state CC,X is applied.

[0075] By reducing the negative gate bias on the semiconductor device, more holes are trapped in the gate oxide and the positive bias instability is compensated for by the negative bias instability, which slows down the rate of degradation. Conversely, by increasing the negative gate bias on the semiconductor device, fewer holes are trapped in the gate oxide and the negative bias instability is reduced.

[0076] Voltage V EE,X ,V soh,X the derivative of , a given gain K, and a previous value V EE,0 can be calculated as a function of V CC,X ,V soh,X the derivative of , a given gain K, and a previous value V CC,0 It can be calculated as a function of V. EE,X =V EE,0 +K EE dV soh,X / dt and V CC,X =V CC,0 +K CC dV soh,X / dt. And for example:K EE =K CC =1min / V.

[0077] In various examples, different gains K can be used depending on the sign of the derivative: -dV soh,X If / dt>0, then K CC <K EE and -dV soh,X If / dt<0, then K CC >K EE is.

[0078] Such a condition / rule is that positive temperature bias instability exists (dV soh,X / dt>0), which limits the further increase in conduction losses when a negative gate bias is present (dV soh,X / dt<0) when (V EE limiting the effect on self-turn-on (due to increased

[0079] {Example F} In some embodiments, a recovery sequence can be applied to a power semiconductor module to eliminate positive or negative bias temperature instability. Advantageously, by applying a gate voltage different from conventional operation for a limited time, trapped gate charge can be removed from the gate oxide. Thus, any charge accumulation that would lead to degradation of the power semiconductor operating mode is prevented before any potentially catastrophic irreversible failure. Furthermore, recovery can be performed in a short time step that avoids propagation of degradation.

[0080] for example: -V soh,X >V soh,0 If the voltage is greater than 1 V, the more negative voltage (V EE,X <V EE,0 ) is applied; -V soh,X <V soh,0 If , a larger (positive) voltage (V CC,X >V CC,0 ) is applied; -V soh,X =V soh,0 If the voltage is the same during the off-state and the on-state (V EE,X =V EE,0 ;V CC,X =V CC,0 ) is applied.

[0081] This mode is V EE and V CC This can be applied during idle states of the power semiconductor module when the temperature is maintained for several hours. To accelerate recovery, the power semiconductor module can be heated.

[0082] {Example G} In some embodiments, a shift in the healthy state (e.g., flatband voltage V fb ) during reverse conduction of the semiconductor device, the off-state gate voltage or the on-state gate voltage V EE and / or VCC Advantageously, this can be done online in applications such as inverters where the device is operating in both forward and reverse conduction modes.

[0083] {Example H} In some embodiments, the degradation and the new applied voltage V CC and V EE In other words, the timing value depends on the applied voltage. Advantageously, all output characteristics of the semiconductor device remain constant.

[0084] The delay time is calculated for the initial gate oxide healthy state and the degraded gate oxide healthy state, and for the initial positive and negative gate voltages V CC , V EE and the obtained positive and negative gate voltages V CC,X , V EE,X It is calculated based on the

[0085] The timing is calculated according to (9) and (10) or (9) and (11).

number

[0086] In a particularly advantageous embodiment, the features of Example H can be combined with the features of Examples C and D. For example: -Rg=12Ω;Ciss=10 -9 and the following initial conditions, i.e., V CC,0 =15V;V EE,0 =-5V;V sohP =V sohN =3V, t ON,0 =500ns;t OFF,0 =250ns;t ON,0 =298.6ns; - Healthy condition after deterioration V sohP,X =V sohN,X = 4; Example C features V CC,X Impose = 16V;V EE =-6V; -Timing OFF,X = 302ns and t ON,X =287.2ns, is.

[0087] {Example Summary} The above examples are summarized in the table below. [Table 1]

[0088] The present disclosure is not limited to the methods, modules, circuits, and computer software described herein, which are merely examples, and the present invention encompasses all alternatives that occur to those skilled in the art upon reading this specification. [Explanation of symbols]

[0089] 1: Module 2: Detection module 3: Computation module 4: Actuation module 5: Gate driver voltage source 11: Semiconductor element 12: Control circuit section 21: Index 22: Index 31: Semiconductor element 32: Voltage source 33: Gate resistor CTRL: Control signal

Claims

1. 1. A method for treating a power semiconductor module comprising at least one semiconductor element including a metal oxide semiconductor element and / or a metal insulator semiconductor element, comprising: a. a first value V corresponding to an initial healthy state of the gate oxide of the power semiconductor module; ｓｏｈ，０ and b. A second value V corresponding to the current state of health of the gate oxide of the power semiconductor module. ｓｏｈ，Ｘ and c. On-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ and, The obtained first value V ｓｏｈ，０ and the second value V ｓｏｈ，Ｘ the turn-on delay time t ON or the turn-off delay time t OFF as a function of and estimating d. The estimated delay time t ＯＮ or t ＯＦＦ The on-state gate voltage V is estimated during ＣＣ or the off-state gate voltage V ＥＥ generating at least one control signal configured to apply to the power semiconductor module; Including, A method, wherein a criterion for estimating the turn-on delay time t ON or the turn-off delay time t OFF further depends on the on-state gate voltage V CC and / or the off-state gate voltage V EE .

2. The following preparatory actions: The at least one semiconductor element Zero or negative gate voltage V ＥＥ and the turn-off delay time t ＯＦＦ or switching from an on state to an off state according to a control logic signal involving Positive on-state gate voltage V ＣＣ and the turn-on delay time t ＯＮ switching from an off state to an on state in accordance with a control logic signal involving: The method of claim 1 further comprising:

3. The applied on-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ The method according to claim 1 or 2, wherein the sign of depends on the on / off state of the at least one semiconductor element.

4. The turn-on delay time t ＯＮ or the turn-off delay time t ＯＦＦ the obtained first value V ｓｏｈ，０ and the obtained second value V ｓｏｈ，Ｘ The criteria to estimate as a function of are: The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the turn-off delay time t ＯＦＦ is the turn-off delay time t ＯＦＦ is increased relative to its previous value, The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the turn-off delay time t ＯＦＦ is the turn-off delay time t ＯＦＦ is decreased relative to its previous value; 3. The method of claim 1 or 2, comprising:

5. The on-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ the obtained first value V ｓｏｈ，０ and the obtained second value V ｓｏｈ，Ｘ The criteria to estimate as a function of are: The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the on-state gate voltage V ＣＣ is the on-state gate voltage V ＣＣ , and the increase is ｓｏｈ，０ and the second value V ｓｏｈ，Ｘ be proportional to or equal to the difference between 3. The method of claim 1 or 2, comprising:

6. The on-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ the obtained first value V ｓｏｈ，０ and the obtained second value V ｓｏｈ，Ｘ The criteria to estimate as a function of are: The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the off-state gate voltage V ＥＥ is the off-state gate voltage V ＥＥ is decreased relative to its previous value; The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the off-state gate voltage V ＥＥ is the off-state gate voltage V ＥＥ is increased relative to its previous value, The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the off-state gate voltage V ＥＥ is the off-state gate voltage V ＥＥ remains equal to its previous value, and 3. The method of claim 1 or 2, comprising:

7. The on-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ the obtained first value V ｓｏｈ，０ and the obtained second value V ｓｏｈ，Ｘ The criteria to estimate as a function of are: The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the off-state gate voltage V ＥＥ is the off-state gate voltage V ＥＥ is decreased relative to its previous value; The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the on-state gate voltage V ＣＣ is the on-state gate voltage V ＣＣ is increased relative to its previous value, The obtained second value V ｓｏｈ，Ｘ The first value V ｓｏｈ，０ If the on-state gate voltage V ＣＣ and the off-state gate voltage V ＥＥ are reinitialized to their default values, and 3. The method of claim 1 or 2, comprising:

8. The following operations: When reverse conduction of the semiconductor device is detected, the estimated on-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ generating at least one control signal configured to apply to the power semiconductor module; The method of claim 1 or 2, further comprising:

9. Part of the method includes determining a second value V ｓｏｈ，Ｘ＋１ 3. The method according to claim 1, wherein a series of operations b to d are repeated at least once starting from the second acquisition of the first signal.

10. At least two second values ​​V ｓｏｈ，Ｘ and V ｓｏｈ，Ｘ＋１ is obtained during operation of the power semiconductor module, and the on-state gate voltage V ＣＣ or the off-state gate voltage V ＥＥ the obtained first value V ｓｏｈ，０ and the second value V ｓｏｈ，Ｘ and V ｓｏｈ，Ｘ＋１ The criteria to estimate as a function of and are: The time derivative dV of the obtained second value ｓｏｈ，Ｘ When / dt is positive, the on-state gate voltage V ＣＣ is the on-state gate voltage V ＣＣ and / or the off-state gate voltage V ＥＥ is the off-state gate voltage V ＥＥ is decreased relative to its previous value; The time derivative dV of the obtained second value ｓｏｈ，Ｘ When / dt is negative, the on-state gate voltage V ＣＣ is the on-state gate voltage V ＣＣ and / or the off-state gate voltage V ＥＥ is the off-state gate voltage V ＥＥ is increased relative to its previous value, 10. The method of claim 9, comprising:

11. 3. A power semiconductor module comprising a single metal oxide semiconductor element, a set of metal oxide semiconductor elements, a single metal insulator semiconductor element, or a set of metal insulator semiconductor elements, the power semiconductor module being configured to perform the method of claim 1 or 2.

12. Computer software comprising instructions for carrying out the method of claim 1 or 2 when said computer software is executed by a processor.

13. A computer-readable non-transitory recording medium having stored thereon software that, when executed by a processor, performs the method of claim 1 or 2.

Images