Semiconductor manufacturing equipment and semiconductor manufacturing method

Abstract

A semiconductor manufacturing apparatus and a semiconductor manufacturing method are provided that can improve the bonding strength between materials by controlling a natural oxide film formed on the surface of a semiconductor material during the transport process of the semiconductor material. [Solution] This method includes a measurement process S1000 in which a first oxide film on the surface of semiconductor materials W1, W2 is measured; a stripping process S1300 in which the first oxide film is stripped and removed by isotropic etching or plasma etching based on the measurement results of the first oxide film; a transport process S1400 in which the semiconductor materials W1, W2 are transported in a predetermined environment; and a bonding process S1500 in which the semiconductor materials W1, W2 are plasma-treated to activate their surfaces, and then a high-vacuum state is created within a predetermined time period to polarize ions on the surfaces of the semiconductor materials W1, W2, and a high-frequency power source is applied to the semiconductor materials W1, W2, thereby removing the second oxide film formed on the surfaces of the semiconductor materials W1, W2 in the transport process S1400, and the ions move over the surfaces of the semiconductor materials W1, W2 to bond them.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor manufacturing apparatus and a semiconductor manufacturing method that include a bonding apparatus for bonding semiconductor materials together by, for example, radio frequency ion flow bonding (RF Ion Flow Bonding (RFIFB)) in a semiconductor manufacturing process. [Background technology]

[0002] Hybrid bonding, which is one type of conventional semiconductor manufacturing process, includes, for example, a plasma treatment step, a cleaning step, a drying step, and a bonding step.

[0003] In the plasma treatment process, for example, atmospheric pressure plasma or vacuum plasma is applied to the semiconductor wafer to activate the surface of the semiconductor wafer. In the cleaning process, for example, a cleaning liquid (pure water or chemical liquid) is dropped onto the semiconductor wafer while the semiconductor wafer is rotated around its central axis to clean the surface of the semiconductor wafer. In the drying process, for example, water droplets are scattered from the surface of the semiconductor wafer while the semiconductor wafer is rotated at high speed around its central axis. In the bonding process, for example, two upper and lower semiconductor wafers that have undergone the plasma treatment process and the drying process are placed face to face and bonded together using a bonding device.

[0004] In conventional bonding devices, semiconductor wafers are placed on planar stages arranged opposite each other, and the pair of opposing semiconductor wafers are bonded together by a surface activated bonding (SAB) method (hereinafter referred to as the "SAB method" as appropriate), which is a room-temperature bonding process.

[0005] Surface activated bonding is a method of bonding materials at low or normal temperatures by ionizing an inert gas such as argon to create an ion beam, and then irradiating the surfaces of the materials to be bonded with this ion beam or plasma, thereby removing any oxide film or contaminant layer present on the surfaces of the materials to be bonded and activating the surfaces.

[0006] In the SAB method, the entire surface of the semiconductor wafer is uniformly activated at one time, and when removing the oxide film, the surface of the semiconductor wafer is processed by sliding the semiconductor wafer or the ion beam source because the ion beam irradiation area is small.

[0007] However, the SAB method has the problem that the surface uniformity of the semiconducting wafer is poor, and the surface becomes rough in some parts of the semiconductor wafer, resulting in a decrease in the bonding strength between the semiconductor wafers. Also, there is a problem that particles and voids are generated by moving the semiconductor wafer or the beam during spot irradiation of the Ar ion beam.

[0008] Therefore, a semiconductor wafer bonding apparatus that can improve the bonding strength between wafers in a semiconductor manufacturing process with a simple configuration is known. The bonding apparatus bonds semiconductor wafers together in the semiconductor manufacturing process by, for example, radio frequency ion flow bonding (RF Ion Flow Bonding, (RFIFB)).

[0009] Specifically, this is a semiconductor wafer bonding device that performs plasma processing on semiconductor wafers to activate their surfaces, then creates a high vacuum within a specified time period to polarize ions on the surfaces of the semiconductor wafers, applies high-frequency power supplies of two different frequencies to each of the opposing semiconductor wafers to remove the oxide film formed on the surfaces of the semiconductor wafers, and the ions move over the surfaces of the semiconductor wafers to increase the bonding strength between the semiconductor wafers (see Patent Document 1 below). [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Patent No. 7645524 Summary of the Invention [Problem to be solved by the invention]

[0011] However, in the apparatus for joining semiconductor materials together by the above-mentioned high frequency ion flow bonding, controlling the oxide film formed on the surface of the semiconductor material becomes an issue in increasing the bonding strength between the semiconductor materials.

[0012] In view of the above, an object of the present invention is to provide a semiconductor manufacturing apparatus and a semiconductor manufacturing method that can improve the bonding strength between semiconductor materials in the semiconductor manufacturing process, for example, by controlling the natural oxide film formed on the surface of the semiconductor material during the semiconductor material transportation process. [Means for solving the problem]

[0013] A first invention is a semiconductor manufacturing apparatus using a semiconductor material bonding apparatus for bonding a pair of semiconductor materials, A first oxide film formed on the surface of the semiconductor material is measured, and based on the measurement results of the first oxide film, the first oxide film is peeled off and removed by isotropic etching with an etching solution or plasma etching, and the semiconductor material that has undergone a transport process in which it is transported in a high vacuum atmosphere, an inert atmosphere, or an atmospheric pressure atmosphere, The bonding device performs plasma processing to activate the surfaces of the semiconductor materials, polarizes ions on the surfaces of the semiconductor materials in a high vacuum within a predetermined time, and applies high-frequency power to the semiconductor materials to remove the second oxide film formed on the surfaces of the semiconductor materials during the transport process, and the ions move over the surfaces of the semiconductor materials to bond the semiconductor materials together.

[0014] It is preferable to optimize processing parameters that govern processing performance relating to the isotropic etching, the plasma etching, and the plasma processing based on the measurement results of the first oxide film.

[0015] If the measurement result of the first oxide film shows an abnormality, it is preferable to remove at least a part of the first oxide film on the surface of the semiconductor material to flatten it before peeling off the first oxide film.

[0016] After the semiconductor materials are bonded, it is preferable to inspect the bonding strength or porosity of the semiconductor materials.

[0017] If the bonding strength or porosity of the semiconductor material does not meet a predetermined standard, it is preferable to adjust the processing parameters.

[0018] The first oxide film is preferably measured at least at 13 selected points on the surface of the semiconductor material using a film thickness meter based on an X-ray fluorescence method.

[0019] In the plasma treatment of the bonding apparatus, it is preferable to monitor the emission spectrum in real time during plasma activation and obtain the concentration of active particles to detect the plasma activity.

[0020] In the inspection of the bonding strength or porosity of the semiconductor material, it is preferable to inspect the bonding interface of the semiconductor material using a scanning acoustic microscope and analyze the acoustic signals to quantitatively evaluate the bonding strength or porosity of the semiconductor material.

[0021] The processing parameters preferably include at least one element of an etching time or an etching solution concentration in the isotropic etching or the plasma etching, a gas flow rate or an applied output of the high frequency power source in the plasma processing, a bonding temperature or a bonding time of the semiconductor material, and a heat treatment temperature or a heat treatment time of the semiconductor material.

[0022] The predetermined time is preferably 0.1 to 10 seconds.

[0023] The semiconductor materials to be joined together are preferably held by an electrostatic chuck as parallel plate plasma electrodes.

[0024] The second invention includes a measuring step of measuring a first oxide film formed on a surface of a semiconductor material; a stripping step of stripping and removing the first oxide film by isotropic etching using an etching solution or plasma etching based on the measurement results of the first oxide film; a transport step of transporting the semiconductor material in a high vacuum atmosphere, an inert atmosphere, or an atmospheric pressure atmosphere; a bonding step in which, after subjecting the semiconductor material to plasma treatment to activate the surface, ions are polarized on the surface of the semiconductor material in a high vacuum within a predetermined time, and a high frequency power source is applied to the semiconductor material to remove the second oxide film formed on the surface of the semiconductor material in the transport step, and the ions move on the surface of the semiconductor material to bond the semiconductor materials together; It has.

[0025] The measuring step preferably includes an optimizing step of optimizing process parameters that govern process performance related to the isotropic etching, the plasma etching, and the plasma processing, based on the measurement results of the first oxide film.

[0026] If an abnormality is found in the measuring step, it is preferable to have a planarizing step of removing and planarizing at least a part of the first oxide film on the surface of the semiconductor material before the peeling step.

[0027] It is preferable to have an inspection step of inspecting the bonding strength or porosity of the semiconductor material after the bonding step.

[0028] It is preferable to have an adjustment step of adjusting the processing parameters if the inspection step determines that the bonding strength or porosity of the semiconductor material does not satisfy a predetermined standard.

[0029] In the measuring step, it is preferable to use a film thickness meter based on an X-ray fluorescence method and to select and measure at least 13 points on the surface of the semiconductor material.

[0030] In the bonding step, it is preferable to monitor the emission spectrum in real time during plasma activation and obtain the concentration of active particles to detect the plasma activity.

[0031] In the inspection step, it is preferable to inspect the bonding interface of the semiconductor material using a scanning acoustic microscope and analyze acoustic signals to quantitatively evaluate the bonding strength or porosity of the semiconductor material.

[0032] The processing parameters preferably include at least one element of an etching time or an etching solution concentration in the isotropic etching or the plasma etching, a gas flow rate or an applied output of the high frequency power source in the plasma processing, a bonding temperature or a bonding time of the semiconductor material, and a heat treatment temperature or a heat treatment time of the semiconductor material.

[0033] The predetermined time is preferably 0.1 to 10 seconds.

[0034] The semiconductor materials to be joined together are preferably held by an electrostatic chuck as parallel plate plasma electrodes. [Effects of the Invention]

[0035] According to the present invention, the bonding strength between semiconductor materials can be increased by controlling the natural oxide film formed on the surface of the semiconductor materials during the transportation process. [Brief explanation of the drawings]

[0036] [Figure 1] 1 is a configuration diagram of a semiconductor wafer bonding device constituting a semiconductor manufacturing apparatus according to an embodiment of the present invention; [Figure 2] 1 is a configuration diagram showing plasma processing and bonding processing by a semiconductor wafer bonding device that constitutes a semiconductor manufacturing apparatus according to an embodiment of the present invention. [Figure 3] 1A to 1C are process diagrams of plasma processing and bonding processing by a semiconductor wafer bonding device that constitutes one embodiment of the semiconductor manufacturing apparatus according to the present invention. [Figure 4] FIG. 1 is a flow diagram illustrating an example of a high-frequency ion flow bonding process. [Figure 5]1 is a plan view of a semiconductor manufacturing system in which a semiconductor wafer bonding device constituting a semiconductor manufacturing apparatus according to an embodiment of the present invention is assembled. [Figure 6] 1 is a side view of a semiconductor manufacturing system in which a semiconductor wafer bonding device constituting a semiconductor manufacturing apparatus according to an embodiment of the present invention is assembled. [Figure 7] FIG. 1 is a diagram illustrating the structure of a monopolar electrostatic chuck. [Figure 8] FIG. 1 is a diagram illustrating the structure of a bipolar electrostatic chuck. [Figure 9] FIG. 1 is a diagram illustrating a state in which semiconductor wafers are bonded together using a bipolar electrostatic chuck provided on a stage constituting a semiconductor wafer bonding apparatus. [Figure 10] 1 is a block diagram showing each part of a semiconductor manufacturing apparatus according to an embodiment of the present invention; [Figure 11] 1 is a flowchart showing a manufacturing process of a semiconductor manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0037] First, a semiconductor manufacturing apparatus and a semiconductor manufacturing method according to one embodiment of the present invention will be described. While the present invention utilizes semiconductor materials and relates to bonding between semiconductor materials, the semiconductor material may be, for example, a semiconductor wafer. An example of a semiconductor wafer is a Si wafer, but it may also be made of glass or the like. Furthermore, the semiconductor wafer is not limited to a semiconductor wafer, and any material suitable for semiconductors, such as ceramic, may be used. In the following embodiments, for convenience of explanation, a "semiconductor wafer" will be used as an example of a semiconductor material, but the present invention is not intended to be limited to a semiconductor wafer.

[0038] As shown in FIG. 10, a semiconductor manufacturing apparatus 300 according to one embodiment of the present invention includes, for example, a control unit 310, a measurement unit 320, a planarization unit 330, a peeling unit 340, a transport unit 350, a bonding unit 360, an inspection unit 370, and an adjustment unit 380.

[0039] The semiconductor manufacturing equipment 300 includes a semiconductor material bonding device 34, which uses a plasma chamber or a vacuum chamber to bond semiconductor materials together. The plasma chamber or vacuum chamber may also be called a bonding chamber, bonding chamber, bonding device, bonding device, or the like.

[0040] The plasma chamber or vacuum chamber may have a pair of holding parts arranged at positions facing each other on a stage, and while the semiconductor materials are adsorbed by the holding parts, plasma may be applied between the semiconductor materials and at least one of the holding parts may be moved, thereby making it possible to bond the opposing semiconductor materials to each other.

[0041] Here, before bonding the semiconductor materials facing each other, it is preferable to use a silicon electrode for one of the semiconductor materials and a semiconductor wafer as the semiconductor material for the other of the semiconductor materials, and after performing the plasma treatment a first time on the silicon electrode and the other semiconductor wafer, change the silicon electrode to a bonded wafer which is a semiconductor material, and perform the plasma treatment a second time on the bonded wafer and the semiconductor wafer.

[0042] Between the first plasma treatment and the second plasma treatment, an oxide film (second oxide film, native oxide film) formed on the surfaces of the semiconductor materials facing each other may be removed by supplying an etching gas.

[0043] The technical concept of the present invention described above is not limited to a semiconductor material bonding apparatus, but also applies to a semiconductor material bonding method having the same features as those described above.

[0044] The control unit 310 of the semiconductor manufacturing equipment 300 controls each unit. The measurement unit 320 performs a measurement step S1000, which will be described later. The planarization unit 330 performs a planarization step S1200, which will be described later. The peeling unit 340 performs a peeling step S1300, which will be described later. The transport unit 350 performs a transport step S1400, which will be described later. The bonding unit 360 performs a bonding step S1500, which will be described later. The inspection unit 370 performs an inspection step S1600, which will be described later. The adjustment unit 380 performs an adjustment step S1800, which will be described later.

[0045] [Technical concept of the present invention] The technical idea of ​​the present invention is a semiconductor manufacturing apparatus or method using a semiconductor material bonding device that uses RF high-frequency ion flow and Coulomb force (also called "electrostatic force"; the same applies hereinafter) in a vacuum environment (or plasma environment) inside a vacuum chamber that performs plasma processing on semiconductor materials to bond a pair of opposing semiconductor materials together, thereby increasing the bonding strength between them, and includes the following semiconductor manufacturing process.

[0046] Specifically, as shown in FIG. 11, the semiconductor manufacturing process of this embodiment includes, for example, the following steps. A measuring step S1000 measures a first oxide film formed on the surface of a semiconductor material. If there is an abnormality in the measuring step S1000 (S1100: Y), a planarizing step S1200 is performed to remove and planarize at least a part of the first oxide film on the surface of the semiconductor material before proceeding to the peeling step S1300. If no abnormality is found in the measuring step S1000 (S1100: N), the first oxide film is stripped and removed by isotropic etching with an etching solution or plasma etching based on the measurement result of the first oxide film in the stripping step S1300. A transport step S1400 transports the semiconductor material in a high vacuum atmosphere, an inert atmosphere, or an atmospheric pressure atmosphere. After the semiconductor materials are subjected to plasma treatment to activate their surfaces, ions are polarized on the surfaces of the semiconductor materials in a high vacuum state or plasma environment within a predetermined time, and two different frequencies from the high-frequency power supplies 110 are applied to each of the opposing semiconductor materials, thereby removing the second oxide film formed on the surfaces of the semiconductor materials in the transporting step S1400, and the ions move on the surfaces of the semiconductor materials to bond the semiconductor materials together in the bonding step S1500. After the bonding step S1500, there is an inspection step S1600 in which the bonding strength or porosity of the semiconductor material is inspected. If the bonding strength or porosity of the semiconductor material does not meet the predetermined standard in the inspection step S1600 (S1700: N), the adjustment step S1800 adjusts the process parameters that govern the processing performance of the peeling step S1300 or the bonding step S1500.

[0047] [Measurement process] In the measuring step S1000, a first oxide film formed in advance on the surfaces of the pair of semiconductor materials is measured.

[0048] Here, the first oxide film is preferably measured using a film thickness gauge based on X-ray fluorescence, selecting at least 13 points on the surface of the semiconductor material. X-rays reaching the underlying semiconductor material are irradiated with fluorescent X-rays, which are then fractionated and analyzed to measure the thickness of films and coatings. Specifically, when X-rays are irradiated onto a substance (atoms), electrons within the substance are repelled by the energy of the X-rays and ejected from the substance. Empty electron spaces are created within the substance, and the atoms enter an unstable excited state, attracting outer electrons. This releases energy as X-rays (fluorescent X-rays). By measuring the wavelength and energy of these fluorescent X-rays, it is possible to detect and measure the type of atoms and the plating thickness of the substance. During fluorescent X-ray detection and fractionation, the thicker the film, the stronger the detection intensity of the film components and the weaker the detection intensity of the underlying components. The measurement system is automated, allowing the operator to set the measurement conditions and measurement position, allowing for accurate and rapid film thickness inspection.

[0049] The measurement step S1000 includes an optimization step for optimizing process parameters that control the process performance of the subsequent stripping step S1300 or bonding step S1500 based on the measurement results of the first oxide film. Hereinafter, the isotropic etching and plasma etching of the subsequent stripping step S1300 and the plasma processing of the bonding step S1500, which will be described later, are performed based on the optimized process parameters. The optimized process parameters are preferably set by the control unit 310 that controls each unit of the semiconductor manufacturing equipment 300, but are not limited to this.

[0050] Here, the processing parameters indicate the processing functions of each part of the semiconductor manufacturing equipment 300, and include at least one element of the etching time in isotropic etching or plasma etching, the concentration of the etching solution, the gas flow rate in plasma processing, the applied output of the high frequency power supply 110, the bonding temperature or bonding time of the semiconductor materials, and the heat treatment temperature or heat treatment time of the semiconductor materials.

[0051] [Flattening process] If there is an abnormality in the measuring step S1000 (S1100: Y), in other words, if the surface condition of the semiconductor material is poor (the first oxide film is thick), the process does not proceed to the peeling step S1300, but instead performs the planarizing step S1200.

[0052] In the planarization step S1200, at least a portion (e.g., thickness in the film thickness direction) of the first oxide film formed on the surface of the semiconductor material is removed by chemical mechanical polishing (CMP) (a technique for polishing and planarizing the surface of the semiconductor material using chemicals containing abrasives and a grindstone) as a pre-process, thereby planarizing the surface. For example, the semiconductor material is held by a member called a carrier, and the semiconductor material is brought into contact with and rotated on a polishing pad while a slurry containing chemicals and abrasive grains is flowed, thereby polishing the surface of the semiconductor material flat.

[0053] CMP uses a slurry containing chemicals and abrasive grains to polish using chemical and mechanical actions. Chemical action By modifying and dissolving the polishing surface with chemicals, it assists mechanical polishing with abrasive grains. Mechanical action The surface of the semiconductor material is polished by the physical action of the abrasive particles contained in the slurry.

[0054] After the planarization step S1200 is completed, the process proceeds to the measurement step S1000 again, where the first oxide film formed on the surface of the semiconductor material is measured. If the measurement result of the first oxide film shows no abnormalities (S1100: N), the process proceeds to the stripping step S1300. If the measurement result of the first oxide film shows abnormalities (S1100: Y), the planarization step S1200 is repeated until the abnormalities are eliminated.

[0055] [Peeling process] In the peeling step S1300, isotropic etching or plasma etching is performed on the semiconductor material using an etching solution, using processing parameters optimized based on the measurement results of the first oxide film formed on the surface of the semiconductor material, to peel off and remove the first oxide film.

[0056] Isotropic etching is a wet etching method in which the surface of a semiconductor material is cleaned with at least one etching solution. The cleaning is preferably, but not limited to, hydrofluoric acid cleaning using hydrofluoric acid (HF). After cleaning with the etching solution, the surface of the semiconductor material is preferably washed with pure water.

[0057] Plasma etching uses gases in a plasma state in a vacuum chamber to remove the first oxide layer on the surface of semiconductor materials. Plasma etching is a processing technique in which gases are turned into a plasma and their active particles are used to remove material.

[0058] [Transportation process] In the transport step S1400, the semiconductor material is transported in a high vacuum atmosphere, an inert atmosphere, or an atmospheric pressure atmosphere. -1 Less than Pa or 10 -6"Inert atmosphere" refers to an environment with a pressure of 100 Pa or higher. "Inert atmosphere" refers to an environment purged with inert gas (N2 (nitrogen), Ar (argon)). "Atmospheric pressure atmosphere" refers to an atmospheric pressure environment in which the semiconductor material is exposed to air. This allows the thickness of the second oxide film (native oxide film, thin film) formed on the surface of the semiconductor material to be controlled to a predetermined thickness or less during the process of transporting the semiconductor material in a high vacuum atmosphere or inert atmosphere. Furthermore, during the process of transporting the semiconductor material in an atmospheric pressure atmosphere, a second oxide film (native oxide film, thin film) with a predetermined thickness is formed on the surface of the semiconductor material, but the second oxide film (native oxide film, thin film) can be removed as described below.

[0059] [Joining process] In the bonding process S1500, gas is introduced into a vacuum device, vacuum chamber, or plasma chamber, and the semiconductor material is subjected to plasma treatment to activate the surface. Thereafter, ions are polarized on the surface of the semiconductor material in a high vacuum state within a predetermined time period, and high-frequency power supplies 110 of two different frequencies are applied to each of the opposing semiconductor materials, thereby removing the second oxide film (native oxide film, thin film) formed on the surface of the semiconductor material in the transport process S1400, and the ions move on the surface of the semiconductor material to bond the semiconductor materials together.

[0060] The bonding step S1500 is performed by a bonding device 34 that bonds semiconductor materials together by radio frequency ion flow bonding (RF Ion Flow Bonding (RFIFB)), and the details of the bonding device 34 will be described later. The bonding device 34 has the function of the bonding unit 360 and performs the bonding step S1500.

[0061] [Inspection process] In the inspection step S1600, after the bonding step S1500, the bonding strength or porosity of the semiconductor materials is inspected. For example, it is preferable to inspect the bonding interface of the semiconductor materials using a scanning acoustic microscope and analyze the acoustic signals to quantitatively evaluate the bonding strength or porosity of the semiconductor materials. By quantitatively evaluating the bonding strength or porosity of the semiconductor materials, the bonding accuracy of the semiconductor materials can be confirmed.

[0062] In the bonding step S1500, it is preferable to monitor the emission spectrum in real time during plasma activation and obtain the active particle concentration to detect the plasma activity. By detecting the plasma activity, the accuracy of the plasma processing can be confirmed.

[0063] In the bonding step S1500, the bonding surfaces of at least two semiconductor materials facing each other are brought into close contact with each other and bonded together. The bonding temperature at this time is preferably room temperature (for example, 0 to 35°C) or 100 to 200°C.

[0064] It is preferable to heat treat the semiconductor materials that have been bonded together. Heat treatment methods include batch, single-wafer RTA, and laser annealing. Batch method is a method in which multiple semiconductor materials are heat treated simultaneously at once, in which the semiconductor materials are placed in a quartz furnace tube and heated from the outside by a heater. Single-wafer RTA is a method in which semiconductor materials are heated one by one at high speed using an infrared lamp. Laser annealing is a method in which only the surface of the semiconductor material is heat treated by irradiating it with an ultraviolet laser.

[0065] [Adjustment process] In the adjusting step S1800, if the quantitative evaluation of the bonding strength or porosity of the semiconductor material in the inspecting step S1600 does not satisfy a predetermined standard (S1700:N), the process parameters that govern the processing performance of the peeling step S1300 or the bonding step S1500 are adjusted. Specifically, the optimized process parameters are adjusted. The adjusted process parameters are stored in, for example, the control unit 310. It is preferable that the output of each unit constituting the semiconductor manufacturing apparatus 300 in FIG. 10 is feedback-controlled based on the adjusted process parameters.

[0066] As described above, the semiconductor manufacturing apparatus and method of this embodiment provide an improved bonding process that combines wet etching and plasma activation. Through the steps of measuring the oxide film thickness of the semiconductor material, wet etching or plasma etching, plasma activation, bonding, interface inspection of the semiconductor material, and feedback control of processing parameters, it is possible to simultaneously remove contaminants from the surface of the semiconductor material and activate the surface, thereby improving process stability and reproducibility.

[0067] The bonding method using a combination of wet etching and plasma activation according to this embodiment has the following beneficial effects. 1. Highly efficient removal of oxide layers and contaminants from material surfaces while improving surface activity. 2. Wet etching removes contaminants and oxide layers through selective reactions, preserving active groups (such as amino groups) to enhance bonding strength. 3. Plasma activation increases the density of hydroxyl groups on the surface, promoting the diffusion of water molecules and enabling low-temperature bonding, thereby reducing material deformation and damage caused by thermal stress and heat. 4. By measuring oxide film thickness, bond strength, and porosity, and adjusting process parameters through feedback, we ensure consistent and repeatable quality. 5. It achieves an interface with high bonding strength and low defect rate, and can withstand post-processing such as polishing and CMP, making it applicable to bonding a wide range of materials, including Si, quartz glass, SiC, and Cu.

[0068] The bonding apparatus used in the semiconductor manufacturing apparatus and semiconductor manufacturing method of this embodiment will be described in detail below. The bonding apparatus 34 bonds semiconductor materials together by, for example, radio frequency ion flow bonding (RF Ion Flow Bonding (RFIFB)). In the following description, a semiconductor wafer will be used as an example of the semiconductor material.

[0069] The semiconductor material that has undergone the measuring step S1000, the planarizing step S1200, the peeling step S1300, and the transporting step S1400 is loaded into the bonding device 34. In the semiconductor material bonding device 34, at least the bonding step S1500 is performed.

[0070] [Configuration of semiconductor wafer bonding equipment] As shown in Fig. 1, the semiconductor wafer bonding apparatus 34 of this embodiment bonds various types of wafers together. The semiconductor wafer and bonded wafer may be, for example, a silicon wafer, but is not limited to a silicon wafer. It is also possible to use semiconductor wafers made of different materials that have been conventionally used, or to bond semiconductor wafers made of different materials together.

[0071] 1, a semiconductor wafer bonding apparatus 34 has a chamber 14 as a housing, a first stage 36 located on the upper side inside the chamber, and a second stage 38 located on the lower side inside the chamber. A first holder 102 capable of holding a semiconductor wafer or an electrode (e.g., a silicon electrode) is arranged on the first stage 36. A second holder 104 capable of holding a semiconductor wafer or an electrode (e.g., a silicon electrode) is arranged on the second stage 38.

[0072] The chamber 14 or the bonding device 34, which is a housing, can also be called a "vacuum chamber."

[0073] Here, for example, an electrostatic chuck or a mechanical clamp is used for the first stage 36 and the second stage 38, or the first holding unit 102 and the second holding unit 104. Note that the electrostatic chuck may be, for example, the electrostatic chuck shown in electrostatic chucks 78 and 80 (FIGS. 7 to 9). The configurations of the electrostatic chucks 78 and 80 shown in FIGS. 7 to 9 will be described later.

[0074] 2, a first holding part 102 and a first replacement device 106 for replacing the semiconductor wafer W1 or silicon electrode G1 held by the first holding part 102 with a semiconductor wafer or silicon electrode held by another holding part are disposed on or near the first stage 36, which is on the upstream side in the direction of gravity. 1and the first holding part 102 that holds the silicon electrode G1 form a set, and it is preferable that the semiconductor wafer W1 and the first holding part 102 that holds the semiconductor wafer W1 be replaced as a set, but this is not limited to this embodiment.

[0075] The silicon electrode G1 is a known material, and is also called, for example, a dummy wafer or a bare wafer.

[0076] The semiconductor wafer W1 held by the first holding part 102 has, for example, silicon In addition to the electrode G1, it also includes the bonded wafer G2 and the like.

[0077] The first replacement device 106 is not limited to being provided on the first stage 36 side, but may be provided as another component of the bonding device 34 or outside the bonding device 34 .

[0078] In addition, a second holding portion is provided on the second stage 38 or in the vicinity thereof, which is downstream in the direction of gravity. 104 and the second holding portion 104 A second replacement device 108 may be provided for replacing the semiconductor wafer W2 or silicon electrode held by the second holder 104 with a semiconductor wafer W2 or silicon electrode held by another holder. In the step of replacing the silicon electrode (not shown) and the semiconductor wafer W2, the silicon electrode (not shown) and the second holder 104 that holds the silicon electrode (not shown) are preferably replaced as a set, with the semiconductor wafer W2 and the second holder 104 that holds the semiconductor wafer W2 being replaced as a set, but the present invention is not limited to this embodiment.

[0079] The second replacement device 108 is not limited to being provided on the second stage 38 side, but may be provided as another component of the bonding device 34 or outside the bonding device 34 .

[0080] It is preferable that at least one of the first replacement device 106 and the second replacement device 108 is provided.

[0081] Here, for example, robot hands are used as the first replacement device 106 and the second replacement device 108, but the present invention is not limited to this.

[0082] The semiconductor wafer W1 held by the first holding part 102 and the semiconductor wafer W2 held by the second holding part 104 are exemplified by, but not limited to, a Si wafer or a SiC wafer.

[0083] 1, a radio frequency power supply 110 is connected to each of the first stage 36 and the second stage 38. The radio frequency power supply 110 has the ability to generate a radio frequency electric field (13.56 MHz, 200 W). When the radio frequency power supply 110 is applied, the electric field promotes the flow and diffusion of atoms, improving the adhesion of the bonding surfaces of the semiconductor wafers W1 and W2.

[0084] In this embodiment or example, a configuration is used in which the high-frequency power supplies 110 are connected to the first stage 36 and the second stage 38, respectively, and it is assumed that a high-frequency voltage is applied to both the semiconductor wafer W1 held on the first stage 36 side and the semiconductor wafer W2 held on the second stage 38 side. However, in a configuration in which the high-frequency power supplies 110 are connected to the first stage 36 and the second stage 38, respectively, a high-frequency voltage may be applied to only one of the semiconductor wafers. In this case, however, the high-frequency power supply 110 may be installed on only one of the first stage 36 or the second stage 38.

[0085] The semiconductor wafer bonding apparatus 34 is provided with an automatic pressure control device 112 (APC) that can control the pressure inside the housing. The automatic pressure control device 112 controls the pressure inside the housing.

[0086] The semiconductor wafer bonding device 34 is provided with a turbo molecular pump (TMP) 114. The turbo molecular pump 114 is composed of, for example, a rotor (moving blades) with turbine-type blades and a stator (fixed blades).

[0087] Turbomolecular pump 114 is 1 x 10 -6 It is a high-performance pump with a high vacuum and high pumping speed of 100 Pa.

[0088] [Effects of semiconductor wafer bonding equipment] The bonding between the wafers becomes stronger. When bonding semiconductor wafers that require different plasma treatment times, the plasma treatment time can be shortened by using the semiconductor wafer that requires a shorter plasma treatment time as the bonded wafer and replacing it with a silicon electrode. This allows for shorter plasma treatment of the bonded wafer. As a result, the surface of the bonded wafer does not deteriorate due to prolonged plasma treatment, and deterioration in the quality of the semiconductor product (semiconductor device, etc.) formed by bonding the wafers can be prevented.

[0089] [First plasma treatment run] As shown in FIGS. 1 and 2, a semiconductor wafer bonding apparatus 34 has a parallel plate electrode structure. The inside of the housing is evacuated, a silicon electrode G1 (also referred to as a "silicon wafer electrode") is held by a first holder 102, and a semiconductor wafer W2 (e.g., a silicon wafer) is held by a second holder 104. A first plasma treatment is then performed using argon plasma or the like. As a result, silicon is sputtered from the silicon electrode G1 using argon plasma inside the vacuum chamber 14, and the surface of the semiconductor wafer W2 held by the second holder 104 is activated by the plasma, forming a silicon deposition film X on the surface of the semiconductor wafer W2. The surface activation of the semiconductor wafer W2 using plasma uses a gas such as argon (Ar) or nitrogen (N), and removes oxide films (second oxide films, native oxide films) and contaminants from the surface of the semiconductor wafer W2. The second plasma treatment also has a similar effect.

[0090] Here, since the high frequency power supply 110 is used, the energy is small, and plasma damage to the surface of the semiconductor wafer W2 is small. silicon A thin vapor-deposited film X is formed on the electrode G1 by sputtering.

[0091] The first plasma treatment may be omitted (the same applies to the following embodiments and examples). In other words, without using an upper silicon electrode (semiconductor wafer), the upper and lower semiconductor wafers may be directly set, and plasma may be generated by applying a high-frequency power supply in the first step, and the upper and lower semiconductor wafers may be bonded together. In particular, if the oxide film on the semiconductor wafer is removed in advance by wet etching before being placed in the apparatus, the oxide film can be removed by a single plasma treatment without dividing it into two steps.

[0092] [Isotropic etching] Between the first plasma treatment and the second plasma treatment described below, an isotropic etching step may be performed to remove an oxide film formed on the surface of the semiconductor wafer W2 by supplying an etching gas such as SF6. After the isotropic etching step, the plasma gas is switched to argon gas (gas replacement), and the wafer surface is activated in the second plasma treatment.

[0093] [Second plasma treatment run] Next, the silicon electrode G1 is replaced with a bonded wafer G2, which is a semiconductor wafer W1. The bonded wafer G2 is, for example, a semiconductor wafer such as a silicon wafer, but is not limited to silicon. G2 The replacement step is performed, for example, by replacing a set of parts including the silicon electrode G1 and the first holding part 102 that holds the silicon electrode G1 with another set of parts including the bonded wafer G2 and the first holding part 102 that holds the bonded wafer G2. Alternatively, the first holding part 102 may be used in common as is, and after only the silicon electrode G1 is separated from the first holding part 102, the bonded wafer G2 may be held by the first holding part 102. During and after the replacement step, plasma processing is performed, and the surfaces of the bonded wafer G2 held by the first holding part 102 and the semiconductor wafer W2 held by the second holding part 104 are activated using a gas such as argon (Ar) or nitrogen (N). The oxide film (second oxide film, natural oxide film) and contaminants are removed from the surface of each of the bonded wafer G2 held by the first holding part 102 and the semiconductor wafer W2 held by the second holding part 104. Then, in an environment where the application of the high frequency power supply 110 continues, the supply of gas such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven at high output, and the degree of vacuum inside the chamber 14 reaches the ultimate vacuum (for example, 1×10) in, for example, about 10 seconds. -6At this time, the plasma is extinguished, but ions remain polarized on the surfaces of the bonded wafer G2 held by the first holding part 102 and the semiconductor wafer W2 held by the second holding part 104.

[0094] The time required for the interior of chamber 14 to reach the ultimate vacuum level is not limited to approximately 10 seconds, and may be set within the range of, for example, 1 to 10 seconds. The shorter the time required for the interior of chamber 14 to reach the ultimate vacuum level, the better.

[0095] Here, the time required for the interior of the chamber 14 to reach the ultimate vacuum may be set appropriately within a range of 0.1 to 30 seconds, such as 0.1 to 10 seconds.

[0096] [Wafer-to-wafer bonding process] In this state, for example, as shown in Figure 3, by moving the first stage 36 and / or the second stage 38 closer to each other, the separation distance between the bonded wafer G2 held by the first holder 102 and the semiconductor wafer W2 held by the second holder 104 is reduced, and the interatomic distance between the wafers is reduced due to the Coulomb force (electrostatic force) generated on the surfaces of both wafers, and they eventually come into contact. At this time, the first stage 36 may be fixed, and the second stage 38 may be moved closer to the first stage 36 side. Alternatively, the second stage 38 may be fixed, and the first stage 36 may be moved closer to the second stage 38 side. The initial bonding force between the bonded wafer G2 held by the first holding part 102 and the semiconductor wafer W2 held by the second holding part 104 becomes strong, but by continuing to apply the high frequency power supply 110 even after the opposing wafers G2 and W2 come into contact with each other, RF high frequency waves flow between the surfaces of the respective wafers G2 and W2, and ion flow (atomic diffusion) occurs due to the electric field, thereby making the bonding between the two even stronger.

[0097] Here, the time from when the ultimate vacuum is reached inside the chamber 14 until the immediate bonding process after the plasma is stopped is preferably in the range of 0.1 to 30 seconds. It may be more preferably set in the range of 0.1 to 10 seconds. Here, 0.1 to 10 seconds means that the semiconductor wafers are bonded together while the plasma is applied and during the process of creating a high vacuum. This includes bonding the semiconductor wafers together while the plasma is maintained.

[0098] Furthermore, the total time taken for the ultimate vacuum level to be reached inside the chamber 14 and the time taken from the ultimate vacuum level being reached until the semiconductor wafers are bonded together may be set within a range of 0.1 seconds to 30 seconds, for example, 0.1 seconds to 10 seconds.

[0099] The semiconductor wafer manufacturing method according to this embodiment is the first of its kind in the industry, and is called RF Ion Flow Bonding (RFIFB).

[0100] It should be noted that the plasma treatment is performed only once on the bonded wafer G2 held by the first holding part 102, whereas the plasma treatment is performed only twice on the semiconductor wafer W2 held by the second holding part 104.

[0101] Furthermore, a preferred configuration is to replace the first holding part 102 and the silicon electrode G1 held by the first holding part 102 with another first holding part 102 and the bonded wafer G2 held by the first holding part 102, and then bond the bonded wafer G2 held by the first holding part 102 to the semiconductor wafer W2 held by the second holding part 104, but this is not limitative. Furthermore, it is preferred that the first holding part 102 be located upstream (upper side) in the direction of gravity, and the second holding part 104 be located downstream (lower side) in the direction of gravity.

[0102] On the other hand, there is a conventional technology called atomic diffusion bonding (ADB). Atomic diffusion bonding is a technology called room temperature activation bonding, and is known to involve activating the surface of a semiconductor wafer with an Ar beam or by activating the surface of a semiconductor wafer with Si sputtering. However, in either case, it takes several minutes to bond activated semiconductor wafers together.

[0103] Generally, the activated state of the semiconductor wafer surface deteriorates in a short time, so quick evacuation and bonding are required.

[0104] Therefore, according to this embodiment, after activating the wafer surfaces by plasma treatment, the turbo molecular pump 114 is used to evacuate the wafers to the ultimate pressure within, for example, about 10 seconds, and the wafers are then bonded together, thereby enabling atomic diffusion bonding with minimal surface activation decay after wafer surface activation.

[0105] That is, this embodiment uses, for example, parallel flat-plate plasma electrodes in the upper and lower directions, a structure (for example, an electrostatic chuck, a mechanical clamp, etc.) that can hold a wafer on the upper and lower electrodes, and one of the electrodes is designed to be replaceable with a bonded wafer.

[0106] According to this embodiment, roughening of the electrode surface due to sputtering of the silicon electrode G1 causes particles to appear in the parallel-plate wafer plasma, resulting in the formation of voids. The sputtering roughens the surface of the silicon electrode G1, and the re-sputtered silicon grows and peels off from the surface of the silicon electrode G1. The peeled-off silicon continues to float as particles due to Brownian motion, causing void defects in the wafer. However, in this embodiment, the silicon electrode G1 (e.g., a Si bare wafer) is used instead of the bonded wafer G2 in the early stages, thereby reducing damage to the bonded wafer G2 due to voids. This prevents quality degradation and deterioration of the semiconductor product obtained by bonding the bonded wafer G2 and the semiconductor wafer W2. It is preferable to periodically replace the silicon electrode G1 after each or multiple bonding operations.

[0107] As described above, the way to be used on one or both sides of the parallel flat plates Ha's By surface activation and soft sputtering due to application of a high frequency power supply 110 to the silicon electrode G1, a vapor deposition film X, which is an extremely thin high purity Si film, is formed on the processing surface of the semiconductor wafer W2 facing the silicon electrode G1.

[0108] In the plasma environment, the surface of the semiconductor wafer W2 is bombarded with ions to expose a clean surface. After the surface of the semiconductor wafer W2 is cleaned, a high-frequency power supply 110 with a different frequency is applied to a silicon electrode G1 (e.g., a silicon wafer) located at the upper (upper) side. As a result, minute Si particles fly out from the silicon electrode G1 and accumulate on the surface of the semiconductor wafer W2 located at the lower (lower) side, forming a vapor-deposited film X, which is a thin film formed by vapor deposition.

[0109] If a thin film formed by vapor deposition is not required, this step can be omitted.

[0110] Next, in bonding the bonded wafer G2 and the semiconductor wafer W2, the surface of the bonded wafer G2 is activated using a gas such as argon (Ar) or nitrogen (N2) while the bonded wafer G2 is set on, for example, an upper (upper) electrode. At this time, the surface of the semiconductor wafer W2 placed below (below) is also activated. For these reasons, surface activation of the bonded wafer G2 is performed only once, and surface activation of the semiconductor wafer W2 is performed only twice.

[0111] Inside the chamber 14, which is a single housing, the surfaces of the two wafers (bonded wafer G2 and semiconductor wafer W2) are activated at a pressure that allows plasma to be applied between the opposing electrodes and that allows plasma to be maintained at as high a vacuum as possible. The electrode structure may be configured with an additional magnetron, ICP coil, etc., to enable plasma to be maintained at a high vacuum.

[0112] Furthermore, after plasma surface activation is completed, the distance between the bonded wafer G2 arranged on the upper side and the semiconductor wafer W2 arranged on the lower side is preferably narrow. Furthermore, the distance between the silicon electrode G1 arranged on the upper side and the semiconductor wafer W2 arranged on the lower side is preferably narrow. For example, the distance may be the minimum distance between the electrodes that allows plasma to be uniformly applied during plasma processing, and may be in the range of 10 μm to 50 μm when the pressure is changed to a high vacuum after completion of plasma processing. This is because narrowing the distance makes it difficult for particles and the like to infiltrate between the electrodes from the outside, preventing particles from being mixed in during the wafer bonding process and shortening the time from reaching vacuum to bonding.

[0113] After the surfaces of the bonded wafer G2 and the semiconductor wafer W2 have been activated by plasma processing, the supply of gas such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven and controlled so that the vacuum pressure reached by the turbomolecular pump 114 (or cryopump) is reached within, for example, about 10 seconds. At this time, the application of the high-frequency power supply 110 continues, but this is not limitative.

[0114] As a result, oxide films (second oxide films, native oxide films) formed on the wafer surfaces during processes such as the transfer of the bonded wafer G2 and the semiconductor wafer W2 are removed, and polarized ions (electrons) remain on the surfaces of the bonded wafer G2 and the semiconductor wafer W2. When the bonded wafer G2 and the semiconductor wafer W2 are bonded in a high vacuum, the ion potential on the surfaces of the bonded wafer G2 and the semiconductor wafer W2 increases atomic motion, making it easier for atoms to temporarily move on the surfaces of the bonded wafer G2 and the semiconductor wafer W2. Furthermore, application of the high-frequency power supply 110 after the bonding of the bonded wafer G2 and the semiconductor wafer W2 also increases atomic motion, making it easier for atoms to temporarily move on the surfaces of the bonded wafer G2 and the semiconductor wafer W2. These synergistic effects rearrange the atoms to a more stable energy state. In particular, when the surfaces of the bonded wafer G2 and the semiconductor wafer W2 are activated, atoms are more likely to be rearranged to more optimal positions. As a result, the energy of the surfaces of the bonded wafer G2 and the semiconductor wafer W2 is minimized, and the bonding strength between the bonded wafer G2 and the semiconductor wafer W2 is improved.

[0115] Generally, the time from the completion of plasma processing of semiconductor wafers to the bonding of the semiconductor wafers is several minutes, which includes the time it takes to transfer the semiconductor wafers from the plasma processing chamber to the bonding chamber, the plasma processing time for the second semiconductor wafer, and the transport time. During this time, the activity of the surface of the semiconductor wafer is attenuated and deteriorated by about 10 to 50% from immediately after plasma processing (attenuation rate 10 to 50%).

[0116] In contrast to this, in this embodiment, instantaneous bonding is performed immediately after the plasma treatment of the bonded wafer G2 and the semiconductor wafer W2, so that the bonded wafer G2 and the semiconductor wafer W2 are bonded together while the activated states of the respective surfaces of the bonded wafer G2 and the semiconductor wafer W2 are maintained at a decay rate of 1% or less. As a result, the bonding between the bonded wafer G2 and the semiconductor wafer W2 is strong.

[0117] [Void-less bonding] Most of the voids are flakes from Si sputtering and particles in the chamber. Frequent replacement of the silicon electrode G1 eliminates the flakes and particles formed by sputtering, reducing the number of voids. In addition, in the vacuum plasma, organic substances that act as seeds for forming voids between the bonded wafer G2 and the semiconductor wafer W2 are removed by the plasma. The plasma also prevents organic substances from penetrating between the wafers from the outside. These results enable void-less bonding.

[0118] [Features of RF ion flow bonding] High frequency ion flow bonding has the following features: (1) The surface of the wafer can be activated and cleaned by controlling the plasma treatment and instantaneous vacuum. (2) The initial bonding strength between wafers can be strengthened by utilizing Coulomb force (electrostatic force). (3) A high-frequency power source (RF high frequency) promotes the flow and diffusion of atoms, improving the bonding strength between wafers.

[0119] [High frequency ion flow bonding process flow] An example of the flow of the high frequency ion flow bonding process will be described. As shown in Figure 4, for example, wafers are removed from a wafer cassette (S100) and aligned (S200). The wafers are cleaned (S300) and transferred to a load lock chamber (S400). Plasma processing is performed on the wafers (S500) and the wafers are bonded together (S600). After that, a semiconductor product formed by bonding the wafers together is removed from the load lock chamber (S700), and the semiconductor product is inspected (S800). Here, the time required from the end of the plasma treatment step (S500) to the end of the bonding step (S600) is preferably, for example, 10 seconds or less. In the plasma treatment step (S500) for the wafer, an oxide film (second oxide film, native oxide film) formed on the surface of the wafer in the wafer transfer step (e.g., S400, etc.) is removed. As described above, for example, Coulomb force control assisted bonding using an ESC chuck can prevent misalignment of opposing wafers when they come into contact with each other, and high-frequency ion flow bonding technology can achieve high-strength bonding.

[0120] (Example) Next, an example of high frequency ion flow bonding will be described.

[0121] [Overview] (1) Two Si wafers are placed in a vacuum with a parallel plate electrode structure. (2) A replaceable silicon wafer electrode is used on one side, and the surface of the silicon wafer electrode is activated with argon plasma. (3) The silicon protruding from the surface of the silicon wafer electrode is deposited by sputtering on the surface of the semiconductor wafer facing the silicon wafer electrode.

[0122] [Process] (1) Surface activation using silicon wafer electrodes The surfaces of the silicon wafer electrode and the semiconductor wafer facing the silicon wafer electrode are activated by a plasma treatment (first time) using argon plasma, and silicon is sputtered from the silicon wafer electrode. The silicon wafer electrode is replaced with a bonded wafer that will serve as the bonding target. The bonded wafer and the semiconductor wafer are subjected to argon plasma treatment (second time), and after the gas supply is stopped, a turbo molecular pump or the like is used to achieve the ultimate vacuum within, for example, about 10 seconds. Although the plasma disappears when the vacuum is drawn, ions remain in a polarized state on the surfaces of the bonded wafer and the semiconductor wafer, which face each other. This removes the oxide film (second oxide film, natural oxide film) formed on the surface of the semiconductor wafer during the semiconductor wafer transfer process. (2) Wafer-to-wafer bonding Ions that are polarized and reside on the surfaces of the bonded wafer and the semiconductor wafer generate Coulomb force (electrostatic force), which shortens the interatomic distance between the wafers and brings them into contact. RF radio waves flow across the surface of each wafer, and an electric field causes ion flow (atomic diffusion) to occur, resulting in a strong bond between the wafers.

[0123] In bonding wafers, after applying plasma, the wafers can be bonded together by quickly creating a high vacuum state, but the wafers can also be bonded together while the plasma is still being applied (by drawing a vacuum while the plasma is excited). In other words, the wafers can be bonded together without changing the degree of vacuum to an area where plasma does not exist. In the case of parallel plate plasma, the area where plasma does not exist is generally about 1 Pa. In the case of magnetron or ICP plasma, it is about 1 x 10 -2 In the case of an argon ion beam, it is about 1×10 -6 That's about it.

[0124] [Specific structure] (1) Parallel plate plasma electrode structure (1-1) Wafer holding mechanism An electrostatic chuck or a mechanical clamp is used as each holding portion, and a structure is provided in which each wafer can be held by the upper electrode and the lower electrode. At least one of the upper and lower electrodes is designed to be replaceable with a bonded wafer. The replacement is preferably performed by a robot hand or the like. It is also preferable to replace the upper electrode with a bonded wafer. This can suppress the generation of particles due to roughness on the electrode surface. (1-2) Electrode sputtering The electrode is a silicon electrode made of a bare silicon wafer, which controls particles during the plasma process, thereby reducing voids during bonding of the bonded wafer and the semiconductor wafer. (1-3) Surface activation of one or both sides of the wafers facing each other Soft sputtering is performed by applying high-frequency power to each electrode, and silicon sputtered from the electrode accumulates on the surface of the opposing wafer, forming a thin, highly pure silicon film. Note that the process of forming a highly pure silicon film (silicon film) can be omitted if necessary. A high frequency power supply of a different frequency may be applied to the upper electrode to sputter Si (silicon).

[0125] (2) Setting the bonded wafers (2-1) Activation of the wafer surface using gas The surface of the wafer is activated using Ar (argon) or N2 (nitrogen) gas. Two wafers, one on top and one on the bottom, are simultaneously subjected to plasma processing in one chamber. (2-2) Plasma treatment Plasma processing is performed in a high vacuum. A magnetron or ICP coil can be used. The space between the electrodes is designed so that the plasma is uniform and is not subject to external influences such as the intrusion of dust from outside. The plasma treatment can remove the oxide film (second oxide film, natural oxide film) formed on the surface of the semiconductor wafer during the semiconductor wafer transfer process. (2-3) Evacuation after plasma treatment The supply of argon gas and nitrogen gas into the chamber is stopped, and the automatic pressure control device (APC) is driven, and the pressure inside the chamber is controlled to reach the ultimate vacuum pressure by the turbomolecular pump in, for example, about 10 seconds. Depending on the product, the application of high frequency power to the upper and lower electrodes may be continued or stopped. (2-4) Vacuum lamination (vacuum bonding) The wafers, each with a charged surface, are brought close together and brought into contact by Coulomb force (electrostatic force). The use of Coulomb force improves the initial bonding strength between the wafers. The use of Coulomb force also increases atomic movement, making it easier for atoms on the surface of each wafer to move. By applying a high frequency power source to each electrode, the atoms are rearranged into a stable energy state, forming a strong bond between the wafers.

[0126] (3) Instant bonding of wafers after plasma processing (instant bonding) By bonding the wafers, for example, in about 10 seconds after the surfaces of the wafers have been activated, it is possible to minimize deterioration of the activated state (activity level) of the wafer surfaces. In contrast, with conventional room-temperature activation bonding or atomic diffusion bonding, it takes time to bond wafers together. Specifically, if there is a wait time of several minutes, the activation state decreases by about 20%. This has caused a problem of deterioration in the quality of semiconductor wafer products, but this problem has been solved by the high-frequency ion flow bonding of this embodiment.

[0127] [In high vacuum (1×10 -6 Decay rate after surface activation in Pa (pascal) Decay rate after 10 seconds in a vacuum: A(10 seconds) ≒ 99.83% A(10 seconds) = 99.83% = 0.17% Decay rate Decay rate after 2 minutes in a vacuum: A(2 minutes) ≒ 81.87% A(2 minutes) = 81.87% = 18.13% Decay rate From the above, it has been found that rapid evacuation and bonding of the wafers together are extremely important for maintaining the surface activation state, and as a result, strong bonding between the wafers can be obtained.

[0128] Next, we analyze the diffusion of ions in the high-frequency ion flow bonding process, in which silicon wafers are subjected to plasma treatment in a vacuum to activate their surfaces, and then the gas is stopped and the wafers are bonded together at high speed in a vacuum while maintaining the surface activation state, and a high-frequency power supply is applied.

[0129] [High frequency ion flow bonding process] (1) Plasma surface activation Organic contaminants and oxides on the wafer surface are chemically removed by plasma etching using fluorine-based gases. Argon sputtering removes any remaining micro-contaminants and non-uniform chemical residues. Activation of the wafer surface and plasma etching removes the oxide film (secondary oxide film, native oxide film) on the wafer surface, cleaning it. At the same time, argon sputtering physically strikes the wafer surface, further activating the atoms on the wafer surface, improving the efficiency of bonding wafers together. The combined effect of cleaning and activating the wafer surface is to diffuse atoms, resulting in high bonding strength between the wafers.

[0130] (2) Gas stop and high-speed vacuuming After the plasma processing of the wafer, the supply of argon gas and nitrogen gas was stopped, and a turbo molecular pump was used to create a high vacuum (1×10 -6 Pa (Pascal) is controlled. The ultimate vacuum level is reached within approximately 10 seconds, and the activated state of the wafer surface is maintained.

[0131] (3) Wafer-to-wafer bonding The wafers are bonded together with the polarized ions remaining on the surface of each wafer. Coulomb force (electrostatic force) reduces the interatomic distance between the surfaces of the adjacent wafers, strengthening the contact between the wafers.

[0132] (4) Application of high-frequency power After the wafers are bonded together, a high frequency power source is applied to generate an electric field on the surface of each wafer. The electric field causes ions on the wafer surface to flow, strengthening the bonds between atoms.

[0133] [Considerations of ion diffusion] (1) Ion state on the wafer surface Due to activation by the plasma treatment, the ions remaining on the wafer surface become polarized. The polarized ions are strongly adsorbed to the wafer surface, facilitating the movement of the ions. In a high vacuum, the electrodes are insulated from each other, and the ions do not ionize (discharge) but remain on the wafer surface.

[0134] (2) High vacuum state In a high vacuum, the activated state of the wafer surface is maintained, and recontamination of the wafer surface is suppressed.

[0135] (3) Effect of high frequency power supply The high frequency electric field (13.56 MHz, 200 W) has the following effects on the wafer surface and interface. (3-1) Fluctuation of surface potential The high frequency electric field generates an alternating electric field on the wafer surface, which causes the potential on the wafer surface to fluctuate, resulting in the following effects: Surface potential fluctuation: A potential of ±200V fluctuates at 13.56MHz, causing the movement of electrons and ions on the wafer surface. Effect of high frequency electric field: A high frequency electric field (alternating electric field) rearranges atoms and ions on the wafer surface. (3-2) Promotion of atomic diffusion at the interface The high frequency electric field exerts the following effects on the wafer surface. Ion movement: The alternating electric field makes it easier for ions on the wafer surface to move. Changes in atomic forces: The alternating electric field changes the atomic forces between the wafers, forming stronger bonds. Reduction of activation energy: The alternating electric field reduces the energy required for atomic diffusion, promoting bonding between atoms.

[0136] [Mechanism of ion diffusion] When a high frequency power source is applied, ion diffusion occurs according to the following mechanism. By applying a high frequency power supply to only one of the opposing wafers, it is possible to achieve all of the following effects: (1) ion migration due to electric field induction, (2) surface diffusion, and (3) strengthening of interatomic bonds. Therefore, by applying a high frequency power supply to at least one of the opposing wafers, it is possible to generate the ion flow phenomenon. (1) Electric field-induced ion migration A high-frequency electric field (RF field) attracts and repels ions on the wafer surface, causing the ions to move uniformly across the entire wafer surface.

[0137] (2) Surface diffusion The movement of ions across the wafer surface rearranges atoms. The rearrangement of the wafer surface atoms creates a more stable energy state.

[0138] (3) Strengthening interatomic bonds The rearrangement of the atoms on the wafer surface strengthens the bonds between the atoms, resulting in a strong bond between the wafers.

[0139] After isotropically etching the oxide film (first oxide film, initial oxide film) on the wafer surface, the RF ion flow bonding process activates the wafer surface by chemically reacting silicon wafers in a vacuum and soft sputtering with argon. Subsequently, an oxide film (second oxide film, native oxide film) forms on the wafer surface during wafer transport. The wafers are then bonded together in a high-vacuum environment at high speed, for example, for approximately 10 seconds, while maintaining the activated state of the wafer surface. Furthermore, by continuing to apply RF power between the wafers, ions on the wafer surface diffuse, removing the oxide film (second oxide film, native oxide film) on the wafer surface. Furthermore, ions on the wafer surface migrate, strengthening the interatomic bonds. This strengthens the bond between the wafers. Thus, RF ion flow bonding is extremely effective in wafer bonding, improving both the bond strength and quality between wafers.

[0140] In addition, frequent automatic electrode replacement and the use of bare wafers contribute to reducing flakes and particles formed by Si sputtering, achieving void-free bonding, which significantly reduces the frequency of chamber cleaning, reduces equipment maintenance time, and contributes to improving equipment availability.

[0141] [Example of a semiconductor manufacturing system] An example in which the semiconductor wafer bonding apparatus of this embodiment and example is assembled into a semiconductor manufacturing system will be described.

[0142] 5 and 6, a semiconductor wafer bonding apparatus 34 can be installed in a semiconductor manufacturing system 200 in place of the plasma chamber 10 of a conventional system. The semiconductor manufacturing system 200 shown in FIGS. 5 and 6 includes a central chamber 202 accommodating a robot hand, a semiconductor wafer bonding apparatus 34 capable of performing plasma processing on semiconductor wafers and bonding wafers together, a vacuum bonding chamber 204, an atomic bonding chamber 206, a rotary cleaning chamber 208, a standby chamber 210, and a load lock chamber 212. A wafer transport mechanism 214 and a plurality of wafer cassettes 216 are arranged near the load lock chamber 212.

[0143] [An example of a wafer holding mechanism] Next, an example of a wafer holding mechanism for holding each wafer will be described.

[0144] The semiconductor wafer bonding apparatus and bonding method of this embodiment are configured such that an electrostatic chuck 80 (see FIGS. 7 to 9) is disposed as a wafer holding mechanism on a first stage 36 and a second stage 38 for holding semiconductor wafers W1 and W2. Note that the electrostatic chuck 80 (see FIGS. 7 to 9) may be disposed instead of the first holding part 102 and the second holding part 104.

[0145] 7 and 8 illustrate the structures of a monopolar electrostatic chuck 78 and a bipolar electrostatic chuck 80. Each of the electrostatic chucks 78, 80 is made of an insulating material such as aluminum oxide (Al2O3) or aluminum nitride (AIN). The chucks have a structure in which an electrode is built into the insulator, and by applying a voltage to this electrode, they attract objects 86, 92 such as semiconductor wafers W1, W2.

[0146] The monopolar electrostatic chuck 78 shown in FIG. 7 is a monopolar electrostatic chuck having a base substrate 82 and an internal electrode (also referred to as an electrode sheet or a polyimide film electrode layer) 84 disposed on the base substrate 82. The base substrate 82 applies either a positive or negative voltage to the internal electrode 84. For example, when a positive voltage is applied to the internal electrode 84, a negative charge is transferred to the surface of the object to be attracted 86, causing the object to be attracted to the monopolar electrostatic chuck 78. When a negative voltage is applied to the internal electrode 84, a positive charge is transferred to the surface of the object to be attracted 86, causing the object to be attracted to the monopolar electrostatic chuck 78.

[0147] The electrostatic chuck 80 shown in Figure 8 is a bipolar type, and includes a base substrate 88 and an internal electrode (also referred to as an electrode sheet or polyimide film electrode layer) 90 disposed on the base substrate 88. The base substrate 88 applies both positive and negative voltages to the internal electrode 90. For example, Voltage A negative charge moves to the surface of the object 92 facing the internal electrode 90 to which negative Voltage A positive (negative) charge is transferred to the surface of the object to be attracted 92 facing the internal electrode 90 to which the voltage is applied, and the object to be attracted 92 is attracted to the bipolar electrostatic chuck 80.

[0148] An example in which a bipolar electrostatic chuck is used in a semiconductor wafer bonding apparatus will be described. As shown in FIG. 9 , an electrostatic chuck 80 is preferably built into each of the first stage 36 and the second stage 38. For ease of explanation, the electrostatic chuck 80 built into the first stage 36 will be referred to as the first electrostatic chuck 80A, and the electrostatic chuck 80 built into the second stage 38 will be referred to as the second electrostatic chuck 80B. Each of the electrostatic chucks 80A and 80B is, for example, a bipolar type. Since the first stage 36 and the second stage 38 are disposed opposite each other, the electrostatic chucks 80A and 80B are disposed opposite each other, thereby constituting a pair of electrostatic chucks.

[0149] The first electrostatic chuck 80A has a first base substrate 88A and a first internal electrode 90A disposed on the first base substrate 88A. The first internal electrode 90A is connected to ground. The first base substrate 88A controls the voltage applied to the first internal electrode 90A. The first internal electrode 90A is composed of two or more adjacent first unit electrodes 91A, and mutually opposite positive and negative voltages are applied to adjacent first unit electrodes 91A, respectively.

[0150] The second electrostatic chuck 80B is disposed opposite the first electrostatic chuck 80A. Similar to the configuration of the first electrostatic chuck 80A, the second electrostatic chuck 80B has a second base substrate 88B and a second internal electrode 90B disposed on the second base substrate 88B. The second internal electrode 90B is connected to ground. The second base substrate 88B controls the voltage applied to the second internal electrode 90B. The second internal electrode 90B is composed of two or more adjacent second unit electrodes 91B, and mutually opposite positive and negative voltages are applied to adjacent second unit electrodes 91B, respectively.

[0151] Here, the first base substrate 88A and the second base substrate 88B control the first unit electrode 91A on the first electrostatic chuck 80A side and the second unit electrode 91B on the second electrostatic chuck 80B side facing the first unit electrode 91A so that voltages of opposite polarities (positive and negative) are applied to them. Therefore, the first unit electrode 91A of the first internal electrode 90A of the first electrostatic chuck 80A, to which a negative voltage is applied, is positioned opposite to the second unit electrode 91B of the second internal electrode 90B of the second electrostatic chuck 80B, to which a positive voltage is applied. Similarly, the first unit electrode 91A of the first internal electrode 90A of the first electrostatic chuck 80A, to which a positive voltage is applied, is positioned opposite to the second unit electrode 91B of the second internal electrode 90B of the second electrostatic chuck 80B, to which a negative voltage is applied. 2 The electrode 91B is positioned opposite to the unit electrode 91B.

[0152] The general principle of the bipolar electrostatic chuck 80 is that, with a semiconductor wafer W1 placed on the first electrostatic chuck 80A and a semiconductor wafer W2 placed on the second electrostatic chuck 80B, positive and negative voltages are applied to the first inner electrode 90A and the second inner electrode 90B, respectively. This causes the positive and negative charges of the semiconductor wafers W1 and W2 to move toward the opposing inner electrodes 90A and 90B in a mutually attractive manner (dielectric polarization). As a result, an attraction force is generated between the first inner electrode 90A and the semiconductor wafer W1, and between the second inner electrode 90B and the semiconductor wafer W2, thereby fixing the semiconductor wafers W1 and W2.

[0153] 7, in a monopolar electrostatic chuck 78, a voltage is generally applied between an object to be attracted (such as a semiconductor wafer) 86 and an internal electrode 84 (also referred to as a chuck or a holding device), generating an electric charge on the surface of the object to be attracted (such as a semiconductor wafer) 86. Specifically, if the internal electrode 84 is positively charged, the surface of the object to be attracted (such as a semiconductor wafer) 86 facing the internal electrode 84 is negatively charged, and if the internal electrode 84 is negatively charged, the surface of the object to be attracted (such as a semiconductor wafer) 86 facing the internal electrode 84 is positively charged. This principle is also applied to a bipolar electrostatic chuck 80 shown in FIG. 8.

[0154] Typically, the surfaces of semiconductor wafers W1 and W2 are negatively (or possibly positively) charged after being activated by plasma processing. Therefore, when attempting to bond semiconductor wafers W1 and W2 with negatively (or positively) charged surfaces together, they electrically repel each other. Forcibly bonding the semiconductor wafers W1 and W2 together in this state results in a mutual repulsion, resulting in misalignment and a reduction in the bonding accuracy of the semiconductor wafers W1 and W2.

[0155] 9, the surface of one of the opposing semiconductor wafers W1 is positively (negatively) charged, and the surface of the other semiconductor wafer W2 is negatively (positively) charged, intentionally creating a state in which the semiconductor wafers to be bonded are charged with opposite polarities. This, for example, utilizes both the van der Waals force (intermolecular force) and the Coulomb force (electrostatic force) generated between the two to improve the adsorptive force and assist in bonding the semiconductor wafers W1 and W2 together.

[0156] Generally, when two negatively charged objects (or two positively charged objects) come together, they repel each other. This is one of the basic properties of static electricity: charges of the same sign (for example, when both are negative) repel each other, and charges of opposite polarities (for example, one is positive and the other is negative) attract each other.

[0157] The semiconductor wafers W1 and W2 are charged to opposite polarities (opposite polarities) and are controlled with a voltage between their surfaces that does not cause discharge, and when the positively charged semiconductor wafer W1 (or W2) comes into contact with the negatively charged semiconductor wafer W2 (or W1), electrons move from the positively charged object to the negatively charged object, neutralizing the charge. This weakens the effect of static electricity and simultaneously increases the bonding attraction force during bonding.

[0158] In a typical bipolar electrostatic chuck, the surface of the semiconductor wafer is brought into electrical equilibrium by applying voltages of the same magnitude (absolute value) to the positive and negative sides. to We are maintaining it.

[0159] In contrast to this, rather than applying voltages of the same magnitude (absolute value) to the positive and negative, voltages of different magnitudes are applied to intentionally disrupt the positive or negative balance. In other words, an imbalance is created between the positive and negative voltages in terms of the magnitude of the applied voltage.

[0160] 9, for example, a voltage of −400 volts is applied to one first unit electrode 91A constituting a first inner electrode 90A of a first electrostatic chuck 80A, and a voltage of +500 volts is applied to the other first unit electrode 91A. At the same time, a voltage of +400 volts is applied to one second unit electrode 91B constituting a second inner electrode 90B of a second electrostatic chuck 80B, and a voltage of −500 volts is applied to the other second unit electrode 91B.

[0161] Here, the first unit electrode 91A of the first inner electrode 90A of the first electrostatic chuck 80A, which is on one side to which a voltage of −400 V is applied, and the second unit electrode 91B of the second inner electrode 90B of the second electrostatic chuck 80B, which is on one side to which a voltage of +400 V is applied, are set to be positioned opposite each other. Although these electrodes have different polarities (positive and negative), voltages of the same absolute value are applied to them.

[0162] Furthermore, the first unit electrode 91A of the first inner electrode 90A of the first electrostatic chuck 80A, which is on the other side to which a voltage of +500 V is applied, and the second unit electrode 91B of the second inner electrode 90B of the second electrostatic chuck 80B, which is on the other side to which a voltage of −500 V is applied, are set to be positioned opposite each other. Although these electrodes have different polarities (positive and negative), voltages of the same magnitude in absolute value are applied to them.

[0163] As a result, the first electrostatic chuck 80A Against The surface of the semiconductor wafer W1 facing the first electrostatic chuck 80A is charged with a charge of +100 volts, which is the difference between +500 volts and -400 volts of the first electrostatic chuck 80A. Against The surface of the facing semiconductor wafer W2 is charged with a charge of −100 volts, which is the difference between +400 volts and −500 volts of the second electrostatic chuck 80B.

[0164] At this time, flow is formed on the surfaces of the semiconductor wafers W1 and W2. Te As a result, by applying a reverse voltage to the mutually opposing internal electrodes 90A, 90B (or unit electrodes), the semiconductor wafers W1, W2 are attracted to each other by a strong Coulomb force and bonded together. As a result, the generation of bubbles when bonding the semiconductor wafers W1, W2 together can be suppressed.

[0165] Here, the semiconductor wafers W1 and W2 held by the pair of electrostatic chucks 80A and 80B are preferably placed in a microspace (minimal space) environment with a separation distance of 10 μm to 50 μm, inclusive. In the microspace, the semiconductor wafers W1 and W2 are bonded to each other while maintaining their planar orientation.

[0166] It should be noted that the present embodiment and examples illustrate one aspect of the present invention, and the present invention is not limited thereto. Differences in the degree of design changes from the present embodiment and examples are naturally included within the scope of the technical idea of ​​the present invention. [Explanation of symbols]

[0167] 14 Chamber 16 stages 34 Semiconductor wafer bonding equipment 36 First Stage 38 Second Stage 78 Single-pole electrostatic chuck 80 Bipolar electrostatic chuck 80A First Electrostatic Chuck 80B Second electrostatic chuck 82 Base 84 Internal electrode 86 Adsorbed object 88 Base 88A First Base 88B Second Base 90 Internal electrode 90A First inner electrode 90B Second internal electrode 91A First unit electrode 91B Second unit electrode 92 Adsorbed object 102 first holding part 104 Second holding part 106 First Replacement Device 108 Second Replacement Device 110 High frequency power supply 112 Automatic pressure control device 114 Turbomolecular Pump 200 Semiconductor Manufacturing System 202 Central Chamber 204 Vacuum Bonding Chamber 206 Atomic Bonding Chamber 208 Rotating Wash Chamber 210 Waiting Chamber 212 Load Lock Chamber 214 Wafer transport mechanism 216 Wafer Cassette 300 Semiconductor manufacturing equipment 310 Control Unit 320 Measuring section 330 Flattening section 340 Peeling part 350 Conveyor 360 joint 370 Inspection Department 380 Adjustment section G1 Silicon wafer (semiconductor material) G2 Bonded wafer (semiconductor material) W1 Semiconductor wafer (semiconductor material) W2 Semiconductor wafer (semiconductor material)

Claims

1. A semiconductor manufacturing apparatus using a semiconductor material bonding apparatus for bonding a pair of semiconductor materials, a first oxide film formed on the surface of the semiconductor material is measured, and the first oxide film is peeled off and removed by isotropic etching or plasma etching based on the measurement result of the first oxide film; and the semiconductor material that has undergone a transport process in which the semiconductor material is transported under a predetermined environment is subjected to the transport process; The bonding device performs plasma processing to activate the surfaces of the semiconductor materials, polarizes ions on the surfaces of the semiconductor materials in a high vacuum state within a predetermined time, and applies a high-frequency power source to the semiconductor materials to remove a second oxide film formed on the surfaces of the semiconductor materials during the transport process, and the ions move on the surfaces of the semiconductor materials to bond the semiconductor materials together; optimizing process parameters that govern process performance related to the isotropic etching, the plasma etching, and the plasma processing based on the measurement results of the first oxide film; Semiconductor manufacturing equipment.

2. A semiconductor manufacturing apparatus using a semiconductor material bonding device for bonding a pair of semiconductor materials, a first oxide film formed on the surface of the semiconductor material is measured, and the first oxide film is peeled off and removed by isotropic etching or plasma etching based on the measurement result of the first oxide film; and the semiconductor material that has undergone a transport process in which the semiconductor material is transported under a predetermined environment is subjected to the transport process; The bonding device performs plasma processing to activate the surfaces of the semiconductor materials, polarizes ions on the surfaces of the semiconductor materials in a high vacuum state within a predetermined time, and applies a high-frequency power source to the semiconductor materials to remove a second oxide film formed on the surfaces of the semiconductor materials during the transport process, and the ions move on the surfaces of the semiconductor materials to bond the semiconductor materials together; If there is an abnormality in the measurement result of the first oxide film, at least a part of the first oxide film on the surface of the semiconductor material is removed and planarized before the first oxide film is stripped. Semiconductor manufacturing equipment.

3. A semiconductor manufacturing apparatus using a semiconductor material bonding device that bonds a pair of semiconductor materials, a first oxide film formed on the surface of the semiconductor material is measured, and the first oxide film is peeled off and removed by isotropic etching or plasma etching based on the measurement result of the first oxide film; and the semiconductor material that has undergone a transport process in which the semiconductor material is transported under a predetermined environment is subjected to the transport process; The bonding device performs plasma processing to activate the surfaces of the semiconductor materials, polarizes ions on the surfaces of the semiconductor materials in a high vacuum state within a predetermined time, and applies a high-frequency power source to the semiconductor materials to remove a second oxide film formed on the surfaces of the semiconductor materials during the transport process, and the ions move on the surfaces of the semiconductor materials to bond the semiconductor materials together; In the plasma treatment of the bonding apparatus, an emission spectrum is monitored in real time during plasma activation, and an active particle concentration is acquired to detect plasma activity. Semiconductor manufacturing equipment.

4. If there is an abnormality in the measurement result of the first oxide film, at least a part of the first oxide film on the surface of the semiconductor material is removed and planarized before peeling off the first oxide film. The semiconductor manufacturing apparatus according to claim 1 .

5. After the semiconductor materials are bonded, the bonding strength or porosity of the semiconductor materials is inspected. The semiconductor manufacturing apparatus according to claim 1 .

6. If the bonding strength or porosity of the semiconductor material does not meet a predetermined standard, adjusting the processing parameters. The semiconductor manufacturing apparatus according to claim 5 .

7. The first oxide film is measured using a film thickness meter based on an X-ray fluorescence method, selecting at least 13 points on the surface of the semiconductor material. The semiconductor manufacturing apparatus according to claim 1 .

8. In the plasma treatment of the bonding apparatus, an emission spectrum is monitored in real time during plasma activation, and an active particle concentration is acquired to detect plasma activity. The semiconductor manufacturing apparatus according to claim 1 .

9. In the inspection of the bonding strength or porosity of the semiconductor material, the bonding interface of the semiconductor material is inspected using a scanning acoustic microscope, and the acoustic signal is analyzed to quantitatively evaluate the bonding strength or porosity of the semiconductor material.

7. The semiconductor manufacturing apparatus according to claim 5 or 6.

10. The processing parameters include at least one element of an etching time or an etching solution concentration in the isotropic etching or the plasma etching, a gas flow rate or an applied output of the high frequency power source in the plasma processing, a bonding temperature or a bonding time of the semiconductor material, and a heat treatment temperature or a heat treatment time of the semiconductor material. The semiconductor manufacturing apparatus according to claim 1 .

11. The predetermined time is 0.1 to 10 seconds. The semiconductor manufacturing apparatus according to claim 1 .

12. The semiconductor materials to be joined together are held by an electrostatic chuck as parallel plate plasma electrodes. The semiconductor manufacturing apparatus according to claim 1 .

13. A measuring step of measuring a first oxide film formed on a surface of a semiconductor material; a stripping step of stripping and removing the first oxide film by isotropic etching or plasma etching based on the measurement results of the first oxide film; a transport step of transporting the semiconductor material under a predetermined environment; a bonding process in which, after subjecting the semiconductor material to plasma treatment to activate the surface, ions are polarized on the surface of the semiconductor material in a high vacuum state within a predetermined time, and a high frequency power source is applied to the semiconductor material to remove the second oxide film formed on the surface of the semiconductor material in the transport process, and the ions move on the surface of the semiconductor material to bond the semiconductor materials together; and the measuring step includes an optimizing step of optimizing process parameters that govern process performances related to the isotropic etching, the plasma etching, and the plasma processing based on the measurement results of the first oxide film. Semiconductor manufacturing methods.

14. A measuring step of measuring a first oxide film formed on a surface of a semiconductor material; a stripping step of stripping and removing the first oxide film by isotropic etching or plasma etching based on the measurement results of the first oxide film; a transport step of transporting the semiconductor material under a predetermined environment; a bonding process in which, after subjecting the semiconductor material to plasma treatment to activate the surface, ions are polarized on the surface of the semiconductor material in a high vacuum state within a predetermined time, and a high frequency power source is applied to the semiconductor material to remove the second oxide film formed on the surface of the semiconductor material in the transport process, and the ions move on the surface of the semiconductor material to bond the semiconductor materials together; and If an abnormality is detected in the measuring step, a planarization step is performed before the peeling step, in which at least a part of the first oxide film on the surface of the semiconductor material is removed and planarized. Semiconductor manufacturing methods.

15. A measuring step of measuring a first oxide film formed on a surface of a semiconductor material; a stripping step of stripping and removing the first oxide film by isotropic etching or plasma etching based on the measurement results of the first oxide film; a transport step of transporting the semiconductor material under a predetermined environment; a bonding process in which, after subjecting the semiconductor material to plasma treatment to activate the surface, ions are polarized on the surface of the semiconductor material in a high vacuum state within a predetermined time, and a high frequency power source is applied to the semiconductor material to remove the second oxide film formed on the surface of the semiconductor material in the transport process, and the ions move on the surface of the semiconductor material to bond the semiconductor materials together; and In the bonding step, an emission spectrum is monitored in real time during plasma activation, and an active particle concentration is acquired to detect plasma activity. Semiconductor manufacturing methods.

16. If an abnormality is found in the measuring step, a planarization step is performed before the peeling step, in which at least a portion of the first oxide film on the surface of the semiconductor material is removed and planarized. The semiconductor manufacturing method according to claim 13.

17. After the bonding step, an inspection step is performed to inspect the bonding strength or porosity of the semiconductor material. The semiconductor manufacturing method according to claim 13.

18. The method further comprises an adjustment step of adjusting the processing parameters if the bonding strength or porosity of the semiconductor material does not satisfy a predetermined standard in the inspection step.

18. The semiconductor manufacturing method according to claim 17.

19. In the measuring step, a film thickness meter based on an X-ray fluorescence method is used to select and measure at least 13 points on the surface of the semiconductor material. The semiconductor manufacturing method according to claim 13.

20. In the bonding step, an emission spectrum is monitored in real time during plasma activation, and an active particle concentration is acquired to detect the plasma activity. The semiconductor manufacturing method according to claim 13.

21. In the inspection step, the bonding interface of the semiconductor material is inspected using a scanning acoustic microscope, and the acoustic signal is analyzed to quantitatively evaluate the bonding strength or porosity of the semiconductor material.

19. The semiconductor manufacturing method according to claim 17 or 18.

22. The processing parameters include at least one element of an etching time or etching solution concentration in the isotropic etching or the plasma etching, a gas flow rate or an applied output of the high frequency power source in the plasma processing, a bonding temperature or bonding time of the semiconductor material, and a heat treatment temperature or heat treatment time for the semiconductor material. The semiconductor manufacturing method according to claim 13.

23. The predetermined time is 0.1 to 10 seconds. The semiconductor manufacturing method according to claim 13.

24. The semiconductor materials to be joined together are held by an electrostatic chuck as parallel plate plasma electrodes. The semiconductor manufacturing method according to claim 13.

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