Test pattern and semiconductor integrated circuit including the same

Abstract

A pattern for inspection is provided with which it is possible to conduct a wafer-level automatic inspection using a cantilever probe card. A pattern for inspection according to an embodiment of the present disclosure comprises a Cu pillar pad formed on a semiconductor substrate, a Cu pillar formed on the Cu pillar pad, and an inspection pad formed on the semiconductor substrate. The inspection pad is contiguous or adjacent to the Cu pillar pad and electrically connected thereto, and provides an area with which a cantilever probe comes into contact when a wafer-level automatic inspection is made.

Description

[Technical Field]

[0001] The present disclosure relates to a test pattern and a semiconductor integrated circuit including the same. [Background technology]

[0002] Conventionally, Cu pillars (copper pillars) have been known for use in flip-chip connections between semiconductor integrated circuit chips and semiconductor package substrates (see, for example, Non-Patent Documents 1 and 2). Cu pillars (copper pillars) are a technology for forming Cu pillars on the aluminum electrode pads of semiconductor integrated circuit chips, enabling narrower pad pitches and higher terminal density.

[0003] The semiconductor integrated circuits used in optical communication modules and optical devices include semiconductor integrated circuits that include optical circuits (hereinafter also referred to as optical semiconductor integrated circuit chips). In recent years, there has been a demand for higher terminal density and narrower pad pitches in optical semiconductor integrated circuit chips to accommodate increased transmission capacity, wider bandwidth, and higher density in optical communications, and Cu pillar technology has come to be used.

[0004] To meet the demand for increased transmission capacity, the integration density of optical communication modules is increasing, and to improve product yield, it is necessary to select good chips by wafer-level automatic inspection of the optical semiconductor integrated circuit chips included in the optical communication modules. This wafer-level automatic inspection involves simultaneous use of optical input / output probes and electrical probes to perform optical and electrical measurements.

[0005] Vertical probe cards that do not have pads and that perform testing by contacting Cu pillars vertically are commercially available for wafer-level automatic testing of semiconductor integrated circuits (see, for example, Non-Patent Document 3). [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] B. Tunaboylu, "Testing of Copper Pillar Bumps for Wafer Sort," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 2, no. 6, pp. 985-993, June 2012, doi: 10.1109 / TCPMT.2011.2173493 [Non-patent document 2] Shinko Electric Industries Co., Ltd., "Cu pillar," [online], Shinko Electric Industries Co., Ltd. website, [searched July 12, 2022], Internet (URL: https: / / www.shinko.co.jp / product / package / assembly / cu-pillar.php) [Non-patent document 3] Seiken Co., Ltd., "Features and Comparison of Probe Cards (Vertical and Cantilever Types)," [online], Seiken Co., Ltd. website, [Retrieved July 12, 2022], Internet (URL: https: / / www.seiken.co.jp / semiconductor / probecard.html) Summary of the Invention

[0007] In wafer-level automatic inspection of wafers on which semiconductor integrated circuits including Cu pillars are formed (hereinafter referred to as semiconductor integrated circuit wafers), a vertical probe card is generally used, which leaves small dents and is less likely to damage the Cu pillars.

[0008] Meanwhile, in wafer-level automatic inspection of wafers on which optical semiconductor integrated circuits included in optical communication devices are formed (hereinafter referred to as optical semiconductor integrated circuit wafers), inspection using optical input / output probes and electric probes simultaneously is necessary to perform optical and electrical measurements. However, in the case of vertical probe cards, due to their structure, it is not possible to provide an area for contacting the optical input / output probes with the optical semiconductor integrated circuit wafer, which has posed a problem in that wafer-level automatic inspection of optical semiconductor integrated circuit chips is not possible.

[0009] Therefore, in wafer-level automatic testing of optical semiconductor integrated circuit chips, a cantilever-type probe card can be used, which can secure an area for contacting the optical input / output probe with the wafer by cutting the probe card into a rectangular or U-shape.However, cantilever-type probe cards generally leave large contact marks, which makes it impossible to make measurements by directly contacting the Cu pillars.

[0010] The present disclosure has been made in consideration of such problems, and its purpose is to provide an inspection pattern and a semiconductor integrated circuit that enable wafer-level automatic inspection using a cantilever-type probe card without contacting the probe with the Cu pillar.

[0011] To achieve this objective, a test pattern according to one embodiment of the present disclosure includes a Cu pillar pad formed on a semiconductor substrate, a Cu pillar formed on the Cu pillar pad, and a test pad formed on the semiconductor substrate, the test pad being adjacent to or close to and electrically coupled to the Cu pillar pad, and providing an area for a cantilever-type probe to contact during wafer-level automatic testing.

[0012] According to the test pattern of the embodiment of the present disclosure, it is possible to perform wafer-level automatic testing without bringing the probe of the cantilever-type probe card into contact with the Cu pillar. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a Cu pillar, where (a) is a top view and (b) is a side view. [Figure 2] FIG. 2 is a diagram showing a test pattern according to an embodiment of the present disclosure, where (a) is a top view and (b) is a side view. [Figure 3]FIG. 3 is a diagram illustrating a schematic configuration of an optical semiconductor integrated circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a state in which a chip having Cu pillars according to an embodiment of the present disclosure is mounted on an external package substrate or circuit board. [Figure 5] 5 is a diagram illustrating a state in which a chip having Cu pillars is mounted on an external package substrate or circuit board. [Figure 6] FIG. 6 is a diagram showing a schematic configuration of an optical semiconductor integrated circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 shows a cantilever probe card and tip during wafer-level automated testing, where (a) is a top view and (b) is a side view. [Figure 8] Figure 8 shows the state in which the tip of a cantilever probe is in contact with the test pad 20, where (a) shows a (newer) cantilever probe with less wear to the tip, and (b) shows a cantilever probe with more wear to the tip. [Figure 9] FIG. 9 is a diagram showing a schematic configuration of an optical semiconductor integrated circuit according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating a schematic configuration of an optical semiconductor integrated circuit according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram illustrating a schematic configuration of an optical semiconductor integrated circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, optical semiconductor integrated circuits according to embodiments of the present disclosure will be described in detail with reference to the drawings. The same or similar reference numerals indicate the same or similar elements, and repeated explanations may be omitted. An optical semiconductor integrated circuit is an integrated circuit that includes an optical circuit, but the present disclosure can also be described using a semiconductor integrated circuit that does not include an optical circuit instead of an optical semiconductor integrated circuit.

[0015] FIG. 1 is a diagram illustrating a Cu pillar, where (a) is a top view and (b) is a side view. An optical semiconductor integrated circuit including an optical circuit according to an embodiment of the present disclosure can also achieve high terminal density and a narrow pad pitch by using Cu pillars. As shown in FIG. 1, a Cu pillar 10 is formed on a Cu pillar pad 11. The Cu pillar 10 has a cylindrical shape and a circular cross section in the horizontal direction (XY plane direction). The Cu pillar pad 11 also has a cylindrical shape and the diameter of its horizontal cross section is larger than the diameter of the Cu pillar 10. Solder 12 is disposed on the top surface of the Cu pillar 10. In top view, the Cu pillar 10 is located inside the Cu pillar pad 11. The solder 12 on the top surface of the Cu pillar 10 forms a bump.

[0016] (First embodiment) An inspection pattern according to the first embodiment of the present disclosure will be described with reference to Fig. 2. Fig. 2 shows the inspection pattern, where (a) is a top view and (b) is a side view. The inspection pattern shown in Fig. 2 is formed in an optical semiconductor integrated circuit on a wafer and is used in wafer-level automatic inspection of the optical semiconductor integrated circuit.

[0017] As shown in Figure 2, the test pattern includes a Cu pillar pad 11, a Cu pillar 10 arranged on the Cu pillar pad 11, and a test pad 20 overlapping the Cu pillar pad 11. The test pad 20 provides an area with which a cantilever probe arranged on a cantilever probe card makes contact during wafer-level automatic testing. The Cu pillar pad 11 and the test pad 20 only need to be arranged adjacent to each other, and there is no need for the Cu pillar pad 11 and the test pad 20 to have an overlapping area in the Z-axis direction.

[0018] For example, when the test pad 20 is formed using Cu as the material, the Cu pillar pad 11 and the test pad 20 can be formed as one continuous region in the same manufacturing process.

[0019] 2 also shows solder 12 on the top surface of the Cu pillar 10. The solder 12 forms a bump in a flip-chip connection.

[0020] According to the inspection pattern of this embodiment (also simply referred to as the inspection pattern in this specification), during wafer-level automatic inspection, it is not necessary to contact the cantilever-type probe with the Cu pillar 10, Cu pillar pad 11, and solder 12. Therefore, no contact marks are left on the Cu pillar 10, Cu pillar pad 11, and solder 12.

[0021] As described above, by providing a test pattern including test pads on an optical semiconductor integrated circuit wafer, wafer-level automatic testing using a cantilever-type probe card becomes possible. Note that this method can be applied not only to optical semiconductor integrated circuit wafers, but also to semiconductor integrated circuit wafers that do not include optical circuits. That is, by providing a test pattern including test pads on a semiconductor integrated circuit wafer, wafer-level automatic testing using a cantilever-type probe card becomes possible. By using a cantilever-type probe card, which is less expensive than a vertical probe card, testing can be carried out at a low cost.

[0022] (Second embodiment) An optical semiconductor integrated circuit according to a second embodiment of the present disclosure will be described with reference to FIGS. 3, 4, and 5. FIG. 3 shows one of a plurality of optical semiconductor integrated circuits formed on a wafer. The optical semiconductor integrated circuit is an integrated circuit including an optical circuit, and is formed on a wafer. As described above, the optical semiconductor integrated circuit is cut out from the wafer after wafer-level automatic inspection as a chip including one optical semiconductor integrated circuit. The chip cut out from the wafer is modularized together with other components to form an optical communications module.

[0023] The optical semiconductor integrated circuit shown in FIG. 3 comprises a rectangular chip 30 (i.e., an optical semiconductor integrated circuit substrate), optical input / output terminals 32 and a semiconductor element 31 formed on the main surface (XY plane) of the chip 30, a plurality of test patterns, and in-chip wiring 33 that electrically connects each of the plurality of test patterns to the semiconductor element 31.

[0024] Each of the multiple test patterns formed on the chip 30 has the test patterns described with reference to FIG. 2 , namely, Cu pillar pads 11, Cu pillars 10, test pads 20, and solder 12. The test pads 20 arranged adjacent to the Cu pillar pads 11 are electrically connected to the semiconductor element 31 by intra-chip wiring 33. The test pads 20 provide areas for contact with cantilever probes arranged on a cantilever probe card during wafer-level automatic testing performed before the chip 30 is cut from the wafer. The Cu pillar pads 11, Cu pillars 10, and solder 12 provide connection points when flip-connecting the chip 30 to one or more of the driver ICs, bias circuits, transimpedance amplifiers (TIAs), and other elements (not shown), such as a wiring board or a radio frequency (RF) wiring board, of the semiconductor element 31.

[0025] As shown in FIG. 3, multiple test patterns are linearly arranged near the end face of a rectangular chip 30, i.e., near the periphery of the chip 30. The Cu pillar pads 11 of each test pattern are arranged closer to the end face than the test pads 20. The test pads 20 of each test pattern are also arranged in a direction away from the nearest end face from the Cu pillar pad 11 (toward the end face opposite the nearest end face). A Cu pillar 10 is arranged on the Cu pillar pad 11, and a solder 12 is arranged on the top surface of the Cu pillar 10. In FIG. 3, the Cu pillar 10 is located below the solder 12.

[0026] The optical input / output terminal 32 is, for example, a grating coupler, and is an optical circuit integrated on the chip 30. The semiconductor element 31 is, for example, a photodiode, and is an optical circuit integrated on the chip 30.

[0027] In this embodiment, when the semiconductor element 31 of the chip 30 is a photodiode, the photodiode of the chip 30 in the optical communications module receives a bias from an external bias source via the Cu pillar 10, performs photoelectric conversion of light incident from another optical circuit via a grating coupler, and supplies an electrical signal to the external TIA via the Cu pillar 10. On the other hand, in wafer-level automatic testing, the photodiode of the chip 30 receives a bias from a testing device via a cantilever probe in contact with the testing pad 20, performs photoelectric conversion of light from the optical probe incident via the grating coupler, and supplies an electrical signal to the testing device via the cantilever probe in contact with the testing pad 20.

[0028] In this embodiment, when the semiconductor element 31 of the chip 30 is a laser diode, the laser diode of the chip 30 in the optical communications module receives a control signal from an external driver IC (or an RF wiring board connected to the external driver IC) via the Cu pillar 10, and operates to emit an optical signal to another optical circuit via a grating coupler. Meanwhile, in wafer-level automatic inspection, the laser diode of the chip 30 receives a control signal from an inspection device via a cantilever-type probe in contact with the inspection pad 20, and operates to supply an optical signal from the optical probe to the inspection device via the grating coupler.

[0029] In the present embodiment, when the semiconductor element 31 of the chip 30 is an optical modulator, the optical modulator of the chip 30 in the optical communications module receives a modulated signal from an external driver IC (or an RF wiring board connected to the external driver IC) via the Cu pillar 10, modulates an optical signal from another optical circuit incident through one part of the grating coupler, and outputs the modulated optical signal to another optical circuit via another part of the grating coupler. Meanwhile, in wafer-level automatic inspection, the optical modulator of the chip 30 receives a modulated signal from an inspection device via a cantilever-type probe in contact with the inspection pad 20, modulates the optical signal incident from the optical probe via the grating coupler, and supplies the modulated optical signal to the inspection device via another optical probe.

[0030] According to the optical semiconductor integrated circuit of this embodiment, in order to reduce the size of the chip 30, the test pads 20 are arranged on the periphery of the chip, and the semiconductor elements constituting the optical circuit (such as a photodiode, laser diode, or optical modulator) are arranged in the center of the chip. When this embodiment is applied to a semiconductor integrated circuit that does not include an optical circuit instead of an optical semiconductor integrated circuit, the semiconductor elements constituting the electronic circuit (such as a transistor constituting an amplifier, a driver IC, etc.) are arranged in the center of the chip.

[0031] 4 is a diagram illustrating a state in which the chip 30 is flip-chip mounted on an external package substrate or circuit board 40 using the Cu pillar 10. As shown in FIG. 4, no stubs (open circuits) occur in the electrical signal path between the external circuit board 40 and the semiconductor element 31 included in the chip 30.

[0032] 5 is a diagram illustrating a state in which a chip 50, in which the positions of the Cu pillar pads 11 and the test pads 20 in the test pattern of the chip 30 in FIG. 4 are swapped, is flip-chip mounted on an external circuit board 40. The test pads 20, which are positioned closer to the end face than the Cu pillar pads 11, act as stubs, which can cause degradation of high-frequency characteristics.

[0033] In the optical semiconductor integrated circuit according to this embodiment, no stubs are generated, and therefore, wafer-level automatic testing can be performed by arranging the test pads 20 and using a low-cost cantilever-type probe card without impairing the high-frequency characteristics.

[0034] (Third embodiment) An optical semiconductor integrated circuit according to a third embodiment of the present disclosure will be described with reference to FIG. 6. Similar to FIG. 3, FIG. 6 illustrates one of multiple optical semiconductor integrated circuits formed on a wafer. In the optical semiconductor integrated circuit according to this embodiment, as in the previously described optical semiconductor integrated circuits, test pads 20 are arranged on the periphery of the chip 60 in order to reduce the size of the chip 60. The rectangular chip 60 illustrated in FIG. 6 differs from the chip 30 illustrated in FIG. 3 in the arrangement of multiple test patterns formed on the chip 60. More specifically, as illustrated in FIG. 6, the chip 60 differs from the chip 30 illustrated in FIG. 3 in that the test pads 20 of each test pattern are arranged closer to the end face than the Cu pillar pads 11, and the Cu pillar pads 11 arranged adjacent to the test pads 20 are electrically connected to the semiconductor element 31 by intra-chip wiring 33.

[0035] FIG. 7 shows a cantilever probe card and a chip during wafer-level automated testing, with (a) being a top view and (b) being a side view. The cantilever probe card 71 shown in FIG. 7 has an opening larger than the size of the chip 70 to be tested, and a cantilever probe 72 is arranged around the opening. FIG. 7 also shows an optical probe 73 for testing the optical input / output to and output from the chip 70 to be tested. As shown in FIG. 7, when wafer-level automated testing is performed using a cantilever probe card, the cantilever probe 72 penetrates the periphery of the chip 70 from the outer periphery toward the inside of the chip, making contact with the test pads. The cantilever probe card is cleaned after testing is completed. This cleaning process involves abrading the tips of the cantilever probes.

[0036] FIG. 8 shows the state in which the tip of a cantilever probe contacts a test pad 20 in a test pattern according to the present disclosure. (a) shows a (newer) cantilever probe with less tip wear, and (b) shows a cantilever probe with more tip wear. As shown in FIG. 8(b), if much of the tip is worn away by cleaning, the cantilever probe 72 approaches the Cu pillar 10 (and solder 12) during wafer-level automated testing. If the cantilever probe 72 collides with the Cu pillar 10 (and solder 12), it will be damaged. To prevent this, the size of the test pad 20 must be increased in advance to allow for a margin for tip wear. For example, the diameter of a typical Cu pillar is 60 μm. Taking into account manufacturing errors of the cantilever probe and the probing accuracy of the testing equipment, the Cu pillar 10 and the cantilever probe 72 must be separated by approximately 30 μm even after cleaning. In this case, the initial size of the test pad 20 needs to be such that the length in the direction in which the cantilever probe 72 skates is about 125 μm.

[0037] On the other hand, in the optical semiconductor integrated circuit according to the embodiment shown in FIG. 6, the test pad 20 is positioned closer to the end face of the chip 60 than the Cu pillar pad 11. This prevents the tip of the cantilever probe 72 from approaching the Cu pillar 10 (and the solder 12) even if it is scraped during cleaning. Therefore, the length of the cantilever probe 72 in the direction of skating, which is the size of the test pad 20, can eliminate the 20 μm margin for tip scraping. In other words, a smaller test pad 20 can be realized compared to the example described above with reference to FIG. 8. This reduces the capacitance of the test pad 20, making it possible to provide an optical semiconductor integrated circuit or semiconductor integrated circuit that can be tested using a low-cost cantilever probe card 71 with the test pad 20 positioned thereon without impairing high-frequency characteristics.

[0038] (Fourth embodiment) An optical semiconductor integrated circuit according to a fourth embodiment of the present disclosure will be described with reference to FIG. 9. Similar to FIG. 3, FIG. 9 illustrates one of multiple optical semiconductor integrated circuits formed on a wafer. In the optical semiconductor integrated circuit according to this embodiment, as in the previously described optical semiconductor integrated circuits, test pads 20 are arranged on the periphery of the chip 60 in order to reduce its size. The rectangular chip 90 shown in FIG. 9 differs from the chip 30 shown in FIG. 3 in the arrangement of multiple test patterns formed on the chip 90. More specifically, as shown in FIG. 9, the chip 60 differs from the chip 30 shown in FIG. 3 in that the test pads 20 and Cu pillar pads 11 of each test pattern are arranged parallel to the nearest end face, and the Cu pillar pads 11 arranged adjacent to the test pads 20 are electrically connected to the semiconductor element 31 by intra-chip wiring 33.

[0039] 6, the optical semiconductor integrated circuit according to this embodiment also does not approach the Cu pillar 10 (and the solder 12) even if the tip of the cantilever probe 72 is scraped off by cleaning. That is, it is possible to realize a test pad 20 that is smaller in size than the example described above with reference to FIG. 8. This makes it possible to provide an optical semiconductor integrated circuit or a semiconductor integrated circuit that can be tested using a low-cost cantilever probe card 71 by arranging the test pad 20 without impairing the high-frequency characteristics by reducing the capacitance component of the test pad 20.

[0040] (Fifth embodiment) An optical semiconductor integrated circuit according to a fifth embodiment of the present disclosure will be described with reference to FIG. 10. Similar to FIG. 3, FIG. 10 illustrates one of a plurality of optical semiconductor integrated circuits formed on a wafer. The optical semiconductor integrated circuit illustrated in FIG. 10 includes a rectangular chip 100 (i.e., an optical semiconductor integrated circuit substrate), a semiconductor element 31 formed on the main surface (XY plane) of the chip 100, a plurality of test patterns, and high-frequency wiring 101 electrically connecting each of the plurality of test patterns to the semiconductor element 31. The two high-frequency wirings 101 illustrated in FIG. 10 are merely exemplary, and the number of high-frequency wirings 101 included in the optical semiconductor integrated circuit, i.e., the number of test patterns, is not limited to two. With the signal line and ground line designated as S and G, respectively, the optical semiconductor integrated circuit may include the number of high-frequency wirings 101 according to a desired configuration, such as an SGS configuration or a GSGSG configuration.

[0041] The test pattern in the optical semiconductor integrated circuit according to this embodiment includes Cu pillar pads 11, Cu pillars 10, solder 12, and a test pad window 102. This test pattern differs from the test pattern described with reference to FIG. 2 in that the intra-chip wiring 33 connecting the Cu pillar pads 11 and the semiconductor element 31 is configured as high-frequency wiring 101, and the test pad window 102 is provided on the high-frequency wiring 101. The test pad window 102 is a portion obtained by removing the passivation film formed on the top surface of the chip 100. The test pad window 102 is rectangular, similar to the test pad 20. The test pad window 102 corresponds to the test pad 20 described above, and provides an area for contact with a cantilever probe arranged on a cantilever probe card during wafer-level automatic testing.

[0042] In the optical semiconductor integrated circuit according to this embodiment, the test pad window 102 of each test pattern is positioned in a direction away from the Cu pillar pad 11 to the closest end face (toward the end face opposite to the closest end face).

[0043] According to the test pattern for the optical semiconductor integrated circuit of this embodiment, by ensuring a sufficient distance between the Cu pillars 10 (and the solder 12) and the test pad window 102, it is possible to eliminate the problem of damage caused by collision between the Cu pillars 10 and the cantilever-type probe 72. Furthermore, there is no need to provide a separate test pad 20. Therefore, it is possible to provide an optical semiconductor integrated circuit or a semiconductor integrated circuit that can be subjected to wafer-level automatic testing using the test pad window 102 and a low-cost cantilever-type probe card, eliminating the increase in capacitance and the accompanying degradation of high-frequency characteristics that come with the addition of a test pad.

[0044] (Sixth embodiment) An optical semiconductor integrated circuit according to a sixth embodiment of the present disclosure will be described with reference to FIG. 11. Similar to FIG. 3, FIG. 11 illustrates one of a plurality of optical semiconductor integrated circuits formed on a wafer. The optical semiconductor integrated circuit illustrated in FIG. 11 includes a rectangular chip 110 (i.e., an optical semiconductor integrated circuit substrate), two semiconductor elements 31a and 31b formed on the main surface (XY plane) of the chip 110, a plurality of test patterns, and high-frequency wiring 111 electrically connecting each of the plurality of test patterns to the semiconductor elements 31a and 31b. As described above with reference to FIG. 10, the number of high-frequency wirings 111 in the chip 110 in FIG. 11 is merely an example, and the chip 110 may include the number of high-frequency wirings 111 according to a desired configuration, such as an SGS configuration or a GSGSG configuration.

[0045] The semiconductor element 31a has a configuration in which a child Mach-Zehnder is arranged in each of two arm optical waveguides that constitute one parent Mach-Zehnder. The configuration of the semiconductor element 31b is similar to that of the semiconductor element 31a. The two semiconductor elements 31a and 31b are arranged in parallel, and one branched portion of input light is modulated by the semiconductor element 31a, and the other branched portion is modulated by the semiconductor element 31b. The optical waveguide 112 shown in FIG. 11 is a waveguide path from which the input light is modulated and output.

[0046] 10 , the test pattern in the optical semiconductor integrated circuit according to this embodiment has Cu pillar pads 11, Cu pillars 10, solder 12, and a test pad window 102. The intra-chip wiring 33 connecting the Cu pillar pads 11 and the semiconductor element 31 is configured as high-frequency wiring 111, and the test pad window 102 is provided above the high-frequency wiring 111. On the other hand, the test pattern in the optical semiconductor integrated circuit according to this embodiment differs from the test pattern described with reference to FIG. 10 in that an optical waveguide 112 that intersects with the high-frequency wiring 111 is formed below the high-frequency wiring 111 between the Cu pillar pads 11 and the test pad window 102.

[0047] Generally, optical waveguides occupy a large portion of the chip space. Furthermore, since electrical elements (transistors) and optical semiconductor elements (optical modulators, photodiodes) exist inside the chip, it can be difficult to secure space for the optical waveguide. Therefore, in this embodiment, the optical waveguide 112 is disposed on the periphery of the chip 110 in order to reduce the area of ​​the chip 110.

[0048] Furthermore, if a Cu pillar 10 is placed on top of the optical waveguide 112, the strain stress generated in the Cu pillar 10 after flip-chip mounting will affect the wavelength characteristics of the optical waveguide 112, which may also affect the performance of the optical circuit. Furthermore, even if an optical waveguide is present below the test pad 20, the stress from the cantilever probe during wafer-level automatic testing may damage the optical waveguide 112 and affect its characteristics, such as increasing loss. For this reason, the optical waveguide 112 cannot be placed below the Cu pillar 10 or the test pad 20.

[0049] Therefore, in the chip 110 of this embodiment, the optical waveguide 112 is arranged on the outer periphery of the chip 110, excluding the layers below the portions to which stress is applied (for example, the Cu pillars 10, the test pads 20, and the test pad window 102). As described above, according to the embodiment of the present application, it is possible to prevent a deterioration in the characteristics of the optical waveguide or the performance of the optical circuit, reduce the size of the chip 110, and provide an optical semiconductor integrated circuit or a semiconductor integrated circuit that is capable of wafer-level automatic testing using a test pad and a low-cost cantilever-type probe card. [Industrial Applicability]

[0050] According to the present disclosure, it is possible to provide an optical semiconductor integrated circuit or a semiconductor integrated circuit that can be subjected to wafer-level automatic inspection using a low-cost cantilever-type probe card. [Explanation of symbols]

[0051] 10 Cu pillars 11 Cu pillar pad 12 Solder 20 test pads 30, 50, 60, 70, 90, 100, 110 Chip (Optical semiconductor integrated substrate) 31 Semiconductor elements (photodiodes, optical modulators) 32 Optical input / output terminal (grating coupler) 33 Chip internal wiring 40 External circuit (or package board) 41 Pad 71 Cantilever type probe card 72 Cantilever probe 73 Optical Probe 101, 111 High frequency wiring 102 Test pad window 112 Optical waveguide

Claims

1. A test pattern, a Cu pillar pad formed on a semiconductor integrated substrate; a Cu pillar formed on the Cu pillar pad; a test pad formed on the semiconductor integrated substrate, the test pad being adjacent to or close to the Cu pillar pad and electrically coupled thereto, and providing an area for a cantilever-type probe to contact during wafer-level automatic testing; an optical waveguide formed between the Cu pillar pad and the test pad; Equipped with the test pattern is disposed near the outer periphery of the semiconductor integrated substrate, the test pad is formed on high-frequency wiring formed on the semiconductor integrated substrate, the high-frequency wiring couples the Cu pillar pad and a semiconductor element, and propagates high-frequency electrical signals between the Cu pillar and the semiconductor element; The test pattern, in which the high-frequency wiring between the Cu pillar pad and the test pad intersects with the optical waveguide.

2. the test pattern is disposed near the outer periphery of the semiconductor integrated substrate, 2. The test pattern according to claim 1, wherein the Cu pillar pads are arranged at positions closer to the outer periphery of the semiconductor integrated substrate than the test pads.

3. the test pattern is disposed near the outer periphery of the semiconductor integrated substrate, 2. The test pattern according to claim 1, wherein the test pads are arranged closer to the outer periphery of the semiconductor integrated substrate than the Cu pillar pads.

4. the test pattern is disposed near the outer periphery of the semiconductor integrated substrate, 2. The test pattern according to claim 1, wherein the Cu pillar pads and the test pads adjacent to or close to the Cu pillar pads and electrically coupled thereto are arranged parallel to the outer periphery of the semiconductor integrated substrate.

5. The test pattern according to claim 1 , a semiconductor element formed on the semiconductor integrated substrate; A semiconductor integrated circuit comprising:

6. The test pattern according to claim 1 ; an optical semiconductor element including an optical circuit formed on the semiconductor integrated substrate; An optical semiconductor integrated circuit comprising:

Images