Power MOSFET with Gate-Source ESD Diode Structure

Abstract

To provide a power metal oxide semiconductor field effect transistor (MOSFET) having a gate source electrostatic discharge (ESD) diode structure and a high voltage resistance and leakage prevention structure.SOLUTION: A power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, 706, a body having first and second body regions 802, 804, a source having first and second source regions 912, 914, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, 953, a gate contact plug 954, a gate source ESD diode structure 929 connected between the gate contact and the source contact, a source contact 962, a gate contact 964, a drain contact 966, and a body ring structure 820 formed under the gate source ESD diode structure, functioning as a high voltage resistance and leakage prevention structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION

[0001] Embodiments of the present invention relate to power metal oxide semiconductor field effect transistors (MOSFETs), and in particular embodiments, to power MOSFETs having a gate-source ESD diode structure and a high voltage and anti-leakage structure. [Background technology]

[0002]

[0002] As semiconductor technology evolves, power MOSFETs have been widely used in various industrial applications. A power MOSFET is a voltage-controlled device. When a control voltage is applied to the gate of a power MOSFET, and the control voltage is greater than the threshold voltage of the power MOSFET, a conductive channel is established between the drain and source of the power MOSFET. This allows current to flow between the drain and source of the power MOSFET. On the other hand, when the control voltage is less than the threshold voltage of the power MOSFET, the power MOSFET is turned off accordingly.

[0003]

[0003] Power MOSFETs can be divided into two main categories: n-channel power MOSFETs and p-channel power MOSFETs. According to their structure, power MOSFETs can be further divided into three subcategories: planar power MOSFETs, lateral power MOSFETs, and vertical power MOSFETs.

[0004]

[0004] Vertical power MOSFETs are widely used in high-voltage and high-current applications due to their low gate drive power, fast switching speed, and low on-resistance. In a vertical power MOSFET, the drain and source are located on opposite sides of the wafer. A trench structure may be formed between the drain and source of a vertical power MOSFET.

[0005]

[0005] The input / output terminals of a vertical power MOSFET must be protected from electrostatic discharge (ESD) voltages. For example, the gate of a vertical power MOSFET is a critical element. Excessive voltage at the gate relative to the source can result in breakdown and damage. To protect the gate of a vertical power MOSFET from ESD, a back-to-back ESD diode structure can be connected between the gate and source terminals of the vertical power MOSFET. The back-to-back ESD diode structure may be implemented as an array of alternating doped p and n+ regions. For example, the array can include a cascade-connected first p-type region, a first n+ region, a second p-type region, a second n+ region, and a third p-type region. Alternatively, the array can include a cascade-connected first n+ region, a first p-type region, a second n+ region, a second p-type region, and a third n+ region. The p-n+ structure is a common configuration for ESD protection diodes. The p-n+ structure helps create a structure that has a low breakdown voltage, making the ESD diode structure suitable for clamping and diverting excessive voltage during an ESD event, thereby preventing the gate of the vertical power MOSFET from being damaged. Summary of the Invention

[0006] These and other problems are generally solved or avoided, and technical advantages are generally achieved, by preferred embodiments of the present disclosure which provide a power MOSFET having a gate-source ESD diode structure and a high voltage and anti-leakage structure.

[0007]

[0007] According to one embodiment, the device comprises a drain and a source on opposite sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode structure connected between the gate contact and the source contact, and a high-voltage and leakage-proof structure formed below the gate-source ESD diode structure.

[0008]

[0008] According to another embodiment, a method includes growing an epitaxial layer on a substrate, forming a plurality of gates in the epitaxial layer, forming a body region and a high voltage withstand and anti-leakage structure in the epitaxial layer, forming a source in the epitaxial layer and a gate-source ESD diode structure on the epitaxial layer, and forming a source contact connected to first terminals of the source and gate-source ESD diode structures and a gate contact connected to second terminals of the plurality of gate and gate-source ESD diode structures.

[0009]

[0009] According to yet another embodiment, a power MOSFET includes an epitaxial layer over a substrate, a plurality of gates formed in the epitaxial layer, a body region formed in the epitaxial layer, a source formed in the body region, a gate-source ESD diode structure formed on the epitaxial layer, a body ring structure formed in the epitaxial layer below the gate-source ESD diode structure, an interlayer insulating layer formed on the epitaxial layer, the interlayer insulating layer having the gate-source ESD diode structure within the interlayer insulating layer, a plurality of source contact plugs, at least one of the plurality of source contact plugs extending through the interlayer insulating layer, the source and partially through the body region, a gate contact plug extending partially through the interlayer insulating layer, a gate contact connected to first terminals of the plurality of gates and gate-source ESD diode structures via the gate contact plug, and a source contact connected to the source, the body region, and a second terminal of the gate-source ESD diode structure via the plurality of source contact plugs.

[0010] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure will be described hereinafter which form the subject of the claims of the present disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims.

[0011] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates a cross-sectional view of a power MOSFET having a gate-source ESD diode structure and a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. [Figure 2] 1A-1C illustrate cross-sectional views of a semiconductor device after growing an epitaxial layer from a substrate according to various embodiments of the present disclosure. [Figure 3] 3 illustrates a cross-sectional view of the semiconductor device shown in FIG. 2 after an etching process is performed on the hard mask layer to define a pattern in the hard mask layer, according to various embodiments of the present disclosure. [Figure 4] 4 illustrates a cross-sectional view of the semiconductor device shown in FIG. 3 after three trenches have been formed in the epitaxial layer according to various embodiments of the present disclosure. [Figure 5] 5 illustrates a cross-sectional view of the semiconductor device shown in FIG. 4 after a thin dielectric layer has been formed in the trench and over the epitaxial layer in accordance with various embodiments of the present disclosure. [Figure 6] 6 illustrates a cross-sectional view of the semiconductor device shown in FIG. 5 after a gate electrode material has been filled into the trench according to various embodiments of the present disclosure. [Figure 7]7 illustrates a cross-sectional view of the semiconductor device shown in FIG. 6 after an etch-back process has been applied to the top surface shown in FIG. 6 according to various embodiments of the present disclosure. [Figure 8] 8 illustrates a cross-sectional view of the semiconductor device shown in FIG. 7 after a body region and a body ring structure have been formed in the epitaxial layer according to various embodiments of the present disclosure. [Figure 9] 9 illustrates a cross-sectional view of the semiconductor device shown in FIG. 8 after an ESD bottom dielectric layer and an ESD layer are formed on the epitaxial layer according to various embodiments of the present disclosure. [Figure 10] 10 illustrates a cross-sectional view of the semiconductor device shown in FIG. 9 after an anisotropic etching process is applied to the ESD bottom dielectric layer and the ESD layer according to various embodiments of the present disclosure. [Figure 11] 11 illustrates a cross-sectional view of the semiconductor device shown in FIG. 10 after a source region has been formed over the body region and an n+ region has been formed in the ESD layer according to various embodiments of the present disclosure. [Figure 12] 12 illustrates a cross-sectional view of the semiconductor device shown in FIG. 11 after a dielectric layer has been formed over the epitaxial layer according to various embodiments of the present disclosure. [Figure 13] 13 illustrates a cross-sectional view of the semiconductor device shown in FIG. 12 after an anisotropic etching process is applied to the dielectric layer to form a plurality of trenches, according to various embodiments of the present disclosure. [Figure 14] 14 illustrates a cross-sectional view of the semiconductor device shown in FIG. 13 after p+ regions have been formed at the bottom of each trench according to various embodiments of the present disclosure. [Figure 15] 15 illustrates a cross-sectional view of the semiconductor device shown in FIG. 14 after a metal material has filled the trenches of the semiconductor device according to various embodiments of the present disclosure. [Figure 16] 16 illustrates a cross-sectional view of the semiconductor device shown in FIG. 15 after source and gate contacts have been formed according to various embodiments of the present disclosure. [Figure 17] 1 shows a cross-sectional view of a second embodiment of a high pressure and leak-proof structure according to various embodiments of the present disclosure. [Figure 18]10 shows a cross-sectional view of a third embodiment of a high pressure and leak-proof structure according to various embodiments of the present disclosure. [Figure 19] 10 shows a cross-sectional view of a fourth embodiment of a high pressure resistance and leak prevention structure according to various embodiments of the present disclosure. [Figure 20] 2 illustrates a cross-sectional view of a semiconductor device after the gate is covered by a dielectric layer according to various embodiments of the present disclosure. [Figure 21] 21 illustrates a cross-sectional view of the semiconductor device shown in FIG. 20 after a body region has been formed in the epitaxial layer according to various embodiments of the present disclosure. [Figure 22] 22 illustrates a cross-sectional view of the semiconductor device shown in FIG. 21 after a first n-type well has been formed within the first p-type well, according to various embodiments of the present disclosure. [Figure 23] 23 illustrates a cross-sectional view of the semiconductor device shown in FIG. 22 after a second p-type well has been formed in the first n-type well, according to various embodiments of the present disclosure. [Figure 24] 24 illustrates a cross-sectional view of the semiconductor device shown in FIG. 23 after a second n-type well is formed in the p-type well according to various embodiments of the present disclosure. [Figure 25] 10 shows a cross-sectional view of a fifth embodiment of a high pressure resistance and leak prevention structure according to various embodiments of the present disclosure. [Figure 26] 10 shows a cross-sectional view of a sixth embodiment of a high pressure resistance and leak prevention structure according to various embodiments of the present disclosure. [Figure 27] 10 shows a cross-sectional view of a seventh embodiment of a high pressure resistance and leak prevention structure according to various embodiments of the present disclosure. [Figure 28] 10 shows a cross-sectional view of an eighth embodiment of a high pressure resistance and leak prevention structure according to various embodiments of the present disclosure. [Figure 29] 10 shows a cross-sectional view of a ninth embodiment of a high pressure resistance and leak prevention structure according to various embodiments of the present disclosure. [Figure 30] 2 shows a flowchart of a method for fabricating the power MOSFET shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 31]17A-17C illustrate cross-sectional views and top views of body ring structures of the power MOSFET shown in FIG. 16 according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0043] Corresponding numbers and symbols in different drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale.

[0014]

[0044] The making and use of presently preferred embodiments are described in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the disclosure and do not limit the scope of the disclosure.

[0015]

[0045] The present disclosure will be described in terms of preferred embodiments in a particular context, namely, a power MOSFET having a gate-source ESD diode structure and a high-voltage and leakage-resistant structure. However, the present disclosure can also be applied to various power transistors. Various embodiments will be described in detail hereinafter with reference to the accompanying drawings.

[0016]

[0046] 1 illustrates a cross-sectional view of a power MOSFET having a gate-source ESD diode structure and a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, and 706, a body including a first body region 802 and a second body region 804, a source including a first source region 912 and a second source region 914, a body ring structure 820, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, and 953, a gate contact plug 954, a gate-source ESD diode structure 929, a source contact 962, a gate contact 964, and a drain contact 966.

[0017]

[0047] As shown in Figure 1, an epitaxial layer 104 is formed on a substrate 102. A plurality of gates 702, 704, and 706 are formed in the epitaxial layer 104. A first body region 802 is formed in the epitaxial layer 104 between gate 702 and gate 704. A second body region 804 is formed in the epitaxial layer 104 between gate 704 and gate 706. It should be noted that although body regions 802 and 804 may be two separate regions from the cross-sectional view shown in Figure 1, body regions 802 and 804 may be part of a continuous body region from a top view.

[0018]

[0048] 1, a first source region 912 is formed in the first body region 802 between the gates 702 and 704. A second source region 914 is formed in the second body region 804 between the gates 704 and 706. It should be noted that although the source regions 912 and 914 may be two separate regions from the cross-sectional view shown in FIG. 1, the source regions 912 and 914 may also be part of a continuous source region from a top view.

[0019]

[0049] An interlayer insulating layer 920 is formed over the epitaxial layer 104. A gate-source ESD diode structure 929 is formed in the interlayer insulating layer 920 over the epitaxial layer. The gate-source ESD diode structure 929 comprises a plurality of alternating n+ regions and a plurality of p-type regions. In some embodiments, the gate-source ESD diode structure 929 comprises a cascaded first p-type region 921, a first n+ region 922, a second p-type region 923, a second n+ region 924, and a third p-type region 925. The first p-type region 921 is connected to a gate contact 964. The third p-type region 925 is connected to a source contact 962.

[0020]

[0050] Body ring structure 820 is formed in epitaxial layer 104 below gate-source ESD diode structure 929. From the cross-sectional view shown in FIG. 1 , body ring structure 820 comprises four pillars 822, 824, 826, and 828. In some embodiments, body ring structure 820 is a concentric ring structure formed in epitaxial layer 104 from a top view.

[0021]

[0051] The body ring structure 820 functions as a high breakdown voltage and anti-leakage structure. In operation, the body ring structure 820 is configured to distribute the electric field over the gate-source ESD diode structure 929. The body ring structure 820 provides an electric field gradient that reduces the peak electric field at the edges of the gate-source ESD diode structure 929, thereby spreading the electric field more evenly. As a result, the breakdown voltage of the power MOSFET 100 can be improved and the leakage of the power MOSFET 100 can be reduced.

[0022]

[0052] 1 , source contact plug 951 extends through interlayer insulating layer 920, first source region 912, and partially through first body region 802. A first terminal of source contact plug 951 is connected to source contact 962. A second terminal of source contact plug 951 is connected to first p+ region 942 formed in first body region 802.

[0023]

[0053] A source contact plug 952 extends through the interlayer insulating layer 920, the second source region 914, and partially through the second body region 804. A first terminal of the source contact plug 952 is connected to a source contact 962. A second terminal of the source contact plug 952 is connected to a second p+ region 944 formed in the second body region 804.

[0024]

[0054] A source contact plug 953 extends partially through interlayer insulating layer 920 and partially through third p-type region 925. A first terminal of source contact plug 953 is connected to source contact 962. A second terminal of source contact plug 953 is connected to fourth p+ region 948 formed in third p-type region 925.

[0025]

[0055] A gate contact plug 954 extends partially through the interlayer insulating layer 920 and partially through the first p-type region 921. A first terminal of the gate contact plug 954 is connected to a gate contact 964. A second terminal of the gate contact plug 954 is connected to a third p+ region 946 formed in the first p-type region 921.

[0026]

[0056] In some embodiments, the power MOSFET shown in FIG. 1 can be implemented as an n-type power MOSFET. The substrate 102 is an n+ substrate. The epitaxial layer 104 is an n-type layer. The doping concentration of the epitaxial layer 104 is lower than the doping concentration of the substrate 102. The body region is a p-type region. The source is an n+ region. The body ring structure 820 is a p-type body ring structure. The n-type regions (e.g., source regions 912 and 914) in FIG. 1 are formed by implanting n-type dopants such as phosphorus, arsenic, etc. Alternatively, the n-type regions can be formed by a diffusion process. The p-type regions (e.g., body regions 802 and 804) in FIG. 1 are formed by implanting p-type doping materials such as boron, gallium, aluminum, indium, or combinations thereof. Alternatively, the p-type regions can be formed by a diffusion process.

[0027]

[0057] 1 can be implemented as a p-type power MOSFET. Substrate 102 is a p+ substrate. Epitaxial layer 104 is a p-type layer. The doping concentration of epitaxial layer 104 is lower than the doping concentration of substrate 102. The body region is an n-type region. The source is a p+ region. Body ring structure 820 is an n-type body ring structure.

[0028]

[0058] 1, the drain contact 966 is formed below the substrate 102. In other words, the source contact 962 and the drain contact 966 of the power MOSFET 100 are fabricated on both sides of the wafer.

[0029]

[0059] 2-16 illustrate cross-sectional views of intermediate steps in fabricating the power MOSFET shown in FIG. 1 according to various embodiments of the present disclosure.

[0030]

[0060] 2 shows a cross-sectional view of a semiconductor device after growing epitaxial layers from a substrate according to various embodiments of the present disclosure. According to one embodiment, the substrate 102 may be an n+ substrate doped with n-type impurities such as phosphorus, arsenic, etc.

[0031]

[0061] An n-type epitaxial layer 104 is grown from the substrate 102. The epitaxial growth of the n-type epitaxial layer 104 can be performed by using a suitable semiconductor manufacturing process such as chemical vapor deposition (CVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), or the like.

[0032]

[0062] 3 illustrates a cross-sectional view of the semiconductor device shown in FIG. 2 after an etching process has been performed on the hard mask layer to define a pattern in the hard mask layer, according to various embodiments of the present disclosure. According to one embodiment, a hard mask layer 106 is deposited on the epitaxial layer 104 using a suitable fabrication technique, such as CVD. The hard mask layer 106 may be formed of a suitable material, such as silicon nitride. The hard mask layer 106 functions as an etch mask.

[0033]

[0063] A photoresist layer 108 is formed on the hard mask layer 106, for example by spin coating. The photoresist layer 108 is patterned using an appropriate photolithography technique. The hard mask layer 106 is then patterned to take into account the locations of the gates 702, 704, and 706 of the power MOSFET 100 shown in FIG.

[0034]

[0064] FIG. 4 illustrates a cross-sectional view of the semiconductor device shown in FIG. 3 after three trenches have been formed in the epitaxial layer according to various embodiments of the present disclosure. The remaining photoresist layer 108 shown in FIG. 3 can be removed by using an appropriate photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, or dry stripping. Photoresist stripping techniques are well known and therefore will not be described in further detail herein to avoid repetition. An etching process, such as reactive ion etching (RIE) or other dry etching, anisotropic wet etching, or any other suitable anisotropic etching or patterning process, is then performed to form three trenches, namely, a first trench 402, a second trench 404, and a third trench 406, in the epitaxial layer 104, as shown in FIG. 4.

[0035]

[0065] 5 illustrates a cross-sectional view of the semiconductor device shown in FIG. 4 after a thin dielectric layer has been formed in the trenches and over the epitaxial layer in accordance with various embodiments of the present disclosure. As shown in FIG. 5, the hard mask layer 106 shown in FIG. 4 has been removed by a suitable hard mask layer removal process, such as a wet etching process. The removal process is performed on the top surface of the semiconductor device until the epitaxial layer 104 is exposed.

[0036]

[0066] The thin dielectric layer 502 is a gate dielectric layer. As shown in Figure 5, the thin dielectric layer 502 is formed on the bottom and sidewalls of the trenches 402, 404, and 406. The thin dielectric layer 502 can be formed of commonly used dielectric materials such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multilayers thereof.

[0037]

[0067] According to one embodiment, the thin dielectric layer 502 is an oxide layer. The thin dielectric layer 502 can be formed by using a suitable thermal processing technique, wet processing technique, or deposition technique such as physical vapor deposition (PVD), CVD, atomic layer deposition (ALD), etc.

[0038]

[0068] 6 illustrates a cross-sectional view of the semiconductor device shown in FIG. 5 after gate electrode material has been filled into the trenches in accordance with various embodiments of the present disclosure. The gate electrode material has been filled into trenches 402, 404, and 406. The gate electrode material also forms a gate electrode layer 602 on epitaxial layer 104.

[0039]

[0069] In some embodiments, the gate electrode material is polysilicon. According to one embodiment, the polysilicon layer is doped with n-type impurity ions to form a gate conductive layer. Phosphorus was used as the n-type impurity ion, but other n-type conductive ions may be used if necessary or desired. The doping of the n-type impurity ions in the polysilicon layer is preferably performed by a separate n-type impurity ion doping process after the polysilicon layer is deposited, or by depositing the polysilicon layer while doping with n-type impurity ions.

[0040]

[0070] The polysilicon layer is subjected to an annealing process. The annealing process is used to diffuse n-type impurity ions into the polysilicon layer. The annealing process can be performed as a rapid thermal process.

[0041]

[0071] 7 illustrates a cross-sectional view of the semiconductor device shown in FIG. 6 after an etch-back process is performed on the top surface shown in FIG. 6 according to various embodiments of the present disclosure. A planarization process, such as a chemical mechanical polishing (CMP) or etch-back process, may be performed to planarize the top surface of the gate electrode layer 602 until a thin dielectric layer is exposed. A polysilicon oxidation process is then performed to form a dielectric layer 710 covering the polysilicon material in the trench. As shown in FIG. 7 , three gates, namely, a first gate 702, a second gate 704, and a third gate 706, may be formed in the epitaxial layer after the CMP process.

[0042]

[0072] FIG. 8 illustrates a cross-sectional view of the semiconductor device shown in FIG. 7 after body regions and a body ring structure have been formed in the epitaxial layer according to various embodiments of the present disclosure. A photoresist layer 812 is formed on the top surface of the semiconductor device using a spin-on method or the like. The photoresist layer 812 is patterned using appropriate photolithography techniques, taking into account the location of the body ring structure in the power MOSFET 100 shown in FIG. 1 . The body regions 802 and 804 and the body ring structure 820 may be formed on top of the epitaxial layer 104. According to one embodiment, the body regions 802 and 804 and the body ring structure 820 may be formed by implanting an appropriate p-type dopant, such as boron, gallium, or indium.

[0043]

[0073] In some embodiments, body ring structure 820 is a concentric ring structure from a top view. As shown in cross section, body ring structure 820 has four pillars 822, 824, 826, and 828. In some embodiments, the bottom surface of body ring structure 820 is flush with the bottom surfaces of body regions 802 and 804, as shown in FIG.

[0044]

[0074] In operation, the body ring structure 820 functions as a pressure-tight and leak-proof structure, the function of which is described below with respect to FIG.

[0045]

[0075] 9 illustrates a cross-sectional view of the semiconductor device shown in FIG. 8 after an ESD bottom dielectric layer and an ESD layer have been formed on the epitaxial layer according to various embodiments of the present disclosure. The remaining photoresist layer 812 shown in FIG. 8 can be removed by using an appropriate photoresist stripping technique. An ESD bottom dielectric layer 902 is then deposited on the top surface of the semiconductor device using an appropriate deposition technique, such as PVD, CVD, or ALD. The ESD bottom dielectric layer 902 may be formed of commonly used dielectric materials, such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multilayers thereof.

[0046]

[0076] An ESD layer 904 is deposited on the ESD bottom dielectric layer 902. The ESD layer 904 may be formed of polysilicon. According to one embodiment, the ESD layer 904 is doped with p-type impurity ions, such as boron. The doping of the ESD layer 904 with p-type impurity ions is preferably performed by a separate p-type impurity ion doping process after the deposition of the ESD layer 904, or by depositing the ESD layer 904 while doping it with p-type impurity ions.

[0047]

[0077] 10 illustrates a cross-sectional view of the semiconductor device shown in FIG. 9 after an anisotropic etching process has been performed on the ESD bottom dielectric layer and the ESD layer in accordance with various embodiments of the present disclosure. The semiconductor device has been subjected to an etching process. As shown in FIG. 10, portions of the ESD bottom dielectric layer and the ESD layer above gates 702, 704, and 706 have been removed as a result.

[0048]

[0078] 11 illustrates a cross-sectional view of the semiconductor device shown in FIG. 10 after a source region has been formed on the body region and an n+ region has been formed in the ESD layer according to various embodiments of the present disclosure. As shown in FIG. 11, n+ regions 912 and 914 are formed on the body regions 802 and 804, respectively, by an appropriate fabrication process, such as an ion implantation process. According to one embodiment, n+ regions 912 and 914 can function as source regions for the power MOSFET 100 shown in FIG. 1. Simultaneously, n+ regions 922 and 924 are formed in the ESD layer 904 shown in FIG. 10. The n+ regions are formed by implanting an appropriate n-type dopant, such as phosphorus or arsenic.

[0049]

[0079] 9, when ESD layer 904 is doped with p-type impurity ions, ESD layer 904 is a p-type layer. Because n+ regions 922 and 924 are formed in ESD layer 904, three p-type regions 921, 923, and 925 are formed in ESD layer 904.

[0050]

[0080] 11, first p-type region 921, first n+ region 922, second p-type region 923, second n+ region 924, and third p-type region 925 are cascaded together. First p-type region 921, first n+ region 922, second p-type region 923, second n+ region 924, and third p-type region 925 form a gate-source ESD diode structure 929.

[0051]

[0081] As shown in FIG. 11 , n+ and p-type regions are alternately formed. The n+ and p-type regions form a back-to-back ESD diode structure. The arrangement of the n+ and p-type regions described above is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, the back-to-back ESD diode structure can include a cascaded first n+ region, a first p-type region, a second n+ region, a second p-type region, and a third n+ region.

[0052]

[0082] 11 , the gate-source ESD diode structure 929 and the body ring structure 820 are separated by the ESD bottom dielectric layer 902. The body ring structure 820 is configured to distribute the electric field over the gate-source ESD diode structure 929. The body ring structure 820 provides an electric field gradient that reduces the peak electric field at the edges of the gate-source ESD diode structure 929, thereby spreading the electric field more evenly. As a result, the body ring structure 820 can improve the performance of the power MOSFET 100.

[0053]

[0083] FIG. 12 illustrates a cross-sectional view of the semiconductor device shown in FIG. 11 after a dielectric layer has been formed over the epitaxial layer according to various embodiments of the present disclosure. The dielectric layer 920 is deposited over the epitaxial layer 104. The dielectric layer 920 may alternatively be referred to as an interlayer dielectric (ILD) layer. The dielectric layer 920 may be a low-k dielectric layer having a low dielectric constant, for example, less than about 3.5. The dielectric layer 920 may also comprise a combination of materials, such as silicon nitride, silicon oxynitride, high-k dielectrics, low-k dielectrics, CVD polysilicon, or other dielectrics. The dielectric layer 920 may be deposited using any suitable deposition technique, such as sputtering, CVD, or the like.

[0054]

[0084] 13 illustrates a cross-sectional view of the semiconductor device shown in FIG. 12 after an anisotropic etching process is performed on the dielectric layer to form a plurality of trenches, in accordance with various embodiments of the present disclosure. By etching the dielectric layer 920 and the area below the dielectric layer 920, a plurality of trenches 932, 934, 936, and 938 are formed.

[0055]

[0085] 13 , trench 932 extends through dielectric layer 920, source region 912, and partially through body region 802. Similarly, trench 934 extends through dielectric layer 920, source region 914, and partially through body region 804. Trench 936 extends partially through dielectric layer 920 and partially through first p-type region 921. Trench 938 extends partially through dielectric layer 920 and partially through third p-type region 925.

[0056]

[0086] 14 illustrates a cross-sectional view of the semiconductor device shown in FIG. 13 after p+ regions have been formed at the bottom of each trench, according to various embodiments of the present disclosure. A suitable implantation process, such as a blanket ion implantation, is performed. P-type impurity ions, such as boron ions, are implanted into body regions 802 and 804, first p-type region 921, and third p-type region 925. Thus, four p+ regions 942, 944, 946, and 948 are formed within the trenches, respectively, as shown in FIG. 14. P+ regions 942, 944, 946, and 948 are specifically designed to further reduce contact resistance.

[0057]

[0087] 15 illustrates a cross-sectional view of the semiconductor device shown in FIG. 14 after a metal material has been filled into the trenches of the semiconductor device in accordance with various embodiments of the present disclosure. A metal material including tungsten, titanium, aluminum, copper, any combination thereof, or the like is filled into trenches 932, 934, 936, and 938 to form contact plugs 951, 952, 953, and 954. The metal material on top of interlayer insulating layer 920 forms metal contact layer 950.

[0058]

[0088] 16 illustrates a cross-sectional view of the semiconductor device shown in FIG. 15 after source and gate contacts have been formed, according to various embodiments of the present disclosure. Considering the locations of the source and gate contacts in the power MOSFET 100 shown in FIG. 1, the metal contact layer 950 is patterned using an appropriate etching technique.

[0059]

[0089] 16 , first source contact plug 951 has a first terminal connected to source contact 962 and a second terminal connected to first source region 912, p+ region 942, and first body region 802. Second source contact plug 952 has a first terminal connected to source contact 962 and a second terminal connected to second source region 914, p+ region 944, and second body region 804. Gate contact plug 954 has a first terminal connected to gate contact 964 and a second terminal connected to p+ region 946 and a first terminal of gate-source ESD diode structure 929. Third source contact plug 953 has a first terminal connected to source contact 962 and a second terminal connected to p+ region 948 and a second terminal of gate-source ESD diode structure 929.

[0060]

[0090] 17 illustrates a cross-sectional view of a second embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure for power MOSFET 200 is implemented as a body ring structure 820 as shown in FIG. 17. Body ring structure 820 shown in FIG. 17 is similar to that shown in FIG. 16 except that body ring structure 820 shown in FIG. 17 has five pillars 822, 824, 825, 826, and 828.

[0061]

[0091] In some embodiments, one sidewall of pillar 822 is vertically aligned with one sidewall of first p-type region 921. One sidewall of pillar 824 is vertically aligned with one sidewall of first n+ region 922. One sidewall of pillar 825 is vertically aligned with one sidewall of second p-type region 923. One sidewall of pillar 826 is vertically aligned with one sidewall of second n+ region 924. One sidewall of pillar 828 is vertically aligned with one sidewall of third p-type region 925.

[0062]

[0092] While FIG. 17 illustrates a pressure-resistant and leak-proof structure having five posts 822, 824, 825, 826, and 828, it should be appreciated that the pressure-resistant and leak-proof structure can accommodate any number of posts.

[0063]

[0093] 18 illustrates a cross-sectional view of a third embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure for power MOSFET 300 is implemented as a body ring structure 820 as shown in FIG. 18. Body ring structure 820 illustrated in FIG. 18 is similar to that illustrated in FIG. 16, except that four pillars 822, 824, 826, and 828 of body ring structure 820 are vertically aligned with the respective ESD diode regions.

[0064]

[0094] In some embodiments, one sidewall of pillar 822 is vertically aligned with a first sidewall of first n+ region 922. One sidewall of pillar 824 is vertically aligned with a second sidewall of first n+ region 922. One sidewall of pillar 826 is vertically aligned with a first sidewall of second n+ region 924. One sidewall of pillar 828 is vertically aligned with a second sidewall of second n+ region 924.

[0065]

[0095] 19 illustrates a cross-sectional view of a fourth embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure of power MOSFET 400 includes alternating n-type wells 974, 976 and p-type wells 973, 975. The n-type wells and p-type wells are configured to distribute an electric field over gate-source ESD diode structure 929. As shown in FIG. 19, the n-type wells and p-type wells are separated from gate-source ESD diode structure 929 by a dielectric layer.

[0066]

[0096] The pnpnp well structure shown in FIG. 19 can achieve a higher level of reliability and durability in the power MOSFET 400, thereby improving the ESD protection design.

[0067]

[0097] The above-described n-well and p-well arrangement is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, an npnpn well structure could be used to replace the well structure shown in FIG. 19. The npnpn well structure completely covers the area under the gate-source ESD diode structure 929. This features multiple pn diodes that improve the electrical characteristics of the power MOSFET 400 and provide greater protection against ESD events.

[0068]

[0098] 20-24 illustrate cross-sectional views of intermediate steps in fabricating the pressure-resistant and leak-proof structure shown in FIG. 19, according to various embodiments of the present disclosure.

[0069]

[0099] 20 shows a cross-sectional view of a semiconductor device after the gate is covered by a dielectric layer according to various embodiments of the present disclosure. The cross-sectional view shown in FIG. 20 is similar to the cross-sectional view shown in FIG. 7 and therefore will not be described again herein to avoid repetition.

[0070]

[0100] 21 illustrates a cross-sectional view of the semiconductor device shown in FIG. 20 after body regions have been formed in the epitaxial layer according to various embodiments of the present disclosure. Body regions 971, 972, and 973 are p-type regions. P-type regions 971, 972, and 973 are formed in epitaxial layer 104 by a suitable semiconductor doping technique, such as an ion implantation process. In some embodiments, epitaxial layer 104 is implanted with a suitable p-type dopant, such as boron, gallium, or indium, to form body regions 971, 972, and 973. Body region 973 is alternatively referred to as a first p-type well.

[0071]

[0101] 22 illustrates a cross-sectional view of the semiconductor device shown in FIG. 21 after a first n-type well 974 has been formed in the first p-type well 974, according to various embodiments of the present disclosure. A photoresist layer 991 is deposited on the semiconductor device using a spin-on method or the like. The photoresist layer 991 is exposed and developed such that only the portion above the first n-type well 974 is removed.

[0072]

[0102] The first n-type well 974 is formed by implanting an n-type dopant such as phosphorus or arsenic. Alternatively, the first n-type well 974 can be formed by a diffusion process. As shown in Figure 22, the first n-type well 974 is surrounded by the first p-type well 973.

[0073]

[0103] 23 illustrates a cross-sectional view of the semiconductor device shown in FIG. 22 after a second p-type well 975 has been formed in the first n-type well 975, according to various embodiments of the present disclosure. A photoresist layer 992 is deposited on the semiconductor device using a spin-on method or the like. The photoresist layer 992 is exposed and developed such that only the portion above the second p-type well 975 is removed.

[0074]

[0104] The second p-type well 975 is formed by implanting a p-type dopant, such as boron, gallium, aluminum, or indium. Alternatively, the second p-type well 975 can be formed by a diffusion process. As shown in Figure 23, the second p-type well 975 is surrounded by the first n-type well 974.

[0075]

[0105] 24 illustrates a cross-sectional view of the semiconductor device shown in FIG. 23 after a second n-type well 976 has been formed in the p-type well, according to various embodiments of the present disclosure. A photoresist layer 993 is deposited on the semiconductor device using a spin-on method or the like. The photoresist layer 993 is exposed and developed such that only the portion above the second n-type well 976 is removed.

[0076]

[0106] The second n-type well 976 is formed by implanting an n-type dopant such as phosphorus, arsenic, etc. Alternatively, the second n-type well 976 can be formed by a diffusion process. As shown in Figure 24, the second n-type well 976 is surrounded by the second p-type well 975.

[0077]

[0107] Those skilled in the art will recognize that Figure 24 shows an ideal profile. The dimensions of the well may change after subsequent manufacturing steps.

[0078]

[0108] 25 shows a cross-sectional view of a fifth embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure of the power MOSFET 500 includes two alternating n-type wells 981, 983 and one p-type well 982. The n-type wells and p-type wells are configured to distribute an electric field over the gate-source ESD diode structure 929. The n-type wells and p-type wells and the gate-source ESD diode structure 929 are separated by a dielectric layer.

[0079]

[0109] 25, a first n-type well 981 is formed in the epitaxial layer 104. A first p-type well 982 is formed in the first n-type well 981. The width of the first p-type well 982 is equal to the width of the first n-type well 981. A second n-type well 983 is formed in the first p-type well 982. The width of the second n-type well 983 is equal to the width of the first p-type well 982.

[0080]

[0110] While FIG. 25 shows a high pressure and leak-proof structure having three wells 981, 982 and 983, it should be understood that the high pressure and leak-proof structure can contain any number of wells arranged in an alternating pattern.

[0081]

[0111] 26 illustrates a cross-sectional view of a sixth embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure of power MOSFET 600 is a reduced surface field (RESURF) structure 990. The RESURF structure is a well-known mechanism for improving the breakdown voltage of high-voltage MOSFETs.

[0082]

[0112] 26, a RESURF structure 990 is disposed below the gate-source ESD diode structure 929. The RESURF structure 990 and the gate-source ESD diode structure 929 are separated by a dielectric layer. The RESURF structure 990 helps distribute the electric field over the gate-source ESD diode structure 929, thereby reducing the risk of electrical breakdown and leakage.

[0083]

[0113] 27 illustrates a cross-sectional view of a seventh embodiment of a high voltage and anti-leakage structure according to various embodiments of the present disclosure. The high voltage and anti-leakage structure of the power MOSFET 700 includes a RESURF structure 990 and a body ring structure 820.

[0084]

[0114] The RESURF structure 990 and the body ring structure 820 are configured to distribute an electric field over the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The RESURF structure 990 and the gate-source ESD diode structure 929 are separated by a dielectric layer. As shown in FIG. 27 , the RESURF structure 990 is between the gate-source ESD diode structure 929 and the body ring structure 820.

[0085]

[0115] 28 illustrates a cross-sectional view of an eighth embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure of a power MOSFET 800 includes multiple n-type wells, multiple p-type wells, and a body ring structure 820. The multiple n-type wells and multiple p-type wells illustrated in FIG. 28 are similar to those illustrated in FIG. 19 and therefore will not be described again herein.

[0086]

[0116] The multiple n-type wells and the multiple p-type wells are arranged alternately. The multiple n-type wells, the multiple p-type wells, and the body ring structure 820 are configured to distribute an electric field over the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The multiple n-type wells and the multiple p-type wells and the gate-source ESD diode structure 929 are separated by a dielectric layer. The multiple n-type wells and the multiple p-type wells are between the gate-source ESD diode structure 929 and the body ring structure 820.

[0087]

[0117] 29 illustrates a cross-sectional view of a ninth embodiment of a high-voltage and anti-leakage structure according to various embodiments of the present disclosure. The high-voltage and anti-leakage structure of a power MOSFET 900 includes multiple n-type wells, multiple p-type wells, and a body ring structure 820. The multiple n-type wells and multiple p-type wells illustrated in FIG. 29 are similar to those illustrated in FIG. 25 and therefore will not be described again herein.

[0088]

[0118] The multiple n-type wells and the multiple p-type wells are arranged alternately. The multiple n-type wells, the multiple p-type wells, and the body ring structure 820 are configured to distribute an electric field over the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The multiple n-type wells and the multiple p-type wells and the gate-source ESD diode structure are separated by a dielectric layer. As shown in FIG. 29 , the multiple n-type wells and the multiple p-type wells are between the gate-source ESD diode structure 929 and the body ring structure 820.

[0089]

[0119] 30 illustrates a flowchart of a method for fabricating the power MOSFET shown in FIG. 1 according to various embodiments of the present disclosure. This flowchart illustrated in FIG. 30 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, various steps illustrated in FIG. 30 may be added, deleted, substituted, rearranged, and repeated.

[0090]

[0120] In step 3002, an epitaxial layer is grown on a substrate.

[0091]

[0121] In step 3004, a plurality of gates are formed in the epitaxial layer.

[0092]

[0122] In step 3006, a body region and high voltage and leakage protection structures are formed in the epitaxial layer.

[0093]

[0123] In step 3008, a source is formed in the epitaxial layer and a gate-source ESD diode structure is formed on the epitaxial layer.

[0094]

[0124] In step 3010, a source contact is formed to connect to a first terminal of the source and gate-source ESD diode structure, and a gate contact is formed to connect to a second terminal of the plurality of gate and gate-source ESD diode structures.

[0095]

[0125] Forming the high breakdown voltage and anti-leakage structure in the epitaxial layer includes forming a RESURF structure by an implantation process, the RESURF structure being on top of the epitaxial layer, and the RESURF structure and the gate-source ESD diode structure being separated by a dielectric layer.

[0096]

[0126] The step of forming the high breakdown voltage and anti-leakage structure in the epitaxial layer includes forming a body ring structure by an implantation process, where the body ring structure is a concentric ring structure and the body ring structure and the gate-source ESD diode structure are separated by a dielectric layer.

[0097]

[0127] The step of forming the high breakdown voltage and anti-leakage structure in the epitaxial layer includes the steps of forming a first p-type well in the epitaxial layer, forming a first n-type well in the first p-type well, where the first n-type well is surrounded by the first p-type well, forming a second p-type well in the first n-type well, where the second p-type well is surrounded by the first n-type well, and forming a second n-type well in the second p-type well, where the second n-type well is surrounded by the second p-type well.

[0098]

[0128] The step of forming the high breakdown voltage and anti-leakage structure in the epitaxial layer includes the steps of forming a first n-type well in the epitaxial layer, forming a first p-type well in the first n-type well, where the width of the first p-type well is equal to the width of the first n-type well, and forming a second n-type well in the first p-type well, where the width of the second n-type well is equal to the width of the first p-type well.

[0099]

[0129] Forming the gate-source ESD diode structure on the epitaxial layer includes forming alternating n-type regions and p-type regions in an interlayer insulating layer on the epitaxial layer.

[0100]

[0130] The method further includes forming an interlayer insulating layer over the epitaxial layer; forming a plurality of trenches in the interlayer insulating layer; forming a plurality of p+ regions at the bottom of each trench; performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs and gate contact plugs; and forming the source contacts and gate contacts by an etching process.

[0101]

[0131] FIG. 31 illustrates a cross-sectional view of the power MOSFET shown in FIG. 16 and a top view of the body ring structure according to various embodiments of the present disclosure. The cross-sectional view is taken along line A-A′. The cross-sectional view of the power MOSFET has been described above with reference to FIGS. 1 and 16 , and will not be repeated here. As shown in the top view of FIG. 31 , the source contact 962 is surrounded by an ESD polysilicon region (e.g., a gate-source ESD diode structure 929). The body ring structure 820 is a concentric ring structure. As shown in FIG. 31 , the body ring structure 820 includes a first rectangle with rounded corners, a second rectangle with rounded corners, a third rectangle with rounded corners, and a fourth rectangle with rounded corners. In the cross-sectional view, the first rectangle is represented by a pillar 822. The second rectangle is represented by a pillar 824. The third rectangle is represented by a pillar 826. The fourth rectangle is represented by pillar 828 .

[0102]

[0132] As shown in Figure 31, the body ring structure 820 comprises a plurality of rectangles with rounded corners. It is within the scope and spirit of the present invention for the body ring structure 820 to include other shapes such as, but not limited to, oval, rectangular, square, or circular.

[0103]

[0133] Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0104]

[0134] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described herein. As will be readily apparent from the present disclosure to those skilled in the art, any currently existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. [Explanation of symbols]

[0105] 100 Power MOSFET 102 Circuit Board 104 Epitaxial layer 106 Hard mask layer 108 Photoresist layer 200 Second embodiment of high-voltage and leak-proof power MOSFET 300 Power MOSFET of the third embodiment with high breakdown voltage and leak-proof structure 400 Power MOSFET of the fourth embodiment with high breakdown voltage and leak-proof structure 402 First Trench 404 Second Trench 406 Third Trench 500 Power MOSFET of the fifth embodiment having high breakdown voltage and leak-proof structure 502 thin dielectric layer 600 Power MOSFET of the sixth embodiment having high breakdown voltage and leak-proof structure 602 gate electrode layer 700 Seventh embodiment of power MOSFET with high breakdown voltage and leak-proof structure 702 First Gate 704 Second Gate 706 Third Gate 710 Dielectric Layer 800 Power MOSFET of the eighth embodiment having high voltage resistance and leak-proof structure 802 First Body Region 804 Second Body Region 812 Photoresist layer 820 Body Ring Structure 822 pillars 824 pillars 825 pillars 826 pillars 828 pillars 900 Power MOSFET of ninth embodiment having high breakdown voltage and leak-proof structure 902 ESD bottom dielectric layer 904 ESD layer 912 First Source Region 914 Second Source Region 920 Interlayer insulation layer (dielectric layer) 921 First p-type region 922 First n+ region 923 Second p-type region 924 Second n+ region 925 Third p-type region 929 Gate-Source ESD Diode Structure 932 Trench 934 Trench 936 Trench 938 Trench 942 First p+ region 944 Second p+ region 946 Third p+ region 948 Fourth p+ region 950 Metal contact layer 951 First source contact plug 952 Second Source Contact Plug 953 Third Source Contact Plug 954 Gate Contact Plug 962 Source Contacts 964 Gate Contact 966 Drain Contact 971 Body Region 972 Body Region 973 Body region (first p-type well) 974 First n-type well 975 Second p-type well 976 Second n-type well 981 First n-type well 982 First p-type well 983 Second n-type well 990 Surface Electric Field Relaxation (RESURF) Structure 991 Photoresist layer 992 Photoresist layer 993 Photoresist layer

Claims

1. a drain and a source on either side of the epitaxial layer; a plurality of gates formed in the epitaxial layer; a source contact connected to the source; a gate contact connected to the plurality of gates; a gate-source electrostatic discharge (ESD) diode structure connected between the gate contact and the source contact; a high voltage withstand and leakage prevention structure formed under the gate-source ESD diode structure; The high voltage withstanding and leak prevention structure comprises a plurality of n-type wells and a plurality of p-type wells arranged alternately. An apparatus comprising:

2. the high breakdown voltage and leakage prevention structure is a surface field relaxation (RESURF) structure, the RESURF structure is configured to distribute an electric field over the gate-source ESD diode structure; the RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer; 10. The apparatus of claim 1.

3. the high pressure resistance and leak prevention structure is a body ring structure, the body ring structure is a concentric ring structure formed within the epitaxial layer; the body ring structure is configured to distribute an electric field over the gate-source ESD diode structure; the body ring structure and the gate-source ESD diode structure are separated by a dielectric layer; 10. The apparatus of claim 1.

4. the plurality of n-type wells and the plurality of p-type wells are configured to distribute an electric field over the gate-source ESD diode structure; the plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure are separated by a dielectric layer; 10. The apparatus of claim 1.

5. a first p-type well of the plurality of p-type wells is formed in the epitaxial layer; a first n-type well of the plurality of n-type wells is formed within the first p-type well, and the first n-type well is surrounded by the first p-type well; a second p-type well of the plurality of p-type wells is formed within the first n-type well, the second p-type well being surrounded by the first n-type well; a second n-type well of the plurality of n-type wells is formed within the second p-type well, and the second n-type well is surrounded by the second p-type well; 5. The apparatus of claim 4.

6. a first n-type well of the plurality of n-type wells formed in the epitaxial layer; a first p-type well of the plurality of p-type wells is formed within the first n-type well, and a width of the first p-type well is equal to a width of the first n-type well; a second n-type well of the plurality of n-type wells is formed within the first p-type well, and a width of the second n-type well is equal to the width of the first p-type well; 5. The apparatus of claim 4.

7. The high pressure resistance and leak prevention structure comprises a RESURF structure and a body ring structure, the RESURF structure and the body ring structure are configured to distribute an electric field over the gate-source ESD diode structure; the body ring structure is a concentric ring structure formed within the epitaxial layer; the RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer; the RESURF structure is between the gate-source ESD diode structure and the body ring structure; 10. The apparatus of claim 1.

8. The high pressure resistance and leak prevention structure comprises a body ring structure, the plurality of n-type wells, the plurality of p-type wells, and the body ring structure are configured to distribute an electric field over the gate-source ESD diode structure; the body ring structure is a concentric ring structure formed in the epitaxial layer; the plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure are separated by a dielectric layer; the plurality of n-type wells and the plurality of p-type wells are between the gate-source ESD diode structure and the body ring structure; 10. The apparatus of claim 1.

9. the gate-source ESD diode structure comprises a cascaded first p-type region, a first n+ region, a second p-type region, a second n+ region, and a third p-type region; the first p-type region is connected to the gate contact; the third p-type region is connected to the source contact; 10. The apparatus of claim 1.

10. the plurality of gates comprising a first gate trench, a second gate trench, and a third gate trench; the source comprises a first source region and a second source region; the first source region is between the first gate trench and the second gate trench; the second source region is between the second gate trench and the third gate trench; 10. The apparatus of claim 1.

11. a first body region and a second body region, the first body region being between the first gate trench and the second gate trench, and the second body region being between the second gate trench and the third gate trench; a first source contact plug having a first terminal connected to the source contact and a second terminal connected to the first source region and the first body region; a second source contact plug having a first terminal connected to the source contact and a second terminal connected to the second source region and the second body region; a gate contact plug having a first terminal connected to the gate contact and a second terminal connected to the first terminal of the gate-source ESD diode structure; a third source contact plug having a first terminal connected to the source contact and a second terminal connected to the second terminal of the gate-source ESD diode structure; an interlayer insulating layer formed on the epitaxial layer, the gate-source ESD diode structure being within the interlayer insulating layer; The apparatus of claim 10 further comprising:

12. growing an epitaxial layer on a substrate; forming a plurality of gates in the epitaxial layer; forming a body region and a high voltage and leakage protection structure in the epitaxial layer, the high voltage and leakage protection structure comprising a plurality of alternating n-type wells and a plurality of p-type wells; forming a source in the epitaxial layer and a gate-source ESD diode structure on the epitaxial layer; forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, and a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure; A method comprising:

13. forming the high voltage and leakproof structure in the epitaxial layer; forming a RESURF structure by an implantation process, the RESURF structure being on top of the epitaxial layer, the RESURF structure and the gate-source ESD diode structure being separated by a dielectric layer. The method of claim 12.

14. forming the high voltage and leakproof structure in the epitaxial layer; forming a body ring structure by an implantation process, the body ring structure being a concentric ring structure, the body ring structure and the gate-source ESD diode structure being separated by a dielectric layer; The method of claim 12.

15. forming the high voltage and leakproof structure in the epitaxial layer; forming a first p-type well of the plurality of p-type wells in the epitaxial layer; forming a first n-type well of the plurality of n-type wells within the first p-type well, the first n-type well being surrounded by the first p-type well; forming a second p-type well of the plurality of p-type wells within the first n-type well, the second p-type well being surrounded by the first n-type well; forming a second n-type well of the plurality of n-type wells within the second p-type well, the second n-type well being surrounded by the second p-type well; Including, The method of claim 12.

16. forming the high voltage and leakproof structure in the epitaxial layer; forming a first n-type well of the plurality of n-type wells in the epitaxial layer; forming a first p-type well of the plurality of p-type wells within the first n-type well, the width of the first p-type well being equal to the width of the first n-type well; forming a second n-type well of the plurality of n-type wells within the first p-type well, the width of the second n-type well being equal to the width of the first p-type well; Including, The method of claim 12.

17. forming an interlayer insulating layer on the epitaxial layer; forming a plurality of trenches in the interlayer insulating layer; forming a plurality of p+ regions at the bottom of each trench; performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs and a plurality of gate contact plugs; forming the source contact and the gate contact by an etching process; The method of claim 12 further comprising:

18. an epitaxial layer on a substrate; a plurality of gates formed in the epitaxial layer; a body region formed in the epitaxial layer; a source formed in the body region; a gate-source ESD diode structure formed on the epitaxial layer; a body ring structure formed in the epitaxial layer below the gate-source ESD diode structure; an interlayer insulating layer formed on the epitaxial layer, the gate-source ESD diode structure being within the interlayer insulating layer; a plurality of source contact plugs, at least one of the plurality of source contact plugs extending through the interlayer insulating layer, the source, and partially through the body region; a gate contact plug extending partially through the interlayer insulating layer; a gate contact connected to the plurality of gates and a first terminal of the gate-source ESD diode structure through the gate contact plug; a source contact connected to the source, the body region, and a second terminal of the gate-source ESD diode structure via the plurality of source contact plugs; A power MOSFET comprising:

19. the substrate is an n-type substrate, the epitaxial layer is an n-type layer, the body region is a p-type region, the source is an n-type region; the body ring structure is a p-type body ring structure, the body ring structure is a concentric ring structure formed within the epitaxial layer; the gate-source ESD diode structure comprises a cascaded first p-type region, a first n+ region, a second p-type region, a second n+ region, and a third p-type region, the first p-type region being connected to the gate contact and the third p-type region being connected to the source contact; 20. The power MOSFET of claim 18.

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