Circuit, housing, and method of manufacturing the housing

Abstract

To provide a filter comprising enclosures, the inside of which is microfabricated by means of semiconductor manufacturing.SOLUTION: An exemplary semiconductor technology implemented microwave filter includes a dielectric substrate with metal traces on one surface that function as frequency selective circuits and reference ground. Other metal traces on another surface of the substrate also provide the reference ground. Bottom and top enclosures that enclose the substrate have respective interior recesses with deposited continuous metal coatings. A plurality of metal bonding bumps or a bonding wall extends outwardly from projecting walls of the bottom and top enclosures. The bonding bumps on the bottom and top enclosures engage reference ground metal traces on respective surfaces of the substrate. As a result of applied pressure, the bonding bumps and respective reference ground metal traces together with the through-substrate vias form a metal-to-metal singly-connected ground reference structure for the entire circuitry.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] Embodiments of the present invention relate to filters made using semiconductor manufacturing techniques having housings comprised of micro-machined interiors that improve filter performance and provide manufacturability with repeatable performance results.

[0002] High-frequency filters, i.e., frequencies above 1 GHz, are constructed using a variety of materials and techniques. However, producing filters with high Q and low input loss that are stable over extreme temperatures is challenging. Designing such high-frequency filters to be manufacturable so as to repeatedly achieve nearly identical performance characteristics is even more challenging. What is needed is a filter and method for making such a filter that substantially overcomes these challenges. Summary of the Invention [Problem to be solved by the invention]

[0003] It is an object of embodiments of the present invention to provide a filter that substantially meets these objectives. [Means for solving the problem]

[0004] An exemplary semiconductor technology for implementing a high-frequency filter includes a dielectric substrate having metal traces on one surface that function as frequency-selective circuits and a reference ground. Other metal traces on the other surface of the substrate also provide the reference ground. Bottom and top housings surrounding the substrate have respective internal recesses with deposited continuous metal coatings. A plurality of metal bonding bumps extend outward from the protruding walls of the bottom and top housings. The bonding bumps on the bottom and top housings engage with reference ground metal traces on their respective surfaces of the substrate. As a result of applied pressure, the bonding bumps and the respective reference ground metal traces, together with the through-substrate vias, form metal-to-metal conductive bonds that establish a common reference ground between the reference ground metal traces and the deposited metal internal coatings of the bottom and top housings.

[0005] An exemplary method for fabricating a housing for a high-frequency filter implemented in semiconductor technology is provided, the substrate having a frequency-selective circuit disposed on a substrate including a reference ground metal wiring on each major surface. The substrate is sandwiched between two housings fabricated in this manner. A first pattern of photoresist dots is applied to a silicon wafer in areas where the wall edges of the housing will be formed. The silicon layer not protected by the first pattern of photoresist is etched away, leaving a plurality of extended bumps, and then the first pattern of photoresist covering the bumps is removed. An oxide coating is deposited to cover the surface of the silicon wafer including the extended bumps. A second pattern of photoresist is applied over the oxide coating in areas where the wall edges extend from the housing, i.e., areas defining the extended bumps present in the second pattern. The deposited oxide coating not protected by the second pattern of photoresist is etched away, and the second pattern of photoresist covering the wall-defining areas is removed. The silicon wafer layer is etched away except in areas with the oxide coating defining the wall edges to form at least one internal recess in the silicon wafer. The oxide coating is removed from the areas defining the walls and the edges of the bumps. The entire exposed surface of the silicon wafer is sputtered with gold, so that the sputtered gold coats the edges of the walls, the bumps on the edges of the walls, all internal recesses in the silicon wafer, and the inside of the walls. The areas covered with the sputtered gold are gold plated.

[0006] Features of exemplary embodiments of the invention will become apparent from the description, claims, and accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is an exploded perspective view of a filter according to an embodiment of the present invention. [Figure 2] 1 shows an exploded view of a filter according to an embodiment of the present invention, illustrating the relationship between elements and layers. [Figure 3] 1 shows a top view of the metallization disposed on the top surface of the substrate relative to the bottom metallization. [Figure 4] 1 shows a bottom view of the metallization disposed on the bottom surface of the substrate relative to the top surface metallization. [Figure 5] 1 shows a representative cross-sectional view of an assembled filter according to an embodiment of the present invention. [Figure 6] 1 illustrates a close-up view of a corner of an exemplary housing according to an embodiment of the present invention. [Figure 7] 10 shows enlarged details of the top metallization associated with coupling signals to and from the filter. [Figure 8] 1 shows an exploded detailed view of a structure supporting a high performance transition between an external microstrip transmission line and a suspended stripline in an embodiment of the present invention. [Figure 9A] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 9B] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 9C] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 9D] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 9E] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 9F] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 9G] 1 illustrates process steps for manufacturing an exemplary housing. [Figure 10] 1 shows a graph illustrating performance characteristics of an exemplary filter over a range of frequencies, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] One aspect of the present invention is the recognition of the difficulties associated with repeatably manufacturing a conductive strip enclosure for enclosing a substrate, which enclosure can provide an effective ground structure for currents along the entire perimeter of the interface as well as at the interior walls of the recess. Recognizing these difficulties has resulted in an enclosure design that can be reliably and repeatably manufactured to provide an effective continuous ground structure around the perimeter of the assembled enclosure and to connect the top and bottom metallized ground traces. Details regarding overcoming these difficulties will be recognized by those skilled in the art in view of the following description.

[0009] An exemplary embodiment of a diplexer is used as an example to convey features and improvements related to embodiments of the present invention. A diplexer functions as a type of filter that separates an input signal at a single input into two separate outputs, one output containing the input signal having a frequency within a first frequency range and the other output containing the input signal having a frequency within a second frequency range, the first and second frequency ranges being different. As used herein, "filter" is utilized to refer to any type of frequency-selective circuit in RF, microwave, or millimeter-wave format suitable for placement on a substrate that can be placed within an enclosure. For example, filters can include, but are not limited to, diplexers, low-pass filters, high-pass filters, band-pass filters, multifunction filters, multi-band filters, power dividers / combiners, resonators, couplers, spiral / coil / toroid inductors, metal-insulator-metal (MIM) capacitors, interdigitated capacitors, vertical (i.e., via-to-via) capacitors, balances, attenuators, phase shifters, any interlayer transitions, transitions from the same interlayer type to a line type, etc.

[0010] FIG. 1 illustrates an exemplary embodiment 100 of a filter or diplexer having a two-piece housing consisting of a bottom housing 105 and a top housing 110. A substantially planar substrate 115 is sized to be sandwiched and enclosed between the bottom housing 105 and the top housing 110 in a ready-to-operate assembly. The substrate 115 has a top surface 120 supporting an upper metallization 125 and a bottom surface 130 supporting a lower metallization 135. An input port 140 receives an input signal with frequency-selective circuitry that routes signals in one frequency range to an output port 145, while frequencies in another frequency range are routed to an output port 150. The bottom housing 105 includes an interior recessed region partially divided by a longitudinal central peninsula 155 that separates a recessed region 160 associated with the output port 145 from a recessed region 165 associated with the output port 150. The upper periphery of both the bottom housing 105 and the top surface of the peninsula 155 represent a reference ground. The top housing 110 is substantially similar to the bottom housing, except for a cutout portion 170 located adjacent to the input port 140 in the assembled position. The cutout portion 170 provides mechanical support for the input port 140 on the substrate 115, facilitating coupling of an input signal via an external probe or line. Similarly, the cutout portions of the top housing opposite the output ports 145 and 150 facilitate clearance for connections to these ports. When assembled, a peninsula 155 engages the substrate 115 on one surface, and a corresponding peninsula on the top housing engages the substrate 115 on the other surface opposite the peninsula 155, forming two parallel recesses separated by two opposing peninsulas when interconnected by a through-substrate via. The ground structure formed by the two peninsulas and the through-substrate via functions as a microwave isolation wall between the two recessed recesses ("channels") in this exemplary filter. Note that the peninsula is the inner wall of the cover. The cover may also have "islands" in addition to the peninsulas. When the inner and protruding surfaces of the cover are metallized, the islands and peninsulas are also metallized at the same time, which typically provide an "inner" interior wall for purposes of insulation, demodeling, field shaping, and impedance control.Note that the interior walls, recessed surfaces, protruding surfaces, including those contributed by the islands and peninsulas, and the bond bumps of both covers and through-substrate vias are all part of the ground reference structure. When assembled, they form a single connected ground structure, or "Faraday cage," for the enclosed stripline circuit. The islands and peninsulas can have any different contoured perimeter, and this presents no difficulty to the manufacturing technique.

[0011] The exemplary splitter 100 is designed to route input signals at input port 140 having frequencies between 0.5 GHz and 10 GHz along a first path to a first output 145, while splitting input signals between 11 GHz and 20 GHz along a second path to a second output 150. The circuitry associated with the first and second paths provides low insertion loss for signals to be coupled to the respective first and second outputs, while providing a substantially high impedance to other signals not desired to be coupled through the respective paths. At such frequencies, the exemplary circuitry is implemented with capacitors, inductors, and respective metallized traces that function as the equivalent of transmission lines to provide frequency selection.

[0012] FIG. 2 shows a representative exploded view of an exemplary filter (diplexer) 200, with elements depicted in FIG. 1 indicated and identified by the same reference numerals. Bottom layer 205 and top layer 210 represent conductive metal layers deposited on the inner surfaces of bottom housing 105 and top housing 110, respectively. A longitudinal perimeter edge 215 of bottom layer 205 and a longitudinal perimeter edge 220 of top layer 210 extend to the longitudinal edges of the inner surfaces of bottom housing 105 and top housing 110, respectively. Similarly, a longitudinal perimeter 225 of bottom metallization 135 and a longitudinal perimeter 230 of top metallization 125 extend to the longitudinal edges of the inner surfaces of bottom housing 105 and top housing 110, respectively. The perimeters 225 and 230 of bottom and top metallization layers 135 and 125 on the substrate represent metallizations where a reference ground is desired. The top metallization layer also includes signal traces 126 that transmit input signals relative to a reference ground. A plurality of metallized through-vias 240 along the longitudinal periphery of the substrate 120 provide effective ground connections between mating regions of the bottom and top metallization layers 135 and 125, respectively. To establish an effective ground, the vias 240 should be appropriately spaced for the electromagnetic frequency under consideration to prevent unwanted electromagnetic resonance moderating within the empty space ("cavity") formed by the surrounding vias when energy at that cavity's resonant frequency is coupled into the cavity. Typically, via spacing is selected to be a small fraction of a quarter wavelength (1 / 4 of a wavelength) of the highest frequency under consideration, e.g., 1 / 5 to 1 / 10 or less. For example, spacings of 750 μm to 375 μm are sufficient to prevent moderating at frequencies below 20 GHz. To enhance effective grounding, vias 240 are disposed within substrate 120 and engage near the interior edge of the ground metallization of bottom metal layer 135, and also engage the opposing ground region on top metal layer 125. Bottom deposited metal layer 205 is continuous within the interior surface of bottom housing 105. That is, a continuously deposited metal layer is present on top surface 106, on top 107 of the interior recess that defines the interior space, and on the substantially vertical sidewalls 108 between surfaces 106 and 107. Top deposited metal layer 210 is also continuous, as similarly described for the bottom deposited metal layer.The bottom housing 105 includes two longitudinal side walls 104 perpendicular to the side walls and two end walls 103. The top housing 110 includes two longitudinal side walls 111 perpendicular to the side walls 111 and two end walls 112. In the example diplexer shown, an opening 113 in the end wall 112 extends substantially perpendicularly from the outer edge of the end wall back inward so as to abut the main interior recess.

[0013] 3 and 4 show views of the top surface 300 and bottom surface 400 of the metallization disposed on the top and bottom surfaces of the substrate, respectively. When assembled, peninsula 155 engages with ground metallization on substrate 115 on one surface, and a corresponding peninsula on the top housing engages with ground metallization on substrate 115 on the other surface opposite peninsula 155, forming two parallel recesses separated by the two opposing peninsulas when interconnected by through-substrate vias. The view shown in FIG. 4 shows a bottom view of the metallization on the bottom surface of the substrate, with the view shown in FIG. 3 rotated 180° longitudinally. Ground potential semi-insulator 305 is located on the top metal layer directly above ground potential semi-insulator 405 on the bottom metal layer. Multiple through vias 310 in the top metal layer correspond to and are substantially identical to through vias 410 in the bottom metal layer, establishing through-substrate connections between the top and bottom metal layers. Multiple vias extend along the entire width and length of the upper and lower metal peninsulas to establish a common ground potential between the upper and lower metal peninsula layers. A U-shaped metal loop 315 at ground potential extends around and completely surrounds input port 140. Similarly, U-shaped metal loops 320 and 325 at ground potential surround output ports 145 and 150, respectively. This U-shaped loop is a feature in the probe-to-microstrip-stripline transition of the exemplary filter that helps minimize wave leakage in the space between the probe and the substrate in the opposite direction (to the suspended stripline) from the desired direction. Note that in other transition designs, such as ribbon junctions or dual-purpose (probing and ribbon junction) designs, utilizing such a ground loop may not be necessary or desirable. While this ground loop enhances a high-performance, wideband transition for probe measurements, it is not a necessary feature of current suspended stripline technology.

[0014] A general description of the circuitry implemented by the wiring shown in FIG. 3 is provided. However, those skilled in the art will understand that this description applies to the specific exemplary diplexer and that various other types of filter elements can be deployed on the substrate to provide frequency-selective circuits including transmission lines, inductive components, capacitive components, dispersive components, and coupling components. Such components can be designed to provide various functions, such as low-pass filters, high-pass filters, band-pass filters, and notch filters, and can include multiple input and / or output ports. In addition, active circuit elements, such as transistors, ICs, and the like, can also be disposed on the supporting substrate housed within the enclosure. The input transition 350 facilitates wide bandwidth adaptation between the microstrip included between the probe and the stripline 355 as shown in FIG. 7. When both the microstrip and the stripline have a 50 ohm transfer impedance, a typical microstrip has a centerline conductor width of approximately 3 mils, while the suspended stripline 355 is 60 mils. Additionally, the electromagnetic field in the microstrip is primarily contained beneath the microstrip line, while the electromagnetic field in the suspended stripline 355 spreads in all directions transverse to the propagation direction, from the signal metal trace to the inner wall of the cover. The transition section 350 uses a wedge-shaped metallization on the bottom of the substrate and a contoured metal lining in the adjacent cover to help fan out the field from the narrowly confined microstrip mode over a short distance into the substantially larger recess of the suspended stripline. The tapering of the housing from the regular channel width to the size of the aperture 113 is designed to function with the wedge-shaped metallization for the same purpose: to help spread the field for a high-performance wideband transition. The neck-down matching section (see the narrowed section in Figure 7) and the tail end section after the probe pad also help achieve wideband performance up to 40 GHz. Region 360 represents the common signal junction where the input signal is coupled by transmission line 355 to two transmission lines, which are respectively coupled to the upper and lower frequency-selective circuits.Elements 360 and 365 similarly function as open stub transmission lines associated with tuning to provide a notch frequency response. Element 370 represents a connecting transmission line. The circuit elements above transmission line 355 and peninsula 305 combine to provide a low-pass filter frequency response, e.g., signals between 0.5 GHz and 10 GHz are passed with low attenuation, while signals having higher frequencies are substantially attenuated, i.e., blocked / reflected at the beginning of the channel due to high impedance. Element 375 represents a coupled line providing a band-pass frequency response. The circuit elements below transmission line 355 and peninsula 305 combine to provide a band-pass filter frequency response, e.g., signals within 11 GHz and 20 GHz fall within the band-pass frequency range and are coupled with low attenuation, while signals outside the range, i.e., between 0.5 GHz and 10 GHz, are substantially attenuated, i.e., blocked / reflected at the beginning of the channel due to high impedance.

[0015] As seen in FIG. 4, vias in the bottom metallization connect to a U-shaped ground loop to enhance the effective ground between the two metal layers. The top recess 330 includes multiple metal traces 126 disposed within the top metal layer, which function as a selective frequency circuit to the output port 145. The selective frequency circuit provides low attenuation for signals between 0.5 GHz and 10 GHz, while providing high impedance and substantial rejection for signals between 11 GHz and 20 GHz. Similarly, the bottom recess 335 includes multiple metal traces 126 disposed within the top metal layer, which function to form a selective frequency circuit to the output port 150. The selective frequency circuit provides high impedance and substantial attenuation for signals between 0.5 GHz and 10 GHz, while providing low attenuation for signals between 11 GHz and 20 GHz. Preferably, the substrate core is silicon carbide, upon which the precision metallization is disposed, and through-wafer vias, which can be fabricated using the same fabrication techniques used for gallium nitride (GaN) high electron mobility transistor (HEMT) fabrication.

[0016] FIG. 5 shows a representative cross-section of an assembled filter according to an embodiment of the present invention, taken at a location on the assembled filter where peninsula 155 is not present. Bottom housing 105 and top housing 110 may be fabricated from silicon with gold-plated linings on their inner surfaces 205 and 210. The gold-plated surfaces of the bottom and top housings engage bottom metallization 135 and top metallization 125, respectively. Conductive vias 240 through the substrate provide a continuous ground connection interconnecting the gold-plated recesses in the bottom and top housings with the top and bottom metal layers, which should be at ground potential. Substrate 120 is preferably silicon carbide or another material with properties that change little with temperature to minimize frequency response variations with temperature. A suspended stripline circuit with a large cross-section filled with low-loss material (air, silicon carbide) facilitates a very high Q, enabling a low-loss filter with sharp band edges and rejection rolloff.

[0017] FIG. 6 shows a representative enlarged corner of the bottom housing 105 with metal plating 205 disposed on the vertical sidewalls, as well as an upward-facing flat surface. Bonding bumps 605 extend generally vertically outward from the upward-facing flat surface along the periphery and along the interior peninsula. Bonding bumps 605 are spaced along the entire perimeter of the bottom housing and engage with bottom metallization 135 in the assembled position. Bonding bumps also extend along peninsula 155 of the bottom housing and engage with bottom metallization 405 in the assembled position. Similarly, bonding bumps extend vertically outward from the downward-facing flat surface of the top housing and engage with ground metallization 125 and ground peninsula metallization 305. While in this example the bonding bumps are formed on the housing rather than on the substrate (or metallization on the substrate), bonding bumps could be formed on both sides of the substrate 115. The bonding process preferably uses high-precision thermocompression bonding, using a tool such as the FC-300 manufactured by SET, to bond gold-plated bonding bumps to a gold-plated metallization surface on the substrate. When the bonding bumps are placed on the substrate, the second side to be bonded will have a much higher density of bumps, so that the opposing bonding bumps on the other side of the substrate used for the other of the bottom and top housings will not be crushed during the pressure application process to bond the first housing to the substrate.

[0018] FIG. 7 shows an enlarged detail 700 of the top surface metallization associated with ports 140, 145, and 150 used to couple signals to and from the filter. These three ports are designed for probe measurements. As an example, port 140 is a ground signal-ground port used to couple an input signal. As seen in this detail, U-shaped ground metallization 315 provides a continuous 270° enclosure around input port center conductor 140. In this example, external probe or interconnect 705 includes a center metal conductor (finger) 710 positioned to engage input port center conductor 140, and two opposing metal fingers 715 on either side of center finger 710 positioned to engage opposing legs of U-shaped ground metallization 315. This configuration of the port provides the necessary compensation features, such as nearby inductance and capacitance, which allows a smooth transition of the fields within the probe to the fields on the signal-carrying wiring on the substrate, thus forming a "transition" from the probe to the short microstrip (i.e., transmission line with ground metallization on the backside of the substrate) and the suspended stripline.

[0019] Figure 8 shows an exploded detailed view of a structure supporting a compact, high-performance, broadband transition between an external microstrip line and a suspended stripline in an embodiment of the present invention. The magnetic field at the probe tip is horizontal, between the signal and ground pins. To withstand pressure from the probe landing, the bottom cover must have no excavations in this area; therefore, a microstrip-type transmission line, i.e., one with metallization (ground) on the backside of the substrate, must be used near the probe landing area. Vias 240 and ground loop 315 help "fold" or "bend" the essentially horizontal magnetic field at the probe tip relative to the essentially vertical magnetic field below the microstrip line. The neckdown 805 next to the probe pad 140 and tail end piece 810 are both features that aid in impedance matching for broadband performance. The essentially vertical magnetic field, which is the junction between the microstrip and the stripline and is concentrated below the microstrip line, must then fan out in all directions (downward, upward, sideways, etc.) within the suspended stripline, which has a cross-section an order of magnitude larger than the microstrip. This field fan-out is aided by the following features: The wedge-shaped metallization 815 on the backside of the substrate can be considered a "diving board" that allows the concentrated microstrip field to gradually loosen and form a connection to the much larger ground structure within the stripline. The tapers on both the top and bottom covers provide a close landing surface for the magnetic field lines near the microstrip-stripline junction, gradually expanding the landing field to a larger cross-section until it fills the full channel dimensions. Note that due to the small distance and therefore strong interaction between the probe-to-microstrip and microstrip-to-stripline transitions, they should be viewed and designed as a single transition, i.e., probe-to-microstrip-to-stripline. Other transitions have also been designed for practical purposes, such as ribbon junctions or ribbon junctions and probing. These transitions may have different dimensions or may have ground via configurations.However, the essential field bending / expanding features such as the wedge and tapered ground are still very effective.

[0020] 9A-9G illustrate process steps for fabricating an exemplary housing associated with a filter, according to one embodiment of the present invention. In this example, an exemplary cross section of bottom housing 105 is shown, with peninsula wall 155 visible. In FIG. 9A, the process begins with a relatively thick silicon wafer 900, e.g., 1 mm. In the next step, shown in FIG. 9B, the top surface of silicon wafer 900 is patterned with photoresist, and reactive ion etching (RIE) is used to micromachine the areas of silicon to be removed, i.e., leaving outward-extending bonding bumps 905. "Micromachining" refers to the creation of a dimensionally precise, smooth surface by semiconductor etching followed by deposition of a metal layer. In the next step, shown in FIG. 9C, the photoresist is removed, and an oxide layer 910 is deposited thick enough to withstand complete erosion during the silicon etch. Next, as shown in FIG. 9D, a photoresist pattern 915 is applied to create what will become three walls 917, and RIE is used to etch away the oxide 910 not protected by the photoresist. As shown in FIG. 9E, the photoresist 915 shown in FIG. 9D is removed, and a deep RIE etch is used to remove the silicon regions that form the internal recess 918 within the housing. In FIG. 9F, the oxide 910 is removed, revealing two longitudinal walls 920 along the longitudinal edges and a central longitudinal peninsula wall 925 that forms two isolated longitudinal recesses 932, 933. The recesses may be up to approximately 40 mils deep, etched to a depth of 15 mils in the exemplary diplexer embodiment. This is followed by sputtering a relatively thin layer of gold 930 over all exposed upward-facing surfaces, including the associated ends of the walls, the bonding bumps, the vertical walls, and the planar recesses. Thus, the exposed ends of the walls 920 and 925, as well as the bond bumps and recessed areas, are all sputtered with gold. In a final step, as shown in FIG. 9G, all of the areas previously sputtered with gold are now plated with a thicker layer of gold. In this example, the bonding bumps have a diameter of 25 μm, a bump height of 1.6 μm, and are preferably spaced apart by a distance of 200 μm.Typically the maximum spacing is about a quarter wavelength, but preferably a tenth wavelength if feasible.

[0021] The excellent dimensional accuracy and surface smoothness of the housing's internal recesses and surfaces achieved by micromachining are critical to the ability to manufacture filters with highly repeatable characteristics and performance, as well as low electrical losses. Housings manufactured by conventional mechanical manufacturing techniques, such as machining, EDM, and electroforming, have tolerances ranging from 0.2 mil to 1 mil, which is one to two orders of magnitude greater than the precision offered by the semiconductor techniques described herein. In addition, the surface roughness from machining can typically be five times greater than that achieved by semiconductor techniques, resulting in additional RF signal loss. For example, the micromachined interior surfaces within an exemplary housing have a peak-to-valley roughness of less than 2 μm, or 1.3 μm, compared to a machined copper housing with a peak-to-valley roughness of approximately 9.4 μm. This provides a more than seven-fold improvement in smoothness.

[0022] Conductive epoxy pastes can be used to achieve silicon-to-SiC assembly, but conductive pastes offer a more difficult technique to control in terms of oozing, thickness variations, voids, and poor electrical contact, as well as placement accuracy.

[0023] Regarding vias, 50-μm-diameter metallized through-wafer vias connecting ground metallization on opposing surfaces of the substrate are used to form a high-isolation electromagnetic via fence. Simulations have shown that vias can be used to provide high isolation up to 100 GHz when spaced at a minimum 100-μm pitch. The via fence and gold-plated silicon enclosure walls allow individual elements of two isolated frequency circuits to be effectively enclosed in their own electromagnetically shielded recesses to minimize cross-coupling. The through-wafer vias facilitate substantially continuous ground continuity for RF return currents between the top and bottom enclosures, enabling probe testing of the filter after fabrication. Note that the "wall" formed by the gold-plated silicon enclosure walls and via fence can be used not only to separate channels, but also to separate individual filter elements. Traditional open-face printed filter designs often have long design cycles because proximity coupling between filter elements makes assumptions and unavoidable repeated simulation cycles when fine-tuning the filter geometry. The separation between the individual filter elements eliminates such undesirable cross-coupling, thus allowing for rapid development and compact layout.

[0024] As can be seen in Table 1, tight manufacturing tolerances are critical to designing first-pass success and manufacturing repeatability, especially for filters with tight cutoff specifications, high isolation requirements, and highly repeatable performance. [Table 1]

[0025] FIG. 10 shows a graph illustrating the performance characteristics of an exemplary filter (diplexer) over a frequency range. The graph is plotted in dB versus exemplary frequencies of interest, i.e., 0.5 GHz to 25 GHz. Line 1005 represents the output characteristic associated with the signal from output port 145, which exhibits very low loss for input signals between 0.5 GHz and 10 GHz, with a sharp increase in attenuation at approximately 11 GHz resulting in approximately 50 dB of attenuation from approximately 12 GHz to 24 GHz. Line 1010 represents the projected characteristic of the signal at output port 145, as calculated using ANSYS's finite element frequency domain analysis tool "HFSS." It is clear that there is a very close correspondence between the projected characteristic and the actual measured characteristic. This is due to the tight manufacturing tolerances mentioned above. Line 1015 represents the output characteristic associated with the signal from output port 150, showing very low loss for signals between 11 GHz and 20 GHz, with attenuation of at least 30 dB from approximately 10 GHz to 0.5 GHz (and greater at decreasing frequencies), with a sharp increase at approximately 11 GHz. Line 1020 represents the projected characteristic of the signal at output port 150 using the same HFSS model as above. Again, it is clear that there is extremely close correspondence between the planned characteristics and the actual measured characteristics. The close correspondence between the planned characteristics from the model analysis and the actual measured characteristics of the fabricated diplexer on the first pass of fabrication is indicative of superior design and manufacturing techniques. The unit-to-unit consistency of the diplexer fabricated on the first pass was also excellent, with seven out of eight fabricated units exhibiting nearly identical performance.

[0026] While exemplary implementations of the present invention have been illustrated and described in detail herein, it will be apparent to those skilled in the art that various modifications, additions, substitutions, etc., can be made without departing from the spirit of the present invention. For example, other microwave circuits, including those described in paragraph

[0018] , can be implemented. The silicon recesses can be of different heights, and the bonding bumps can be made using various chip and wafer bonding techniques, including eutectic bonding such as indium-gold or gold-tin, or copper pillar bonding. The bonding bumps can be made on the substrate 115 instead of the silicon, and the assembly can be bonded as an entire wafer rather than a smaller filter-sized block. The recess height is limited only by the manufacturing capabilities of the silicon etching tool. Silicon recesses with two different etch depths are possible and can be used in terahertz waveguide devices and in filters of the type described herein. The substrate 115 can be made of another material, such as 5-mil thick alumina, as long as there are conductive vias through the wafer.

[0027] The scope of the present invention is defined in the following claims.

Claims

1. a flat dielectric substrate; a metal wiring that functions as a frequency selection circuit and a reference ground and is disposed on one of the two main surfaces of the substrate; another metal wiring that functions as the reference ground and is disposed on the other of the two main surfaces of the substrate; the frequency selection circuit disposed on the substrate; an upper housing implemented using semiconductor technology, the upper housing having at least one internal recess and a peripheral wall extending around its periphery and including a first flat end region parallel to the substrate, the first flat end region being aligned with one of the metal traces on one major surface of the substrate that serves as an electrical ground, and all of the internal surfaces, including the first flat end region, and the at least one internal recess, having a deposited metal coating; a conductive coupling means for engaging the one metal trace on the one major surface aligned with the first flat end region to form a conductive bond for establishing a common reference ground between the deposited metal coating of the upper housing and the other metal trace; a longitudinal peninsula on the upper housing proximate a longitudinal centerline thereof separating an interior of the upper housing into a first longitudinal recess and a second longitudinal recess; A circuit implemented using semiconductor technology, comprising: the longitudinal peninsula has a flat end region; the conductive coupling means engages the flat end region of the longitudinal peninsula and one metal trace of the reference ground on the one major surface to electromagnetically isolate one frequency selective circuit on one side of the longitudinal peninsula from another frequency selective circuit on the other side of the longitudinal peninsula; the at least one internal recess is sized to surround the frequency selective circuitry and provide electromagnetic shielding for the frequency selective circuitry. circuit.

2. 2. The circuit of claim 1, wherein said conductive coupling means comprises a conductive metal bump extending from said first flat end region of said upper housing.

3. a bottom housing having the at least one internal recess and a peripheral wall extending outwardly and including a flat second end region parallel to the substrate; Furthermore, all interior surfaces of the bottom housing, including the flat second end region, and the at least one interior recess, have a metal coating deposited thereon; the flat second end region is aligned with the other metal wiring on the other major surface of the substrate, which serves as the reference ground; The circuit of claim 1 .

4. 10. The circuit of claim 1, wherein the interior surface of the upper housing is formed by micromachining a wafer to deposit a deposited metal having a peak-to-valley roughness of less than 2 microns.

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