Ion Current Droop Compensation

Abstract

To provide a plasma system including: a power supply for generating a high frequency waveform that can be used to generate a plasma in a plasma chamber; and a power supply that generates a high voltage pulse that accelerates charged plasma particles toward a wafer in the plasma chamber.SOLUTION: A high voltage power supply is disclosed that provides a plurality of high voltage pulses without any voltage droop between two subsequent pulses. A high voltage power supply is disclosed that provides a voltage waveform versus time having a voltage above 1kV and a plurality of high voltage pulses having a substantially flat portion between the pulses. A high voltage power supply is disclosed that includes a snubber including a snubber resistor R3 having a resistance of about 7.5 mΩ to 1.25 Ω and a snubber capacitor C5 having a capacitance of about 2 μF to 35 μF.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to ion current droop compensation. [Background technology]

[0002] Some plasma systems include at least two power sources: one that generates a radio frequency waveform that can be used to generate a plasma in the plasma chamber, and the other that generates high voltage pulses that accelerate charged plasma particles toward the wafer in the plasma chamber. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made to solve the problems in the prior art described above. [Means for solving the problem]

[0004] Some embodiments include a power supply that provides multiple high voltage pulses with no voltage droop between two subsequent pulses.

[0005] Some embodiments include a power supply that provides a voltage waveform versus time having a voltage greater than 1 kV and having multiple high voltage pulses with substantially flat portions between the pulses.

[0006] Some embodiments include a power supply including an RF driver that generates an RF signal having an RF frequency, a nanosecond pulser that generates high-voltage pulses having a pulse repetition frequency lower than the RF frequency, a pulse width, and a peak voltage greater than 2 kV, the nanosecond pulser including a snubber circuit, and a filter circuit disposed between the RF driver and the plasma chamber. The snubber circuit can include a snubber resistor having a resistance between about 7.5 mΩ and 1.25 Ω and a snubber capacitor having a capacitance between about 2 μF and 35 μF.

[0007] In some embodiments, the filter circuit includes a filter inductor having an inductance of approximately 0 to 2.5 μH.

[0008] In some embodiments, the power supply has a stray inductance of less than about 800 nH.

[0009] In some embodiments, the pulse width has a duration of about 100-250 ns.

[0010] In some embodiments, the RF signal has a voltage greater than 100V.

[0011] In some embodiments, the nanosecond pulser includes a DC power supply with a voltage greater than 500V.

[0012] In some embodiments, the voltage between two successive pulses changes by less than 1 V / ns.

[0013] In some embodiments, the voltage between two successive pulses without an RF signal changes by less than 1 V / ns.

[0014] In some embodiments, the average voltage between two successive pulses changes by less than 1 V / ns.

[0015] In some embodiments, the power supply outputs a waveform having an RF signal during each of a plurality of high voltage pulses.

[0016] Some embodiments include a semiconductor processing system comprising a plasma chamber and a power supply as disclosed herein coupled to the plasma chamber and configured to introduce RF signals and drive pulses into the plasma chamber.

[0017] In some embodiments, the plasma chamber has an inductance of less than about 20 nH.

[0018] In some embodiments, the chamber includes a chuck having a capacitance of less than about 10 nF.

[0019] Some embodiments include a pulse generator comprising: a power supply that provides a voltage greater than 2 kV; a transformer comprising a transformer core, a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead, and a secondary winding wound around at least a portion of the transformer core. The pulse generator also comprises a droop compensation circuit in electrical communication with the first lead of the primary winding, a first switch in electrical communication with the droop compensation circuit and a power supply, a second switch in electrical communication with the second lead of the primary winding and the power supply, and a pulse output in electrical communication with the secondary winding of the transformer that outputs a square wave pulse. The first switch and the second switch can, for example, be opened and closed at different time intervals.

[0020] In some embodiments, the pulsed output has a voltage greater than about 2 kV and outputs pulses having a pulse frequency greater than 1 kHz.

[0021] In some embodiments, the droop compensation circuit includes a droop diode biased to allow current to flow from the first switch toward the transformer.

[0022] In some embodiments, the droop compensation circuit includes a first inductor and a first resistor arranged in series and electrically connected across the droop diode. The first inductor has, for example, an inductance of less than about 50 μH. The first resistor has, for example, a resistance of less than about 1 Ω. The droop circuit also includes, for example, a second inductor electrically connected to the droop diode and the first lead of the primary winding. The second inductor has, for example, an inductance of less than about 50 nH.

[0023] The pulse generator may also include a third resistor and a third inductor disposed in series between the second switch and the second lead of the primary winding. The third inductor may have an inductance of, for example, less than about 35 nH. The third resistor may have a resistance of, for example, less than about 1 Ω.

[0024] Some embodiments include a pulse generator comprising: a DC power supply providing a voltage greater than 2 kV; and a transformer comprising a transformer core, a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead, and a secondary winding wound around at least a portion of the transformer core. The pulse generator may include a plurality of switches arranged in a full-bridge configuration, a first portion of the plurality of switches electrically connecting to a droop compensation circuit and a power source, and a second portion of the plurality of switches electrically connecting to a second lead of the primary winding and the power source. The first portion of the plurality of switches and the second portion of the plurality of switches may, for example, be open and closed at different time intervals. The pulse generator may include a damping circuit electrically disposed between the first portion of the plurality of switches and / or the second portion of the plurality of switches and the transformer. The attenuation circuit can include a diode biased from a first portion of the plurality of switches toward the first lead, a first resistor disposed between the diode and the first lead, a first inductor, and a second resistor disposed in series with the first inductor and electrically connected across the diode. The pulse generator can be a pulse output electrically connected to a secondary winding of a transformer that outputs pulses having a voltage greater than about 2 kV and a pulse frequency greater than 1 kHz.

[0025] In some embodiments, the first inductor has an inductance of less than about 35 nH. In some embodiments, the first resistor has a resistance of less than about 1 Ω. In some embodiments, the second resistor has a resistance of less than about 1 Ω.

[0026] In some embodiments, the pulse generator can include a second inductor and a third resistor disposed in series between a second portion of the plurality of switches and the second lead.

[0027] The Summary of the Invention and the various embodiments described herein are not offered to limit or define the scope of the disclosure or claims. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a circuit diagram of a power system driving a load stage according to some embodiments. [Figure 2] FIG. 2 is a circuit diagram of a power system having a resistive output stage driving a load stage, according to some embodiments. [Figure 3] FIG. 3 is an example of two waveforms generated by a power system without RF power, according to some embodiments. [Figure 4] FIG. 4 is an example of two waveforms generated by a power system with RF power, according to some embodiments. [Figure 5] FIG. 5 is an example of two waveforms generated by a power system without RF power, according to some embodiments. [Figure 6] FIG. 6 is an example of two waveforms generated by a power system with RF power, according to some embodiments. [Figure 7] FIG. 7 is an example of two waveforms generated by a power system without RF power, according to some embodiments. [Figure 8] FIG. 8 is an example of two waveforms generated by a power system with RF power, according to some embodiments. [Figure 9] FIG. 9 shows an example of a side-by-side display of waveforms with and without droop compensation generated by a nanosecond pulser without a system according to some embodiments. [Figure 10A]10A and 10B are histograms of wafer potential with and without droop correction, according to some embodiments. [Figure 10B] Same as above. [Figure 11] FIG. 11 is a circuit diagram of a power system having a droop compensation circuit driving a load circuit, according to some embodiments. [Figure 12] FIG. 12 is a circuit diagram of a power system having a droop compensation circuit driving a load stage, according to some embodiments. [Figure 13] FIG. 13 is a circuit diagram of a pulser and plasma system according to some embodiments. [Figure 14] Figure 14 is a circuit diagram of a pulser and a plasma system that combines the pulser and plasma system with an energy recovery circuit. DETAILED DESCRIPTION OF THE INVENTION

[0029] Some embodiments include a power system including a nanosecond pulser that generates pulses (e.g., square wave pulses) to drive a plasma in a plasma chamber, and the power system can include a snubber circuit that includes circuit elements to cancel ion currents in the plasma that occur after the pulse is completed.

[0030] FIG. 1 is a circuit diagram of a pulser and plasma system 100 for driving pulses into a plasma chamber 106, according to some embodiments. These pulses may include, for example, square wave pulses. A pulser stage 101 may generate multiple pulses that may be injected into the plasma chamber 106. An RF generator 108 may generate an RF signal, for example, a sinusoidal signal. A filter circuit 103 may prevent the RF signal and the pulses from interfering with each other. The values ​​of components in the snubber circuit, for example, snubber resistor R3, snubber inductor L3, and / or snubber capacitor C5, may be selected to reduce droop of the pulses injected into the plasma chamber 106.

[0031] For example, snubber resistor R3 may have a resistance of less than about 100 mΩ, e.g., 75, 50, 25, 10, 5, 1, 0.5 mΩ, etc. Alternatively or additionally, snubber resistor R3 may have a resistance of between about 7.5 mΩ and 1.25 mΩ. For example, the snubber capacitor may have a capacitance of less than about 50 μF, e.g., between about 2 μF and 35 μF.

[0032] In some embodiments, plasma chamber 106 may represent an idealized or effective circuit for a semiconductor processing chamber, such as a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc. Capacitor 12 may represent, for example, the capacitance of an electrostatic chuck on which a semiconductor process wafer may rest. The chuck may include, for example, a dielectric material (e.g., aluminum oxide or other ceramic material and a conductor encased within the dielectric material). For example, capacitor 11 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0033] Capacitor 13 may represent, for example, the sheath capacitance between the plasma and the wafer. Resistor 56 may represent, for example, the sheath resistance between the plasma and the wafer. Inductor 40 may represent, for example, the sheath inductance between the plasma and the wafer. Current source I2 may represent, for example, the ion current through the sheath. For example, capacitor 11 or capacitor 13 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0034] Capacitor 18 can represent, for example, the plasma sheath capacitance to the chamber wall. Resistor 57 can represent, for example, the resistance between the plasma and the chamber wall. Current source I1 can represent, for example, the ion current in the plasma. For example, capacitor 11 or capacitor 18 can have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0035] In some embodiments, the plasma voltage may be the voltage measured from ground to circuit point 123, the wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer, the chucking voltage is the voltage measured from ground to circuit point 121, the electrode voltage is the voltage measurement from ground to circuit point 124 (e.g., on the electrode), and the input voltage is the voltage measured from ground to circuit point 125.

[0036] In some embodiments, the pulser and plasma system 100 can include a DC bias circuit 104 as shown in FIG.

[0037] In some embodiments, bias capacitor 20 can isolate (or decouple) the DC bias voltage from other circuit elements. Bias capacitor 20 can, for example, allow a potential shift from one portion of the circuit to another. In some embodiments, this potential shift can ensure that the electrostatic force holding the wafer in place on the chuck remains below a voltage threshold. Resistor R2 can isolate the DC bias power supply from the high voltage pulse output from pulser stage 101.

[0038] The bias capacitor 20 may have a capacitance of, for example, about 100 pF, 10 pF, 1 pF, 100 μF, 10 μF, less than 1 μF, etc. Resistor R2 may have a high resistance, for example, about 1 kΩ, 10 kΩ, 100 kΩ, 1 MΩ, 10 MΩ, 100 MΩ, etc.

[0039] Circuit 105 may represent a transmission line from the circuit to plasma chamber 106. Resistor 63 may represent, for example, the resistance of a lead or transmission line connecting the output of a high voltage power system to an electrode (e.g., plasma chamber 106). Capacitor 11 may represent, for example, the stray capacitance of a lead or transmission line.

[0040] In some embodiments, the pulser stage 101 can generate pulses having high pulse voltages (e.g., voltages greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high frequencies (e.g., frequencies greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), fast rise times (e.g., rise times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), fast fall times (e.g., fall times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), and / or short pulse widths (e.g., pulse widths less than about 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0041] For example, pulser stage 101 may include all or any portion of any of the devices described in U.S. patent application Ser. No. 14 / 542,487, entitled "High Voltage Nanosecond Pulser," which is incorporated herein for all purposes, or may include all or any portion of any of the devices described in U.S. patent application Ser. No. 14 / 635,991, entitled "Galvanically Isolated Output Variable Pulse Generator Disclosure," which is incorporated herein for all purposes, or may include all or any portion of any of the devices described in U.S. patent application Ser. No. 14 / 798,154, entitled "High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency," which is incorporated herein for all purposes.

[0042] In some embodiments, pulser stage 101 may include one or more nanosecond pulsers connected in any manner.

[0043] In some embodiments, the pulser stage 101 can include a DC power supply that provides a constant DC voltage that is switched by switch S6 and supplies the switched power to the transformer T1. The DC power supply can include a voltage source V5 and an energy storage capacitor C7. If the turns ratio of the transformer T1 is 1:10, the transformer can generate 10 kV at the load.

[0044] In some embodiments, if the load capacitance (e.g., capacitor 13 and capacitor 18) is small compared to the capacitance of energy storage capacitor C7, a doubled voltage may (or may not) occur at the transformer input. For example, if energy storage capacitor C7 provides 500V, 1 kV may be measured at the input of transformer T1.

[0045] Switch S6 may include, for example, one or more solid-state switches, such as IGBTs, MOSFETs, SiC MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc. Switch S6 may be switched based on signals from a controller labeled Sig6+ and Sig6−.

[0046] In some embodiments, switch S6 can switch so fast that the switched voltage never becomes the full voltage (e.g., the voltage of energy storage capacitor C7 and / or voltage source V5). In some embodiments, a gate resistor connected to switch S6 can be set with a short turn-on pulse.

[0047] In some embodiments, pulser stage 101 may include a freewheeling diode D2. In some embodiments, freewheeling diode D2 can be used in combination with an inductive load to ensure that any stored energy in the inductive load is dissipated by allowing current to continue flowing in the same direction through the inductor after switch S6 opens, thereby ensuring that the energy is dissipated in the resistive elements of the circuit. If freewheeling diode D2 were not included, for example, a reverse voltage could develop across switch S6.

[0048] In some embodiments, the pulser stage 101 may include a stray inductance L1 and / or a stray resistance R1. The stray inductance L1 may be, for example, less than about 10 nH, 100 nH, 1,000 nH, 10,000 nH, etc. The stray resistance R1 may be, for example, less than about 1 Ω, 100 mΩ, 10 mΩ, etc.

[0049] In some embodiments, the energy recovery circuit 110 can be electrically connected to the secondary side of the transformer and / or the energy storage capacitor C7. The energy recovery circuit 110 can include, for example, a crowbar diode 130 across the secondary side of the transformer T1. The energy recovery circuit 110 can include, for example, an energy recovery diode 120 and an energy recovery inductor 115 (arranged in series) to allow current to flow from the secondary side of the transformer T1 and charge the energy storage capacitor C7. The energy recovery diode 120 and the energy recovery inductor 115 can be electrically connected to the secondary side of the transformer T1 and the energy storage capacitor C7. In some embodiments, the energy recovery circuit 110 can include the crowbar diode 130 and / or an inductor 140 electrically connected to the secondary side of the transformer T1. The inductor 140 can represent stray inductance and / or include stray inductance of the transformer T1.

[0050] In some embodiments, the energy recovery inductor 115 can include any type of inductor, such as a ferrite core inductor or an air core inductor. In some embodiments, the energy recovery inductor 115 can have any type of shape, such as a solenoidal winding, a toroidal winding, etc. In some embodiments, the energy recovery inductor 115 can have an inductance greater than about 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, the energy recovery inductor 115 can have an inductance between about 1 μH and about 100 mH.

[0051] In some embodiments, the order of the energy recovery inductor 115 and the energy recovery diode 120 can be reversed. For example, the energy recovery diode 120 can follow the energy recovery inductor 115, or the energy recovery inductor 115 can follow the energy recovery diode 120.

[0052] In some embodiments, when the nanosecond pulser is turned on, current can charge the plasma chamber 106 (e.g., charging capacitor 13, capacitor 12, or capacitor 18). For example, if the voltage on the secondary side of transformer T1 rises above the charging voltage of energy storage capacitor C7, some current can flow through energy recovery inductor 115. When the nanosecond pulser is turned off, current can flow from a capacitor in the plasma chamber (e.g., capacitor 11) through energy recovery inductor 115 to charge energy storage capacitor C7 until the voltage across energy recovery inductor 115 reaches zero. Crowbar diode 130 can prevent the capacitor in the plasma chamber 106 from ringing with inductance in the plasma chamber 106 or DC bias circuit 104.

[0053] The energy recovery diode 120 can, for example, prevent charge from flowing from the energy storage capacitor C7 to a capacitor within the plasma chamber 106.

[0054] The value of the energy recovery inductor 115 can be selected to control the fall time of the current. In some embodiments, the energy recovery inductor 115 can have an inductance value between 1 μH and 600 μH. In some embodiments, the energy recovery inductor 115 can have an inductance value greater than 50 μH. In some embodiments, the energy recovery inductor 115 can have an inductance less than approximately 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 400 μH, 400 μH, 500 μH, etc.

[0055] For example, if energy storage capacitor C7 supplies 500V, 1 kV can be measured at the input of transformer T1 (e.g., by voltage doubling, as described above). The 1 kV at transformer T1 can be divided among the components of energy recovery circuit 110 when switch S6 is open. If the values ​​are appropriately selected (e.g., snubber inductor L3 has an inductance smaller than that of energy recovery inductor 115), the voltage across energy recovery diode 120 and energy recovery inductor 115 can be greater than 500V. Current can then flow through energy recovery diode 120 and / or charge energy storage capacitor C7. Current may also flow through diode D3 and inductor L8. When energy storage capacitor C7 is charged, current cannot flow through diode D3 and energy recovery inductor 115.

[0056] In some embodiments, the energy recovery circuit 110 can transfer energy (or charge) from the plasma chamber 106, for example, on a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The stray resistance of the energy recovery circuit can be low to ensure that the pulse across the plasma chamber 106 has a fast fall time tf. The stray resistance of the energy recovery circuit 110 can have a resistance of, for example, less than about 1 Ω, 100 mΩ, 10 mΩ, etc. In some embodiments, the efficiency of energy transfer from the plasma chamber 106 can be high, for example, greater than about 60%, 70%, 80%, or 90%, etc.

[0057] Any number of the components shown in FIG. 1, such as diode 135 or crowbar diode 130, or inductor 140, may or may not be required.

[0058] In some embodiments, a diode can be placed between voltage source V1 and the point where energy recovery circuit 110 connects to voltage source V1 and / or energy storage capacitor C7. This diode can be placed, for example, to allow current to flow from voltage source V1 to energy storage capacitor C7, but not to allow current to flow from the energy recovery circuit to energy storage capacitor C7.

[0059] In some embodiments, the energy recovery circuit 110 may be eliminated. In some embodiments, a resistive output stage or bias compensation circuit may be included. Various other circuits or circuit elements may be included.

[0060] In some embodiments, the pulser and plasma system 100 can include a filter circuit 103. In this example, the filter circuit includes a filter capacitor 185 and / or a filter inductor 180. The filter capacitor 185 can, for example, filter low-frequency signals from the pulser stage 101. These low-frequency signals can have frequencies (e.g., most of the spectral content) between about 100 kHz and about 10 MHz, for example, about 10 MHz. The filter capacitor 185 can have a value between about 1 pF and 1 nF, for example, less than about 100 pF.

[0061] In some embodiments, the filter inductor 180 can filter high frequency signals, for example, from the RF generator 108. These high frequency signals can have frequencies, for example, between about 1 MHz and 200 MHz, for example, greater than about 1 MHz or 10 MHz. The filter inductor 180 can have a value, for example, between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 can have a low coupling capacitance therebetween. In some embodiments, the coupling capacitance can be less than 1 nF.

[0062] In some embodiments, either or both of the filter capacitor 185 and the filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulser stage 101 (or vice versa). For example, the filter capacitor 185 can isolate pulses generated by the pulser stage 101 from pulses generated by the RF generator 108. The filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulser stage 101.

[0063] 2 is a circuit diagram of a power system 200 having a resistive output stage 220 driving a load stage, according to some embodiments. In this example, the energy recovery circuit 110 is removed from the pulser and plasma system 100 and replaced with the resistive output stage 220.

[0064] Resistive output stage 220 may include any resistive output stage known in the art. For example, resistive output stage 220 may include any resistive output stage described in U.S. patent application Ser. No. 16 / 178,538, entitled "HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT," which is incorporated herein in its entirety for all purposes.

[0065] For example, resistive output stage 220 may include inductor L11, resistor R10, resistor R11, and capacitor C11. In some embodiments, inductor L11 may include an inductance between about 5 μH and about 25 μH. In some embodiments, resistor R11 may include a resistance between about 50 Ω and about 250 Ω. In some embodiments, resistor R10 may include stray resistance in resistive output stage 220.

[0066] In some embodiments, resistor R11 may include multiple resistors arranged in series and / or parallel. Capacitor C11 may represent the stray capacitance of resistor R11, including the capacitance of the resistors arranged in series and / or parallel. The capacitance of stray capacitance C11 may be, for example, less than 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, etc. For example, the capacitance of stray capacitance C11 may be less than the capacitance of the load capacitance, for example, 12, 13, and / or 18.

[0067] In some embodiments, resistor R11 can discharge a load (e.g., plasma sheath capacitance). In some embodiments, resistive output stage 220 can be configured to discharge an average power of more than about 1 kilowatt during each pulse cycle and / or discharge an energy of 1 joule or less in each pulse cycle. In some embodiments, resistor R11 of resistive output stage 220 can have a resistance value of less than 200 Ω. In some embodiments, resistor R11 can comprise multiple resistors arranged in series or parallel (e.g., 111) with a combined capacitance of less than about 200 pF.

[0068] In some embodiments, resistive output stage 220 may include a collection of circuit elements that can be used to control the shape of a voltage waveform at a load. In some embodiments, resistive output stage 220 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, resistive output stage 220 may include active circuit elements (e.g., switches) as well as passive circuit elements. In some embodiments, resistive output stage 220 may be used to control, for example, the rise time of a voltage waveform and / or the fall time of a voltage waveform.

[0069] In some embodiments, the resistive output stage 220 can discharge capacitive loads (e.g., the wafer and / or plasma). For example, these capacitive loads can have small capacitances (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0070] In some embodiments, resistive output stage 220 can be used in circuits having high pulse voltages (e.g., voltages greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), and / or high frequencies (e.g., frequencies greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), and / or pulses having frequencies of about 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0071] In some embodiments, resistive output stage 220 may be selected to handle high average power, high peak power, fast rise times, and / or fast fall times. For example, the average power rating may be greater than about 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., and / or the peak power rating may be greater than about 1 kW, 10 kW, 100 kW, 1 MW, etc.

[0072] In some embodiments, resistive output stage 220 can include a network of passive elements in series or parallel. For example, resistive output stage 220 can include a resistor, a capacitor, and an inductor in series. As another example, resistive output stage 220 can include a capacitor in parallel with an inductor, and a capacitor-inductor combination in series with a resistor. For example, L11 can be selected to be large enough so that significant energy is not injected into resistive output stage 220 when voltage is coming out of the rectifier. The values ​​of R10 and R11 can be selected so that a suitable capacitor in the load can discharge faster than the RF frequency in L / R time.

[0073] In some embodiments, the pulser stage 101 of either the pulser and plasma system 100 or the power system 200 may include a snubber circuit. In some embodiments, the snubber circuit may include a snubber capacitor C5. In some embodiments, the snubber circuit may include a snubber capacitor C5 and a snubber resistor R3. In some embodiments, the snubber circuit may include a snubber capacitor C5, a snubber inductor L3, and a snubber resistor R3.

[0074] In some embodiments, the snubber circuit may include a snubber resistor R3, and / or a snubber inductor L3 may be arranged in parallel with a snubber diode D4. The snubber inductor L3, snubber resistor R3, and snubber diode D4 may be arranged in series with a snubber capacitor C5. In some embodiments, the snubber resistor R3 and / or snubber diode D4 may be arranged between the collector of switch S6 and the primary winding of transformer T1. The snubber diode D4 may be used to mitigate overvoltages during switching. A large and / or high-speed snubber capacitor C5 may be connected to either the emitter or collector side of switch S6. A freewheeling diode D2 may also be connected to the emitter side of switch S1. Various other elements not shown may be included. One or more switches and / or circuits may be arranged in parallel or in series.

[0075] In some embodiments, to suppress ion current in the chamber, a positive current can be drawn from the pulser stage 101 after the pulse ends. This can be achieved, for example, by adjusting the inductance of snubber inductor L3 (which can be removed, for example), and the resistance of snubber resistor R3 and / or the capacitance of snubber capacitor C5 are such that snubber capacitor C5 can discharge during the pulse and / or may not fully charge before the next pulse. This can, for example, allow a decaying current to flow from energy storage capacitor C7 and / or voltage source V1 in the same direction as current flow during the pulse. This can produce a waveform shape on the wafer that does not include droop.

[0076] Droop may also appear as a voltage rise between pulses generated by pulser stage 101. Droop may consist of a voltage rise of 0.2 V / ns (e.g., for a chuck with a capacitance of about 5 nF and an ion current of 1 Amp) or 1 V / ns (e.g., for a chuck with a capacitance of about 5 nF and an ion current of 5 Amp).

[0077] An RF generator 108 may be electrically connected to the plasma chamber 106. The RF generator 108 may, for example, introduce a high frequency RF signal into the plasma chamber, thereby generating a plasma from components within the chamber.

[0078] The RF generator 108 can include any type of device that generates RF power to be applied to the cathode. The RF generator 108 can include, for example, a nanosecond pulser, a resonant system driven by a half-bridge or full-bridge circuit, an RF amplifier, a nonlinear transmission line, an RF plasma generator, etc. In some embodiments, the RF generator 108 can include an impedance matching network.

[0079] In some embodiments, the RF generator 108 can include one or more RF drivers capable of generating RF power signals having multiple different RF frequencies, e.g., 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz. Typical RF frequencies can include, for example, frequencies between 200 kHz and 800 MHz. In some embodiments, the RF generator 108 can generate and maintain a plasma in the plasma chamber. The RF generator 108 can, for example, supply an RF signal to a cathode (and / or antenna) to excite various gases and / or ions in the chamber and generate a plasma.

[0080] In some embodiments, the RF generator 108 may be connected to or include an impedance matching circuit that can match the non-standard output impedance of the RF generator 108 to the industry standard characteristic impedance of a 50 Ω coaxial cable or any cable.

[0081] In some embodiments, the RF generator 108 may generate bursts at an RF frequency that is higher than the pulse repetition frequency of the pulses generated by the pulser stage 101 .

[0082] In some embodiments, the pulser and plasma system 100 can include a filter capacitor 185 and / or a filter inductor 180. The filter capacitor 185 can, for example, filter low-frequency signals from the pulser stage 101. These low-frequency signals can have frequencies (e.g., most of the spectral content) between about 100 kHz and about 10 MHz, for example, about 10 MHz. The filter capacitor 185 can have a value between about 1 pF and 1 nF, for example, less than about 100 pF.

[0083] In some embodiments, the filter inductor 180 can filter high frequency signals, for example, from the RF generator 108. These high frequency signals can have frequencies, for example, between about 1 MHz and 200 MHz, for example, greater than about 1 MHz or 10 MHz. The filter inductor 180 can have a value, for example, between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 can have a low coupling capacitance therebetween. In some embodiments, the coupling capacitance can be less than 1 nF.

[0084] In some embodiments, either or both of the filter capacitor 185 and the filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulser stage 101 (or vice versa). For example, the filter capacitor 185 can isolate pulses generated by the pulser stage 101 from pulses generated by the RF generator 108. The filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulser stage 101.

[0085] 3 is an example of two waveforms generated by the power system without RF power (e.g., without an RF signal from RF generator 108), according to some embodiments. In this example, chuck waveform 305 is the chuck voltage (e.g., circuit node 121), and wafer waveform 310 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 75 mΩ, snubber capacitor C5 has a capacitance of 12 μF, the pulse width is 100 ns, and the inductance of filter inductor 180 can be, for example, approximately 100 nH. The DC voltage supplied by voltage source V1 is 500 V. As shown, wafer waveform 310 is approximately flat between pulses. For example, between pulses, wafer waveform 310 has a slope less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0086] FIG. 4 illustrates two example waveforms generated by a power system with RF power (e.g., with an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 405 is the chuck voltage (e.g., circuit node 121), and wafer waveform 410 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 75 mΩ, snubber capacitor C5 has a capacitance of 12 μF, the pulse width is 100 ns, and the inductance of filter inductor 180 is approximately 100 nH. The DC voltage supplied by voltage source V1 is 500 V. As shown, wafer waveform 410 is approximately flat between pulses. Wafer waveform 410 may vary with smaller successive pulse changes, e.g., changes between successive pulses of less than 1 V / ns.

[0087] 5 is an example of two waveforms generated by the power system without RF power (e.g., without an RF signal from RF generator 108), according to some embodiments. In this example, chuck waveform 505 is the chuck voltage (e.g., circuit node 121), and wafer waveform 510 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, the pulse width is 150 ns, and the inductance of filter inductor 180 is approximately 0 nH. The DC voltage supplied by voltage source V1 is 750 V. As shown, wafer waveform 510 is approximately flat between pulses. For example, between pulses, wafer waveform 510 has a slope less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0088] FIG. 6 illustrates two example waveforms generated by a power system with RF power (e.g., with an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 605 is the chuck voltage (e.g., circuit node 121), and wafer waveform 610 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, the pulse width is 150 ns, and the inductance of filter inductor 180 is approximately 0 nH. The DC voltage supplied by voltage source V1 is 750 V. As shown, wafer waveform 610 is approximately flat between pulses. For example, between pulses, wafer waveform 610 has a slope less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0089] FIG. 7 illustrates two example waveforms generated by the power system without RF power (e.g., without an RF signal from RF generator 108), according to some embodiments. In this example, chuck waveform 705 is the chuck voltage (e.g., circuit node 121), and wafer waveform 710 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, the pulse width is 250 ns, and the inductance of filter inductor 180 is approximately 0 nH. The DC voltage supplied by voltage source V1 is 700 V. As shown, wafer waveform 710 is approximately flat between pulses. For example, between pulses, wafer waveform 710 has a slope less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0090] FIG. 8 illustrates two example waveforms generated by a power system with RF power (e.g., with an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 805 is the chuck voltage (e.g., circuit node 121), and wafer waveform 810 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, the pulse width is 250 ns, and the inductance of filter inductor 180 is approximately 0 nH. The DC voltage supplied by voltage source V1 is 800 V. As shown, wafer waveform 810 is approximately flat between pulses. For example, between pulses, wafer waveform 810 has a slope less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0091] 9 shows an example of side-by-side waveforms generated by a nanosecond pulser without droop compensation in accordance with some embodiments. In this example, chucking waveform 905 is the chucking voltage without droop compensation, and chucking waveform 915 is the chucking voltage with droop compensation. In this example, wafer waveform 910 is the chucking voltage without droop compensation, and wafer waveform 920 is the chucking voltage with droop compensation. In this example, without droop compensation, snubber resistor R3 has a resistance of 1.25 Ω and snubber capacitor C5 has a capacitance of 2 μF; with droop compensation, snubber resistor R3 drops to 75 Ω and snubber capacitor C5 has a capacitance of 12 μF.

[0092] 10A and 10B are histograms of wafer potential without and with droop compensation, respectively, according to some embodiments.

[0093] FIG. 11 is a circuit diagram of a power system 1100 having a droop compensation circuit 165 for driving a plasma chamber 106, according to some embodiments. In some embodiments, the droop compensation circuit 165 can include a crowbar diode 130 and a droop capacitor 170. The droop capacitor 170 can have a capacitance of about 1 nF to about 100 nF. In this example, the addition of the droop capacitor 170 allows current flowing through the crowbar diode 130 and the energy recovery circuit 110 to induce a voltage change across the droop capacitor 170, counteracting the droop. The droop capacitor 170 can limit the flow of current until the droop capacitor 170 is charged and no longer droops. A switch 171 can be used to discharge charge from the droop capacitor 170 to ground during a pulse. The switch 171 can be switched at the same switching frequency and / or period as the switch 171, for example, using the same signal. For example, when switch 171 is closed, pulser stage 101 pulses and switch 171 closes to discharge droop capacitor 170 .

[0094] In some embodiments, the power supply 174 can provide a DC offset or bias, if desired. In some embodiments, when the charge is discharged from the droop capacitor 170, the power supply 174 can also be charged.

[0095] In some embodiments, inductor 172 may be a current-limiting inductor. Inductor 172 may have, for example, an inductance of about 10 nH to about 500 nH. Diode 173 and / or diode 175 may be a crowbar diode. Diode 175 may, for example, allow current to flow when switch 171 is open and may allow voltage spikes to flow to ground.

[0096] In some embodiments, inductor 172, diode 173 and / or diode 175 may be replaced with a resistor.

[0097] Switch 171 can include any type of switch capable of switching high voltages at high frequencies. In some embodiments, switch 171 includes a high voltage switch as described in U.S. patent application Ser. No. 62 / 717,637, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," and / or U.S. patent application Ser. No. 16 / 178,565, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," which are incorporated herein in their entireties for all purposes.

[0098] In some embodiments, the energy recovery circuit 110 can be removed or replaced with a primary sink circuit and / or a resistive output stage. In some embodiments, the energy recovery circuit 110 may be connected to ground after the energy recovery inductor 115.

[0099] In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes an offset supply voltage V5, which can, for example, bias the output voltage either positively or negatively. In some embodiments, the offset supply voltage V5 can be adjusted to vary the potential between the wafer voltage and the chuck voltage. In some embodiments, the offset supply voltage V5 can have a kV voltage of approximately ±5 kV, ±4 kV, ±3 kV, ±2 kV, ±1 kV, etc. The DC bias circuit 104 may or may not be included in the power system 1100.

[0100] The power system 1100 may include an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals may have frequencies, for example, between about 1 MHz and 200 MHz, such as about 1 MHz or greater than 10 MHz. The filter inductor 180 may have a value, for example, between about 10 nH and 10 μH, such as greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance therebetween. In some embodiments, the coupling capacitance may be less than 1 nF.

[0101] 12 is a circuit diagram of a pulser and plasma system 1200 having a droop compensation circuit 190 driving a plasma chamber 106, according to some embodiments. The droop compensation circuit 190 can include a negative DC power supply 182, a switch 181, and a current-limiting resistor 183 or a current-limiting inductor 184. The current-limiting resistor 183 can have a resistance of, for example, about 0.1 Ω to about 50 Ω, or about 10 mΩ to about 500 Ω. The current-limiting inductor 184 can have an inductance of, for example, about 1 nH to about 100 nH. When the switch 181 is closed, the negative DC power supply 182 can pull down the voltage to eliminate and limit droop.

[0102] Switch 181 can include any type of switch capable of switching high voltages at high frequencies. In some embodiments, switch 181 includes a high voltage switch as described in U.S. patent application Ser. No. 62 / 717,637, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," and / or U.S. patent application Ser. No. 16 / 178,565, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," which are incorporated herein in their entireties for all purposes.

[0103] In some embodiments, the pulser and plasma system 1200 can include an energy recovery circuit (eg, the energy recovery circuit 110 ) rather than a resistive output stage 220 .

[0104] The pulser and plasma system 1200 can include an RF generator 108 and a filter inductor 180. The filter inductor 180 can, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals can have frequencies of, for example, about 1 MHz to 200 MHz, such as about 1 MHz or greater than 10 MHz. The filter inductor 180 can have a value of, for example, about 10 nH to 10 μH, such as greater than about 1 μH. In some embodiments, the filter inductor 180 can have a low coupling capacitance therebetween. In some embodiments, the coupling capacitance can be less than 1 nF.

[0105] 13 is a circuit diagram of a pulser and plasma system 1300 according to some embodiments. The pulser and plasma system 1300 can include, for example, a pulse driver 1305, which is shown in a full-bridge configuration but may also be in a half-bridge configuration, a droop compensation circuit 1310, a transformer 1345, and a voltage source V1. The droop compensation circuit 1310 can, for example, mitigate or reduce voltage droop.

[0106] In this example, the pulser and plasma system 1300 may include a pulse driver 1305. The pulse driver 1305 may be, for example, a half-bridge driver or a full-bridge driver. The pulse driver 1305 may include a voltage source V1, which may be a DC voltage source (e.g., a capacitive source, an AC-DC converter, etc.). In some embodiments, the pulse driver 1305 may include four bridge switches 661, 662, 664, 664. In some embodiments, the pulse driver 1305 may include multiple switches 661, 662, 664, and 664 in series or parallel. These switches 661, 662, 664, and 664 may include, for example, any type of solid-state switch, such as an IGBT, a MOSFET, a SiC MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. These switches 661, 662, 664, and 664 may be capable of switching at high frequencies and / or generating high-voltage pulses. These frequencies may include, for example, frequencies of approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, and the like.

[0107] Each of switches 661, 662, 664, and 664 can be connected in parallel with a respective bridge diode and can include a stray inductance. In some embodiments, the stray inductances of the bridge switches can be equal. In some embodiments, the stray inductances of the bridge switches can be less than approximately 50 nH, 100 nH, 150 nH, 500 nH, 1,000 nH, etc. The combination of a switch (661, 662, 664, or 664) and its respective bridge diode can be connected in series with a respective bridge inductor. For example, the bridge inductors associated with switches 663 and 664 can be connected to ground. For example, the bridge inductor associated with switch 661 can be electrically connected to bridge switch 664 and to resistor 1315 and / or inductor 1316 of droop compensation circuit 1310. Also, the bridge inductor associated with switch 662 can be electrically connected to bridge switch 663 and diode 1313 of droop compensation circuit 1310, for example.

[0108] When the switches in the pulse driver 1305 are switched at the resonant frequency, the output voltage of the transformer 1345 is amplified. In some embodiments, the resonant frequency is about 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0109] In some embodiments, transformer 1345 (or transformer T1) may include a transformer such as that disclosed in U.S. patent application Ser. No. 15 / 365,094, entitled "High Voltage Transformer," which is incorporated herein in its entirety for all purposes.

[0110] For example, the duty cycle of the switches can be adjusted by changing the duty cycle of signal Sig1 that opens and closes bridge switch 661, changing the duty cycle of signal Sig2 that opens and closes bridge switch 662, changing the duty cycle of signal Sig3 that opens and closes bridge switch 664, and changing the duty cycle of signal Sig4 that opens and closes bridge switch 663.

[0111] In some embodiments, each bridge switch 661, 662, 664, or 664 in pulse driver 1305 can be switched independently or in conjunction with one or more other switches. For example, signal Sig1 can be the same signal as signal Sig3. As another example, signal Sig2 can be the same signal as signal Sig4. As another example, each signal can be independent and can control each bridge switch 661, 662, 664, or 664 independently or separately.

[0112] In some embodiments, the output of the droop compensation circuit 1310 can be connected to a half-wave rectifier that can include a blocking diode that can be placed on the secondary side of the transformer 1345 or the primary side of the transformer 1345.

[0113] In some embodiments, the output of the droop compensation circuit 1310 can be connected to a resistive output stage, such as the resistive output stage 220 shown in FIG. 12. The resistive output stage may include any resistive output stage known in the art. For example, the resistive output stage may include any of the resistive output stages described in U.S. Patent Application No. 16 / 178,538, entitled "HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT," which is incorporated herein in its entirety for all purposes.

[0114] The pulser and plasma system 1300 does not include a conventional matching network, e.g., a 50 Ω matching network, nor an external or standalone matching network. In fact, the embodiments described herein do not require a 50 Ω matching network to adjust the switching power applied to the wafer chamber. Furthermore, the embodiments described herein provide a variable output impedance RF generator without a conventional matching network, which allows for rapid changes in the power drawn by the plasma chamber. Typically, this matching network adjustment takes at least 100 μs to 200 μs. In some embodiments, a power change can occur within one or two RF cycles, e.g., 2.5 μs to 5.0 μs at 400 kHz.

[0115] In some embodiments, pulse driver 1305 can include switches arranged in a full-bridge topology as shown, or a half-bridge topology with two switches. Switches 661, 662, 663, and 664 can switch the DC charge stored in energy storage capacitor C7. Voltage source V1, which can be a DC voltage source (e.g., a capacitive power supply, an AC-DC converter, etc.), can charge energy storage capacitor C7. Pulse driver 1305 may or may not drive droop compensation circuit 1310 at a pulse frequency that is substantially equal to or substantially unequal to the resonant frequency of droop compensation circuit 1310, for example.

[0116] In some embodiments, the pulse driver 1305 can be replaced by a half-bridge topology with two switches.

[0117] The droop compensation circuit 1310 may include a diode 1313, an inductor 1312, an inductor 1314, an inductor 1316, a resistor 1315, and / or a resistor 1311. The diode 1313 may be forward biased between the pulse driver 1305 and the transformer 1345. The resistor 1315 may be, for example, very small. For example, the resistor 1315 may have a resistance of less than about 1 Ω, such as about 50, 25, 10, or 5 mΩ. As another example, the resistor 1315 may be as low as 0 Ω. For example, the resistor 1311 may be very small. For example, the resistor 1311 may have a resistance of less than about 5 Ω, such as about 10, 5, 2, 1, 0.75, 0.5, or 0.25 Ω. Inductor 1316 and / or inductor 1314 can have an inductance of, for example, less than about 100 nH, such as about 75, 50, 25, 10, 5 nH, etc.

[0118] The inductor 1312 may have an inductance of less than about 50H, for example, about 25, 10, 5, 2.5, 1H, etc.

[0119] The pulser and plasma system 1300 can include an RF generator 108 and a filter inductor 180. The filter inductor 180 can, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals can have frequencies, for example, between about 1 MHz and 200 MHz, such as about 1 MHz or greater than 10 MHz. The filter inductor 180 can have a value, for example, between about 10 nH and 10 μH, such as greater than about 1 μH. In some embodiments, the filter inductor 180 can have a low coupling capacitance therebetween. In some embodiments, the coupling capacitance can be less than 1 nF.

[0120] 14 is a circuit diagram of a pulser and plasma system 1400 that combines the pulser and plasma system 1300 with an energy recovery circuit 110. As another example, instead of combining the energy recovery circuit 110 with the pulser and plasma system 1300, a droop compensation circuit 190 may be combined with the pulser and plasma system 1300.

[0121] Unless otherwise specified, the term "substantially" means within 5% or 10% of the stated value or within manufacturing tolerances. Unless otherwise specified, the term "about" means within 5% or 10% of the stated value or within manufacturing tolerances.

[0122] The conjunction "or" is inclusive.

[0123] The terms "first," "second," "third," etc. are used to distinguish between elements and are not used to indicate a particular order of these elements unless otherwise noted or an order is explicitly described or required.

[0124] Numerous specific details are described in order to provide a thorough understanding of claimed subject matter. However, those skilled in the art will understand that claimed subject matter may be practiced without these specific details. In other instances, methods, apparatuses, or systems that would be known to those skilled in the art have not been described in detail so as not to obscure claimed subject matter.

[0125] Embodiments of the disclosed methods may be performed in operation on such a computing device. The order of the blocks shown in the above examples may be changed, e.g., the blocks may be rearranged, combined, and / or divided into sub-blocks. Some blocks or processes may be performed in parallel.

[0126] The use of "adapted" or "configured" means open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps. Additionally, the use of "based on" means open and inclusive in that a process, step, calculation, or other operation that is "based on" one or more enumerated conditions or values ​​may, in fact, be based on additional conditions or values ​​beyond those enumerated. The included headings, lists, and numbers are for ease of description only and are not intended to be limiting.

[0127] While the present subject matter has been described in detail with reference to specific embodiments thereof, it will be understood that those skilled in the art, once they arrive at the foregoing understanding, can readily make alterations, variations, and equivalents of such embodiments. Accordingly, it will be understood that the present disclosure has been presented by way of example and not limitation, and is not intended to exclude the inclusion of such alterations, variations, and / or additions to the present subject matter as would be readily apparent to those skilled in the art. [Appendix 1] 1. A power supply system, comprising: an RF driver that generates an RF signal having an RF frequency; a nanosecond pulser that generates high voltage pulses having a pulse repetition frequency and pulse width lower than the RF frequency and a peak voltage exceeding 2 kV, the nanosecond pulser comprising: a snubber resistor having a resistance of approximately 7.5 mΩ to 1.25 Ω; a nanosecond pulser having a snubber circuit including a snubber capacitor having a capacitance of approximately 2 μF to 35 μF; a filter circuit disposed between the RF driver and the plasma chamber. [Appendix 2] 2. The power supply of claim 1, wherein the nanosecond pulser generates a square wave. [Appendix 3] 2. The power supply of claim 1, wherein the filter circuit includes a filter inductor having an inductance of approximately 0 to 2.5 μH. [Appendix 4] 10. The power supply of claim 1, wherein the power supply has a stray inductance of less than about 800 nH. [Appendix 5] 2. The power supply of claim 1, wherein the pulse width has a duration of about 100 to 250 ns. [Appendix 6] 2. The power supply of claim 1, wherein the voltage between two successive pulses without the RF signal changes by less than 1 V / ns. [Appendix 7] 2. The power supply of claim 1, wherein the average voltage between two successive pulses varies by less than 1 V / ns. [Appendix 8] 10. The power supply of claim 1, wherein the power supply outputs a waveform having an RF signal during each of a plurality of high voltage pulses. [Appendix 9] 1. A semiconductor processing system comprising: A plasma chamber; and a power supply of claim 1 connected to the plasma chamber and configured to introduce the RF signal and the drive pulse into the plasma chamber. [Appendix 10] 10. The power supply of claim 9, wherein the plasma chamber has an inductance of less than about 20 nH. [Appendix 11] 10. The power supply of claim 9, wherein the chamber includes a chuck having a capacitance of less than about 10 nF. [Appendix 12] A pulse generator comprising: a power source providing a voltage greater than 2 kV; It is a transformer, A transformer core and a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead; a secondary winding wound around at least a portion of the transformer core; a droop compensation circuit electrically connected to the first lead of the primary winding; a first switch electrically connecting the droop compensation circuit and the power source; a second switch electrically connected to the second lead of the primary winding and to the power source, the first switch and the second switch opening and closing at different time intervals; a pulse output electrically connected to the secondary winding of the transformer, the pulse output outputting a square wave pulse. [Appendix 13] 13. The pulse generator of claim 12, wherein the pulse output outputs pulses having a voltage greater than about 2 kV and a pulse frequency greater than 1 kHz. [Appendix 14] 13. The pulse generator of claim 12, wherein the droop compensation circuit includes a droop diode biased to allow current to flow from the first switch toward the transformer. [Appendix 15] 15. The pulse generator of claim 14, wherein the droop compensation circuit includes a first inductor and a first resistor arranged in series and electrically connected across the droop diode. [Appendix 16] 16. The pulse generator of claim 15, wherein the first inductor has an inductance of less than about 50 μH. [Appendix 17] 16. The pulse generator of claim 15, wherein the first resistor has a resistance of less than about 1 Ω. [Appendix 18] 16. The pulse generator of claim 15, wherein the droop circuit further comprises a second inductor in electrical communication with the droop diode and the first lead of the primary winding. [Appendix 19] 19. The pulse generator of claim 18, wherein the second inductor has an inductance of less than about 50 nH. [Appendix 20] 19. The pulse generator of claim 18, further comprising a third resistor and a third inductor disposed in series between the second switch and the second lead of the primary winding. [Appendix 21] 21. The pulse generator of claim 20, wherein the third inductor has an inductance of less than about 35 nH. [Appendix 22] 21. The pulse generator of claim 20, wherein the third resistor has a resistance of less than about 1 Ω. [Appendix 23] A pulse generator comprising: a DC power source providing a voltage greater than 2 kV; It is a transformer, A transformer core and a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead; a secondary winding wound around at least a portion of the transformer core; a plurality of switches arranged in a full bridge configuration, a first portion of the plurality of switches electrically connected to the droop compensation circuit and the power source, a second portion of the plurality of switches electrically connected to the second lead of the primary winding and the power source, the first portion of the plurality of switches and the second portion of the plurality of switches being opened and closed at different time intervals; an attenuation circuit electrically disposed between the first portion of the plurality of switches and / or the second portion of the plurality of switches and the transformer, the attenuation circuit comprising: a diode biased from the first portion of the plurality of switches toward a first lead; a first resistor disposed between the diode and the first lead; a first inductor; a damping circuit comprising: a second resistor disposed in series with the first inductor and electrically connected across the diode; a pulse output in electrical communication with the secondary winding of the transformer, the pulse output having a voltage greater than about 2 kV and a pulse frequency greater than 1 kHz. [Appendix 24] 24. The pulse generator of claim 23, wherein the first inductor has an inductance of less than about 35 nH. [Appendix 25] 24. The pulse generator of claim 23, wherein the first resistor has a resistance of less than about 1 Ω. [Appendix 26] 24. The pulse generator of claim 23, wherein the second resistor has a resistance of less than about 1 Ω. [Appendix 27] 24. The pulse generator of claim 23, further comprising a second inductor and a third resistor disposed in series between the second portion of the plurality of switches and the second lead.

Claims

1. 1. A power supply system, comprising: an RF driver that generates an RF signal having an RF frequency; a nanosecond pulser that generates high voltage pulses having a pulse repetition frequency and pulse width lower than said RF frequency and a peak voltage greater than 2 kV; A transformer core and a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead; a secondary winding wound around at least a portion of the transformer core; a nanosecond pulser comprising: a transformer comprising: a damping circuit electrically coupled to the nanosecond pulser, A diode and a first resistor disposed between the diode and the first lead; a first inductor; a second resistor disposed in series with the first inductor and electrically connected across the diode; an attenuation circuit comprising: a pulse output electrically connected to the secondary winding of the transformer, the pulse output output outputting pulses having a voltage greater than 2 kV and a pulse frequency greater than 1 kHz, the pulse output configured to be connected to a plasma chamber; A power supply system comprising:

2. The power system of claim 1 , wherein the nanosecond pulser generates a square wave.

3. 10. The power system of claim 1, wherein the pulse width of the pulsed output has a duration of about 100 to 250 ns.

4. 2. The power supply system of claim 1, wherein the voltage between two successive pulses of the pulsed output without the RF signal varies by less than 1 V / ns.

5. 2. The power supply system of claim 1, wherein the average voltage between two successive pulses varies by less than 1 V / ns.

6. The power system of claim 1 , wherein the power system outputs a waveform having an RF signal during each of a plurality of high voltage pulses.

7. 10. The power system of claim 1, wherein the plasma chamber has an inductance of less than 20 nH.

8. 10. The power system of claim 1, wherein the plasma chamber includes a chuck having a capacitance of less than 10 nF.

9. A pulse generator comprising: a DC power supply providing a voltage greater than 2 kV; It is a transformer, A transformer core and a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead; a secondary winding wound around at least a portion of the transformer core; a transformer comprising: a plurality of switches arranged in a full bridge configuration, a first portion of the plurality of switches electrically connected to the first lead and to the DC power source and a second portion of the plurality of switches electrically connected to the second lead of the primary winding and to the DC power source, the first portion of the plurality of switches and the second portion of the plurality of switches being opened and closed at different time intervals; an attenuation circuit electrically disposed between the first portion of the plurality of switches and / or the second portion of the plurality of switches and the transformer, a diode biased from the first portion of the plurality of switches toward a first lead; a first resistor disposed between the diode and the first lead; a first inductor; a second resistor disposed in series with the first inductor and electrically connected across the diode; an attenuation circuit comprising: a pulse output electrically connected to the secondary winding of the transformer, the pulse output output having a voltage greater than 2 kV and a pulse frequency greater than 1 kHz, the pulse output configured to be connected to a plasma chamber; A pulse generator comprising:

10. 10. The pulse generator of claim 9, wherein the first inductor has an inductance of less than 35 nH.

11. 10. The pulse generator of claim 9, wherein the first resistor has a resistance of less than 1 ohm.

12. 10. The pulse generator of claim 9, wherein the second resistor has a resistance of less than 1 ohm.

13. 10. The pulse generator of claim 9, further comprising a second inductor and a third resistor disposed in series between the second portion of the plurality of switches and the second lead.

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