Gold plating on metal layers for backside connection access

Abstract

To provide a backside connection access structure and a fabrication method.SOLUTION: A method includes forming a gold layer on at least a portion of a substrate. The method also includes forming a metal layer on the gold layer, and forming an opening in the substrate to expose at least a portion of the gold layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Patent Application No. 62 / 665,239, filed May 1, 2018, and U.S. Patent Application No. 16 / 394,521, filed April 25, 2019, both of which are incorporated by reference in their entireties.

[0002] [Technical field] FIELD OF THE INVENTION Embodiments of the present invention relate to electrical connections. In particular, embodiments of the present invention relate generally to backside access for electrical connections. [Background technology]

[0003] The manufacture of devices that include electrical traces requires access to the electrical traces to electrically connect them to one or more electrical circuits or components. There is a continuing need for improved circuit structures to gain access to the electrical traces of devices. There is also a continuing need for effective and efficient processes for manufacturing circuits and other structures. Summary of the Invention

[0004] A backside interconnect access structure and method of fabrication are described. The method includes forming a gold layer on at least a portion of a substrate. The method also includes forming a metal layer on the gold layer. The method then includes forming an opening in the substrate to expose at least a portion of the gold layer. Other features and advantages of embodiments of the present invention will become apparent from the accompanying drawings and the detailed description that follows.

[0005] Embodiments of the present invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like reference numerals represent similar elements and in which: [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 illustrates a backside connection access structure according to an embodiment. [Figures 2a-2d] 2a-2d illustrate a process for forming a backside connection access structure according to an embodiment. [Figures 2e-2g] 2e-2g illustrate a process for forming a backside connection access structure according to an embodiment. [Figures 3a-3d] 3a-3d illustrate a process of forming a backside connection access structure by forming a dielectric layer before a gold layer according to an embodiment. [Figure 3e-3g] 3e-3g illustrate a process of forming a backside connection access structure by forming a dielectric layer before a gold layer, according to an embodiment. [Figures 4a-4e] 4a-4e illustrate a process for forming a backside contact access structure including a barrier layer according to an embodiment. [Figure 4f-4h] 4f-4h illustrate a process for forming a backside contact access structure including a barrier layer according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] In an embodiment of the present invention, a backside connection access and a method of fabrication are described. The backside connection access is configured to provide electrical contact to one or more of an electrical trace and a contact. The backside connection access includes a gold layer between the substrate and a metal layer. The metal layer may be a trace or a contact. can be formed as contacts. Openings are formed in the substrate to provide access to the gold layer and the metal layer for forming electrical connections with the metal layer. The gold layer allows for the use of additive and subtractive manufacturing methods similar to those used to form one or more of the metal layer, dielectric layer, covercoat layer, or any other layer or structure of the device.

[0008] Structures including a gold layer between the substrate and the metal layer eliminate the need to use methods such as laser ablation to form openings for backside connection access in devices, which would otherwise have to be performed as a separate step from the additive and subtractive processes used to form the device's structures or layers. Furthermore, the gold layer allows for the use of a single etch profile to form backside connection access. The backside connection access structure provides the metal layer surface to be coplanar with the dielectric side of the substrate. Furthermore, the use of similar additive and subtractive processes to form openings used to form other layers of the device offers cost and efficiency advantages. The backside connection access structures and methods for forming the backside connection access structures allow the structures to be used in a variety of products and devices, such as suspension assemblies, medical devices, optical image stabilizer assemblies, camera lens suspensions, and other electromechanical devices.

[0009] FIG. 1 illustrates a backside connection access structure according to an embodiment. The backside connection access structure 102 includes a substrate 104 with a gold layer 106 formed between the substrate 104 and a metal layer 108. In some embodiments, the substrate 104 is a stainless steel layer. The backside connection access structure also includes a dielectric layer 110 and a covercoat layer 112. In some embodiments, the dielectric layer 110 is a polyimide layer. The covercoat layer 112 is, in some embodiments, a polyimide layer. An opening 114 in the substrate 104 provides backside access to at least a portion of the gold layer 106. The opening 114 can be used to establish electrical connection with the metal layer 108. The metal layer 108 can include one or more of electrical traces and contact pads. The metal layer 108 can be formed from copper, aluminum, alloys, and other metals known in the art.

[0010] 2a-2g illustrate a process for forming a backside connection access structure according to an embodiment. A substrate 204 is cleaned as shown in FIG. 2a. By way of example, the substrate is cleaned using a plasma cleaning process. The substrate is a metal, which in some embodiments is used as a base layer. Metals include, but are not limited to, stainless steel, copper, aluminum, alloys, and other metals. As shown in FIG. 2b, an optional strike layer 206 is formed on the substrate 204. In some embodiments, the strike layer 206 is a nickel layer used to improve adhesion of a gold layer 208 to the substrate 204. The strike layer 206 is formed on the substrate 204 using methods known in the art, including, but not limited to, electrolytic plating, sputtering, and electroless plating.

[0011] 2c, the gold layer 208 is formed on a strike layer 206 disposed on the substrate 204. In embodiments without a strike layer 206, the gold layer 208 is formed on the substrate 204. The gold layer 208 is formed on the substrate 204 using methods known in the art, including, but not limited to, electrolytic plating. The gold layer 208 and optional strike layer 206, in some embodiments, are formed to be disposed in one or more locations on the substrate 204. That is, the gold layer 208 and optional strike layer 206 are formed in a pattern on the substrate, with the gold layer and optional strike disposed on those portions of the substrate 204 where backside access is desired.

[0012] Dielectric layer 210 is formed on substrate 204 using techniques including those known in the art. Dielectric layer 210 may include, but is not limited to, polymers such as polyimide, SU-8, KMPR, epoxy, and other insulating materials including ceramic and glass. As shown in FIG. 2d, dielectric layer 210 is patterned to expose at least a portion of gold layer 208. Dielectric layer 210, in some embodiments, is patterned using photolithography and etching techniques including those known in the art.

[0013] As shown in FIG. 2e, a metal layer 212 is formed. The metal layer may be formed on any one or more of the traces and contacts as defined by the dielectric layer. In some embodiments, the metal layer is formed by depositing a metal within the pattern formed by the dielectric layer 210. The metal layer may be formed from copper, aluminum, alloys, and other metals. In some embodiments, the metal layer is formed using electrolytic plating. Other embodiments include using sputtering, electroless plating, chemical vapor deposition, or other techniques, including those known in the art, to form the metal layer 212.

[0014] As shown in FIG. 2f, a covercoat layer 214 is formed on at least a portion of the dielectric layer 210 and the metal layer 212. The covercoat layer 214 can be formed by applying a liquid material onto the dielectric layer 210 and the metal layer 212 and curing the material. In other embodiments, the dielectric layer 210 is applied using techniques including, but not limited to, sputtering, chemical vapor deposition, thermal spraying, and screen printing techniques. In some embodiments, the covercoat layer can be patterned and etched to provide access to one or more portions of the metal layer 212 using techniques known in the art, including those described herein. The covercoat layer 214 can be formed using materials including, but not limited to, polymers such as polyimide, SU-8, KMPR, epoxy, and other insulating materials including ceramic and glass. As shown in FIG. 2g, one or more openings 216 are formed in the substrate 204 to expose at least a portion of the gold layer 106 using etching techniques, including those known in the art. The gold layer 208 acts as an etch stop so that the substrate 204 can be etched without damaging the metal layer 212 formed on the opposite side of the substrate 204. This avoids, for example, yield loss or degradation of the functionality of the circuits formed from the metal layer when other techniques for providing backside connection access to the metal layer are used.

[0015] In some embodiments, the one or more openings 216 are formed by applying a dielectric layer over the substrate 204 and patterning the dielectric layer to expose one or more portions of the substrate 204. The exposed one or more portions of the substrate 204 are etched using techniques including those described herein and known in the art. In some embodiments, the dielectric layer formed over the substrate to create the one or more openings 216 is removed from the substrate 204 using techniques including those known in the art. In some embodiments, the openings 216 are large enough to allow for the creation of electrical contacts to electrically connect at least a portion of the metal layer 212 that is in electrical contact with the portion of the gold layer 208 exposed by the openings. The electrical contacts can be created using techniques known in the art, including, but not limited to, soldering, using conductive adhesives, and ultrasonic welding.

[0016] 3a-3g illustrate a process for forming a backside connection access structure according to embodiments. A substrate 304, such as those described herein, is cleaned using techniques such as those described herein, as shown in FIG. 3a. An optional strike layer 306, such as those described herein, is formed on the substrate 304 using techniques such as those described herein, as shown in FIG. 3b. A dielectric layer 310, such as those described herein, is formed on the substrate 304 using techniques including those known in the art. As shown in FIG. 3c, the dielectric layer 310 is patterned to expose at least a portion of the strike layer 306, if used, or a portion of the substrate if no strike layer 306 is used. The dielectric layer 310 is patterned, in some embodiments, using techniques including those described herein.

[0017] As shown in Figure 3d, a gold layer 308 is formed on a strike layer 306 disposed on a substrate 304 using techniques such as those described herein. In embodiments without a strike layer 306, a gold layer 308 is formed on the substrate 304 using techniques such as those described herein. As shown in Figure 3e, a metal layer 312 is formed using techniques such as those described herein. The metal layer 312 is formed on one or more of any of the traces and contacts as defined by the dielectric layer. The metal layer can be formed from copper, aluminum, alloys, and other metals.

[0018] As shown in FIG. 3f, a covercoat layer 314 is formed on at least a portion of the dielectric layer 310 and the metal layer 312 using techniques such as those described herein. The covercoat layer 314 can be formed using materials such as those described herein. As shown in FIG. 3g, one or more openings 316 are formed in the substrate 304 to expose at least a portion of the gold layer 308 using etching techniques, including those known in the art. The one or more openings 316 are formed using techniques such as those described herein. In some embodiments, the dielectric layer formed on the substrate to create the one or more openings 316 is removed from the substrate 304 using techniques including those known in the art. In some embodiments, the openings 316 are large enough to allow for the creation of electrical contacts to electrically connect at least a portion of the metal layer 312 in electrical contact with the portion of the gold layer 308 exposed by the openings. The electrical contacts can be created using techniques known in the art, including, but not limited to, soldering, the use of conductive adhesives, and ultrasonic welding.

[0019] 4a-4g illustrate a process for forming a backside connection access structure according to embodiments. A substrate 404, such as those described herein, is cleaned using techniques such as those described herein, as shown in FIG. 4a. An optional strike layer 406, such as those described herein, is formed on the substrate 404 using techniques such as those described herein, as shown in FIG. 4b. A gold layer 408 is formed on the strike layer 406 disposed on the substrate 404 using techniques such as those described herein, as shown in FIG. 4c. In embodiments without a strike layer 406, the gold layer 408 is formed on the substrate 404. As shown in FIG. 4d, a barrier layer 407 is formed on the gold layer 408 using techniques such as those described herein. In some embodiments, the barrier layer 407 is a nickel layer. The barrier layer 407 separates layers in some embodiments to prevent chemical reactions between layers and / or improve adhesion of layers disposed thereon.

[0020] A dielectric layer 410, such as those described herein, is formed on the substrate 404 using techniques including those known in the art. As shown in Figure 4e, the dielectric layer 410 is patterned to expose at least a portion of the barrier layer 406. The dielectric layer 410, in some embodiments, is patterned using techniques including those described herein.

[0021] As shown in FIG. 4f, a metal layer 412 is formed using techniques such as those described herein. The metal layer 412 is formed on one or more of the traces and contacts as defined by the dielectric layer. The metal layer can be formed from copper, aluminum, alloys, and other metals. As shown in FIG. 4g, a covercoat layer 414 is formed on at least a portion of the dielectric layer 410 and the metal layer 412 using techniques such as those described herein. The covercoat layer 414 can be formed using materials such as those described herein. As shown in FIG. 4h, one or more openings 416 are formed in the substrate 404 to expose at least a portion of the gold layer 408 using etching techniques, including those known in the art. The one or more openings 416 are formed using techniques such as those described herein. In some embodiments, the dielectric layer formed on the substrate to create the one or more openings 416 is removed from the substrate 404 using techniques, including those known in the art. In some embodiments, opening 416 is large enough to allow for the creation of an electrical contact to electrically connect at least a portion of metal layer 412 in electrical contact with the portion of gold layer 408 exposed by the opening. The electrical contact can be made using techniques known in the art, including, but not limited to, soldering, using conductive adhesives, and ultrasonic welding.

[0022] In some embodiments, such as those described herein, the gold layer is a finish layer comprised of gold. In other embodiments, the finish layer is formed from a metal, including, but not limited to, tin, solder, and other conductive materials. The finish layer is formed using techniques, such as those described herein, for depositing, e.g., sputtering and patterning, metals.

[0023] While described with respect to these embodiments, those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims

1. forming a gold layer on a portion of a substrate; forming a first dielectric layer on the substrate; patterning the first dielectric layer to expose at least a portion of the gold layer; forming a metal layer on the gold layer to form one or more of traces and contacts as defined by the first dielectric layer; applying a second dielectric layer onto the substrate; and patterning the second dielectric layer to remove portions of the substrate, thereby forming openings in the substrate to expose at least a portion of the gold layer, such that the metal layer is not exposed within the openings in the substrate.

2. The method of claim 1 , wherein forming the gold layer on a portion of a substrate comprises forming a strike layer on at least a portion of the substrate and forming the gold layer on the strike layer.

3. forming the metal layer on the gold layer The method of claim 1 , further comprising depositing a metal within the first dielectric layer to form the metal layer.

4. The method of claim 1 , further comprising forming a covercoat layer over at least a portion of the metal layer.

5. The method of claim 3 , wherein depositing the metal in the first dielectric layer is performed by using electrolytic plating.

6. The method of claim 1 , wherein forming the opening in the substrate is performed by etching the substrate.

7. The method of claim 1 , wherein the substrate is stainless steel.

8. The method of claim 7 , wherein the substrate is part of a flexure for a suspension assembly.

9. The method of claim 7 , wherein the substrate is part of a medical device.

10. The method of claim 7 , wherein the substrate is part of an optical image stabilizer assembly.

11. The method of claim 1 , further comprising forming a barrier layer on the gold layer, the barrier layer being formed between the gold layer and the metal layer.

12. The method of claim 11 , wherein the barrier layer is a nickel layer.

13. forming the gold layer The method of claim 1 , comprising depositing gold on said portion of said substrate.

14. A substrate; a first dielectric layer formed on the substrate; a gold layer formed on the substrate; the first dielectric layer is patterned to expose an opening in the first dielectric layer and to uncover at least a portion of the gold layer on a first side of the gold layer; a metal layer having one or more traces and contacts formed in the openings formed in the first dielectric layer on the first side of the gold layer and defined by the first dielectric layer; a second dielectric layer on the substrate, the second dielectric layer is patterned to form an opening formed in the substrate, the opening configured to expose at least a portion of a second side of the gold layer such that the metal layer is not exposed within the opening in the substrate.

15. a metal substrate defining an opening; a metal layer within an opening formed in a first dielectric layer having a portion of the metal layer positioned opposite the opening in the metal substrate, the metal layer having one or more traces and contacts formed thereon as defined by the first dielectric layer; a gold layer within the opening, the gold layer being disposed between the opening of the metal substrate on a first side and the metal layer within the opening on a second side such that the metal layer is not exposed within the opening of the metal substrate; the opening is configured to expose at least a portion of the gold layer on the first side of the gold layer by a second dielectric layer on the metal substrate that is patterned to expose the opening in the metal substrate.

16. 16. The device of claim 15, including a strike layer initially configured between the metal substrate and the gold layer.

17. The device of claim 14 including a strike layer between the substrate and the gold layer.

18. 18. The device of claim 16 or 17, wherein the strike layer is a nickel layer.

19. 16. The device of claim 14 or 15, including a barrier layer between the gold layer and the metal layer.

20. 20. The device of claim 19, wherein the barrier layer is a nickel layer.

21. 16. The device of claim 14 or 15, wherein the second dielectric layer is removed.

22. The method of claim 1 , further comprising removing the second dielectric layer.

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