Apparatus and method for reducing lock time through frequency band calibration - Patents.com

Abstract

An apparatus and related method for reducing lock time includes pre-calibrating and storing adaptive values ​​for a phase-locked loop (PLL) and / or an injection-locked oscillator (ILO) upon startup and loading the pre-calibrated values ​​upon a rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store and configured to select a predetermined frequency band in response to a command signal, retrieve from the data store the operational settings associated with the predetermined frequency band, and apply the retrieved operational settings to the controllable frequency circuit. The pre-calibration may advantageously reduce PLL and / or ILO lock time upon a rate change in a multi-rate serializer / deserializer (SERDES) link.

Description

[Technical Field]

[0001] Various embodiments relate generally to frequency band calibration. [Background technology]

[0002] Data represents information that has useful value. Data can take the form of stored information. Data storage can be in analog form. Data storage can be in digital form. Digital form data can be communicated between two nodes. When data is communicated, it can be received and interpreted, for example, as a function of time. Some systems that receive communicated digital form data can be based on a clock that determines when a voltage signal is sampled to determine whether a symbol in the data stream is, for example, a 1 or a 0. In some cases, data can be received without knowing its specific phase information. Phase alignment can be performed before initiating or receiving the data to ensure data accuracy and data integrity. Summary of the Invention

[0003] An apparatus and associated method for reducing lock time includes pre-calibrating and storing adaptive values ​​for a phase-locked loop (PLL) and / or an injection-locked oscillator (ILO) upon startup and loading the pre-calibrated values ​​upon a rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine coupled to the controllable frequency circuit and the data store may be configured to select a predetermined frequency band in response to a command signal, retrieve from the data store the operational setting associated with the predetermined frequency band, and apply the retrieved operational setting to the controllable frequency circuit. The pre-calibration may advantageously reduce PLL and / or ILO lock time upon a rate change in a multi-rate serializer / deserializer (SERDES) link.

[0004] Various embodiments may achieve one or more advantages. For example, some embodiments may accelerate lock times of the PLL and / or ILO. Some embodiments may be flexibly used in programmable logic, such as, for example, a field programmable gate array (FPGA), which may allow frequency band and / or rate change operations to be reconfigurable in the art. In some embodiments, cost, size, or power may be reduced by implementation in a fixed hardware platform, such as, for example, an application-specific integrated circuit (ASIC). Some implementations may include execution of pre-programmed instructions and / or software executed by a processor to reduce lock times when changing rates in frequency-controlled circuits. In some embodiments, the apparatus and / or method may enable the PLL and / or ILO to operate with a wide range of protocols, such as peripheral component interconnect express (PCIe). In various embodiments, the apparatus and / or method may cost-effectively avoid the need to use a dedicated narrow-band PLL. In some embodiments, by sharing pre-calibration circuitry and / or state machines by different transceivers, fewer hardware resources may be used and a smaller area may be achieved.

[0005] In one exemplary aspect, an integrated circuit includes a controllable frequency circuit operable at a frequency within each of a plurality of frequency bands, a data store configured to store an operational setting associated with each frequency band of the plurality of frequency bands, and a state machine coupled to the controllable frequency circuit and the data store, the state machine configured to select a predetermined frequency band in response to a command signal, retrieve from the data store the operational setting associated with the predetermined frequency band, and apply the retrieved operational setting to the controllable frequency circuit.

[0006] In some embodiments, the controllable frequency circuit may include a phase-locked loop (PLL). The PLL may include a voltage-controlled oscillator (VCO). In some embodiments, the controllable frequency circuit may include an injection-locked oscillator (ILO). In some embodiments, the command signal may be associated with a change of operation from a first one of the frequency bands to a second one of the frequency bands. In some embodiments, the integrated circuit may also include a pre-calibration circuit operable to pre-calibrate the controllable frequency circuit to generate the operating configuration. The pre-calibration circuit (250a) may be configured to pre-calibrate decision feedback equalizer (DFE) parameters of a serializer / deserializer (SERDES) link. The pre-calibration circuit (250a) may also be configured to pre-calibrate clock data recovery (CDR) parameters of the serializer / deserializer (SERDES) link.

[0007] In some embodiments, the state machine may be configured to enable the pre-calibration circuit to perform automatic frequency band selection of the controllable frequency circuit to generate the operational configuration. In some embodiments, the state machine may also be configured to disable the pre-calibration circuit (250b) in response to generating the operational configuration.

[0008] In another exemplary aspect, a method for configuring a controllable frequency circuit includes receiving, by a state machine, a user command signal to configure the controllable frequency circuit to generate a desired frequency, The method also includes selecting a predetermined frequency band in response to the command signal, obtaining a corresponding operational setting associated with the predetermined frequency band, and applying the obtained operational setting to the controllable frequency circuit.

[0009] In some embodiments, the controllable frequency circuit may include a phase-locked loop (PLL). The PLL may include a voltage-controlled oscillator (VCO). In some embodiments, the controllable frequency circuit may include an injection-locked oscillator (ILO). The ILO may include a voltage-controlled oscillator (VCO). In some embodiments, the controllable frequency circuit may include a phase-locked loop (PLL) connected in series with the injection-locked oscillator (ILO).

[0010] In some embodiments, the corresponding operational settings may be pre-configured by pre-determining one or more desired frequencies f(n) to be generated by the controllable frequency circuitry, enabling the pre-calibration circuitry to perform automatic frequency band selection via a state machine, setting the controllable frequency circuitry to the frequency f(n), reading and storing the corresponding frequency band and operating parameters in a data store when the frequency f(n) is locked, and disabling the automatic frequency band selection until each of the one or more frequencies f(n) has a corresponding frequency band and operating parameters.

[0011] In some embodiments, the pre-calibration circuit may pre-calibrate decision feedback equalizer (DFE) parameters of a serializer / deserializer (SERDES) link. In some embodiments, the pre-calibration circuit may pre-calibrate clock data recovery (CDR) parameters of the serializer / deserializer (SERDES) link. In some embodiments, the command signal may be associated with a change of operation from a first one of the frequency bands to a second one of the frequency bands.

[0012] The details of various embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0013] [Figure 1]1 illustrates an exemplary programmable integrated circuit (IC) in which the disclosed circuits and processes may be implemented. [Figure 2] 1 illustrates an exemplary controllable frequency circuit implemented in a high-speed digital computing system. [Figure 3A] 1 illustrates an exemplary clock signal generator incorporated into an FPGA. [Figure 3B] 1 illustrates another exemplary clock signal generator incorporated into an FPGA. [Figure 4] 1 shows a flowchart of an exemplary method for pre-calibrating a controllable frequency circuit. [Figure 5] 1 shows a flowchart of an exemplary run-time method for pre-calibrating a controllable frequency circuit. DETAILED DESCRIPTION OF THE INVENTION

[0014] Like reference symbols in the various drawings indicate like elements.

[0015] To aid in understanding, this document is organized as follows: First, with reference to FIG. 1, an exemplary platform (e.g., an FPGA) suitable for performing PLL and / or ILO calibration is briefly introduced. Second, with reference to FIGS. 2-3B, the description is directed to introducing how PLL and / or ILO adaptation values ​​are pre-calibrated and stored for loading upon rate change. Third, FIG. 4 is described to introduce a method for pre-calibrating a PLL and / or ILO. Finally, with reference to FIG. 5, the description discloses an exemplary implementation of frequency band calibration at runtime.

[0016] 1 illustrates an exemplary programmable integrated circuit (IC) in which the disclosed circuits and processes may be implemented. The programmable IC 100 includes FPGA logic. The programmable IC 100 may be implemented with a variety of programmable resources and may be referred to as a system on chip (SOC). Various examples of FPGA logic may include several different types of programmable logic blocks in an array.

[0017] 1 shows a programmable IC 100 that includes a number of different programmable tiles, including a multi-gigabit transceiver (MGT) 101, a configurable logic block (CLB) 102, a random access memory block (BRAM) 103, an input / output block (IOB) 104, configuration and clock logic (CONFIG / CLOCKS) 105, a digital signal processing block (DSP) 106, specialized input / output blocks (I / O) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable IC 100 includes a dedicated processor block (PROC) 110. The programmable IC 100 may include internal and external reconfiguration ports (not shown).

[0018] In various examples, the serializer / deserializer may be implemented using MGT 101. MGT 101 may include various data serializers and deserializers. The data serializer may include various multiplexer implementations. The data deserializer may include various demultiplexer implementations.

[0019] In some examples of FPGA logic, each programmable tile includes a programmable interconnect element (INT) 111, with standard interconnects 124 between corresponding interconnect elements in each adjacent tile. Thus, the programmable interconnect elements taken together implement the programmable interconnect structure of the illustrated FPGA logic. The programmable interconnect element INT 111 includes intra-connections 120 between programmable logic elements within the same tile, as shown by the example included in FIG. 1. The programmable interconnect element INT 111 includes inter-INT connections 122 between programmable interconnect elements INT 111 within the same tile, as shown by the example included in FIG. 1.

[0020] For example, CLB 102 may include configurable logic elements (CLEs) 112 that can be programmed to implement user logic and a single programmable interconnect element INT 111. BRAM 103 may include BRAM logic elements (BRLs) 113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a tile may depend on the height of the tile. In the illustrated embodiment, the BRAM tile has the same height as five CLBs, although other numbers (e.g., four) may also be used. DSP tile 106 may include DSP logic elements (DSPLs) 114 and one or more programmable interconnect elements. IOB 104 may include, for example, two instances of input / output logic elements (IOLs) 115 and one instance of programmable interconnect element INT 111. The actual I / O bond pads, for example, connected to I / O logic elements 115, may be fabricated using metal layered over the various illustrated logic blocks and may not be limited to the area of ​​the input / output logic elements 115.

[0021] In the illustrated embodiment, columnar regions near the center of the die (shown shaded in FIG. 1) are used for configuration, clock, and other control logic. Horizontal regions 109 extending from the columns distribute clock and configuration signals across the width of programmable IC 100. Note that references to "columnar" and "horizontal" regions are relative to viewing the drawings vertically.

[0022] Some programmable ICs utilizing the architecture shown in Figure 1 may include additional logic blocks that disrupt the regular columnar structure that makes up the majority of the programmable IC. The additional logic blocks may be programmable blocks and / or dedicated logic. For example, the processor block PROC 110 shown in Figure 1 spans several columns of CLBs 102 and BRAMs 103.

[0023] 1 illustrates an exemplary programmable IC architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks contained in a column, the relative sizes of the logic blocks, and the interconnect / logic implementation are provided purely by way of example. For example, an actual programmable IC may include more than one adjacent column of CLBs 102, wherever CLBs 102 appear, to facilitate efficient implementation of user logic.

[0024] At least one transceiver may be incorporated into the FPGA to perform data transmission and data reception during communication. Data may be transmitted or received at different frequencies. A phase-locked loop (PLL) and / or an injection-locked oscillator (ILO) may be used by the transceiver to generate clock signals with different frequencies and / or phases. Because different customers may use the FPGA at different frequencies using various protocols, a wide range of frequency outputs may need to be supported.

[0025] 2 shows an exemplary controllable frequency circuit implemented in a high-speed digital computing system 205. The high-speed digital computing system 205 includes multiple interconnected circuit subsystems, one of which is a central processing unit (CPU) 210 electrically connected to an FPGA 215. The FPGA 215 may include many high-speed data transmission lines.

[0026] In this depicted example, FPGA 215 includes a Peripheral Component Interconnect Express (PCIe) unit 220. PCIe unit 220 is configured to connect FPGA 215 and CPU 210. FPGA 215 also includes a first transceiver 225 and a second transceiver 230 configured to perform data transfers.

[0027] In this illustrated example, the first transceiver 220 and the second transceiver 225 each include a controllable frequency circuit for generating one or more desired clock signals required during data transfer, which in this illustrated example include a phase-locked loop (PLL) 235 and / or an injection-locked oscillator (ILO) 240.

[0028] The PLL 235 of the illustrated example, which has a voltage-controlled oscillator (VCO) 245, may be used to generate clock signals having different frequencies. To support a wide range of frequencies, the VCO 245 for the PLL 235 and / or ILO 240 may be configured to operate in multiple frequency bands. To select the optimal frequency band, when the controllable frequency circuit (e.g., the PLL 235 and / or the ILO 240) attempts to lock on the frequency, the pre-calibration circuit 250 may step through the various frequency bands, monitor the voltage of the VCO 255 ​​to see if it is within an ideal range, and adjust as necessary. The pre-calibration circuit 250 is configured to calibrate the controllable frequency circuit (e.g., the PLL 235 and / or the ILO 240), for example, upon serializer / deserializer (SERDES) link rate changes. In some embodiments, the pre-calibration circuit 250 may be located off-chip. In this illustrated example, the pre-calibration circuit 250 is located in the FPGA 215.

[0029] In various examples, some protocols may have strict requirements regarding rate change time. For example, PCIe has a lock time specification of 1 ms that must be met. To shorten the lock time, a state machine 255 is introduced to control the pre-calibration circuit 250. The state machine 255 controls the pre-calibration circuit 250 in the transceiver 230. More specifically, the state machine 255 enables or disables the pre-calibration circuit 250 from performing automatic frequency band selection for the PLL 235 and / or the ILO 240. The state machine 255 may also be configured to receive one or more user command signals via a user input interface. For example, a serializer / deserializer (SERDES) link may use four different frequencies f1 (e.g., 2.5 Gb / s), f2 (e.g., 5.0 Gb / s), f3 (e.g., 8.0 Gb / s), and f4 (e.g., 16.0 Gb / s) for PCIe. A user may input those four frequencies into state machine 255. State machine 255 may enable pre-calibration circuit 250 to calibrate the four frequencies upon startup. Once pre-calibration circuit 250 performs a corresponding frequency (e.g., frequency f1) calibration and the controllable frequency circuit (e.g., PLL 235 and / or ILO 240) is locked with respect to the frequency (e.g., frequency f1), the calibrated settings for obtaining frequency f1 may be stored in non-volatile memory (NVM) 260. Once all four different frequencies f1, f2, f3, and f4 have been pre-calibrated and the corresponding settings obtained, one or more look-up tables may be formed and stored in NVM 260. The calibrated values ​​may then be loaded into the controllable frequency circuit (e.g., PLL 235 and / or ILO 240), for example, upon a SERDES rate change.

[0030] In this illustrated example, state machine 255 is located in the same programmable logic (e.g., FPGA 215) as transceivers 225 / 230, but in various embodiments, state machine 255 may be implemented in different programmable logic (e.g., another FPGA) to control pre-calibration.

[0031] In some embodiments, state machine 255 may be implemented as a hard block fixed circuit. For example, an application specific integrated circuit (ASIC) may provide the state machine for controlling pre-calibration. In some embodiments, some or all of the functionality of state machine 255 may be implemented in a processor configured to execute a set of instructions stored in a data store to control pre-calibration. The processor may be located on the same integrated circuit, which may be an FPGA (e.g., FPGA 215) with transceiver 230. For example, state machine 255 and a data store (e.g., NVM 260) may be implemented in programmable logic blocks of a system-on-chip (SoC), or may be implemented in a hard block using fixed circuitry of the SoC, with transceiver 230 being implemented in another hard block using fixed circuitry of the SoC.

[0032] 3A shows an exemplary clock signal generator incorporated in an FPGA. The exemplary clock signal generator 300a includes a controllable frequency circuit. In this illustrated example, the controllable frequency circuit includes a PLL (e.g., PLL 235). The PLL 235 receives an input clock signal 305a and generates an output clock signal 310a. The PLL 235 can be configured to generate different output clock signals 310a having different frequencies. In some embodiments, the controllable frequency circuit can be configured by replacing the PLL 235 with an ILO (e.g., ILO 240) to generate clock signals having different phases.

[0033] The clock signal generator 300a also includes a pre-calibration circuit 250a connected to the PLL 235. When used in a multi-rate SERDES link, multiple frequencies may be required. The multiple frequencies may be predetermined by a user. The pre-calibration circuit 250a may step through various frequency bands and monitor the voltage of a VCO (e.g., VCO 245) to verify whether the VCO 245 is within an ideal range. Once the PLL 235 is locked, the corresponding frequency band and operating settings of the PLL 235 for generating the locked frequency may be obtained.

[0034] Pre-calibration circuit 250a is controlled by state machine 255a. State machine 255a controls pre-calibration circuit 250 to begin pre-calibration at startup and to stop calibration when all predetermined frequencies have the corresponding frequency band and operating setting. A look-up table may be established during startup calibration and used during rate changes. In this illustrated example, the look-up table is stored in non-volatile memory (e.g., NVM 260).

[0035] The state machine 255a, which may be configured with a user interface, allows a user to select a frequency band and operating settings from a lookup table in manual override mode during PLL rate changes and configure the PLL 235 with the selected frequency band and operating settings. Directly selecting the stored adaptation values ​​from the startup calibration eliminates the need to sweep through different PLL frequency bands during PLL lock. Lock time is therefore significantly reduced. In some embodiments, the pre-calibration circuit 250a may be configured to calibrate other SERDES link adaptation parameters. For example, decision feedback equalizer (DFE) parameters and / or clock data recovery (CDR) parameters may be pre-calibrated and stored. Pre-calibration may also reduce SERDES adaptation and link lock time.

[0036] 3B shows another exemplary clock signal generator integrated into an FPGA. The exemplary clock signal generator 300b includes a controllable frequency circuit. The controllable frequency circuit includes a PLL (e.g., PLL 235) connected in series with an ILO (e.g., ILO 240). The controllable frequency circuit receives an input clock signal 350a and generates an output clock signal 310b. In some embodiments, the order of the PLL 235 and the ILO 240 may be changed.

[0037] The clock signal generator 300b also includes a pre-calibration circuit 250b connected to both the PLL 235 and the ILO 240. When used with SERDES, multiple frequencies may be used. The multiple frequencies may be predetermined by a user. The pre-calibration circuit 250b may step through various frequency bands and monitor the VCO voltage to verify whether the VCO 245 is within an ideal range. Once the PLL 235 and the ILO 240 are locked, the corresponding frequency band and operating settings for generating the locked frequency may be obtained.

[0038] Pre-calibration circuit 250b is controlled by state machine 255b. State machine 255b controls pre-calibration circuit 250 to begin pre-calibration at startup and to stop pre-calibration when all predetermined frequencies have acquired their corresponding frequency band selection and operating settings. A look-up table may be established during startup calibration and used during rate changes. In this illustrated example, the look-up table is stored in non-volatile memory (e.g., NVM 260).

[0039] The state machine 255, which may be configured with a user interface, allows a user to select a frequency band and operating settings from a lookup table in manual override mode during PLL rate changes and reset the PLL 235 and ILO 240 to the selected frequency band and operating settings. Directly selecting stored adaptation values ​​from startup calibration eliminates the need to sweep through different PLL and ILO frequency bands during PLL and ILO locking. Lock time is therefore significantly reduced. In some embodiments, the pre-calibration circuit 250b may be configured to calibrate other SERDES adaptation parameters. For example, decision feedback equalizer (DFE) parameters and / or clock data recovery (CDR) parameters may be pre-calibrated and stored. Pre-calibration may also reduce SERDES adaptation and link lock time.

[0040] Although the illustrated diagram shows an exemplary hardware implementation using circuitry, some or all of the functionality of state machine 255 may be performed by a general-purpose processor (e.g., a microcontroller) executing a program of instructions to perform the described operations.

[0041] FIG. 4 shows a flowchart of an exemplary method for pre-calibrating a controllable frequency circuit. A method 400 for pre-calibrating the controllable frequency circuits 234, 240 in the clock signal generator 300b is described. The method 400 includes, at 405, triggering a calibration routine by enabling automatic frequency band selection in a pre-calibration circuit (e.g., the pre-calibration circuit 250b). This triggering may be controlled by a state machine (e.g., the state machine 255b). At 410, the state machine (e.g., the state machine 255b) introduces a variable n and initializes the variable n to equal 1. At 415, the state machine 255b sets the PLL 235 to a first predetermined frequency (e.g., f1). At 420, the PLL 235 and the ILO 240 in the controllable frequency circuit are reset. At 425, the state machine dynamically monitors whether the controllable frequency circuit is locked at the first predetermined frequency. At 430, if the controllable frequency circuit is locked, the state machine 255b reads the frequency band selection and parameter settings of the PLL and ILO for the first predetermined frequency and stores the frequency band selection and parameter settings in memory (e.g., NVM 260).

[0042] If there are more predetermined frequencies (e.g., f2, f3, f4) subsequently required by the user at 430, state machine 255b increments variable n at 435 and loops back to 415. If all predetermined frequencies have corresponding frequency band selections and operating settings, state machine 255b disables the calibration routine by disabling the automatic frequency band selection of pre-calibration circuit 250b at 440. Pre-calibration is then terminated.

[0043] 5 shows a flowchart of an exemplary runtime method for pre-calibrating a controllable frequency circuit. The runtime method 500 includes, at 505, the state machines 255a, 255b dynamically determining whether a user wants to configure the controllable frequency circuit to generate a different frequency. If so, at 510, the state machines receive a user-desired frequency value, for example, via a user interface. At 515, the state machines 255a, 255b retrieve the corresponding frequency band and parameter settings from a data store (e.g., NVM 260).

[0044] At 520, the state machine applies the obtained frequency band and parameter settings to the controllable frequency circuit and resets the controllable frequency circuit.

[0045] In some embodiments, if the controllable frequency circuit includes only a PLL (e.g., PLL 235), the lookup table may include only one lookup table for PLL 235. The state machine (e.g., state machine 255a) may then apply the obtained corresponding frequency band and parameter settings to PLL 235.

[0046] Although various embodiments have been described with reference to the drawings, other embodiments are possible. For example, a clock signal generator may include more than one PLL and / or more than one ILO. A pre-calibration circuit may calibrate the PLL and / or ILO to obtain one or more desired frequencies and / or phases. In some embodiments, each transceiver in an FPGA may be calibrated by an independent pre-calibration circuit. In some embodiments, two or more transceivers in an FPGA may share one pre-calibration circuit. In some embodiments, each pre-calibration circuit may be controlled by a corresponding state machine. In some embodiments, two or more pre-calibration circuits may be controlled by the same state machine.

[0047] Some aspects of the embodiments, such as the lookup table access of the state machine 255, may be implemented as a computer system. For example, various implementations may include digital and / or analog circuitry, computer hardware, firmware, software, or combinations thereof. Apparatus elements may be implemented in a computer program product tangibly embodied in an information carrier, e.g., a machine-readable storage device, for execution by a programmable processor, and methods may be performed by the programmable processor executing a program of instructions to perform the functions of the various embodiments by manipulating input data and generating output. Some embodiments may be suitably implemented in one or more computer programs executable on a programmable system including at least one programmable processor coupled to receive data and instructions from a data store, at least one input, and / or at least one output, and to transmit data and instructions to the data store, at least one input, and / or at least one output. The data store may include, for example, one or more registers or memory locations within a memory space. A computer program is a set of instructions that can be used directly or indirectly in a computer to perform a particular activity or bring about a particular result. The computer program may be written in any form of programming language, including compiled or interpreted languages, and it may be implemented in any form, including a stand-alone program, or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0048] Various embodiments may be implemented using reconfigurable programmable logic blocks (e.g., FPGAs), while other embodiments may be implemented in fixed instantiations (e.g., ASICs) or single integrated circuits (e.g., SoCs). While dedicated hard block circuitry in ASIC implementations may not be reconfigurable after being instantiated within an integrated circuit, for example, ASIC implementations may, in some implementations, provide a minimized platform, e.g., with respect to power consumption and / or die area.

[0049] Processors suitable for executing a program of instructions include, by way of example and not limitation, both general-purpose and special-purpose microprocessors, which may include a single processor or one of multiple processors. Generally, a processor receives instructions and data from a read-only memory or a random-access memory, or both. The essential elements of a computer are a processor for executing instructions and one or more memories for storing instructions and data. Storage devices suitable for tangibly embodying computer program instructions and data include, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks and removable disks, magneto-optical disks, and all forms of non-volatile memory, including CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated in an ASIC (application-specific integrated circuit), or may be combined in a single integrated circuit (e.g., SoC). In some embodiments, the processor and memory may be supplemented by or incorporated in a programmable logic device, such as an FPGA.

[0050] In some embodiments, each system may be programmed with the same or similar information and / or initialized with substantially identical information stored in volatile and / or non-volatile memory. For example, one data interface may be configured to perform auto-configuration, auto-download, and / or auto-update functions when coupled to an appropriate host device, such as a desktop computer or server.

[0051] In some implementations, one or more user interface features may be custom configured to perform specific functions. Exemplary embodiments may be implemented on a computer system including a graphical user interface and / or an internet browser. To provide for user interaction, some implementations may be implemented on a computer having a display device, such as an LCD (liquid crystal display) monitor, for displaying information to the user, a keyboard, and a pointing device, such as a mouse or trackball, through which the user may provide input to the computer.

[0052] In various embodiments, the system may communicate using appropriate communication methods, equipment, and techniques. For example, the system may communicate with compatible devices (e.g., devices capable of transferring data to and / or from the system) using point-to-point communication, in which messages are transferred directly from a source to a receiver via a dedicated physical link (e.g., fiber optic link, infrared link, ultrasonic link, point-to-point wiring, daisy chain). System components may exchange information over a communication network by analog or digital data communication of any form or medium, including packet-based messages. Examples of communication networks include, for example, LANs (local area networks), WANs (wide area networks), MANs (metropolitan area networks), wireless and / or optical networks, and the computers and networks forming the Internet. Other embodiments may transfer messages by broadcasting them to all or substantially all devices coupled together by the communication network, for example, using omnidirectional radio frequency (RF) signals. Still other embodiments may transfer messages characterized by high directionality, such as RF signals transmitted using directional (i.e., narrow beam) antennas or infrared signals, optionally used with focusing optics. Still other implementations are possible using suitable interfaces and protocols, such as, by way of example and not limitation, USB 2.0, FireWire, ATA / IDE, RS-232, RS-422, RS-485, 802.11a / b / g / n, Wi-Fi, Wi-Fi-Direct, Li-Fi, BlueTooth, Ethernet, IrDA, FDDI (Fiber Distributed Data Interface), token ring networks, or frequency, time, or code division based multiplexing techniques. Some implementations may optionally incorporate features such as error checking and correction (ECC) for data integrity, or security measures such as encryption (e.g., WEP) and password protection.

[0053] In various embodiments, a computer system may include non-transitory memory. The memory may be coupled to one or more processors and configured to store data and computer-readable instructions, including processor-executable program instructions. The data and computer-readable instructions may be accessible to the one or more processors. The processor-executable program instructions, when executed by the one or more processors, may cause the one or more processors to perform various operations.

[0054] Various examples of modules may be implemented using circuitry including various electronic hardware. By way of example and not limitation, the hardware may include transistors, resistors, capacitors, switches, integrated circuits, and / or other modules. In various examples, modules may include analog and / or digital logic, discrete components, wiring, and / or memory circuitry fabricated on silicon substrates, including various integrated circuits (e.g., FPGAs, ASICs, SoCs). In some embodiments, modules may include pre-programmed instructions and / or software execution executed by a processor. For example, various modules may include both hardware and software.

[0055] Several implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, suitable results may be achieved if the steps of the disclosed techniques are performed in a different order, or if the components of the disclosed systems are combined in a different way, or if components are supplemented with other components. Accordingly, other implementations are within the scope of the following claims.

Claims

1. An integrated circuit (300a), a controllable frequency circuit (235, 240) operable in multiple frequency bands; a data store (260) configured to store a respective frequency band and a respective operational setting associated with each of a plurality of frequencies, and to store decision feedback equalizer (DFE) parameters or clock data recovery (CDR) parameters of a serializer / deserializer (SERDES) link; a pre-calibration circuit (250a, 250b) operable to pre-calibrate the controllable frequency circuits (235, 240) by verifying operation of the controllable frequency circuits across the plurality of frequency bands, and to pre-calibrate the DFE parameters or the CDR parameters of the SERDES link; a state machine (255a, 255b) coupled to the controllable frequency circuit (235, 240), the data store (260), and the pre-calibration circuit (250a, 250b), enabling the pre-calibration circuits (250a, 250b) to perform automatic frequency band selection of the controllable frequency circuits (235, 240) to generate the respective operating settings and the respective frequency bands associated with the plurality of frequencies; selecting a predetermined frequency band from the frequency bands in response to a command signal; obtaining from the data store (260) a first operational setting of the operational settings and a first parameter of the DFE parameter or the CDR parameter associated with the predetermined frequency band; Applying the obtained first operating settings to the controllable frequency circuit and applying the obtained first parameters to the SERDES link. and a state machine (255a, 255b) configured as follows: An integrated circuit (300a) comprising:

2. The controllable frequency circuit (235, 240) a phase-locked loop (PLL) (235), or Injection Locked Oscillator (ILO) (240) The integrated circuit (300a) of claim 1, comprising at least one of:

3. The integrated circuit (300a) of claim 1, wherein the controllable frequency circuit comprises a PLL (235) and a voltage controlled oscillator (VCO) (245).

4. 2. The integrated circuit (300a) of claim 1, wherein the command signal directs a change of operation from a first one of the frequency bands to a second one of the frequency bands.

5. the state machine (255a, 255b) is further configured to disable the pre-calibration circuit (250a, 250b) in response to generating the operational configuration. The integrated circuit (300a) of claim 1.

6. 1. A method for configuring a controllable frequency circuit, comprising: receiving, by a state machine, a user command signal to configure a controllable frequency circuit (235, 240) operable in a plurality of frequency bands to generate a desired frequency; verifying operation of the controllable frequency circuit through the plurality of frequency bands and pre-calibrating the controllable frequency circuit to enable a pre-calibration circuit to perform automatic frequency band selection of the controllable frequency circuit (235, 240) to generate a respective operating setting and respective frequency band for each of a plurality of frequencies; Pre-calibrating decision feedback equalizer (DFE) or clock data recovery (CDR) parameters of a serializer / deserializer (SERDES) link; selecting, by the state machine, a predetermined frequency band within the frequency band in response to the command signal; retrieving a first one of the operational settings and a first one of the DFE or CDR parameters associated with the predetermined frequency band from a data store (260), the data store (260) being configured to store the frequency band, the operational setting, and the DFE or CDR parameter associated with each of the plurality of frequencies; applying the obtained first operating settings to the controllable frequency circuit and applying the obtained first parameters to the SERDES link; A method comprising:

7. The controllable frequency circuit (235, 240) a phase-locked loop (PLL) (235); an injection-locked oscillator (ILO) (240), or PLL connected in series with ILO The method of claim 6 , comprising at least one of:

8. 7. The method of claim 6, wherein the controllable frequency circuit (235, 240) comprises a PLL (235) and a voltage controlled oscillator (VCO) (245).

9. The method of claim 6, wherein the controllable frequency circuit comprises an ILO (240), and the ILO comprises a VCO (245).

10. predetermining one or more desired frequencies f(n) to be generated by the controllable frequency circuit; enabling the pre-calibration circuit (250a, 250b) to perform automatic frequency band selection by the state machine; setting the controllable frequency circuit (235, 240) to the frequency f(n); reading and storing in said data store (260) the frequency band and operating parameters corresponding to said frequency f(n) when said frequency f(n) is locked; Disabling the automatic frequency band selection until each of the one or more frequencies f(n) has a corresponding frequency band and operating parameters. The method of claim 6 , further comprising pre-calibrating the corresponding operational settings by:

11. The method of claim 6 , wherein the command signal directs a change of operation from a first one of the frequency bands to a second one of the frequency bands.

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