Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

Abstract

To obtain a semiconductor device that enables insulation reliability to be kept, a power conversion device, and a method for manufacturing a semiconductor device.SOLUTION: A semiconductor substrate (1) includes a drift layer (10) of a first conductivity type. In an active region, a main current flows in a thickness direction of the semiconductor substrate (1). Terminal regions (7, 8) of a second conductivity type are formed in a surface layer of the drift layer (10) so as to surround the active region. Covering materials (18, 20, 25) cover the terminal regions (7, 8), An outer peripheral well region (9) of a first conductivity type formed in the surface layer of the drift layer (10) on an outer side of the terminal regions (7, 8), the outer peripheral well region having impurity concentration higher than that of the drift layer (10). An outer peripheral end of the covering materials (18, 20, 25) is arranged on an inner side of an outer peripheral end of the semiconductor substrate (1). The outer peripheral well region (9) is at least partially formed under the covering materials (18, 20, 25) and not formed under an outer peripheral end of the covering materials (18, 20, 25).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] In vertical semiconductor devices used in power devices, a p-type guard ring region is formed in the so-called termination region around the periphery of an n-type semiconductor layer to ensure breakdown voltage performance. The guard ring region is also called a termination well region. When a reverse voltage is applied to the main electrode, an electric field is generated, but this electric field is alleviated by a depletion layer formed by the pn junction between the n-type semiconductor layer and the p-type guard ring region.

[0003] For example, a channel stopper layer is formed around the outer edge of the semiconductor device to suppress excessive expansion of the depletion layer from the p-type guard ring region, and an n + A structure in which a type source layer extends to the outer peripheral edge of a semiconductor substrate has been disclosed (see, for example, Patent Document 1). With this structure, the potential is kept constant around the outer peripheral edge of the semiconductor device, and the electric field is more effectively alleviated. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-60017 Summary of the Invention [Problem to be solved by the invention]

[0005] In such semiconductor devices, a protective film such as polyimide may be formed on the substrate, or the semiconductor device may be sealed with resin. In a humid environment, the resin or polyimide may contain moisture, and the surface of the semiconductor substrate may be exposed to moisture. When a high voltage is applied in this state, n-type semiconductors may be formed on the surface of the semiconductor substrate. +Because the ionization effect is strong in the region where the mold layer is formed, residual metal reacts with moisture during the fabrication of the semiconductor device, resulting in the deposition of metal oxides, or the metal acts as a catalyst to cause the semiconductor to react with moisture, resulting in the deposition of semiconductor oxides. When foreign matter precipitates on the surface of the semiconductor substrate in this way, film peeling occurs in the surrounding area, and a leak path different from that observed in normal semiconductor device operation is formed. This can result in a loss of insulation reliability for the semiconductor device.

[0006] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device that can maintain insulation reliability. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a semiconductor substrate having a drift layer of a first conductivity type, an active region in which a main current flows in a thickness direction of the semiconductor substrate, a termination region of a second conductivity type formed in a surface layer of the drift layer so as to surround the periphery of the active region, a covering material covering the termination region, and a periphery well region of the first conductivity type formed in the surface layer of the drift layer outside the termination region and having a higher impurity concentration than the drift layer, wherein the periphery edge of the covering material is located inside the periphery edge of the semiconductor substrate, and at least a portion of the periphery well region is formed below the periphery edge of the covering material. The peripheral well region has a first peripheral well region formed below the coating material and a second peripheral well region formed on the outer periphery side of the coating material and spaced apart from the first peripheral well region. It is characterized by: [Effects of the Invention]

[0008] In the present disclosure, a first conductivity type peripheral well region having a higher impurity concentration than the drift layer is formed in the surface layer of the drift layer outside the termination region, and at least a portion of the peripheral well region is formed below the covering material, but not below the outer edge of the covering material, thereby maintaining insulation reliability. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a top view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is a top view showing a semiconductor portion of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line I-II in FIG. 2. [Figure 4] 1 is a top view showing a semiconductor portion of a first modified example of the semiconductor device according to the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing a second modification of the semiconductor device according to the first embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a first modification of the semiconductor device according to the second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a second modification of the semiconductor device according to the second embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a third modification of the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a first modification of the semiconductor device according to the fourth embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a second modification of the semiconductor device according to the fourth embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a third modification of the semiconductor device according to the fourth embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing an active region of a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 13 is a top view showing a semiconductor portion of a semiconductor device according to a sixth embodiment. [Figure 18] FIG. 18 is a cross-sectional view taken along line I-II in FIG. [Figure 19] FIG. 20 is a top view showing a first modification of the semiconductor device according to the sixth embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing an active region of a second modified example of the semiconductor device according to the sixth embodiment. [Figure 21] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a sixth embodiment. [Figure 22] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a sixth embodiment. [Figure 23] 10 is a block diagram schematically showing the configuration of a power conversion system including a power conversion device 200 according to a seventh embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] A semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device according to embodiments will be described with reference to the drawings. The same or corresponding components will be given the same reference numerals, and repeated description may be omitted. The drawings are shown schematically, and the size and positional relationship of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. n and p indicate the conductivity type of the semiconductor, and in this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may also be p-type and the second conductivity type as n-type. Also, n - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0011] Embodiment 1 FIG. 1 is a top view showing a semiconductor device according to a first embodiment. This semiconductor device is a MOSFET. A gate pad 2 is formed on a part of the surface (first main surface) of a semiconductor substrate 1. A source electrode 3 is formed adjacent to the gate pad 2. A gate wiring 4 is formed so as to extend from the gate pad 2. For convenience, other components on the top surface of the MOSFET are omitted from FIG. 1.

[0012] 2 is a top view showing a semiconductor portion of the semiconductor device according to the first embodiment. Unit cell regions each consisting of a p-type well region 5 and an n-type isolation region 6 are repeatedly arranged in a stripe pattern in a plan view. The region in which the well region 5 is formed is called the active region. The region in which the p-type well region 7 and JTE region 8 are formed so as to surround the periphery of the active region is called the termination region.

[0013] 3 is a cross-sectional view taken along the line I-II in FIG. 2. The semiconductor substrate 1 has an n-type drift layer 10. An active region in which a main current flows in the thickness direction of the semiconductor substrate 1 is formed below the source electrode 3. A plurality of striped p-type well regions 5 are formed in the surface layer of the drift layer 10 in the active region. The plurality of well regions 5 may be connected to each other or may be separated from each other. When the surface of the semiconductor substrate 1 has a plane orientation of (0001) with an off-angle in the <11-20> direction, the striped well regions 5 may be formed parallel to the <11-20> direction or parallel to a direction perpendicular to the off-axis direction.

[0014] An n-type source region 11 is formed in the surface layer of each well region 5 at a position a predetermined distance inward from the periphery of the well region 5. A low-resistance p-type contact region 12 is formed in the surface layer of each well region 5, further inward from the source region 11.

[0015] An ohmic electrode 13 is formed on the n-type source region 11 and the p-type contact region 12. A source electrode 3 is formed on the ohmic electrode 13. The ohmic electrode 13 is formed by depositing a film of Ni or the like and then silicidating it. The source electrode 3 is formed as a thick film of aluminum or the like. The p-type well region 5 can easily transfer electrons and holes to and from the ohmic electrode 13 via the low-resistance p-type contact region 12.

[0016] The region of the drift layer 10 between adjacent well regions 5 forms an n-type separation region 6. The n-type impurity concentration of the separation region 6 may be the same as the n-type impurity concentration of the drift layer 10, or may be higher or lower than the n-type impurity concentration of the drift layer 10. A gate insulating film 14 made of silicon oxide is formed on the surfaces of adjacent well regions 5, the separation region 6 therebetween, and the source regions 11 in each well region 5. A gate electrode 15 made of polycrystalline silicon is formed on the gate insulating film 14 at least above the well region 5. The surface layer of the well region 5 facing the gate electrode 15 via the gate insulating film 14 is called a channel region.

[0017] A p-type well region 7 is formed in the surface layer of drift layer 10 outside the outermost well region 5. The region of drift layer 10 between well region 5 and well region 7 is an n-type separation region 16. The n-type impurity concentration of separation region 16 may be the same as the n-type impurity concentration of drift layer 10, or may be higher or lower than the n-type impurity concentration of drift layer 10.

[0018] A gate insulating film 14 is also formed on the well region 7. A gate electrode 15 is formed on the gate insulating film 14 at least above the well region 7. The gate electrode 15 extends in the stripe direction in a plan view, and its end is connected to the gate wiring 4 above the well region 7.

[0019] An n-type or p-type conductive layer 17 having a lower sheet resistance than the well region 7 is formed on a portion of the surface layer of the well region 7. An interlayer insulating film 18 made of silicon oxide is formed on the semiconductor substrate 1 between the gate electrode 15 and the source electrode 3. The gate electrode 15 above the well region 7 is connected to the gate wiring 4 via a gate contact hole 19 formed in the interlayer insulating film 18.

[0020] A p-type JTE region 8 is formed in the surface layer of the drift layer 10, on the outer periphery side of the well region 7. The impurity concentration of the JTE region 8 is lower than the impurity concentration of the well region 7. A field limiting ring (FLR) may be formed instead of the JTE region 8. Alternatively, both the JTE region 8 and the FLR may be formed.

[0021] A gate insulating film 14 and a field insulating film 20, which is thicker than the gate insulating film 14, are formed on the well region 7, conductive layer 17, and JTE region 8. When a displacement current flows due to a sudden voltage rise, the JTE region 8 and well region 7 become a current path, and a potential gradient is generated when multiplied with the resistance in the planar direction. At this time, the gate electrode 15 is structured to ride on the field insulating film 20 so that the insulating film does not break down due to the potential difference with the gate electrode 15. Note that the field insulating film 20 may be omitted for chips with a low breakdown voltage of 1200 V or less. In that case, the gate insulating film 14 is formed entirely below the gate electrode 15 in the termination region, resulting in a gate electrode 15 without any steps.

[0022] A termination region contact hole 21 is formed in a part of the gate insulating film 14 or field insulating film 20 and interlayer insulating film 18 on the conductive layer 17. Through this opening, the conductive layer 17 makes an ohmic connection with the source electrode 3 formed thereon via a termination ohmic electrode 22. The width of the conductive layer 17 is greater than the diameter of the termination region contact hole 21. The termination region contact hole 21 is continuous or discontinuous and surrounds the active region in a plan view.

[0023] In the active region, a source electrode 3 is formed on an interlayer insulating film 18. The source electrode 3 is connected to the ohmic electrode 13 via an active region contact hole 23 that penetrates the interlayer insulating film 18 and the gate insulating film 14. A drain electrode 24 is formed on the back surface (second main surface) of the semiconductor substrate 1. The gate electrode 15 is electrically insulated from the ohmic electrode 13 and the source electrode 3 by the interlayer insulating film 18.

[0024] A surface protective film 25 is formed to cover the source electrode 3, gate pad 2, gate wiring 4, field insulating film 20, and interlayer insulating film 18. The surface protective film 25 has openings (not shown) above the source electrode 3 and gate pad 2. The source electrode 3 and gate pad 2 can be electrically connected to the outside through these openings. The surface protective film 25 is made of organic materials such as polyimide, polybenzoxal, and acrylic resin, or inorganic materials such as silicon nitride. The surface protective film 25 may be made of a plurality of materials. The surface protective film 25 and the surface of the semiconductor substrate 1 may be covered with a resin (not shown) such as silicone gel or epoxy resin.

[0025] Since surface protection film 25 has high viscosity, it gets in the way when dicing the wafer into chips. Therefore, surface protection film 25 does not cover a certain width of the outer periphery of the surface of semiconductor substrate 1, and the outer periphery of surface protection film 25 is located inside the outer periphery of semiconductor substrate 1.

[0026] In the termination region, the surface protective film 25 completely covers the field insulating film 20 and the interlayer insulating film 18 exposed from the source electrode 3, the gate pad 2, and the gate wiring 4. Although the outer peripheral edge of the field insulating film 20 and the outer peripheral edge of the interlayer insulating film 18 are aligned, this is not necessarily the case.

[0027] In the termination region, an n-type peripheral well region 9 having a higher impurity concentration than the drift layer 10 is formed on the surface layer of the drift layer 10, closer to the outer periphery than the JTE region 8. The peripheral well region 9 extends from the inner periphery to the outer periphery, straddling the outer periphery edges of the field insulating film 20 and the interlayer insulating film 18. However, the outer periphery edge of the peripheral well region 9 is located inside the outer periphery edge of the surface protective film 25. The peripheral well region 9 is not electrically connected to anything other than the drift layer 10. Note that if the outer periphery edge of the field insulating film 20 and the outer periphery edge of the interlayer insulating film 18 do not coincide, the peripheral well region 9 may be configured to straddle the outer periphery edge of either the field insulating film 20 or the interlayer insulating film 18. The field insulating film 20 may be omitted, and the peripheral well region 9 may be configured to straddle the outer periphery edge of the interlayer insulating film 18.

[0028] Next, a method for manufacturing a semiconductor device according to this embodiment will be described. First, a substrate made of n-type silicon carbide with low resistance and a 4H polytype is prepared. The surface of the substrate has a (0001) plane orientation with an off-axis angle. A 1×10 15 From 1×10 17 cm -3 A semiconductor layer made of n-type silicon carbide having a thickness of 5 to 100 μm is epitaxially grown with an impurity concentration of 100 μm to 100 μm, thereby forming a semiconductor substrate 1 having an n-type drift layer 10.

[0029] Next, an implantation mask is formed on a predetermined region of the drift layer 10 using photoresist or the like, and p-type impurity Al (aluminum) ions are implanted. The depth of the Al ion implantation is set to about 0.5 to 3 μm, which does not exceed the thickness of the drift layer 10. The impurity concentration of the implanted Al ions is 1×10 17 From 1×10 19 cm -3The impurity concentration is set to a range higher than the impurity concentration of the drift layer 10. The implantation mask is then removed. When the implanted Al ions are activated by heat treatment, which will be described later, they become well region 5 in the active region and well region 7 in the termination region. The heat treatment after ion implantation is similar below, so its explanation will be omitted. Each region is formed by activating the impurities by heat treatment of the ion-implanted region.

[0030] Next, an implantation mask is formed on the drift layer 10 in the termination region using photoresist or the like, and Al ions with a p-type impurity concentration are implanted. The depth of the Al ion implantation is set to about 0.5 to 3 μm, which does not exceed the thickness of the drift layer 10. The impurity concentration of the implanted Al ions is 1×10 16 From 1×10 18 cm -3 , which is higher than the impurity concentration of the drift layer 10 and lower than the impurity concentration of the well region 5. Then, the implantation mask is removed. The region where Al is ion-implanted becomes the JTE region 8. Similarly, a predetermined region is implanted with 1×10 18 From 1×10 21 cm -3 The contact region 12 is formed by ion implanting Al with an impurity concentration in the range of 1000 to 15000 .mu.m.

[0031] Next, an implantation mask is formed using photoresist or the like so that a predetermined location inside the well region 5 on the surface of the drift layer 10 is opened, and N (nitrogen), an n-type impurity, is ion-implanted. The depth of N ion implantation is shallower than the thickness of the well region 5. The impurity concentration of the ion-implanted N is 1×10 18 From 1×10 21 cm -3 This ranges from 0 to 1000 psig, which is higher than the p-type impurity concentration of the well region 5. Of the regions into which N is implanted in this step, the region exhibiting n-type impurities becomes the source region 11.

[0032] Similarly, an implantation mask is formed using photoresist or the like so that a predetermined location on the outer periphery of the JTE region 8 of the termination region is opened, and N (nitrogen), an n-type impurity, is ion-implanted. The depth of N ion implantation is shallower than the thickness of the well region 5. The impurity concentration of the ion-implanted N is 1×10 18 From 1×10 21 cm -3 The region that exhibits n-type among the regions into which N is implanted in this step becomes the peripheral well region 9.

[0033] Similarly, an implantation mask is formed using photoresist or the like so that a predetermined location inside the well region 7 of the termination region is opened, and N, which is an n-type impurity, or Al, which is a p-type impurity, is ion-implanted. When N ions are implanted, the ion implantation depth is shallower than the thickness of the well region 5. The impurity concentration of the implanted N or Al is 1×10 18 From 1×10 21 cm -3 and the concentration of the p-type impurities in the well region 5 is in the range of 0.05 to 1.05, and is higher than the p-type impurity concentration in the well region 5. Of the regions into which N is implanted in this step, the region that exhibits n-type or p-type conductivity becomes the conductive layer 17. When the conductive layer 17 is n-type, the thickness of the conductive layer 17 only needs to be smaller than the thickness of the well region 7.

[0034] When the conductive layer 17 is of n-type, the conductive layer 17 may be formed in the same process as the source region 11 and the peripheral well region 9 to the same thickness and the same impurity concentration, or may be formed in a separate process to a different thickness and impurity concentration. When the conductive layer 17 is of p-type, the conductive layer 17 may be formed in the same process as the contact region 12 to the same thickness and impurity concentration, or may be formed in a separate process to a different thickness and impurity concentration.

[0035] Next, annealing is performed in a heat treatment device in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900°C for 30 seconds to 1 hour. This annealing electrically activates the implanted N and Al ions.

[0036] Next, using a CVD method, photolithography technology, or the like, a field insulating film 20 is formed on the semiconductor layer in a region excluding the active region that roughly corresponds to the region where the well region 5 is formed. The field insulating film 20 is made of silicon oxide and has a thickness of 0.5 to 2 μm, which is larger than the thickness of the gate insulating film 14.

[0037] Next, the silicon carbide surface that is not covered with the field insulating film 20 is thermally oxidized to form a silicon oxide film of a desired thickness as the gate insulating film 14. Next, a conductive polycrystalline silicon film is formed on the gate insulating film 14 and the field insulating film 20 by low-pressure CVD, and is patterned to form the gate electrode 15.

[0038] Next, an interlayer insulating film 18 made of silicon oxide and having a thickness larger than that of the gate insulating film is formed by low-pressure CVD. The interlayer insulating film 18 may be an insulating film containing B (boron) or P (phosphorus), such as BPSG (Boro-Phospho Silicate Glasses), or may be a laminated film of BPSG and silicon oxide without impurities. Note that the field insulating film 20 may be omitted by forming the interlayer insulating film 18 in the same location as the field insulating film 20.

[0039] Next, the interlayer insulating film 18 and the gate insulating film 14 are etched to form an active region contact hole 23 that reaches the contact region 12 and the source region 11 in the active region, and a termination region contact hole 21 that reaches the conductive layer 17 in the termination region.

[0040] Next, a metal film containing Ni as its main component is formed by sputtering or the like, followed by heat treatment at a temperature of 600 to 1100°C. This causes the metal film containing Ni as its main component to react with the silicon carbide layer in the active region contact holes 23 and termination region contact holes 21, forming silicide between the silicon carbide layer and the metal film. Next, the remaining metal film other than the silicide formed by the reaction is removed by wet etching. As a result, the remaining silicide becomes ohmic electrode 13 and termination region ohmic electrode 22.

[0041] Next, a metal film containing Ni as a main component is formed on the rear surface of the semiconductor substrate 1, and a rear ohmic electrode (not shown) is formed on the rear surface of the semiconductor substrate 1 by heat treatment.

[0042] Next, the interlayer insulating film 18 is removed from a predetermined location on the outer periphery of the JTE region 8 in the termination region and from a location that will become the gate contact hole 19. At this time, the interlayer insulating film 18 on the outer periphery of the field insulating film 20 is also removed.

[0043] Next, wiring metal such as Al is formed by sputtering or vapor deposition on the surface of the substrate that has been processed up to this point, and processed into a predetermined shape by photolithography to form the source electrode 3 connected to the source-side ohmic electrode 13 and the termination ohmic electrode 22, and the gate pad 2 and gate wiring 4 connected to the gate electrode 15. A protective film such as polyimide is formed, and then shaped into a predetermined shape by photolithography to form the surface protective film 25. The semiconductor device of this embodiment is manufactured by the above steps.

[0044] Next, the operation of the semiconductor device of this embodiment will be described. Here, the built-in potential of the pn junction will be described using a semiconductor device whose semiconductor material is 4H-type silicon carbide as an example.

[0045] <On state operation> The "on state" refers to the state in which a high voltage is applied to the drain electrode 24 relative to the source electrode 3, and a positive voltage equal to or greater than the threshold voltage is applied to the gate electrode 15. In the on state, an inversion channel is formed in the channel region, forming a path for electrons (carriers) to flow between the n-type source region 11 and the n-type separation region 6. Following the electric field formed by the positive voltage applied to the drain electrode 24, electrons travel from the source electrode 3 through the ohmic electrode 13, the source region 11, the channel region, the separation region 6, and the drift layer 10 to the drain electrode 24. Therefore, applying a positive voltage to the gate electrode 15 causes an on-current to flow from the drain electrode 24 to the source electrode 3. In other words, a main current flows in the thickness direction of the semiconductor substrate 1 in the active region. The voltage applied between the source electrode 3 and the drain electrode 24 is called the on-voltage. The on-voltage divided by the on-current density is called the on-resistance, which is equal to the sum of the resistances of the above-mentioned electron-flow paths. The product of the on-resistance and the square of the on-current is equal to the conduction loss consumed by a MOSFET when it is conducting, so a low on-resistance is preferable.

[0046] <Off state operation> The "off state" refers to the state in which a high voltage is applied to the drain electrode 24 relative to the source electrode 3, and a voltage below the threshold is applied to the gate electrode 15. In the off state, there are no inversion carriers in the channel region, so no on-current flows. In the on state, the high voltage that was applied to the load is applied between the source electrode 3 and drain electrode 24 of the MOSFET.

[0047] When the MOSFET is in the off state, a high electric field is applied near the pn junction interfaces between the drift layer 10 and the well region 5, between the drift layer 10 and the well region 7, and between the drift layer 10 and the JTE region 8. The voltage applied to the drain electrode 24 when this electric field reaches a critical electric field and avalanche breakdown occurs is defined as the maximum voltage (avalanche voltage) of the MOSFET. Typically, the rated voltage is determined so that the MOSFET can be used within a voltage range where avalanche breakdown does not occur.

[0048] In the off state, a depletion layer spreads from these pn junction interfaces toward the drain electrode 24 (downward in FIG. 3) and toward the periphery of the drift layer 10 (from the active region toward the termination region in FIG. 3). The extent of the depletion layer spreading from the pn junction interface between the drift layer 10 and the JTE region 8 depends greatly on the impurity concentration of the JTE region 8. When the impurity concentration of the JTE region 8 is relatively low, the depletion layer spreads widely inside the JTE region 8, and the extent of the depletion layer spreading toward the drift layer 10 is small. On the other hand, when the impurity concentration of the JTE region 8 is relatively high, the spread of the depletion layer into the JTE region 8 is suppressed, and the depletion layer spreads widely toward the drift layer 10.

[0049] Because the impurity concentration of the peripheral well region 9 is high at the surface of the drift layer 10, the depletion layer that spreads from the pn junction interface between the drift layer 10 and the JTE region 8 to the drift layer 10 does not spread beyond the inner end of the peripheral well region 9. At this time, a potential gradient of the applied voltage is formed inside the depletion layer that spreads from the pn junction interface between the JTE region 8 and the drift layer 10, and this potential gradient is inherited at the interface between the JTE region 8 and the field insulating film 20 and at the interface between the drift layer 10 and the field insulating film 20. Furthermore, the formation of the peripheral well region 9 prevents the depletion layer from spreading to the outer periphery of the peripheral well region 9. Therefore, no potential gradient is formed at the interface between the drift layer 10 and the surface protective film 25, and on the surface of the drift layer 10 on the outer periphery side of the surface protective film 25, and the potential becomes the same as the voltage applied to the drain electrode 24. Therefore, a high electric field is not applied between the surface protective film 25 and the outside of the semiconductor device, and insulation deterioration of the surface protective film 25 and the peripheral materials of the semiconductor device is suppressed.

[0050] <Operation under high humidity> Consider the case where a MOSFET is turned off under high humidity. The sealing resin formed to cover the semiconductor device may contain moisture. Therefore, the surface of the drift layer 10 on the outer periphery side of the surface protection film 25 is exposed to moisture at the same potential as the voltage applied to the drain electrode 24. + If a mold layer is formed, n +The mold layer has a strong ionization effect, and trace amounts of metals, such as Ni, which are necessary for forming the ohmic electrode 13 and the termination ohmic electrode 22, tend to adhere and remain when fabricating the MOSFET. When a high voltage is applied to the drain electrode 24 in this state, the trace amounts of metals may react with moisture to precipitate metal oxides, or the metal may act as a catalyst to react with silicon carbide and moisture to precipitate silicon oxides.

[0051] When foreign matter precipitates on the surface of the drift layer 10 on the outer periphery of the surface protection film 25, peeling occurs at the interface between the drift layer 10 and the sealing resin. Furthermore, if the deposition of foreign matter on the surface of the drift layer 10 progresses to the interface between the drift layer 10 and the surface protection film 25, peeling occurs at the interface between the drift layer 10 and the surface protection film 25. Further moisture may accumulate in these peeled areas, forming a leak path that differs from that occurring in normal semiconductor device operation. The peeling may progress to the point where electrical insulation cannot be maintained. As a result, the insulating performance of the semiconductor device is impaired.

[0052] In contrast to this, in this embodiment, the outer periphery edge of the peripheral well region 9 is disposed inside the outer periphery edge of the surface protection film 25. Therefore, the n + Even when a mold region is not formed and a high voltage is applied to the drain electrode 24 under high humidity conditions, the deposition of foreign matter can be suppressed. This prevents film peeling from occurring around the periphery and the formation of a leak path that differs from the operation of a normal semiconductor device, and maintains insulation reliability even when used under high humidity conditions.

[0053] In Figure 2, the unit cell regions are repeatedly arranged in a stripe pattern in plan view, but various modifications of the active region are possible. Figure 4 is a top view showing a semiconductor portion of Modification 1 of the semiconductor device according to Embodiment 1. The unit cell regions are repeatedly arranged vertically and horizontally in a lattice pattern in plan view. The configuration of the termination region is the same as above, and therefore produces the same effects.

[0054] 5 is a cross-sectional view showing Modification 2 of the semiconductor device according to Embodiment 1. The outer periphery edge of peripheral well region 9 is located more inward than the outer periphery edges of field insulating film 20 and interlayer insulating film 18. Peripheral well region 9 is covered by field insulating film 20 and interlayer insulating film 18 and is not in contact with surface protective film 25.

[0055] If stress is applied to the semiconductor device during or after manufacturing due to sealing, the surface protective film 25 may peel off. Furthermore, if the semiconductor device is sealed with epoxy resin or the like which has a high stress, an even higher stress is applied to the periphery of the chip, and the surface protective film 25 is likely to peel off. Furthermore, if sealing is performed with silicone gel or the like which has a low stress, the surface protective film 25 may be omitted. Even in such a case, since the outer periphery edge of the peripheral well region 9 is located inside the outer periphery edges of the field insulating film 20 and the interlayer insulating film 18, the n-type semiconductor layer 14 is formed on the surface of the drift layer 10 on the outer periphery side of the field insulating film 20 and the interlayer insulating film 18. + No mold region is formed, which makes it possible to suppress the deposition of foreign matter outside the field insulating film 20 and the interlayer insulating film 18 when a high voltage is continuously applied in a high humidity environment.

[0056] If the outer peripheral edge of the field insulating film 20 does not coincide with the outer peripheral edge of the interlayer insulating film 18, the outer peripheral edge of the peripheral well region 9 is located inside the outer peripheral edge of either the field insulating film 20 or the interlayer insulating film 18. Alternatively, the field insulating film 20 may be omitted and the outer peripheral edge of the peripheral well region 9 may be located inside the outer peripheral edge of the interlayer insulating film 18.

[0057] The impurity concentration on the front side of the peripheral well region 9 may be higher than that of the drift layer 10, and the impurity concentration on the back side may be lower than that on the front side and higher than that of the drift layer 10. If the impurity concentration on the back side of the peripheral well region 9 is higher than that on the front side, foreign matter is less likely to precipitate on the semiconductor surface. The source region 11 may be formed in the same process as the peripheral well region 9, with the same thickness and the same impurity concentration, or may be formed in a different process, with a different thickness and impurity concentration.

[0058] Embodiment 2 6 is a cross-sectional view showing a semiconductor device according to a second embodiment. An n-type peripheral well region 26 is formed in the surface layer of the drift layer 10, spaced apart from the peripheral well region 9 and closer to the periphery than the surface protection film 25. The peripheral well region 26 has a higher impurity concentration than the drift layer 10, and extends to the peripheral edge of the drift layer 10. The peripheral well region 26 is not electrically connected to anything other than the drift layer 10. The peripheral well region 26 is formed by an n-type well region formed by a test pattern or the like. + This is the mold region. The other configurations are the same as those of the first embodiment.

[0059] The outer peripheral edge of the surface protective film 25 is disposed between the outer peripheral well regions 9 and 26. That is, the outer peripheral well regions 9 and 26 are not formed below the outer peripheral edge of the surface protective film 25. Therefore, when a high voltage is applied to the drain electrode 24 under high humidity, the n-type semiconductor layer exposed from the surface protective film 25 + Foreign matter is deposited only on the surface of the peripheral well region 26, which is the mold region. Because the deposition of foreign matter does not reach the peripheral edge of the surface protection film 25, peeling of the surface protection film 25 can be suppressed. Therefore, insulation reliability can be maintained even when used in a high humidity environment.

[0060] The peripheral well region 9 and the peripheral well region 26 are formed in the same process to the same thickness and impurity concentration. The impurity concentration on the front side of the peripheral well region 26 may be higher than that of the drift layer 10, and the impurity concentration on the back side may be lower than that on the front side and higher than that of the drift layer 10. If the impurity concentration on the back side of the peripheral well region 26 is higher than that on the front side, foreign matter is less likely to precipitate on the semiconductor surface.

[0061] Foreign matter deposited on the surface of the peripheral well region 26 may be removed by airflow or by immersing it in a chemical solution. If the surface protective film 25 is omitted, the peripheral well region 26 is formed outside the field insulating film 20 and the interlayer insulating film 18. This limits the deposition of foreign matter to the outside of the field insulating film 20 and the interlayer insulating film 18, making it possible to prevent the field insulating film 20 and the interlayer insulating film 18 from peeling off.

[0062] 7 is a cross-sectional view showing a first modification of the semiconductor device according to the second embodiment. The peripheral well region 26 does not extend to the peripheral edge of the semiconductor substrate 1. This prevents the deposition of foreign matter at the chip edge, where stress is likely to occur between the semiconductor device and the sealing resin, and thus prevents the semiconductor device from peeling off from the sealing resin. The other configurations and effects are the same as those of the device in FIG. 6.

[0063] 8 is a cross-sectional view showing Modification 2 of the semiconductor device according to Embodiment 2. A peripheral insulating film 27 is formed on the semiconductor substrate 1 so as to cover part or all of the peripheral well region 26. The material of the peripheral insulating film 27 is the same as that of the field insulating film 20 or the interlayer insulating film 18, such as SiO2. The peripheral insulating film 27 may be formed by leaving the field insulating film 20 and the interlayer insulating film 18 on the surface of the peripheral well region 26 without etching them. By covering the peripheral well region 26 formed by a test pattern or the like with the peripheral insulating film 27, foreign matter is prevented from being deposited on the peripheral well region 26.

[0064] 9 is a cross-sectional view showing a third modification of the semiconductor device according to the second embodiment. A plurality of peripheral well regions 26 are formed spaced apart in a plan view. This reduces the area on the surface of peripheral well region 26 where foreign matter may precipitate, thereby preventing peeling between the semiconductor device and the encapsulating resin. Furthermore, peripheral well region 26 is not limited to a rectangular layout and can have various other layouts, making it possible to use it as a test pattern for checking the finished configuration of a portion of the semiconductor device.

[0065] A plurality of field insulating films 20 may be formed spaced apart in plan view so as to cover a part or all of a plurality of spaced-apart peripheral well regions 26. This makes it possible to suppress the deposition of foreign matter on the surface of the peripheral well region 26, thereby maintaining performance as a test pattern.

[0066] Embodiment 3 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. A peripheral electrode 28 is formed on the semiconductor substrate 1 and extends over the outer periphery of the field insulating film 20 and the interlayer insulating film 18. The peripheral electrode 28 is not electrically connected to any part other than the drift layer 10 and the peripheral well region 9. The peripheral electrode 28 has approximately the same potential as the voltage applied to the drain electrode 24, which can prevent the depletion layer from excessively expanding from the pn junction interface between the JTE region 8 and the drift layer 10.

[0067] The surface protective film 25 completely covers the peripheral electrode 28. The peripheral electrode 28 can be formed simultaneously with the formation of the source electrode 3, gate pad 2, and gate wiring 4. In the termination region, the peripheral well region 9 straddles the peripheral edges of the field insulating film 20 and interlayer insulating film 18, and the peripheral edge of the peripheral well region 9 is located more inward than the peripheral edge of the peripheral electrode 28. In other words, at least a portion of the peripheral well region 9 is formed below the field insulating film 20 and interlayer insulating film 18, and is not formed below the peripheral edge of the peripheral electrode 28. The other configurations are the same as those of the first embodiment.

[0068] If stress is applied to the semiconductor device during or after manufacturing due to sealing, the surface protective film 25 may peel off. Furthermore, if the semiconductor device is sealed with an epoxy resin or the like that has a large stress, an even larger stress is applied to the periphery of the peripheral electrode 28, making the surface protective film 25 more likely to peel off. Furthermore, if sealing is performed with a silicone gel or the like that has a small stress, the surface protective film 25 may be omitted. In contrast, the outer peripheral edge of the peripheral well region 9 is located inside the outer peripheral edge of the peripheral electrode 28. Therefore, the surface layer of the drift layer 10 on the outer peripheral side of the peripheral electrode 28 is covered with n + Even when a mold region is not formed and a high voltage is applied to the drain electrode 24 under high humidity conditions, the deposition of foreign matter can be suppressed. This prevents film peeling from occurring around the periphery and the formation of a leak path that differs from the operation of a normal semiconductor device, and maintains insulation reliability even when used under high humidity conditions.

[0069] Note that an n-type peripheral well region 26 having a higher impurity concentration than the drift layer 10 may be formed in the surface layer of the drift layer 10, spaced apart from the peripheral well region 9 and outside the peripheral electrode 28. In this case, the peripheral edge of the peripheral electrode 28 is disposed between the peripheral well region 9 and the peripheral well region 26. That is, the peripheral well regions 9, 26 are not formed below the peripheral edge of the peripheral electrode 28. Therefore, foreign matter precipitates only on the surface of the peripheral well region 26 and does not reach the peripheral edge of the peripheral electrode 28, thereby preventing peeling of the peripheral electrode 28.

[0070] Embodiment 4 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. A step 29 that is deeper than the peripheral well region 9 is formed on the surface of the semiconductor substrate 1 outside the peripheral well region 9. The step 29 extends to the peripheral edge of the semiconductor substrate 1. The peripheral edge of the surface protective film 25 is located in the step 29. When the step 29 is formed by etching, a portion of the peripheral well region 9 is removed. Because the remaining peripheral well region 9 is formed inside the surface protective film 25, foreign matter does not precipitate outside the surface protective film 25 even when a high voltage is applied to the drain electrode 24 under high humidity conditions.

[0071] 12 is a cross-sectional view showing a first modification of the semiconductor device according to the fourth embodiment. The outer peripheral edge of the step portion 29 is located inside the outer peripheral edge of the semiconductor substrate 1. The outer peripheral edge of the surface protective film 25 is located outside the outer peripheral edge of the step portion 29. The other configurations and effects are the same as those of the device in FIG.

[0072] FIG. 13 is a cross-sectional view showing a second modification of the semiconductor device according to the fourth embodiment. The outer peripheral edge of the step portion 29 is located inside the outer peripheral edge of the semiconductor substrate 1. The outer peripheral edge of the surface protective film 25 is located in the step portion 29. FIG. 14 is a cross-sectional view showing a third modification of the semiconductor device according to the fourth embodiment. The outer peripheral edge of the surface protective film 25 is located outside the outer peripheral edge of the step portion 29. A peripheral well region 26 is formed in the surface layer of the drift layer 10 outside the outer peripheral edges of the step portion 29 and the surface protective film 25. Therefore, when a high voltage is applied to the drain electrode 24 under high humidity, the n-type ... + The foreign matter is deposited only on the surface of the peripheral well region 26, which is the mold region. Since the deposited foreign matter does not reach the peripheral edge of the surface protection film 25, peeling of the surface protection film 25 can be suppressed.

[0073] 15 is a cross-sectional view showing an active region of Modification 4 of the semiconductor device according to Embodiment 4. In the unit cell region of the active region, a gate trench 30 is formed as a trench structure on the surface of the drift layer 10. Inside the gate trench 30, a gate electrode 15 is formed on the surface of the drift layer 10 via a gate insulating film 14. The depth of the step portion 29 is deeper than that of the gate trench 30. Therefore, the shallow trench structure reduces the on-resistance of the active region, while the deep step portion 29 increases the n-type charge of the peripheral well region 9. + The mold area can be etched.

[0074] The gate trench 30 and the step portion 29 are formed by reactive ion etching or the like. The depth of the step portion 29 is greater than the depth of the gate trench 30. Simultaneous formation of the gate trench 30 and the step portion 29 in the active region can reduce the number of manufacturing steps. When reactive ion etching or the like is used, the step portion 29 with a larger area can be made deeper than the gate trench 30 with a smaller area. Therefore, the depth of the gate trench 30 can be reduced to reduce the on-resistance or the electric field strength below the gate trench 30, while the step portion 29 that is deeper than the peripheral well region 26 can be formed. The gate trench 30 and the step portion 29 may be formed before or after annealing to electrically activate the ion-implanted N and Al.

[0075] Embodiment 5. 16 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. A termination trench 31 is formed widely in the termination region. The termination trench 31 is formed inside the outer peripheral ends of the field insulating film 20 and the interlayer insulating film 18. A well region 7 and a JTE region 8 are formed at the bottom of the termination trench 31. A p-type surface well region 32 is formed in the surface layer of the drift layer 10 around the periphery of the termination trench 31. The impurity concentration of the surface well region 32 may be the same as the impurity concentration of the well region 5.

[0076] An n-type peripheral well region 9 having a higher impurity concentration than the surface well region 32 is formed inside the surface well region 32. The peripheral well region 9 straddles the peripheral edges of the field insulating film 20 and the interlayer insulating film 18, and the peripheral edge of the peripheral well region 9 is located inside the peripheral edge of the surface protective film 25. Therefore, the n-type peripheral well region 9 is formed in the surface layer of the drift layer 10 on the peripheral side of the surface protective film 25. + Even when a p-type region is not formed and a high voltage is applied to drain electrode 24 under high humidity conditions, deposition of foreign matter can be suppressed. As a result, even when a high voltage is applied to drain electrode 24 under high humidity conditions in a configuration in which a p-type region is formed over the entire surface of semiconductor substrate 1, deposition of foreign matter can be suppressed.

[0077] If the outer peripheral edge of the field insulating film 20 does not coincide with the outer peripheral edge of the interlayer insulating film 18, the outer periphery well region 9 may be configured to straddle the outer peripheral edge of either the field insulating film 20 or the interlayer insulating film 18. The field insulating film 20 may be omitted, and the outer periphery well region 9 may be configured to straddle the outer peripheral edge of the interlayer insulating film 18.

[0078] In the case of a MOSFET having a trench structure in the unit cell region, the number of manufacturing steps can be reduced by simultaneously forming the p-type region that will become the well region 5 and the surface well region 32, and then forming the gate trench 30 and the termination trench 31. The termination trench 31 may also be formed simultaneously with the gate trench 30. In this case, the p-type region that will become the well region 5 and the surface well region 32 is formed on the entire surface of the drift layer 10 without performing a photolithography step, and then the gate trench 30 and the termination trench 31 are formed, thereby omitting the manufacturing steps of the semiconductor device.

[0079] Embodiment 6 The configuration, operation, and manufacturing method of a semiconductor device according to a sixth embodiment will be described below. The semiconductor device according to this embodiment is a MOSFET with an SBD region built in. When viewed from above, the semiconductor device according to this embodiment has the same plan view as the MOSFET in FIG.

[0080] 17 is a top view showing a semiconductor portion of a semiconductor device according to a sixth embodiment. Unit cell regions each consisting of an n-type isolation region 33 and a p-type well region 5 are repeatedly arranged in one direction in a plan view. The isolation region 33 roughly corresponds to an SBD region. The p-type well region 5 roughly corresponds to a MOSFET region. Therefore, unit cell regions each having a MOSFET region formed on both sides of an SBD region are arranged in a stripe pattern. The region in which the SBD-integrated MOSFET is formed becomes the active region. The region on the outer periphery of the active region where the p-type well region 7 and the like are formed becomes the termination region.

[0081] 18 is a cross-sectional view taken along line I-II in FIG. 17. Stripe-shaped separation regions 33 penetrating well region 5 are formed in the surface layer of drift layer 10, inside contact region 12. The n-type impurity concentration of separation regions 33 may be the same as, or may be higher or lower than, the n-type impurity concentration of drift layer 10.

[0082] A stripe-shaped Schottky electrode 34 is formed on the surface side of the separation region 33. The Schottky electrode 34 is in Schottky contact with the separation region 33. It is desirable that the Schottky electrode 34 is formed to include at least the corresponding separation region 33 when viewed from above. An ohmic electrode 13 is formed on the surface of the source region 11. A source electrode 3 is formed on and connected to the ohmic electrode 13, the Schottky electrode 34, and the contact region 12. The ohmic electrode 13, the Schottky electrode 34, the source electrode 3, and the gate electrode 15 are electrically insulated from one another by an interlayer insulating film 18. The well region 5 can easily exchange electrons and holes with the ohmic electrode 13 via the low-resistance contact region 12. The other configurations are the same as those of the first embodiment.

[0083] Although the above description concerns a MOSFET in which unit cell regions are repeatedly arranged in a stripe pattern in plan view, various modifications of the active region are conceivable. Fig. 19 is a top view showing a first modification of a semiconductor device according to the sixth embodiment. In this MOSFET, unit cell regions are repeatedly arranged vertically and horizontally in a lattice pattern in plan view. Even in this case, the configuration of the termination region is the same as that of the sixth embodiment, and similar effects are achieved. Furthermore, the termination region of the SBD-integrated MOSFET according to the sixth embodiment can also have any of the configurations shown in the second to fifth embodiments.

[0084] FIG. 20 is a cross-sectional view showing an active region of a semiconductor device according to a second modification of the sixth embodiment. An SBD-integrated MOSFET having a trench structure is formed in a unit cell region of the active region. Striped gate trenches 30 and striped Schottky trenches 35 are arranged parallel to each other and alternately. Inside the gate trench 30, a gate electrode 15 is formed on the surface of the drift layer 10 via a gate insulating film 14. A Schottky electrode 34 is buried inside the Schottky trench 35. Furthermore, in the termination region of the SBD-integrated MOSFET according to the second modification, if the structure shown in the fourth embodiment is adopted, the depth of the step portion 29 is deeper than the depths of the gate trench 30 and the Schottky trench 35.

[0085] Next, the method for manufacturing a semiconductor device according to this embodiment will be described in terms of differences from embodiment 1. Figures 21 and 22 are cross-sectional views showing a method for manufacturing a semiconductor device according to embodiment 6. When forming active region contact hole 23 and termination region contact hole 21, the insulating film is left in the area where Schottky electrode 34 is to be formed.

[0086] As shown in FIG. 21 , etching using a resist mask 36 removes the interlayer insulating film 18 on the separation region 33, the gate insulating film 14, and the interlayer insulating film 18 at a position that will become the gate contact hole 19. At this time, the interlayer insulating film 18 on the outer periphery of the field insulating film 20 is also removed. The removal method is wet etching that does not damage the surface of the silicon carbide layer that will become the Schottky interface. There is a possibility that the interlayer insulating film 18 will be wet-etched in unintended areas due to insufficient adhesion between the surface of the silicon carbide layer, the ohmic electrode 13, or the SiO2 of the interlayer insulating film 18 and the resist mask 36. Therefore, a metal mask 37 such as Ni is used below the resist mask 36.

[0087] After removing the resist mask 36, a metal film 38 is deposited by sputtering or the like, as shown in Fig. 22. The metal film 38 is patterned using photoresist or the like to form a Schottky electrode 34 on the separation region 33 in the active region contact hole 23, and heat treatment is then performed. The material of the Schottky electrode 34 is Ti, Mo, or the like. The other manufacturing steps are the same as those of the first embodiment.

[0088] Next, a description will be given of the operation of the semiconductor device of this embodiment that differs from that of embodiment 1. In the on state, a Schottky junction formed at the contact portion between separation region 33 and Schottky electrode 34 is applied with an electric field (reverse bias) in a direction that makes it difficult for a current to flow through the Schottky junction, i.e., in the reverse direction, so that no current flows.

[0089] During freewheeling, bipolar current flows through the pn junction. If a basal plane dislocation or other initiation point is present at this location, stacking faults can expand, increasing resistance during on-state operation. This increases on-state voltage and power loss. By incorporating an SBD, bipolar forward current (a bipolar current) can be prevented from flowing through the pn junction during freewheeling, thereby preventing power loss in the semiconductor device.

[0090] In the off state, an electric field is applied in the same direction as in the on state to the Schottky junction formed at the contact point between the separation region 33 and the Schottky electrode 34, so ideally no current flows. However, a much stronger electric field than in the on state is applied, so leakage current may occur. A large leakage current increases heat generation in the MOSFET and may thermally destroy the MOSFET and the module using the MOSFET. Therefore, it is preferable to keep the electric field applied to the Schottky junction low to reduce leakage current.

[0091] In a MOSFET with an SBD, residues of the metal mask 37 or the metal film 38 of the Schottky electrode 34 are likely to remain on the surface of the drift layer 10 on the outer periphery side of the surface protection film 25. Therefore, compared to a MOSFET without an SBD, deposition of foreign matter is accelerated on the surface of the drift layer 10 on the outer periphery side of the surface protection film 25 during operation under high humidity. This causes peeling at the interface between the drift layer 10 and the surface protection film 25, which can impair the insulating performance of the semiconductor device, becoming a significant problem.

[0092] In contrast, in the present embodiment, the outer periphery edge of the peripheral well region 9 is disposed inside the outer periphery edge of the surface protective film 25, as in the first embodiment. + Even when a mold region is not formed and a high voltage is applied to the drain electrode 24 under high humidity conditions, the deposition of foreign matter can be suppressed. This prevents film peeling from occurring around the periphery and the formation of a leak path that differs from the operation of a normal semiconductor device, and maintains insulation reliability even when used under high humidity conditions.

[0093] Furthermore, by combining the SBD-integrated MOSFET according to this embodiment with the modified example of the first embodiment or the configurations of the second to fifth embodiments, the same effects as those of the modified example can be obtained.

[0094] In the above embodiment, the p-type impurity is aluminum (Al), but it may be boron (B) or gallium (Ga). The n-type impurity is not limited to nitrogen (N) but may be phosphorus (P). The gate insulating film 14 is not limited to an oxide film such as SiO2, but may be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film. Although silicon oxide obtained by thermally oxidizing silicon carbide is used as the gate insulating film 14, silicon oxide deposited by a CVD method may also be used. In the above embodiment, specific examples of the crystal structure, plane orientation of the main surface, off-angle, and each implantation condition are described, but the applicable range is not limited to these numerical ranges. The semiconductor device may be a MOSFET having a superjunction structure with an SBD built in.

[0095] The semiconductor substrate 1 is not limited to being made of silicon, but may also be made of a wide-bandgap semiconductor having a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. Semiconductor devices made of such wide-bandgap semiconductors have high voltage resistance and allowable current density, allowing for miniaturization. By using such miniaturized semiconductor devices, semiconductor modules incorporating such semiconductor devices can also be miniaturized and highly integrated. Furthermore, the high heat resistance of the semiconductor device allows for miniaturization of the heat dissipation fins of the heat sink, enabling water-cooled parts to be replaced by air-cooled parts, further miniaturizing the semiconductor module. Furthermore, the low power loss and high efficiency of the semiconductor device allow for high efficiency of the semiconductor module.

[0096] Switching elements made of wide bandgap semiconductors can be used in high voltage regions where unipolar operation is difficult with Si semiconductors, and can significantly reduce the switching loss that occurs during switching operation. This allows for a significant reduction in power loss. Furthermore, switching elements made of wide bandgap semiconductors are suitable for high-frequency switching operation. Therefore, when applied to converter circuits that require higher frequencies, increasing the switching frequency also makes it possible to reduce the size of reactors or capacitors connected to the converter circuit.

[0097] Embodiment 7 A power conversion device and a method of manufacturing the power conversion device according to embodiment 7 will be described. In this embodiment, the semiconductor devices according to the above embodiments 1 to 6 are applied to a power conversion device. In the following description, components similar to those described in embodiments 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. The power conversion device to which the present invention is applied is not limited to one for a specific purpose, but the following description will be given of the case where the present invention is applied to a three-phase inverter.

[0098] FIG. 23 is a block diagram showing a schematic configuration of a power conversion system including a power conversion apparatus 200 according to the seventh embodiment. The power conversion system includes a power supply 100, the power conversion apparatus 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion apparatus 200. The power supply 100 can be configured from various sources, such as a DC system, a solar cell, or a storage battery. The power supply 100 can also be configured from a rectifier circuit or an AC-DC converter connected to an AC system. The power supply 100 can also be configured from a DC-DC converter that converts DC power output from a DC system into predetermined power.

[0099] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. The power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals for driving each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.

[0100] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electric devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0101] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). The switching element performs a switching operation to convert DC power supplied from the power source 100 into AC power, which is then supplied to the load 300.

[0102] There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit and can be configured with six switching elements and six freewheeling diodes connected in anti-parallel to each switching element.

[0103] The semiconductor devices according to the first to sixth embodiments are applied to each of the switching elements in the main conversion circuit 201. The six switching elements are connected in series in groups of two to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0104] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies the drive signals to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, based on control signals output from a control circuit 203 (described later), the drive circuit 202 outputs a drive signal that turns the switching elements on and a drive signal that turns the switching elements off to the control electrodes of the respective switching elements.

[0105] When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) that is less than the threshold voltage of the switching element.

[0106] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the on time of the switching elements according to the voltage to be output.

[0107] Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to a switching element that should be in an ON state at each point in time, and an OFF signal is output to a switching element that should be in an OFF state at each point in time. Based on the control signal, the drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0108] In the power conversion device 200 according to the present embodiment, the semiconductor devices according to the above-described first to sixth embodiments are applied as switching elements of the main conversion circuit 201, and therefore the on-resistance after a current cycle can be stabilized. When the semiconductor devices according to the first to sixth embodiments are applied to the power conversion device 200 in this manner, the semiconductor devices are usually used while embedded in gel, epoxy resin, or the like, but these materials cannot completely block moisture, so the insulation protection of the semiconductor devices according to the first to sixth embodiments is maintained. In other words, the reliability of the power conversion device 200 can be improved by applying the semiconductor devices according to the first to sixth embodiments.

[0109] In the present embodiment, an example has been described in which the semiconductor device according to the first to sixth embodiments is applied to a two-level three-phase inverter, but the present invention is not limited to this and the semiconductor device according to the first to sixth embodiments can be applied to various power conversion devices. In addition, in the present embodiment, a two-level power conversion device has been described, but the semiconductor device according to the first to sixth embodiments can be applied to a three-level or multi-level power conversion device. In addition, when power is supplied to a single-phase load, the semiconductor device according to the first to sixth embodiments can be applied to a single-phase inverter. In addition, when power is supplied to a DC load or the like, the semiconductor device according to the first to sixth embodiments can be applied to a DC-DC converter or an AC-DC converter.

[0110] Furthermore, the power conversion device to which the semiconductor device according to any one of the first to sixth embodiments is applied is not limited to the case where the load is an electric motor, and can also be used as a power supply device for, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system. Furthermore, the power conversion device to which the semiconductor device according to any one of the first to sixth embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0111] Next, a method for manufacturing a power conversion device according to this embodiment will be described. First, a semiconductor device is manufactured using the manufacturing method described in the first to sixth embodiments. Then, a main conversion circuit 201 having the semiconductor device is incorporated into a power conversion device 200. The main conversion circuit 201 is a circuit for converting input power and outputting it. Then, a drive circuit 202 is incorporated into the power conversion device 200. Then, a control circuit 203 is incorporated into the power conversion device 200.

[0112] In the above embodiments, the physical properties, materials, dimensions, shapes, relative positional relationships, and implementation conditions of each component may be described, but these are merely examples in all respects and the present disclosure is not limited to those described. Therefore, countless variations not exemplified are contemplated within the scope of the present disclosure. For example, these include modifying, adding, or omitting any component, and extracting at least one component from at least one embodiment and combining it with components from other embodiments.

[0113] Furthermore, unless a contradiction arises, a component described in each of the above embodiments as being provided with "one" may be provided with "one or more." Furthermore, the components constituting the present disclosure are conceptual units, and one component may include multiple structures, or one component may correspond to a part of a structure. Furthermore, each component of the present disclosure includes structures having different structures or shapes as long as they perform the same function. Note that within the scope of the present disclosure, each embodiment can be freely combined, modified, or omitted as appropriate.

[0114] Although this disclosure has been described in detail, the above description is illustrative in all respects and does not limit the disclosure thereto. It is understood that countless variations not illustrated can be assumed without departing from the scope of this disclosure. Furthermore, the descriptions in this specification are to be used as reference for all purposes of this disclosure, and unless otherwise specified, they are not to be acknowledged as prior art.

[0115] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. Various aspects of the present disclosure are summarized below as appendices.

[0116] (Appendix 1) a semiconductor substrate having a drift layer of a first conductivity type; an active region in which a main current flows in a thickness direction of the semiconductor substrate; a second conductivity type termination region formed on a surface layer of the drift layer so as to surround the periphery of the active region; a covering material covering the termination region; a first conductivity type outer well region formed in a surface layer of the drift layer outside the termination region and having a higher impurity concentration than the drift layer, an outer circumferential edge of the covering material is disposed inside the outer circumferential edge of the semiconductor substrate; The semiconductor device is characterized in that at least a portion of the peripheral well region is formed below the covering material, and is not formed below the outer peripheral edge of the covering material. (Appendix 2) a surface electrode connected to the active region and formed on the semiconductor substrate; the covering material includes an insulating film that covers the termination region and a surface protection film that covers the insulating film and the surface electrode, 2. The semiconductor device according to claim 1, wherein the peripheral well region is not formed below the peripheral edge of the surface protection film. (Appendix 3) 3. The semiconductor device according to claim 2, wherein the outer periphery edge of the peripheral well region is located inside the outer periphery edge of the insulating film. (Appendix 4) the covering material has an insulating film that covers the termination region, and a peripheral electrode that is formed on the semiconductor substrate and extends over the outer periphery of the insulating film; The semiconductor device described in Appendix 1, characterized in that at least a portion of the peripheral well region is formed below the insulating film and is not formed below the peripheral end of the peripheral electrode. (Appendix 5) The semiconductor device described in any one of Appendices 1 to 4, characterized in that the peripheral well region has a first peripheral well region formed below the covering material and a second peripheral well region formed away from the first peripheral well region and more outer than the covering material. (Appendix 6) 6. The semiconductor device according to claim 5, wherein the second peripheral well region does not extend to the peripheral edge of the semiconductor substrate. (Appendix 7) 7. The semiconductor device according to claim 5, further comprising a peripheral insulating film covering the second peripheral well region. (Appendix 8) 8. The semiconductor device according to any one of claims 1 to 7, wherein a step portion deeper than the peripheral well region is formed on the surface of the semiconductor substrate outside the peripheral well region. (Appendix 9) a transistor having a trench structure is formed in the active region; 9. The semiconductor device according to claim 8, wherein the step portion is deeper than the trench structure. (Appendix 10) a second conductivity type surface well region formed in a surface layer of the semiconductor substrate from inside the outer circumferential edge of the coating material to the outer circumferential edge of the semiconductor substrate, 10. The semiconductor device according to any one of claims 1 to 9, wherein the peripheral well region is formed in a surface layer of the surface well region. (Appendix 11) 11. The semiconductor device according to any one of claims 1 to 10, wherein an SBD region and a MOSFET region are formed in the active region. (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, wherein the semiconductor substrate is made of a wide bandgap semiconductor. (Appendix 13) A main conversion circuit having the semiconductor device according to any one of Supplementary Notes 1 to 12, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit. (Appendix 14) 3. A method for manufacturing the semiconductor device according to claim 2, wherein a metal mask is used when patterning the insulating film. (Appendix 15) 12. A method for manufacturing a semiconductor device according to claim 11, characterized in that a metal film is formed on a surface of the semiconductor substrate and then heat-treated to form a Schottky electrode in the SBD region. [Explanation of symbols]

[0117] 1 semiconductor substrate, 3 source electrode (surface electrode), 7 well region (termination region), 8 JTE region (termination region), 9, 26 peripheral well region, 10 drift layer, 18 interlayer insulating film (coating material), 20 field insulating film (coating material), 25 surface protection film (coating material), 27 peripheral insulating film, 28 peripheral electrode (coating material), 29 step portion, 30 gate trench (trench structure), 32 surface well region, 34 Schottky electrode, 37 metal mask, 38 metal film, 201 main conversion circuit, 202 drive circuit, 203 control circuit

Claims

1. a semiconductor substrate having a drift layer of a first conductivity type; an active region in which a main current flows in a thickness direction of the semiconductor substrate; a second conductivity type termination region formed on a surface layer of the drift layer so as to surround the periphery of the active region; a covering material covering the termination region; a first conductivity type outer well region formed in a surface layer of the drift layer outside the termination region and having a higher impurity concentration than the drift layer; an outer circumferential edge of the covering material is disposed inside the outer circumferential edge of the semiconductor substrate; the peripheral well region is at least partially formed below the cladding material and is not formed below the peripheral edge of the cladding material; The semiconductor device is characterized in that the peripheral well region has a first peripheral well region formed below the covering material, and a second peripheral well region formed on the outer side of the covering material and spaced apart from the first peripheral well region.

2. a surface electrode connected to the active region and formed on the semiconductor substrate; the covering material includes an insulating film that covers the termination region and a surface protection film that covers the insulating film and the surface electrode, 2. The semiconductor device according to claim 1, wherein the peripheral well region is not formed below the peripheral edge of the surface protection film.

3. 3. The semiconductor device according to claim 2, wherein the outer periphery edge of the outer periphery well region is located inside the outer periphery edge of the insulating film.

4. the covering material has an insulating film that covers the termination region, and a peripheral electrode that is formed on the semiconductor substrate and extends over the outer periphery of the insulating film; 2. The semiconductor device according to claim 1, wherein at least a portion of the peripheral well region is formed below the insulating film, and is not formed below the peripheral end of the peripheral electrode.

5. 5. The semiconductor device according to claim 1, wherein the second peripheral well region does not extend to the peripheral edge of the semiconductor substrate.

6. 5. The semiconductor device according to claim 1, further comprising a peripheral insulating film covering the second peripheral well region.

7. 5. The semiconductor device according to claim 1, wherein a step portion deeper than the peripheral well region is formed on the surface of the semiconductor substrate outside the peripheral well region.

8. a transistor having a trench structure is formed in the active region; 8. The semiconductor device according to claim 7, wherein the step portion has a depth greater than that of the trench structure.

9. a second conductivity type surface well region formed in a surface layer of the semiconductor substrate from inside the outer circumferential edge of the coating material to the outer circumferential edge of the semiconductor substrate, 5. The semiconductor device according to claim 1, wherein the peripheral well region is formed in a surface layer of the surface well region.

10. 5. The semiconductor device according to claim 1, wherein an SBD region and a MOSFET region are formed in the active region.

11. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide bandgap semiconductor.

12. a main conversion circuit including the semiconductor device according to any one of claims 1 to 4, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit.

13. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a metal mask is used when patterning the insulating film.

14. 11. A method for manufacturing a semiconductor device according to claim 10, wherein a metal film is formed on a surface of the semiconductor substrate and then heat-treated to form a Schottky electrode in the SBD region.

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