Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device in which electric field concentration at an external terminal is alleviated.SOLUTION: A terminal portion 20 of a semiconductor device includes a second external terminal 20c, an insulating sheet 20b arranged on the second external terminal 20c, and a first external terminal 20a arranged on the insulating sheet 20b, and the second external terminal 20c, the insulating sheet 20b, and the first external terminal 20a are arranged stepwise. In the first external terminal 20a, the closer the rear surface 20a6 of a first end portion 20a3 along the side of the outer end is to the tip, the closer the rear surface other than the first end portion 20a3 is to the front surface side. This reduces the electric field strength at the outer end of the second external terminal 20c.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Semiconductor devices used in power conversion devices are generally configured as follows: First, a semiconductor chip is mounted by soldering to a wiring pattern on an insulating substrate. One end of an external terminal integrally formed with a terminal case is joined to the wiring pattern on the insulating substrate. The semiconductor chip and the wiring pattern, the wiring pattern and the external terminal, or the semiconductor chip and the external terminal are joined using metal wire or the like, and the inside of the terminal case is sealed by injecting a filler material (see Patent Document 1). A metal plate is soldered to a metal foil formed on the surface of the insulating substrate opposite to the side on which the semiconductor chip is mounted. The outer surface of this metal plate can be abutted against a heat dissipation fin or the like to dissipate heat generated by the semiconductor chip to the outside.

[0003] In such semiconductor devices, the higher the voltage handled, the more important it is to improve the insulating strength against the insulating substrate. To this end, it is known that the electric field in high-electric-field areas can be alleviated by making the upper creepage distance from the edge of the metal coating (corresponding to the wiring pattern) to the edge of the insulating substrate shorter than the lower creepage distance from the edge of the metal coating (corresponding to the metal foil) to the edge of the insulating substrate (see Patent Document 2). It is also known that, in addition to making the upper creepage distance shorter than the lower creepage distance, filling the gap between the insulating substrate and the metal plate with an insulating material with a lower dielectric constant than the sealing filler improves the insulating performance by alleviating the electric field and suppressing defects (see Patent Document 3).

[0004] It is also known that in a semiconductor device having a circuit board in which copper plates are arranged on the top and bottom surfaces of a ceramic insulating substrate at positions offset inward from the outer periphery of the insulating substrate, with the edge of the upper copper plate positioned more inward than the edge of the lower copper plate, and in which the insulating substrate, the upper copper plate, and the lower copper plate are sealed with resin except for the underside of the lower copper plate, an electric field is concentrated at the edge of the upper copper plate that contacts the insulating substrate (see Non-Patent Document 1).It is also known that an electric field can be suppressed when the circuit board has a ceramic insulating substrate, an upper conductor layer that is an electric circuit pattern arranged on the top surface of the insulating substrate and offset inward from the outer periphery of the insulating substrate, and a lower conductor layer that is arranged on the bottom surface of the insulating substrate and offset inward from the outer periphery of the insulating substrate in a plan view and extends outward beyond the edge of the conductor layer, and has a cross-sectional structure in which the edge of the joint surface between the upper conductor layer and the insulating substrate is recessed more inward than the outermost edge of the upper conductor layer (see Patent Document 4).

[0005] It is also known to form a curved surface at the end of a recess in an insulating substrate placed on a base substrate, form a metal layer in this recess, and place a circuit-side conductor on the metal layer (see Patent Document 5).

[0006] It is also known that if the solder material that joins the surface electrode corresponding to the wiring pattern to the insulating substrate is made to protrude out to the side of the insulating substrate, the protruding portion will shield the space between the surface electrode and the back electrode of the insulating substrate, thereby reducing the electric field strength at the upper end portion of the surface electrode (see Patent Document 6).

[0007] Furthermore, it is known that if the intersection between the main surface of an insulating substrate and the side surface of a conductive plate arranged on this main surface is covered with an ion gel containing an ionic liquid, the local concentration of electric field at the intersection can be alleviated, thereby improving the dielectric strength voltage (see Patent Document 7).

[0008] There is also a semiconductor device that reduces electric field concentration at the end of a wiring pattern to which a high voltage is applied (see Patent Document 8). According to this semiconductor device, between two adjacent wiring patterns that have a potential difference among the wiring patterns carrying multiple sets of semiconductor chips, another wiring pattern is disposed that has a potential between the potential differences between the adjacent wiring patterns.

[0009] Incidentally, some semiconductor devices are provided with external terminals to which a large-capacity capacitor can be connected externally (see Patent Document 9). The capacitor is intended to smooth fluctuations in the input DC power supply voltage. The external terminals of the semiconductor device are electrically connected to the electrodes of the capacitor by ultrasonic bonding. The electrodes of the capacitor are configured such that plate-shaped positive and negative external electrodes are arranged in parallel with an insulating member sandwiched between them. This suppresses the generation of inductance in the capacitor electrodes and reduces the resistance value of the joint.

[0010] Also known is a power module in which multiple plate-shaped conductors protrude from the side of the power module with an insulating plate sandwiched therebetween, and the end of the upper conductor coincides with the end of the insulating plate in a plan view. In this power module, the tip ends of each DC bus bar connected to the positive and negative electrodes of the smoothing capacitor are electrically connected to the positive and negative main electrodes, respectively, by brazing material (see Patent Documents 10 and 11). [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 11-26691 (Fig. 1) [Patent Document 2] JP 2002-270730 A (Fig. 4) [Patent Document 3] JP 2012-9815 A (Fig. 3) [Patent Document 4] Japanese Patent Application Laid-Open No. 9-135057 (Fig. 4) [Patent Document 5] JP 2001-57409 A (Fig. 1) [Patent Document 6] JP 2019-197816 A (Fig. 6) [Patent Document 7] JP 2017-28132 A (Fig. 1) [Patent Document 8] WO 2011 / 040054 (Figure 8) [Patent Document 9] JP 2007-234694 A (Fig. 1) [Patent Document 10] JP 2009-5512 A (Fig. 4) [Patent Document 11] JP 2006-121834 A (Fig. 1) [Non-patent literature]

[0012] [Non-Patent Document 1] Yuichiro Hinata et al., Fuji Electric Technical Report, 2016, Vol.89, no.4, pp242-246 Summary of the Invention [Problem to be solved by the invention]

[0013] In all of the conventional semiconductor devices, there are descriptions of reducing the electric field concentration at the ends of the wiring patterns on the circuit board within the device. However, because the same high voltage as that applied to the wiring patterns is also applied to the external terminals connecting the capacitors, there is a problem in that the application of high voltage for a long period of time at the locations where the electric field concentration occurs deteriorates the insulating material, resulting in poor insulation.

[0014] The present invention has been made in view of the above points, and has as its object to provide a semiconductor device in which electric field concentration at external terminals is alleviated. [Means for solving the problem]

[0015] In one aspect of the present invention, a semiconductor device is provided, comprising: a first external terminal having an end portion including a first end portion; a second external terminal having a terrace region on a portion of its front surface, the portion of the front surface excluding the terrace region being disposed opposite the back surface of the first external terminal; and an insulating sheet disposed between the first and second external terminals and adjacent to the terrace region of the second external terminal, wherein the front surface of the first external terminal is flat, and the back surface of the end portion of the first external terminal is farther from the second external terminal as it approaches the tip of the end portion, and the first external terminal is closer to the second external terminal in plan view. The first external terminal has a second end and a third end which are the ends of both sides in a direction perpendicular to the direction in which the terrace region and the first external terminal are arranged, and the back surfaces of the second end and the third end are farther from the second external terminal the closer they are to the tip of the end, and the sides of the front surface of the second end and the front surface of the third end of the first external terminal overlap with the ends of the second external terminal in a planar view, and the second external terminal has cutouts at the ends of the second external terminal at positions facing the corners formed by the first end, the second end, and the third end of the first external terminal in a planar view.

[0016] In another aspect of the present invention, a method for manufacturing a terminal includes the steps of: preparing a first external terminal having a front surface and a back surface, the front surface being flat, and the back surface of an end portion being closer to the front surface than the back surface of the other end portion as it approaches the tip; preparing an insulating sheet; preparing a second external terminal having a terrace region on a portion of the front surface; arranging the insulating sheet on the second external terminal adjacent to the terrace region; and arranging the first external terminal so that the back surface of the first external terminal faces, via the insulating sheet, a portion of the front surface of the second external terminal excluding the terrace region. A method for manufacturing a semiconductor device is provided, in which the insulating sheet has a first end and a second end and a third end which are ends of both sides opposing the first end, the insulating sheet has an insulating region that does not contact the first external terminal in a planar view, the step of preparing the first external terminal includes a step of forming the back surface of the second end and the back surface of the third end so that the closer to the tips of the second end and the third end, the closer to the front surface side than the back surfaces of the parts other than the second end and the third end, and the step of arranging the first external terminal is a step of overlapping the edge of the front surface of the second end and the edge of the front surface of the third end of the first external terminal with the edge of the second external terminal in a planar view. [Effects of the Invention]

[0017] The semiconductor device having the above configuration has the advantage that the back surface of the end of the first external terminal facing the insulating sheet is farther from the second external terminal the closer it is to the tip of the end, thereby mitigating electric field concentration. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 2 is a cross-sectional view taken along the X1-X1 arrows in FIG. 1. [Figure 3] 2 is a cross-sectional view showing a connection state between a terminal portion and a capacitor of the semiconductor device according to the first embodiment. FIG. [Figure 4] 4A and 4B are diagrams showing the configuration of a terminal portion, in which (A) is a plan view of the terminal portion and (B) is a bottom view of the terminal portion. [Figure 5]4(A) is a cross-sectional view taken along the line X2-X2 of FIG. [Figure 6] 4(A) is a cross-sectional view taken along the line X3-X3 in FIG. [Figure 7] FIG. 10 is a diagram showing an electric field relaxation effect. [Figure 8] 10A and 10B are diagrams showing the configuration of a terminal portion of a semiconductor device according to a second embodiment, in which (A) is a plan view of the terminal portion and (B) is a bottom view of the terminal portion. [Figure 9] FIG. 8B is an enlarged view of part A in FIG. [Figure 10] 10A and 10B are diagrams showing a state in which the terminal portion is sealed with resin by the case. [Figure 11] FIG. 10 is a diagram showing an electric field relaxation effect. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, parts denoted by the same reference numerals indicate the same components. Each embodiment can be implemented by partially combining multiple embodiments within a consistent range.

[0020] [First embodiment] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment, FIG. 2 is a cross-sectional view taken along the line X1-X1 in FIG. 1, and FIG. 3 is a cross-sectional view showing a connection state between a terminal portion of the semiconductor device according to the first embodiment and a capacitor.

[0021] The semiconductor device 10 according to the first embodiment can be, for example, a power conversion device used in an inverter for driving a three-phase motor. The semiconductor device 10 for such an application has a function of receiving AC supplied from a power source, rectifying and smoothing the AC to convert it into DC, and then converting the DC back into AC for driving the three-phase motor.

[0022] The semiconductor device 10 has a case 12 that forms a rectangular frame. The case 12 has three circuit housing sections 14, 16, and 18 along its length, and for example, the circuit housing section 14 houses a U-phase drive circuit, the circuit housing section 16 houses a V-phase drive circuit, and the circuit housing section 18 houses a W-phase drive circuit. Note that the U-phase drive circuit, V-phase drive circuit, W-phase drive circuit, control terminals, etc. are not shown in Figure 1.

[0023] Case 12 is formed by insert molding, in which a heated and melted thermoplastic resin is injected into an injection mold into which various terminals for connecting to external circuits have been inserted, and the inserted terminals are integrated with the resin. Examples of thermoplastic resins include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polybutylene succinate (PBS), polyamide (PA), and acrylonitrile butadiene styrene (ABS). Case 12 includes terminals 20, 22, and 24 for connecting large-capacity capacitors for stabilizing the input DC voltage, as well as a U-phase output terminal 32, a V-phase output terminal 34, and a W-phase output terminal 36.

[0024] The terminal section 20 has a first external terminal 20a connected to the positive terminal (P terminal) of the capacitor, an insulating sheet 20b, and a second external terminal 20c connected to the negative terminal (N terminal) of the capacitor. The terminal section 22 has a first external terminal 22a connected to the positive terminal (P terminal) of the capacitor, an insulating sheet 22b, and a second external terminal 22c connected to the negative terminal (N terminal) of the capacitor. The terminal section 24 has a first external terminal 24a connected to the positive terminal (P terminal) of the capacitor, an insulating sheet 24b, and a second external terminal 24c connected to the negative terminal (N terminal) of the capacitor.

[0025] Because the terminal portions 20, 22, and 24 have the same structure, the following description will focus on terminal portion 20. As shown in the cross-sectional view of FIG. 2, terminal portion 20 has a laminated structure in which an insulating sheet 20b is disposed on the front surface (upper surface in the figure) of second external terminal 20c, and a first external terminal 20a is disposed on the front surface of insulating sheet 20b. In terminal portion 20, the outer end (the right end in FIG. 2) of second external terminal 20c is flush with the surface of the outer wall of case 12, and insulating sheet 20b and first external terminal 20a are sequentially shifted inward from the outer end of second external terminal 20c, forming an overall stepped structure. Here, on the front surface of second external terminal 20c of terminal portion 20 where insulating sheet 20b is disposed, a terrace region 20c1 is formed between the outer end and the outer end of insulating sheet 20b. The insulating sheet 20b of the terminal unit 20 defines an insulating region 20b1 between the area where the first external terminal 20a is in contact and the terrace region 20c1 on the front surface where the first external terminal 20a is located. Because the insulating region 20b1 is exposed to the atmosphere, it is necessary to ensure the creepage insulation distance and spatial insulation distance between the terminals, and this must be set in accordance with the product's rated voltage standard. Therefore, the length by which the insulating region 20b1 protrudes from the end of the first external terminal 20a must be longer the higher the potential difference applied between the first external terminal 20a and the second external terminal 20c, thereby ensuring sufficient creepage insulation distance and spatial insulation distance. The front surface of the first external terminal 20a of the terminal unit 20 that protrudes beyond the case 12 defines the exposed region 20a1.

[0026] As shown in Fig. 3, the terminal portion 20 is a terminal electrically connected to the capacitor 38. The capacitor 38 has a first connection terminal 40 extending from the upper surface of the capacitor case, a flexible insulating sheet 42, and a second connection terminal 44. After coming out of the capacitor case, the first connection terminal 40 of the capacitor 38 is bent to the right in the figure and extends parallel to the upper surface of the capacitor case. After coming out of the capacitor case, the second connection terminal 44 is bent to the left in the figure at a position higher than the first connection terminal 40 and extends parallel to the upper surface of the capacitor case.

[0027] Next, an example of connection between the semiconductor device 10 and the capacitor 38 will be described. The first external terminal 20a of the terminal portion 20 of the semiconductor device 10 is joined to the second connection terminal 44 of the capacitor 38 via a flat connecting member 46, and the second external terminal 20c of the terminal portion 20 is directly joined to the first connection terminal 40 of the capacitor 38. Here, the order of joining the capacitor 38 and the terminal portion 20 is as follows: first, the tip of the first connection terminal 40 of the capacitor 38 is placed on the terrace region 20c1 of the second external terminal 20c, and the first connection terminal 40 of the capacitor 38 and the second external terminal 20c of the terminal portion 20 are joined by laser welding at the welding portion 48. Next, the insulating sheet 42 is folded to cover the welding portion 48, and the connecting member 46 is placed so as to span between the upper surface of the second connection terminal 44 of the capacitor 38 and the exposed region 20a1 of the first external terminal 20a. The coupling member 46 and the second connection terminal 44 of the capacitor 38 are joined at a welding portion 50 by laser welding, and the coupling member 46 and the first external terminal 20a of the terminal portion 20 are joined at a welding portion 52 by laser welding.

[0028] As a result, the negative and positive conductors are arranged in parallel between the semiconductor device 10 and the capacitor 38, sandwiching the insulating sheets 20b and 42, and currents flow in opposite directions, thereby reducing the inductance at this connection point.

[0029] Next, the terminal portion 20 of the semiconductor device 10 will be described in detail. 4A and 4B are diagrams showing the configuration of the terminal portion, where (A) is a plan view of the terminal portion and (B) is a bottom view of the terminal portion, FIG. 5 is a cross-sectional view taken along the X2-X2 arrow in FIG. 4A, FIG. 6 is a cross-sectional view taken along the X3-X3 arrow in FIG. 4A, and FIG. 7 is a diagram showing the electric field relaxation effect.

[0030] 4(A) and 4(B), the terminal section 20 of the semiconductor device 10 has a laminated structure in which a first external terminal 20a is disposed on an insulating sheet 20b, and the insulating sheet 20b is disposed on a second external terminal 20c. The first external terminal 20a has an exposed region 20a1 at the center of the outer edge of its front surface, and the insulating sheet 20b has an insulating region 20b1 at the center of the outer edge of its front surface that is not in contact with the first external terminal 20a. The second external terminal 20c has a terrace region 20c1 at the center of the outer edge of its front surface.

[0031] The first external terminal 20a has through holes 20a2 on both sides of an exposed region 20a1 along the edge of the outer end. The insulating sheet 20b has through holes 20b3 in extensions 20b2 extending from the edge of the center of the outer end on both sides of the insulating region 20b1, and has through holes 20b4 near the edge of the inner end that does not overlap with the first external terminal 20a in plan view. The second external terminal 20c has through hole 20c2 at a position that overlaps with through hole 20b3 of the insulating sheet 20b in plan view. These through holes 20a2, 20b3, 20b4, and 20c2 are used to position the first external terminal 20a, insulating sheet 20b, and second external terminal 20c within an injection molding die.

[0032] Here, the first external terminal 20a and the second external terminal 20c are made of copper or a copper alloy, and the first external terminal 20a has a thickness of 0.6 mm or more. It may be 0.8 mm or more and 1.2 mm or less. The insulating sheet 20b is a single sheet or a stack of multiple sheets, and is thinner than the thickness of the first external terminal 20a, with a thickness of 0.05 mm or more. The material of the insulating sheet 20b is one or more selected from the group consisting of aramid fiber, glass fiber, ceramic, polyimide, mica, and composite materials of one or more of these materials.

[0033] The first external terminal 20a of the terminal section 20 has a first end 20a3, a second end 20a4, and a third end 20a5 on three sides surrounding the exposed region 20a1. The first end 20a3 is an end along the outer edge of the first external terminal 20a. The second end 20a4 and the third end 20a5 are end portions of both side edges in a direction perpendicular to the direction in which the exposed region 20a1 of the first external terminal 20a, the insulating region 20b1 of the insulating sheet 20b, and the terrace region 20c1 of the second external terminal 20c are arranged in a plan view.

[0034] As shown in FIG. 5, the back surface 20a6 of the first end 20a3 of the first external terminal 20a is processed. That is, the back surface 20a6 of the first end 20a3 is shaped so that the closer to the tip of the first end 20a3, the closer it is to the front surface than the back surface of the other end portions of the first end 20a3. In the illustrated example, the cross section of the first end 20a3 from the back surface 20a6 to the front surface has an R-chamfered structure with a curvature radius fr_R. An alternative to this R-chamfered structure may be a curved surface formed by press working. Furthermore, the back surface 20a6 of the first end 20a3 may have a C-chamfered structure instead of the R-chamfered structure.

[0035] As shown in FIG. 6 , the second end 20a4 and the third end 20a5 of the first external terminal 20a have their back surfaces 20a7 and 20a8 respectively processed. That is, the back surfaces 20a7 and 20a8 of the second end 20a4 and the third end 20a5 are shaped such that the closer to the tip of the second end 20a4 and the third end 20a5, the closer to the front surface than the back surfaces of the other end portions 20a4 and 20a5. In the illustrated example, the back surfaces 20a7 and 20a8 of the second end 20a4 and the third end 20a5 have an R-chamfered structure with a curvature radius si_R. An alternative to this R-chamfered structure may be a curved surface formed by press processing. Furthermore, the back surfaces 20a7 and 20a8 of the second end 20a4 and the third end 20a5 may have a C-chamfered structure instead of an R-chamfered structure.

[0036] The radius of curvature fr_R of the first end 20a3 of the first external terminal 20a and the radius of curvature si_R of the second end 20a4 and the third end 20a5 of the first external terminal 20a are preferably 0.5 mm or more and 1.0 mm or less, and are set to approximately 40% to 80% of the thickness of the first external terminal 20a. The thickness of the first external terminal 20a is determined appropriately depending on the current capacity of the semiconductor device, and here the thickness of the first external terminal 20a is set to, for example, 1.2 mm.

[0037] By providing the R-chamfered structure to the back surface 20a6 of the first end 20a3 at the outer edge of the first external terminal 20a and the back surfaces 20a7 of the second end 20a4 and 20a8 of the third end 20a5 at both side edges of the first external terminal 20a, respectively, it is possible to alleviate electric field concentration at the first end 20a3, the second end 20a4, and the third end 20a5. That is, as shown in Fig. 7, it can be seen that the electric field intensity is significantly alleviated when the curvature radii fr_R and si_R are set to 60% or more of the plate thickness (1.2 mm) compared to when the R-chamfered structure is not provided.

[0038] Regarding the terminal portion 20 of the semiconductor device 10 according to the first embodiment, the first external terminal 20a has been described as a positive terminal (P terminal) and the second external terminal 20c as a negative terminal (N terminal), but the first external terminal 20a may be a negative terminal (N terminal) and the second external terminal 20c may be a positive terminal (P terminal).

[0039] [Second embodiment] 8A and 8B are diagrams showing the configuration of the terminal portion of a semiconductor device according to the second embodiment, in which (A) is a plan view of the terminal portion and (B) is a bottom view of the terminal portion, FIG. 9 is an enlarged view of part A in FIG. 8B, FIG. 10 is a diagram showing the state of resin sealing of the terminal portion by a case, and FIG. 11 is a diagram showing the electric field relaxation effect.

[0040] 8(A) and 8(B), the terminal portion 60 of the semiconductor device according to the second embodiment has a layered structure in which a first external terminal 60a, an insulating sheet 60b, and a second external terminal 60c are arranged in a stepped manner. Although not shown, the first external terminal 60a has a rounded chamfered structure on the back surfaces of the first end portion 60a1, the second end portion 60a2, and the third end portion 60a3, similar to the terminal portion 20 of the semiconductor device according to the first embodiment.

[0041] In the first external terminal 60a of the terminal portion 60, the front side of the second end 60a2 and the front side of the third end 60a3 overlap with the ends 60c1 and 60c2 of the second external terminal 60c in a plan view. The second end 60a2 and the third end 60a3 of the first external terminal 60a overlap with the ends 60c1 and 60c2 of the second external terminal 60c in a plan view. This allows the cross-sectional area of ​​each external terminal to be increased within a limited width, thereby reducing the inductance of the first external terminal 60a and the second external terminal 60c and reducing power loss. The first external terminal 60a has a corner 60a4 formed by the first end 60a1 and the second end 60a2 and a corner 60a5 formed by the first end 60a1 and the third end 60a3. The second external terminal 60c has a notch 60c3 at the position of the end 60c1 facing the corner 60a4 of the first external terminal 60a, and a notch 60c4 at the position of the end 60c2 facing the corner 60a5 of the first external terminal 60a.

[0042] The notches 60c3 and 60c4 have symmetrical shapes, so only the notch 60c3 will be described here. As shown in FIG. 9 , the notch 60c3 has an arc shape with a curvature radius ar_R centered at a position facing the corner 60a4 of the first external terminal 60a in a plan view. The corner 60c5 formed by the notch 60c3 of the second external terminal 60c and the end 60c1 of the second external terminal 60c is rounded into an arc shape by a fillet 60c6 with a curvature radius fi_R. By providing the notch 60c3 at the end 60c1 of the second external terminal 60c facing the corner 60a4 of the first external terminal 60a, the creepage distance between the corner 60a4 of the first external terminal 60a and the end 60c1 of the second external terminal 60c can be extended. Similarly, by providing a notch 60c4 in the end 60c2 of the second external terminal 60c that faces the corner 60a5 of the first external terminal 60a, the creepage distance between the corner 60a5 of the first external terminal 60a and the end 60c2 of the second external terminal 60c can be extended.

[0043] The radius of curvature ar_R of the cutout 60c3 is not less than 0.5 mm and not more than 1.5 mm, and the radius of curvature fi_R of the fillet 60c6 is not less than 0.5 mm and not more than 1.5 mm. The cutout 60c3 and the fillet 60c6 of the second external terminal 60c are formed by press working.

[0044] 10, the terminal portion 60 has a second end 60a2 and a third end 60a3 of the first external terminal 60a, a portion of the insulating sheet 60b, and ends 60c1 and 60c2 of the second external terminal 60c sealed with the resin of the case 12. In the illustrated example, the second end 60a2 of the first external terminal 60a and the end 60c1 of the second external terminal 60c are located approximately 1.5 mm inward from the edge 12a of the case 12, and are sealed with resin, including the notched portion 60c3 of the second external terminal 60c and the corner 60a4 of the first external terminal 60a. In addition, the third end 60a3 of the first external terminal 60a and the end 60c2 of the second external terminal 60c are located approximately 1.5 mm inside the edge 12b of the case 12, and are sealed with resin, including the notch 60c4 of the second external terminal 60c and the corner 60a5 of the first external terminal 60a.

[0045] The terminal portion 60 has rounded chamfered back surfaces of the first end 60a1, the second end 60a2, and the third end 60a3 of the first external terminal 60a. In addition, notches 60c3 and 60c4 are provided at the ends 60c1 and 60c2 of the second external terminal 60c, which face the corners 60a4 and 60a5 of the first external terminal 60a. This configuration allows for sufficient reduction in electric field strength, even when the rounded chamfered structure of the first external terminal 60a alone is insufficient. Specifically, as shown in FIG. 11 , even when the curvature radii fr_R and si_R of the rounded chamfers are 0.5 mm, the electric field strength can be reduced by increasing the curvature radii ar_R of the cutouts 60c3 and 60c4 and the curvature radius fi_R of the fillet 60c6.

[0046] In the terminal section 60 of the semiconductor device according to the second embodiment, the first external terminal 60a has been described as a positive terminal (P terminal) and the second external terminal 60c as a negative terminal (N terminal), but the first external terminal 60a may be a negative terminal (N terminal) and the second external terminal 60c may be a positive terminal (P terminal). This is because when the polarities of the first external terminal 60a and the second external terminal 60c were switched and the effect of electric field relaxation was confirmed, no difference was found due to the polarity. [Explanation of symbols]

[0047] 10 Semiconductor device 12 cases 12a,12b Edge 14, 16, 18 Circuit storage section 20 Terminal section 20a First external terminal 20a1 exposed area 20a2 through hole 20a3 1st end 20a4 Second end 20a5 3rd end 20a6,20a7,20a8 Back side 20b Insulation sheet 20b1 Insulation area 20b2 Extension 20b3,20b4 through hole 20c 2nd external terminal 20c1 Terrace area 20c2 through hole 22 Terminal section 22a 1st external terminal 22b Insulation sheet 22c 2nd external terminal 24 Terminal section 24a 1st external terminal 24b Insulation sheet 24c 2nd external terminal 32 U phase output terminal 34 V phase output terminal 36 W-phase output terminal 38 Capacitor 40 First connection terminal 42 Insulation sheet 44 Second connection terminal 46 Connecting member 48, 50, 52 Welding parts 60 Terminal section 60a First external terminal 60a1 First end 60a2 2nd end 60a3 Third end 60a4,60a5 corners 60b Insulation sheet 60c 2nd external terminal 60c1,60c2 end 60c3,60c4 notch 60c5 Corner 60c6 fillet

Claims

1. a first external terminal having an end portion including a first end portion; a second external terminal having a terrace region on a part of a front surface thereof, the part of the front surface excluding the terrace region being disposed opposite the back surface of the first external terminal; an insulating sheet disposed between the first external terminal and the second external terminal and adjacent to the terrace region of the second external terminal; The front surface of the first external terminal is flat, the rear surface of the end of the first external terminal is farther from the second external terminal as it approaches the tip of the end, the first external terminal has a second end portion and a third end portion which are the end portions of both sides in a direction perpendicular to a direction in which the terrace region of the second external terminal and the first external terminal are arranged in a plan view, and a back surface of the second end portion and a back surface of the third end portion are farther from the second external terminal as they approach the tip of the end portion; a side of a front surface of the second end portion of the first external terminal and a side of a front surface of the third end portion of the first external terminal overlap with an end portion of the second external terminal in a plan view; the second external terminal has notches at the end of the second external terminal at positions facing corners formed by the first end, the second end, and the third end of the first external terminal in a plan view, Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the insulating sheet has an insulating region that is not in contact with the first external terminal between the first end and the terrace region of the second external terminal in a plan view.

3. 3. The semiconductor device according to claim 1, wherein a cross section of the end of the first external terminal from the back surface to the front surface has an R-chamfered structure, and a radius of curvature of the R-chamfered structure is 60% or more and 80% or less of a thickness of the first external terminal.

4. The semiconductor device according to claim 1 , wherein the first external terminal has a thickness of 0.6 mm or more and 1.2 mm or less.

5. 4. The semiconductor device according to claim 3, wherein the radius of curvature of the R-chamfered structure of the first external terminal is not less than 0.5 mm and not more than 1.0 mm.

6. The semiconductor device according to claim 1 , wherein the notch of the second external terminal is sealed with a resin.

7. 2. The semiconductor device according to claim 1, wherein the notch of the second external terminal is semicircular with a radius of curvature of 0.5 mm or more and 1.5 mm or less in plan view.

8. 8. The semiconductor device according to claim 7, wherein a corner formed by the notch of the second external terminal and the end of the second external terminal has a fillet arc shape with a curvature radius of 0.5 mm or more and 1.5 mm or less in a plan view.

9. 2. The semiconductor device according to claim 1, wherein a portion of said second external terminal, a portion of said insulating sheet, said second end portion and said third end portion of said first external terminal are sealed with resin.

10. The semiconductor device according to claim 1 , wherein the insulating sheet has a thickness smaller than that of the first external terminal.

11. The insulating sheet is a single sheet or a stack of multiple sheets, 11. The semiconductor device according to claim 10, wherein the material of the insulating sheet is at least one selected from the group consisting of aramid fiber, glass fiber, ceramic, polyimide, mica, and composite materials of at least one of these materials.

12. 2. The semiconductor device according to claim 1, wherein the first external terminal is a negative electrode and the second external terminal is a positive electrode, or the first external terminal is a positive electrode and the second external terminal is a negative electrode.

13. preparing a first external terminal having a front surface and a back surface, the front surface being flat, and the back surface of an end portion being closer to the front surface than the back surface of a portion other than the end portion as the back surface approaches a tip; providing an insulating sheet; preparing a second external terminal having a terrace region on a portion of a front surface thereof; disposing the insulating sheet on the second external terminal adjacent to the terrace region; a step of arranging the first external terminal so that a back surface of the first external terminal faces a partial region of a front surface of the second external terminal excluding the terrace region, via the insulating sheet; Equipped with the first external terminal has a first end portion which is one of the end portions, and a second end portion and a third end portion which are the end portions on both sides opposite to each other with the first end portion interposed therebetween; the insulating sheet has an insulating region that is not in contact with the first external terminal in a plan view, the step of preparing the first external terminal includes a step of forming a back surface of the second end portion and a back surface of the third end portion so that the back surfaces of the second end portion and the third end portion are closer to the front surface side than the back surfaces of the portions other than the second end portion and the third end portion as they approach the tips of the second end portion and the third end portion; the step of arranging the first external terminal is a step of overlapping an edge of a front surface of the second end portion of the first external terminal and an edge of a front surface of the third end portion of the first external terminal with an end portion of the second external terminal in a plan view; A method for manufacturing a semiconductor device.

14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein said step of preparing said first external terminals includes the step of forming rear surfaces of said end portions of said first external terminals by press working.

15. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the step of preparing the second external terminal includes a step of forming notches in the ends of the second external terminal at positions where the second external terminal faces a corner formed by the first end, the second end, and the third end of the first external terminal in a planar view.

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