Electrostatic discharge protection structure, semiconductor power device, and method for manufacturing the same

Abstract

To provide a trench-type semiconductor power device having an electrostatic discharge protection structure, and a method for manufacturing the same.SOLUTION: An electrostatic discharge protection structure 150 in a semiconductor device includes a first trench structure TR2 including a first polysilicon structure 144, and a first oxide layer 143 surrounding the first polysilicon structure. A second trench structure TR3 includes a second polysilicon structure 146, and a second oxide layer 145 surrounding the second polysilicon structure. A first diode string 151 is disposed between the first trench structure and the second trench structure and adjoins the first polysilicon structure and the second polysilicon structure. A first spacing oxide layer SX1 is disposed on the first diode string. A second diode string 156 is disposed on the first spacing oxide layer and connected in parallel with the first diode string.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001]

[0001] Cross - reference to Related Applications This patent application claims the priority of Chinese Patent Application No. 202410126085.1, entitled "ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE, SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR POWER DEVICE", filed on January 30, 2024, and this Chinese patent application is incorporated herein by reference as if the entire disclosure were set forth herein.

[0002]

[0002] The present disclosure relates generally to the field of semiconductor devices, and more particularly, to techniques and mechanisms for an electrostatic discharge protection structure, a semiconductor power device, and a manufacturing method of a semiconductor power device. Certain embodiments provide a trench - type semiconductor power device having an electrostatic discharge protection structure and a manufacturing method thereof.

Background Art

[0003]

[0003] Semiconductor power devices are widely used in the field of electronics. A trench power device that grows a gate oxide layer on the sidewall of a gate trench and fills it with polysilicon to form a gate is one of the most common power - switching devices. The trench power device can improve the utilization efficiency of the device area, and thus can achieve a greater current conduction capacity by obtaining a larger device unit channel width per unit area.

[0004]

[0004] Semiconductor power devices are susceptible to voltage spikes caused by electrostatic discharge (ESD) events. The instantaneous large currents and high voltages caused by ESD events can cause dielectric breakdown of the gate oxide layer of trench power devices, leading to damage, burnout, or high leakage. Therefore, semiconductor power devices need to have ESD protection. [Overview of the project]

[0005]

[0005] Technical advantages are generally achieved by embodiments of the present disclosure describing electrostatic discharge protection structures, semiconductor power devices, and methods for manufacturing semiconductor power devices.

[0006]

[0006] Embodiments of the present disclosure relate to electrostatic discharge protection structures. The electrostatic discharge protection structure includes a first trench structure, a second trench structure, a first diode array, a first spacer oxide layer, and a second diode array. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. The first diode array is adjacent to the first and second polysilicon structures and is arranged between the first and second trench structures. The first spacer oxide layer is arranged on the first diode array. The second diode array is arranged on the first spacer oxide layer and is arranged in parallel with the first diode array.

[0007]

[0007] Embodiments of the present disclosure relate to semiconductor power devices. The semiconductor power device includes a substrate, a low-density doped layer, a first trench structure, a source-doped region, an interlayer dielectric layer, a source electrode, a gate electrode, and an electrostatic discharge protection structure. The low-density doped layer is located on the substrate. The first trench structure is located within the low-density doped layer and extends toward the substrate. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The source-doped region is located within the low-density doped layer and is separated from the substrate. The interlayer dielectric layer is located on the low-density doped layer. The source electrode is connected to the source-doped region. The gate electrode is connected to the first polysilicon structure. The electrostatic discharge protection structure is located within the interlayer dielectric layer and includes a first diode array, a second diode array, and a first spacer oxide layer. The second diode array is located on the first diode array. The first spacer oxide layer is placed between the first diode array and the second diode array. The first and second diode arrays are arranged in parallel between the source electrode and the gate electrode.

[0008]

[0008] Embodiments of the present disclosure relate to a method for manufacturing a semiconductor power device. This manufacturing method includes: forming a low-concentration doped layer on a substrate; forming a first opening, a second opening, and a third opening extending toward the substrate on the low-concentration doped layer; forming a first diode array on the second and third openings; forming a first spacer oxide layer on the first diode array, surrounding the first diode array; forming a second diode array on the first spacer oxide layer; forming a first trench structure within the first opening, including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source-doped region within the low-concentration doped layer, located between the first trench structure and the second opening; and forming a source electrode connected to the source-doped region and a gate electrode connected to the first polysilicon structure. The first and second diode arrays are arranged in parallel between the source electrode and the gate electrode.

[0009]

[0009] According to one aspect of the present disclosure, an electrostatic discharge protection structure for use in a semiconductor device is provided. The electrostatic discharge protection structure includes: a first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a second trench structure comprising a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; a first diode array disposed between the first trench structure and the second trench structure and adjacent to the first polysilicon structure and the second polysilicon structure; a first spacer oxide layer disposed on the first diode array; and a second diode array disposed on the first spacer oxide layer, wherein the second diode array and the first diode array are connected in parallel.

[0010]

[0010] According to another aspect of the present disclosure, a semiconductor power device is provided comprising: a low-doping layer disposed on a substrate; a first trench structure disposed within the low-doping layer and extending toward the substrate, comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; an interlayer dielectric layer disposed on the low-doping layer; a source electrode connected to a source-doped region disposed within the low-doping layer; a gate electrode connected to the first polysilicon structure; and an electrostatic discharge protection structure disposed within the interlayer dielectric layer. The electrostatic discharge protection structure comprises: a first diode array; a second diode array disposed above the first diode array and connected in parallel with the first diode array between the source electrode and the gate electrode; and a first spacer oxide layer disposed between the first diode array and the second diode array.

[0011]

[0011] Another aspect of the present disclosure provides a method for manufacturing a semiconductor power device, the method comprising: forming a low-density doped layer on a substrate; forming a first opening, a second opening, and a third opening extending toward the substrate on the low-density doped layer; forming a first diode array above the second and third openings; forming a first spacer oxide layer on the first diode array surrounding the first diode array; forming a second diode array on the first spacer oxide layer; forming a first trench structure within the first opening, comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source-doped region within the low-density doped layer, located between the first trench structure and the second opening; forming a source electrode connected to the source-doped region; and forming a gate electrode connected to the first polysilicon structure, wherein the first and second diode arrays are connected in parallel between the source electrode and the gate electrode.

[0012]

[0012] The above provides a fairly broad overview of the features and technical advantages of the Disclosure in order to better understand the detailed description of the Disclosure below. Further features and advantages of the Disclosure that form the subject matter of the claims of the Disclosure are described below. Those skilled in the art will understand that the concepts and specific embodiments disclosed can be readily used as a basis for modifying or designing other structures or processes to accomplish the same purpose as the Disclosure. They will also understand that such equivalent configurations will not deviate from the spirit and scope of the Disclosure as set out in the appended claims.

[0013]

[0013] Some embodiments of the present disclosure can be best understood by considering the following detailed description in conjunction with the accompanying drawings. Note that various structures may not be drawn to scale. In fact, the dimensions of various structures may be enlarged or reduced as appropriate for clarity in the description.

[0014]

[0014] Herein, for a more complete understanding of the present disclosure and its advantages, the following description is to be referenced together with the accompanying drawings. [Brief explanation of the drawing]

[0015] [Figure 1] This is a schematic diagram of an exemplary semiconductor power device according to an embodiment of the present disclosure. [Figure 2] This is a schematic diagram of an exemplary semiconductor power device according to an embodiment of the present disclosure. [Figure 3A] This is a schematic diagram illustrating an exemplary electrostatic discharge protection structure according to an embodiment of the present disclosure. [Figure 3B] This is a circuit diagram of an electrostatic discharge protection structure according to an embodiment of the present disclosure. [Figure 4] This is a flowchart of a method for manufacturing a semiconductor power device according to an embodiment of the present disclosure. [Figure 5] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 6] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 7] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 8] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 9] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 10] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 11] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 12] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 13] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 14] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 15] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 16] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 17] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 18] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 19] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 20] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [[ID=2,2]] [Figure 21] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 22] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 23] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 24] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 25] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 26] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 27] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 28] A schematic diagram showing an exemplary semiconductor power device during manufacturing according to an embodiment of the present disclosure. [Figure 29]This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 30] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 31] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 32] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 33] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 34] This is a schematic diagram showing an exemplary semiconductor power device under manufacture according to an embodiment of the present disclosure. [Figure 35] This is a schematic diagram of another exemplary semiconductor power device according to an embodiment of the present disclosure. [Figure 36] A schematic diagram of yet another exemplary semiconductor power device according to an embodiment of the present disclosure, and an enlarged view of a portion thereof. [Modes for carrying out the invention]

[0016]

[0023] Identical or similar components are indicated by the same reference numerals in the drawings and detailed description. Several embodiments of this disclosure will be readily apparent from the following detailed description in conjunction with the accompanying drawings.

[0017]

[0024] Corresponding numbers and symbols in different figures generally refer to the corresponding parts unless otherwise specified. The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to a fixed scale.

[0018]

[0025] The fabrication and use of embodiments of this disclosure will be described in detail below. However, it should be understood that the concepts disclosed herein can be embodied in a wide variety of specific circumstances, and that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0019]

[0026] Furthermore, one or more features from one or more of the embodiments described below can be combined to produce alternative embodiments not explicitly described, and features suitable for such combinations are understood to be within the scope of this disclosure. Accordingly, the appended claims are intended to encompass any such modifications or embodiments.

[0020]

[0027] This disclosure describes embodiments in specific situations, namely electrostatic discharge protection structures, semiconductor power devices, and methods for manufacturing semiconductor power devices. However, this disclosure may be applied to various semiconductor devices. Various embodiments are described below in detail with reference to the accompanying drawings.

[0021]

[0028] The following disclosure provides numerous different embodiments or examples for implementing the different features provided. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on top of a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that they do not have to be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations described.

[0022]

[0029] The following is a detailed description of embodiments of the present disclosure. However, it should be understood that the present disclosure provides a number of applicable concepts that can be embodied in a variety of specific environments. The specific embodiments described are illustrative and do not limit the scope of the present disclosure.

[0023]

[0030] This disclosure provides an electrostatic discharge protection structure. This electrostatic discharge protection structure uses a stacked design, and therefore multiple diode arrays for discharging instantaneous large currents can be arranged in parallel with each other according to the stacked structure, which does not occupy additional circuit area (footprint) and also increases the amount of conductive current for electrostatic discharge. Compared with general electrostatic discharge protection structures, the electrostatic discharge protection structure of this disclosure can have more diode arrays on the same circuit area for discharging instantaneous large currents, thereby enabling greater electrostatic discharge protection capability.

[0024]

[0031] Furthermore, this disclosure provides a semiconductor power device and a method for manufacturing the same. This semiconductor power device includes the electrostatic discharge protection structure described above and, compared to general semiconductor power devices, can accommodate more diode arrays on the same circuit area to dissipate instantaneous large currents, and has greater electrostatic discharge protection capability.

[0025]

[0032] Figure 1 is a schematic diagram of a semiconductor power device 1 according to several embodiments of the present disclosure. The semiconductor power device 1 includes a power transistor, a gate resistor RG, and an electrostatic discharge protection structure 150, having a gate electrode G, a drain electrode D, and a source electrode S (sometimes referred to as the gate terminal G, drain terminal D, and source terminal S, respectively). In some embodiments, the power transistor may be a vertical power transistor 10. The power transistor 10 may be various types of semiconductor power devices or may be manufactured by different techniques. The source and drain of the power transistor 10 are connected to the source electrode S and the drain electrode D, respectively. The gate of the power transistor 10 is connected to the gate electrode G via the gate resistor RG. The electrostatic discharge protection structure 150 is connected between the gate electrode G and the source electrode S.

[0026]

[0033] In the embodiment shown in Figure 1, the power transistor 10 is an N-type transistor. However, the disclosure is not limited thereto, and in other embodiments, the power transistor 10 may be a P-type transistor.

[0027]

[0034] In some embodiments, the electrostatic discharge protection structure 150 includes multiple diode arrays connected in parallel between the gate electrode G and the source electrode S. Each diode array includes multiple back-to-back diodes connected in series. In some embodiments, each diode array has the same configuration.

[0028]

[0035] In the embodiment shown in Figure 1, the electrostatic discharge protection structure 150 may include diode arrays 151 and 156, each of which may include two back-to-back diodes. The disclosure uses the number of diode arrays and back-to-back diodes shown in Figure 1 for illustrative purposes only, but the disclosure is not limited thereto, and various numbers of diode arrays and back-to-back diodes may be included in the electrostatic discharge protection structure 150, and these are also within the scope of the disclosure.

[0029]

[0036] The number of back-to-back diodes in a single diode array determines the withstand voltage of the electrostatic discharge protection structure 150, and the number of diode arrays connected in parallel determines the amount of conductive current of the electrostatic discharge protection structure 150. The electrostatic discharge protection structure 150 can be considered as a current path, the number of back-to-back diodes in a single diode array can determine the conduction voltage threshold, and the number of diode arrays connected in parallel can determine the width of the current path.

[0030]

[0037] In some embodiments, the number of back-to-back diodes may be determined by the withstand voltage of the semiconductor power device 1, such as the dielectric breakdown voltage of the gate oxide layer of the power transistor 10. More specifically, in the event of an electrostatic discharge event, the gate resistor RG can prevent the instantaneous large current generated by the electrostatic discharge event from the gate electrode G from directly attacking the gate of the power transistor 10 (e.g., the gate oxide), and can allow the instantaneous large current to flow away from the power transistor 10 to the source electrode S via the electrostatic discharge protection structure 150. In some embodiments, the source electrode S may be connected to a ground terminal, and thus the instantaneous large current caused by the electrostatic discharge event can flow to the ground terminal through the electrostatic discharge protection structure 150. In other words, in the event of an electrostatic discharge event, the gate resistor RG and the electrostatic discharge protection structure 150 can provide electrostatic discharge protection to the power transistor 10. However, for the electrostatic discharge protection structure 150 to function, it is necessary to satisfy the condition that the withstand voltage of the electrostatic discharge protection structure 150 is lower than the dielectric breakdown voltage of the gate oxide layer of the power transistor 10. If the voltage caused by a sudden large current reaches the withstand voltage of the electrostatic discharge protection structure 150 first, the electrostatic discharge protection structure 150 can be turned on, preventing current from flowing to the gate of the power transistor 10. Therefore, the number of back-to-back diodes in each diode array is limited by the dielectric breakdown voltage of the gate oxide layer of the power transistor 10.

[0031]

[0038] Figure 2 is a schematic diagram of a semiconductor power device 1 according to several embodiments of the present disclosure. The semiconductor power device 1 includes a substrate 100, a low-concentration doped layer 110, and an interlayer dielectric layer 130. The low-concentration doped layer 110 is disposed on the substrate 100, and the interlayer dielectric layer 130 is disposed on the low-concentration doped layer 110.

[0032]

[0039] In some embodiments, the substrate 100 may be positioned adjacent to the upper surface of a silicon wafer or other semiconductor material substrate. In some embodiments, the substrate 100 is a portion of a silicon wafer. The material of the substrate 100 may include single-crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphate (GaAsP), or other semiconductor materials. In some embodiments, the doping concentration of the substrate 100 may be higher than the doping concentration of the low-concentration doped region 110.

[0033]

[0040] In some embodiments, the low-doping layer 110 may include, for example, single-crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphate (GaAsP), or other semiconductor material, which may be N-type or P-type. In some embodiments, the low-doping layer 110 is an N-type (first conductivity type) epitaxial material. For ease of explanation, N-type is used as an example for the low-doping layer 110 and the power transistor 10, but the disclosure is not limited thereto. Whether the low-doping layer 110 is N-type (first conductivity type) or P-type (second conductivity type) may be adjusted according to the conductivity type of the power transistor 10.

[0034]

[0041] The semiconductor power device 1 further includes a plurality of trench structures TR1, trench structures TR2, trench structures TR3, and an electrostatic discharge protection structure 150. The plurality of trench structures TR1, TR2, and TR3 are arranged within a low-concentration doped layer 110 and extend toward the substrate 100 without contact with the substrate 100. Each trench structure may have side walls and a bottom surface. In some embodiments, each trench structure may have vertical side walls and an arc-shaped bottom surface. The electrostatic discharge protection structure 150 is arranged within an interlayer dielectric layer 130.

[0035]

[0042] Each trench structure TR1 includes a polysilicon structure 142 and an oxide layer 141 surrounding the polysilicon structure 142. Trench structure TR2 includes a polysilicon structure 144 and an oxide layer 143 surrounding the polysilicon structure 144. Trench structure TR3 includes a polysilicon structure 146 and an oxide layer 145 surrounding the polysilicon structure 146. In some embodiments, multiple trench structures TR1 may be part of the gate structure of the power transistor 10, and the oxide layer 141 within the trench structure TR1 is the gate oxide layer of the power transistor 10. In some embodiments, trench structures TR2 and TR3 may be part of an electrostatic discharge protection structure 150. Figure 2 shows two trench structures TR1 within the semiconductor power device 1, but there may be three or more trench structures TR1.

[0036]

[0043] The semiconductor power device 1 may further include a plurality of body-doped regions 121, a plurality of source-doped regions 122, a plurality of high-concentration doped regions 123, a drain-doped region 124, a high-concentration doped region 125, a plurality of conductive plugs CP1, and a conductive plug CP2. The body-doped regions 121, source-doped regions 122, high-concentration doped regions 123, drain-doped regions 124, and high-concentration doped regions 125 are arranged within a low-concentration doped layer 110. One of the body-doped regions 121 may be located between two adjacent trench structures TR1 and adjacent to the oxide layer 141 of the two adjacent trench structures TR1. Another body-doped region 121 may be located between a trench structure TR2 and an adjacent trench structure TR1 to trench structure TR2 and adjacent to the oxide layer 141 of trench structure TR1 and the oxide layer 143 of trench structure TR2. One of the source-doped regions 122 may be located between two adjacent trench structures TR1 and on the corresponding body-doped region 121. Another source-doped region 122 may be located between trench structure TR2 and the adjacent trench structure TR1 and on the corresponding body-doped region 121. In some embodiments, the thickness of the source-doped region 122 may be less than the thickness of the body-doped region 121. The source-doped region 122 may be adjacent to the body-doped region 121, the oxide layer 141, and / or the oxide layer 143. The drain-doped region 124 may be separated from trench structures TR1, TR2, and TR3.

[0037]

[0044] Multiple high-concentration doped regions 123 may be located within multiple body-doped regions 121. In some embodiments, the high-concentration doped regions 123 do not need to be adjacent to source-doped regions 122. The high-concentration doped region 125 may be located within a low-concentration doped layer 110 below the drain-doped region 124 and does not need to be adjacent to the drain-doped region 124. Multiple conductive plugs CP1 may extend through the interlayer dielectric layer 130, further extend through each of the multiple source-doped regions 122, and extend into the high-concentration doped regions 123 within the multiple body-doped regions 121. Conductive plugs CP2 may extend through the interlayer dielectric layer 130 and the drain-doped region 124 and reach the high-concentration doped region 125. The configuration of each conductive plug may vary depending on process or electrical requirements. The material of the conductive plug may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, conductive plug CP1 and conductive plug CP2 may have substantially the same length. In some embodiments, conductive plug CP1 and conductive plug CP2 may have a configuration that is wider at the top and narrower at the bottom.

[0038]

[0045] The semiconductor power device 1 may further include metal wires 161, 162, and 163 disposed on the interlayer dielectric layer 130. Metal wire 161 may be electrically connected to a source-doped region 122 via a conductive plug CP1 and to a source electrode S via an interconnection structure (not shown). Metal wire 162 may be electrically connected to a polysilicon structure 142 in a trench structure TR1 and to a gate electrode G via an interconnection structure. Metal wire 163 may be electrically connected to a drain-doped region 124 via a conductive plug CP2 and to a drain electrode D via an interconnection structure. An electrostatic discharge protection structure 150 may be connected between metal wires 161 and 162. In other words, the electrostatic discharge protection structure 150 is connected between the source electrode S and the gate electrode G.

[0039]

[0046] In some embodiments, the width of metal wire 161 may be greater than the widths of metal wires 162 and 163. The materials of metal wires 161, 162, and 163 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. In some embodiments, metal wires 161, 162, and 163 may be the metal layer closest to the low-concentration doped layer 110 (e.g., the M1 layer).

[0040]

[0047] To facilitate explanation and keep the diagrams simple, please refer to Figures 3A and 3B for symbols and details of the electrostatic discharge protection structure 150. Figure 3A is a schematic diagram of the electrostatic discharge protection structure 150 in Figure 2. Figure 3B is a circuit diagram of the electrostatic discharge protection structure 150 in Figure 2.

[0041]

[0048] The electrostatic discharge protection structure 150 may include a trench structure TR2, a trench structure TR3, a diode array 151, a diode array 156, a spacer oxide layer SX1, a spacer oxide layer SX2, a conductive plug CP3, and a conductive plug CP4. Trench structures TR2 and TR3 are arranged within a low-concentration doped layer 110. Diode array 151 is connected between trench structures TR2 and TR3 and is arranged on the low-concentration doped layer 110. Diode array 156 is arranged on diode array 151 and is electrically insulated from each other by spacer oxide layer SX1. Spacer oxide layer SX2 is arranged on diode array 156 and surrounds diode array 156.

[0042]

[0049] Conductive plugs CP3 and CP4 are electrically connected to the source electrode S and gate electrode G via metal wires 161 and 162, respectively. Diode arrays 151 and 156 are connected in parallel between conductive plugs CP3 and CP4. In other words, diode arrays 151 and 156 are connected in parallel between the source electrode S and gate electrode G.

[0043]

[0050] Trench structure TR2 includes a polysilicon structure 144 and an oxide layer 143 surrounding the polysilicon structure 144. Trench structure TR3 includes a polysilicon structure 146 and an oxide layer 145 surrounding the polysilicon structure 146. As shown in Figures 2 and 3A, the oxide layers 143 and 145 extend along the low-concentration doped layer 110 and are adjacent to each other. In some embodiments, the oxide layers 143 and 145 may be a single continuous structure.

[0044]

[0051] The diode array 151 includes multiple doped regions 151a and multiple doped regions 151b arranged alternately. The doped regions 151a and 151b are of different conductivity types. The following description uses, as an example, the number of doped regions as shown in Figures 2 and 3A, based on doped regions 151a being N-type and doped regions 151b being P-type, but this is not intended to limit the disclosure.

[0045]

[0052] In some embodiments, the diode array 151 includes three N-type doped regions 151a and two P-type doped regions 151b. Doped region 151a includes doped region 151a1, doped region 151a2, and doped region 151a3, and doped region 151b includes doped region 151b1 and doped region 151b2. Doped regions 151a1, 151b1, 151a2, 151b2, and 151a3 may be arranged in order, and doped regions 151a1 and 151a3 may function as the first and second ends of the diode array 151, respectively. The first end of the diode array 151 is connected to the source electrode S and may be adjacent to the polysilicon structure 144 of the trench structure TR2. In some embodiments, the doped region 151a1 and the polysilicon structure 144 may be a single continuous structure. The second end of the diode array 151 may be connected to the gate electrode G and adjacent to the polysilicon structure 146 of the trench structure TR3. In some embodiments, the doped region 151a3 and the polysilicon structure 146 may be a single continuous structure.

[0046]

[0053] In diode array 151, two adjacent doped regions have different conductivity types, and therefore a PN junction is formed at the interface of the adjacent doped regions. As shown in Figure 3B, diode array 151 includes four interfaces of adjacent doped regions, namely the interface between adjacent doped regions 151a1 and 151b1, the interface between adjacent doped regions 151b1 and 151a2, the interface between adjacent doped regions 151a2 and 151b2, and the interface between adjacent doped regions 151b2 and 151a3, thus forming four PN junctions. Because the different conductivity types are arranged alternately, these four PN junctions form two back-to-back diodes connected in series.

[0047]

[0054] In some embodiments, diode arrays 151 and 156 have the same number and type of doped regions. In some embodiments, diode arrays 151 and 156 have the same structure.

[0048]

[0055] In some embodiments, the diode array 156 includes three N-type doped regions 156a and two P-type doped regions 156b. Doped region 156a includes doped region 156a1, doped region 156a2, and doped region 156a3, and doped region 156b includes doped region 156b1 and doped region 156b2. Doped regions 156a1, 156b1, 156a2, 156b2, and 156a3 may be arranged in order, and doped regions 156a1 and 156a3 may function as the first and second ends of the diode array 156, respectively. The first end of the diode array 156 is connected to the source electrode S, and the second end of the diode array 156 is connected to the gate electrode G. The diode array 156 forms four PN junctions by including four interfaces of adjacent doped regions. The four PN junctions form two back-to-back diodes connected in series.

[0049]

[0056] The spacer oxide layer SX1 is positioned on and surrounding the diode array 151. As shown in Figure 2, the spacer oxide layer SX1 may further extend onto the surface of the low-concentration doped layer 110, covering the source-doped region 122, the drain-doped region 124, and the trench structure TR1. Conductive plugs CP1 and CP2 extend further through the spacer oxide layer SX1. The spacer oxide layer SX2 is positioned on and surrounding the diode array 156. The spacer oxide layer SX2 may be adjacent to the spacer oxide layer SX1 along the side of the diode array 156. The diode arrays 151 and 156 may be separated from the interlayer dielectric layer 130 by the spacer oxide layers SX1 and SX2.

[0050]

[0057] The electrostatic discharge protection structure 150 may further include a high-concentration doped region 147 and a high-concentration doped region 148. The high-concentration doped region 147 may be located within doped region 151a1, and the high-concentration doped region 148 may be located within doped region 151a3. Conductive plug CP3 extends through the spacer oxide layer SX2, doped region 156a1, and spacer oxide layer SX1 to the high-concentration doped region 147 within doped region 151a1, connecting the source electrode S to doped region 151a1 and doped region 156a1. Conductive plug CP4 extends through the spacer oxide layer SX2, doped region 156a3, and spacer oxide layer SX1 to the high-concentration doped region 148 within doped region 151a3, connecting the gate electrode G to doped region 151a3 and doped region 156a3.

[0051]

[0058] The end of conductive plug CP3 is in contact with the high-concentration doped region 147. The width of the high-concentration doped region 147 may be greater than the width of the end of conductive plug CP3, and therefore the high-concentration doped region 147 may surround the end of conductive plug CP3. The end of conductive plug CP4 is in contact with the high-concentration doped region 148. The width of the high-concentration doped region 148 may be greater than the width of the end of conductive plug CP4, and therefore the high-concentration doped region 148 may surround the end of conductive plug CP4.

[0052]

[0059] In the case of certain electrostatic discharge protection structures in the prior art, the current that can turn on the electrostatic discharge protection structure at a preset fixed withstand voltage is limited by the available circuit area. Furthermore, multiple diodes in the electrostatic discharge protection structure are usually arranged on the same plane. In contrast, embodiments of the present disclosure make better use of three-dimensional space to provide multiple diodes within the electrostatic discharge protection structure 150. The diodes are arranged in stacks or layers within the available circuit area, and spacer oxide layers SX1 are used to separate diode rows of different layers. Therefore, for the same circuit area, the electrostatic discharge protection structure 150 provided in embodiments of the present disclosure has a higher density of diodes. Furthermore, by using parallel arrangement to increase the width of the equivalent current channel and decrease the resistance, the current value that can turn on the electrostatic discharge protection structure 150 is increased.

[0053]

[0060] Figure 4 is a flowchart of a semiconductor power device manufacturing method 4 according to some embodiments of the present disclosure. Manufacturing method 4 includes steps S41, S42, S43, S44, S45, S46, and S47. Figures 5 to 34 are schematic diagrams of the semiconductor power device manufacturing process according to some embodiments of the present disclosure. For ease of understanding, manufacturing method 4 will be described with reference to Figures 5 to 34. Manufacturing method 4 can be shown as an operation used to manufacture the semiconductor power device 1 as described with respect to Figure 1, and Figures 5 to 34 show the semiconductor power device 1 at various stages of the manufacturing process. Manufacturing method 4 may also be applied to manufacture other semiconductor devices having an electrostatic discharge protection structure 150, such as the semiconductor devices in Figures 35 and 36, for example, without departing from the spirit and principles of the present disclosure.

[0054]

[0061] Referring to Figure 5, in step S41, a low-concentration doped layer 110 is formed on the substrate 100. Next, an oxide hard mask 201 can be formed on the low-concentration doped layer 110, for example, using a thermal oxidation process, and a patterned photoresist layer 202 can be formed on the oxide hard mask 201. The oxide hard mask 201 can be etched according to the patterned photoresist layer 202 to transfer the pattern on the photoresist layer 202 to the oxide hard mask 201. In some embodiments, after the pattern on the photoresist layer 202 has been transferred to the oxide hard mask 201, the photoresist layer 202 is removed.

[0055]

[0062] Referring to Figure 6, in step S42, a plurality of openings O1, O2, and O3 extending toward the substrate 100 are formed in the low-concentration doped layer 110. The positions of the plurality of openings O1, O2, and O3 correspond to the pattern of the oxidized hard mask 201.

[0056]

[0063] Referring to Figure 7, the oxidized hard mask 201 is removed after multiple openings O1, O2, and O3 have been formed.

[0057]

[0064] In some embodiments, after the oxide hard mask 201 is removed, an oxidation process may be used to form a sacrificial oxide layer on the exposed surface of the low-concentration doped layer 110, which is then removed. The oxidation process can be carried out by adding oxygen and heating so that an oxide such as silicon dioxide is formed on the surface of the low-concentration doped layer 110. In some embodiments, the formation and removal of the sacrificial oxide layer optimizes the surface of the low-concentration doped layer 110.

[0058]

[0065] Referring to Figures 8 to 10, in step S43, the diode array 151 is formed on openings O2 and O3. As shown in Figure 8, the gate oxide layer 203 is formed on the surface of the low-concentration doped layer 110. The gate oxide layer 203 is also formed on the surfaces of openings O1, O2, and O3. In some embodiments, the thickness of the gate oxide layer 203 may be substantially uniform.

[0059]

[0066] As shown in Figure 9, polysilicon may be formed on the gate oxide layer 203, filling openings O1, O2, and O3. In some embodiments, after the polysilicon is formed, a planarization process may be further performed to give the polysilicon a smooth surface. Next, an ion implantation process can be performed on the polysilicon to form a second conductive type (P-type) polysilicon 204. In some embodiments, a thermal annealing process can be performed on the polysilicon 204 to eliminate damage to the polysilicon 204 caused by the ion implantation process.

[0060]

[0067] As shown in Figure 10, a photoresist layer 205 can be formed on polysilicon 204, and the photoresist layer 205 defines the positions of doped regions 151a1, 151a2, and 151a3 in the diode array 151. The openings in the photoresist layer 205 expose a portion of the surface of polysilicon 204. Then, using the photoresist layer 205 as a shield, an ion implantation process can be performed on the exposed portion of polysilicon 204 so that the exposed portion of polysilicon 204 forms the doped regions 151a1, 151a2, and 151a3. In addition, due to the performed ion implantation process, the doping concentration of polysilicon 204 in openings O2 and O3 changes, thereby resulting in polysilicon 204 in opening O2 becoming polysilicon structure 144 and polysilicon 204 in opening O3 becoming polysilicon structure 146. After the ion implantation process is performed, the photoresist layer 205 is removed. Since portions of the polysilicon 204 are formed into doped regions 151a1, 151a2, and 151a3, the polysilicon 204 between doped region 151a1 and doped region 151a3 are doped regions 151b1 and 151b2. Thus, doped regions 151a and 151b of the diode array 151 are formed in the process shown in Figure 10. The conductivity types of doped regions 151a1, 151a2, 151a3, polysilicon structure 144, and polysilicon structure 146 formed after the ion implantation process are different from the conductivity type of polysilicon 204. In other words, the conductivity types of doped region 151a1, doped region 151a2, doped region 151a3, polysilicon structure 144, and polysilicon structure 146 are different from the conductivity types of doped region 151b1 and doped region 151b2.

[0061]

[0068] Referring to Figure 11, the hard mask layer 206 may be formed on the polysilicon 204, doped region 151a, and doped region 151b, and the photoresist layer 207 may be formed on the hard mask layer 206. The photoresist layer 207 may be used to define the position of the electrostatic discharge protection structure 150. More specifically, the photoresist layer 207 covers the position of the electrostatic discharge protection structure 150.

[0062]

[0069] Referring to Figure 12, an etching process can be performed on the hard mask layer 206 based on the photoresist layer 207 to remove the portion of the hard mask layer 206 that is not covered by the photoresist layer 207. Then the photoresist layer 207 is removed.

[0063]

[0070] Referring to Figure 13, based on the hard mask layer 206, an etching process can be performed on the polysilicon 204 to remove the polysilicon 204 not covered by the hard mask layer 206. In some embodiments, the polysilicon 204 filling the opening O1 does not need to be removed. Once the etching process is complete, the upper surface of the remaining polysilicon 204 may be substantially coplanar with the upper surface of the low-concentration doped layer 110.

[0064]

[0071] Referring to Figure 14, the hard mask layer 206 covering the diode array 151 and the gate oxide layer 203 covering the low-concentration doped layer 110 are removed. The original gate oxide layer 203 becomes several discontinuous portions. The gate oxide layer 203 within opening O1 becomes oxide layer 141, and the gate oxide layer 203 within openings O2 and O3 become oxide layer 143 and oxide layer 145, respectively.

[0065]

[0072] Referring to Figure 15, an oxide layer 207 can be formed on the low-concentration doped layer 110. The oxide layer 207 can further cover the diode array 151, the oxide layer 141, the polysilicon 204, a portion of the oxide layer 143, and a portion of the oxide layer 145. In some embodiments, the oxide layer 207 may be formed by a thermal oxidation process.

[0066]

[0073] Referring to Figure 16, a photoresist layer 208 can be formed on the oxide layer 207. The photoresist layer 208 can be used to define the location of the body-doped region 121. Next, an ion implantation process can be performed on the low-concentration doped layer 110 based on the photoresist layer 208 so that a portion of the low-concentration doped layer 110 becomes the body-doped region 121.

[0067]

[0074] Referring to Figure 17, after the body-doped region 121 is formed, the photoresist layer 208 and the oxide layer 207 are removed.

[0068]

[0075] Referring to Figure 18, in step S44, a spacer oxide layer SX1 is formed on the diode array 151, surrounding it. The spacer oxide layer SX1 is also formed on the low-concentration doped layer 110, polysilicon 204, oxide layer 141, oxide layer 143, and oxide layer 145. After the spacer oxide layer SX1 is formed, the diode array 151 is surrounded by the spacer oxide layer SX1, oxide layer 143, and oxide layer 145. In some embodiments, the thickness of the spacer oxide layer SX1 may be greater than the thickness of the oxide layer 207. In some embodiments, the spacer oxide layer SX1 may be formed by a thin-film process such as chemical vapor deposition (CVD). In some embodiments, the insulation between the diode array 151 and adjacent components can be determined by the thickness of the spacer oxide layer SX1, and the thickness of the spacer oxide layer SX1 formed by CVD can be precisely controlled.

[0069]

[0076] Referring to Figures 19 to 24, in step S45, a diode array 156 is formed on the spacer oxide layer SX1. As shown in Figure 19, a polysilicon 209 of a second conductivity type (P-type) is formed on the spacer oxide layer SX1. In some embodiments, the polysilicon 209 may be conformally formed on the spacer oxide layer SX1. As shown in Figure 20, a hard mask layer 210 may be formed on the polysilicon 209, and a photoresist layer 211 may be formed on the hard mask layer 210. The photoresist layer 211 is used to define the position of the diode array 156. As shown in Figure 21, an etching process is performed on the hard mask layer 210 based on the photoresist layer 211 such that the hard mask layer 210 located below the photoresist layer 211 is maintained and the rest of the hard mask layer 210 is removed. After the etching process is complete, the photoresist layer 211 is removed. As shown in Figure 22, a separate etching process can be performed on the polysilicon 209 according to the remaining hard mask layer 210, such that the polysilicon 209 not covered by the hard mask layer 210 is removed, while the polysilicon 209 beneath the hard mask layer 210 is retained. After the etching process for the polysilicon 209 is complete, the hard mask layer 210 is removed.

[0070]

[0077] As shown in Figure 23, the spacer oxide layer SX2 is formed on the polysilicon 209 and surrounds the polysilicon 209. The spacer oxide layer SX2 extends along the sidewall of the polysilicon 209 and is adjacent to the spacer oxide layer SX1.

[0071]

[0078] As shown in Figure 24, a photoresist layer 211 can be formed on the spacer oxide layer SX2. The photoresist layer 211 is used to define the positions of the doped region 156a, the source doped region 122, and the drain doped region 124. Next, in step S46, an ion implantation process is performed on the polysilicon 209, the low-concentration doped region 110, and the body doped region 121 based on the photoresist layer 211 to form the trench structure TR1 and the source doped region 122. Regions on the polysilicon 209 where the photoresist layer 211 is not present form N-type (first conductivity type) doped regions 156a1, 156a2, and 156a3. The upper part of the body doped region 121 forms the source doped region 122. The polysilicon 204 becomes the polysilicon structure 142. A portion of the low-concentration doped region 110 forms the drain doped region 124. Since a portion of the polysilicon 209 is formed into doped regions 156a1, 156a2, and 156a3, the polysilicon 209 between doped region 156a1 and doped region 156a3 is doped region 156b1 and doped region 156b2. Therefore, doped regions 156a and 156b of the diode array 156 are formed in the process shown in Figure 24, and doped regions 156a and 156b have different conductivity types.

[0072]

[0079] Referring to Figure 25, the photoresist layer 211 is removed after the ion implantation process is complete. In some embodiments, after the photoresist layer 211 is removed, a thermal annealing process may be performed on the polysilicon structure 142, the source-doped region 122, the doped region 156a, and the drain-doped region 124.

[0073]

[0080] Referring to Figure 26, an interlayer dielectric layer 130 is formed on the spacer oxide layer SX1 and the spacer oxide layer SX2.

[0074]

[0081] Referring to Figure 27, a photoresist layer 212 can be formed on the interlayer dielectric layer 130. The photoresist layer 212 is used to define the positions of conductive plugs CP1, CP2, CP3, and CP4.

[0075]

[0082] Referring to Figure 28, based on the photoresist layer 212, an etching process can be performed on the interlayer dielectric layer 130, the spacer oxide layer SX1, and the spacer oxide layer SX2 to form openings OC1, OC2, OC3, and OC4. Specifically, openings OC1, OC2, OC3, and OC4 correspond to conductive plugs CP1, CP2, CP3, and CP4, respectively. A portion of the source doped region 122 is exposed by opening OC1, a portion of the drain doped region 124 is exposed by opening OC2, a portion of the doped region 156a1 is exposed by opening OC3, and a portion of the doped region 156a3 is exposed by opening OC4.

[0076]

[0083] Referring to Figure 29, the photoresist layer 212 is removed after the etching process is complete.

[0077]

[0084] Referring to Figure 30, an etching process can be performed on the source doped region 122, drain doped region 124, doped region 156a1, and doped region 156a3 through openings OC1, OC2, OC3, and OC4. After the etching process, opening OC1 extends toward the substrate 100 and reaches the upper surface of the body doped region 121, opening OC2 extends toward the substrate 100 and reaches the bottom surface of the drain doped region 124, and openings OC3 and OC4 extend toward the substrate 100 and reach the upper surface of the spacer oxide layer SX1. In some embodiments, the interlayer dielectric layer 130 can be partially etched at the same time to reduce the thickness of the interlayer dielectric layer 130.

[0078]

[0085] Referring to Figure 31, an etching process can be performed on the spacer oxide layer SX1 through openings OC3 and OC4 such that the openings OC3 and OC4 extend toward the substrate 100, penetrate the spacer oxide layer SX1, and reach the upper surfaces of the doped regions 151a1 and 151a3.

[0079]

[0086] Referring to Figure 32, an etching process can be performed on the body-doped region 121, the low-concentration doped layer 110, the doped region 151a1, and the doped region 151a3 through openings OC1, OC2, OC3, and OC4, respectively. After the etching process, opening OC1 extends into the body-doped region 121 toward the substrate 100, opening OC2 extends into the low-concentration doped layer 110 toward the substrate 100, opening OC3 extends into the doped region 151a1 toward the substrate 100, and opening OC4 extends into the doped region 151a3 toward the substrate 100.

[0080]

[0087] Referring to Figure 33, the ion implantation process can be performed on the body-doped region 121, the low-concentration doped layer 110, the doped region 151a1, and the doped region 151a3 through openings OC1, OC2, OC3, and OC4, respectively, to form the high-concentration doped regions 123, 125, 147, and 148. The high-concentration doped regions 123, 125, 147, and 148 are P-type (second conductivity type) doped regions and are used as ohmic contacts between the conductive plug and the doped regions.

[0081]

[0088] Referring to Figures 34 and 2, in step S47, the source electrode S can be formed to bond to the source-doped region 122, and the gate electrode G can be formed to bond to the polysilicon structure 142. As shown in Figure 34, the conductive material can be formed in the openings OC1, OC2, OC3, and OC4, and on the interlayer dielectric layer 130, after which an etch-back process can be performed so that the upper surface of the interlayer dielectric layer 130 is coplanar with the upper surface of the conductive material. After the conductive material has filled the openings OC1, OC2, OC3, and OC4, the conductive plugs CP1, CP2, CP3, and CP4 are formed. In some embodiments, the conductive material to be filled may be a metal. In some embodiments, the conductive material to be filled may be tungsten (W).

[0082]

[0089] Referring again to Figure 2, metal wires 161, 162, and 163 can be formed on the interlayer dielectric layer 130, and the metal wires 161, 162, and 163 are spaced apart from each other. Metal wire 161 is used for connection to the source electrode S, metal wire 162 is used for connection to the gate electrode G, and metal wire 163 is used for connection to the drain electrode D. Metal wire 161 is adjacent to conductive plugs CP1 and CP3, and therefore conductive plugs CP1 and CP3 can be electrically connected to the source electrode S via metal wire 161. Metal wire 162 is adjacent to conductive plug CP4, and therefore conductive plug CP4 can be electrically connected to the gate electrode G via metal wire 162. Metal wire 163 is adjacent to conductive plug CP2, and therefore conductive plug CP2 can be electrically connected to the drain electrode D via metal wire 163.

[0083]

[0090] It should be understood that the semiconductor power device 1 of this disclosure is not limited to the structure described above. For example, the gate of the semiconductor power device 1 may be implemented in a different structure, and this is also within the scope of this disclosure.

[0084]

[0091] Referring to Figures 35 and 36, Figure 35 is a schematic diagram of another exemplary semiconductor power device 2 according to an embodiment of the present disclosure, and Figure 36 is a schematic diagram and a partial enlargement of yet another exemplary semiconductor power device 3 according to an embodiment of the present disclosure. For ease of understanding, the symbols in Figures 35 and 36 follow the symbols in Figures 1, 2, 3A, and 3B, but this does not mean that components using the same symbols must be identical.

[0085]

[0092] The semiconductor power device 2 is substantially the same as the semiconductor power device 1, except for the trench structure. Specifically, the trench structure TR1 of the semiconductor power device 2 is arranged in the form of a split gate. The trench structure TR1 of the semiconductor power device 2 has two separate polysilicon structures, namely polysilicon structure 142a and polysilicon structure 142b, with polysilicon structure 142a positioned above polysilicon structure 142b. In addition, the oxide layer 141 of the trench structure TR1 may extend further between polysilicon structure 142a and polysilicon structure 142b. In some embodiments, polysilicon structure 142a may be part of the gate structure, and polysilicon structure 142b may be part of the source structure.

[0086]

[0093] The semiconductor power device 3 is substantially similar to the semiconductor power device 1, except that the power transistor of the semiconductor power device 3 includes a dual trench structure. The semiconductor power device 3 further includes a trench structure TR5, a conductive plug CP5, a high-density doped region 126, and a high-density doped region 127. The trench structure TR5 is located between two trench structures TR1, and between trench structure TR2 and the trench structure TR1 adjacent to trench structure TR2. As an example, Figure 36 shows two trench structures TR5. One trench structure TR5 is located between two trench structures TR1, and the other is located between trench structure TR2 and the trench structure TR1 adjacent to trench structure TR2. The trench structure TR5 is located within a low-density doped layer 110, extends toward the substrate 100 through a source-doped region 122, and protrudes from a body-doped region 121. The depth of the trench structure TR5 may be less than the depth of the trench structure TR1.

[0087]

[0094] As an example for explanation, the trench structure TR5 may include a polysilicon structure 172 and an oxide layer 171 surrounding the polysilicon structure 172. Two conductive plugs CP5 are positioned on either side of the trench structure TR5. The conductive plugs CP5 are connected to metal wires 161 and extend through the interlayer dielectric layer 130, the spacer oxide layer SX1, and the source-doped region 122, reaching a high-concentration doped region 126 within the body-doped region 121.

[0088]

[0095] The highly doped region 127 is located within the polysilicon structure 142 and is adjacent to the spacer oxide layer SX1. The conductive plug CP1 is located on the trench structure TR1 and extends into the highly doped region 127. In some embodiments, the oxide layer 171 and the polysilicon structure 172 may be part of the gate structure, and the oxide layer 141 and the polysilicon structure 142 may be part of the source structure.

[0089]

[0096] According to one aspect of the present disclosure, an electrostatic discharge protection structure is provided, comprising: a first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a second trench structure comprising a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; a first diode array adjacent to the first and second polysilicon structures and disposed between the first and second trench structures; a first spacer oxide layer disposed on the first diode array; and a second diode array disposed on the first spacer oxide layer and connected in parallel to the first diode array.

[0090]

[0097] In any of the above embodiments, the first diode array comprises a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are arranged alternately, and a PN junction is formed at the interface between each first doped region and an adjacent second doped region.

[0091]

[0098] Optionally, in any of the above embodiments, the first ends of the plurality of first doped regions are adjacent to the first polysilicon structure, and the second ends of the plurality of first doped regions are adjacent to the second polysilicon structure.

[0092]

[0099] In any of the above embodiments, the first polysilicon structure and the second polysilicon structure have a first conductivity type.

[0093]

[0100] At will, in any of the above embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0094]

[0101] In any of the above embodiments, the second diode array comprises a plurality of third doped regions of a first conductivity type and a plurality of fourth doped regions of a second conductivity type, wherein the plurality of third doped regions and the plurality of fourth doped regions are arranged alternately, and a PN junction is formed at the interface between each third doped region and an adjacent fourth doped region.

[0095]

[0102] Optionally, in any of the above embodiments, the electrostatic discharge protection structure may further include: a first conductive plug that reaches the first end of a plurality of third doped regions through a first spacer oxide layer and connects a first electrode to the first end of a plurality of third doped regions and the first end of a plurality of first doped regions; a second conductive plug that reaches the second end of a plurality of first doped regions through a second end of a plurality of third doped regions and a first spacer oxide layer and connects a second electrode to the second end of a plurality of third doped regions and the second end of a plurality of first doped regions; a first high-concentration doped region disposed within the first end of a plurality of first doped regions and surrounding the end of the first conductive plug; and a second high-concentration doped region disposed within the second end of a plurality of first doped regions and surrounding the end of the second conductive plug.

[0096]

[0103] Optionally, in any of the above embodiments, the electrostatic discharge protection structure may further include a second spacer oxide layer disposed on and surrounding the second diode array.

[0097]

[0104] In any of the above embodiments, the first oxide layer and the second oxide layer are adjacent to each other, and the first diode array is positioned between the first spacer oxide layer and the adjacent first oxide layer and second oxide layer.

[0098]

[0105] In any of the above embodiments, the first diode array and the second diode array each comprise a plurality of back-to-back diodes connected in series.

[0099]

[0106] According to another aspect of the present disclosure, a semiconductor power device is provided comprising: a substrate; a low-density doped layer disposed on the substrate; a first trench structure disposed within the low-density doped layer and extending toward the substrate, comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a source-doped region disposed away from the substrate within the low-density doped layer; an interlayer dielectric layer disposed on the low-density doped layer; a source electrode connected to the source-doped region; a gate electrode connected to the first polysilicon structure; and an electrostatic discharge protection structure disposed within the interlayer dielectric layer, wherein the electrostatic discharge protection structure comprises: a first diode array; a second diode array disposed on the first diode array; and a first spacer oxide layer disposed between the first diode array and the second diode array, the first diode array and the second diode array being connected in parallel between the source electrode and the gate electrode.

[0100]

[0107] In any of the above embodiments, the electrostatic discharge protection structure further comprises a second spacer oxide layer adjacent to the first spacer oxide layer, which is disposed on and on the side surface of the second diode row.

[0101]

[0108] Optionally, in any of the above embodiments, each of the first diode array and the second diode array comprises a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the plurality of second doped regions and the plurality of first doped regions are arranged alternately, and a PN junction is formed at the interface between each first doped region and an adjacent second doped region.

[0102]

[0109] Optionally, in any of the above embodiments, the semiconductor power device may further include: a first conductive plug reaching the first diode row through a second diode row and a first spacer oxide layer, with a source electrode connected to the first end of a plurality of first doped regions of the first diode row and the first end of a plurality of first doped regions of the second diode row; a second conductive plug reaching the first diode row through the second diode row and a first spacer oxide layer, with a gate electrode connected to the second end of a plurality of first doped regions of the first diode row and the second end of a plurality of first doped regions of the second diode row; a first highly concentrated doped region located within the first end of a plurality of first doped regions of the first diode row and surrounding the end of the first conductive plug; and a second highly concentrated doped region located within the second end of a plurality of first doped regions of the first diode row and surrounding the end of the second conductive plug.

[0103]

[0110] At will, in any of the above embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0104]

[0111] Optionally, in any of the above embodiments, the semiconductor power device may further include a body-doped region located within a low-concentration doped layer and adjacent to the first oxide layer, and a drain-doped region located within the low-concentration doped layer, wherein the source-doped region is located within the body-doped region.

[0105]

[0112] In any of the above embodiments, the first spacer oxide layer extends to the sidewalls and low-concentration doped layers of the first diode array, covering the source-doped region, the drain-doped region, and the first trench structure.

[0106]

[0113] Optionally, in any of the above embodiments, the semiconductor power device may further include a third highly doped region located within the body-doped region, and a third conductive plug connected to a source electrode, extending through the interlayer dielectric layer and the source-doped region to reach the body-doped region, wherein the third highly doped region surrounds one end of the third conductive plug.

[0107]

[0114] Optionally, in any of the above embodiments, the semiconductor power device may further include a drain electrode disposed on an interlayer dielectric layer, a fourth high-concentration doped region disposed within a body-doped region, and a fourth conductive plug connected to the drain electrode and extending through the interlayer dielectric layer and the drain-doped region to reach a low-concentration doped layer, wherein the fourth high-concentration doped region surrounds one end of the fourth conductive plug.

[0108]

[0115] In any of the above embodiments, the dielectric breakdown voltage of the first diode array is substantially equal to the dielectric breakdown voltage of the second diode array.

[0109]

[0116] In any of the above embodiments, the dielectric breakdown voltage of the first diode array is lower than the dielectric breakdown voltage of the first oxide layer.

[0110]

[0117] A method for manufacturing a semiconductor power device is provided, comprising: forming a low-density doped layer on a substrate; forming a first opening, a second opening, and a third opening extending toward the substrate on the low-density doped layer; forming a first diode array on the second and third openings; forming a first spacer oxide layer surrounding the first diode array on the first diode array; forming a second diode array on the first spacer oxide layer; forming a first trench structure within the first opening, comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source-doped region within the low-density doped layer, located between the first trench structure and the second opening; and forming a source electrode connected to the source-doped region and a gate electrode connected to the first polysilicon structure, wherein the first and second diode arrays are connected in parallel and located between the source electrode and the gate electrode.

[0111]

[0118] Optionally, in any of the above embodiments, the manufacturing method may further include forming a second spacer oxide layer that is arranged on and surrounding the second diode array and adjacent to the first spacer oxide layer, and forming an interlayer dielectric layer on a low-concentration doped layer, wherein the source electrode and gate electrode are formed on the interlayer dielectric layer.

[0112]

[0119] Optionally, in any of the above embodiments, the manufacturing method may further include forming a first conductive plug, a second conductive plug, and a third conductive plug, wherein the first conductive plug reaches a source-doped region through an interlayer dielectric layer and a first spacer oxide layer, and the second and third conductive plugs reach a first diode array through a second spacer oxide layer, a second diode array, and a first spacer oxide layer.

[0113]

[0120] In any of the above embodiments, the first conductive plug connects its source electrode to the source-doped region, the second conductive plug connects its source electrode to the first diode array and the second diode array, and the third conductive plug connects its gate electrode to the first diode array and the second diode array.

[0114]

[0121] Optionally, in any of the above embodiments, the manufacturing method may further include forming a drain-doped region in a low-concentration doped layer, forming a fourth conductive plug that reaches the drain-doped region through the interlayer dielectric layer and the first spacer oxide layer, and forming a drain electrode, wherein the fourth conductive plug connects the drain electrode to the drain-doped region.

[0115]

[0122] Optionally, in any of the above embodiments, the step of forming a first diode array on a second opening and a third opening includes forming a first semiconductor material within the second opening and the third opening, patterning the first semiconductor material, and performing ion implantation on the patterned first semiconductor material to form a plurality of first doped regions having a first conductivity type and a plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are arranged alternately, and a PN junction is formed at the interface between each first doped region and an adjacent second doped region.

[0116]

[0123] Optionally, in any of the above embodiments, the step of forming a second diode array on a first spacer oxide layer includes forming a second semiconductor material on the first spacer oxide layer, patterning the second semiconductor material, and performing ion implantation on the patterned second semiconductor material to form a plurality of third doped regions having a first conductivity type and a plurality of fourth doped regions having a second conductivity type, wherein the plurality of third doped regions and the plurality of fourth doped regions are arranged alternately, and a PN junction is formed at the interface between each third doped region and an adjacent fourth doped region.

[0117]

[0124] In this disclosure, for ease of explanation, spatially relative terms such as “downward,” “below,” “underside,” “upward,” “upper side,” “left side,” and “right side” may be used to describe the relationship between one component or feature and one or more other components or features as shown in the accompanying drawings. In addition to the orientations shown in the accompanying drawings, spatially relative terms are intended to encompass various orientations of the device in use or operation. The device may be oriented in other ways (90-degree rotation or other orientations), and the spatially relative terms used herein may be interpreted similarly in the corresponding ways. When one component is referred to as “connected” or “joined” to another component, it should be understood that it may be directly connected to or joined to the other component, or there may be an intervening component.

[0118]

[0125] When used herein, the terms “approximately,” “basically,” “substantially,” and “about” are used to describe and explain small variations. When used in relation to an event or case, these terms may refer to embodiments in which the event or case exactly exists, as well as embodiments in which the event or case nearly exists. When used herein in relation to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. Ranges herein may be referred to as being from one endpoint to another, or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the difference in position between two surfaces relative to the same plane is within a few micrometers (μm), e.g., within 10 μm, 5 μm, 1 μm, or 0.5 μm. When values ​​or characteristics are said to be "substantially" the same, this term may refer to values ​​within ±10%, ±5%, ±1%, or ±0.5% of the mean of the values.

[0119]

[0126] The features and detailed aspects of some embodiments of the present disclosure have been outlined above. The embodiments described herein can be readily used as a basis for designing or modifying other processes and structures to perform the same or similar purposes as those of the embodiments presented herein, and / or to achieve the same or similar advantages. Such equivalent configurations can be made in various ways, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0120]

[0127] While the description has been detailed, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure as defined by the attached claims. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, for it will be readily apparent to those skilled in the art that processes, machines, manufactures, compositions, means, methods, or steps that currently exist or will be developed in the future can be used in accordance with this disclosure to perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the attached claims are intended to include such processes, machines, manufactures, compositions, means, methods, or steps within their scope. [Explanation of Symbols]

[0121] 1. Semiconductor power devices 2. Semiconductor Power Devices 3. Semiconductor Power Devices 4 Manufacturing method 10 Vertical Power Transistors 100 circuit boards 110 Low-concentration doped layer, low-concentration doped region 121 Body Doping Area 122 Source-doped area 123 High-concentration doped area 124 Drain-doped area 125 High-concentration doped area 126 High-concentration doped area 127 High-concentration doped area 130 Interlayer dielectric layers 141 Oxide layer 142 Polysilicon structure 142a Polysilicon structure 142b Polysilicon structure 143 Oxide layer 144 Polysilicon structure 145 Oxide layer 146 Polysilicon structure 147 High-concentration doped area 148 High-concentration doped area 150 Electrostatic discharge protection structure 151 First diode array 151a N-type doped region 151a1 Doping area 151a2 Doping area 151a3 Doping area 151b P-type doped region 151b1 Doping area 151b2 Doping area 156 Second diode array 156a Doping area 156a1 Doping area 156a2 Doping area 156a3 Doping area 156b P-type doped region 156b1 Doping area 156b2 Doping area 161 Metal wire 162 Metal wire 163 Metal wire 171 Oxide layer 172 Polysilicon structure 201 Oxide hard mask, Oxide hard mask 202 Patterned photoresist layer 203 Gate oxide layer 204 Polysilicon 205 Photoresist layer 206 Hard Mask Layer 207 Photoresist layer, oxide layer 208 Photoresist layer 209 Polysilicon 210 Hard mask layer 211 Photoresist layer 212 Photoresist layer CP1 conductive plug CP2 conductive plug CP3 conductive plug CP4 conductive plug CP5 conductive plug D drain electrode G Post Office O1 opening O2 opening O3 opening OC1 opening OC2 opening OC3 opening OC4 opening RG gate resistor S Source electrode, source terminal SX1 Spacer Oxide Layer SX2 Spacer Oxide Layer TR1 Trench Structure TR2 Trench Structure TR3 Trench Structure TR5 Trench Structure

Claims

1. A first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure, A second trench structure comprising a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure, Displaced between the first trench structure and the second trench structure, and adjacent to the first polysilicon structure and the second polysilicon structure, A first spacer oxide layer disposed on the first diode array, A second diode array disposed on the first spacer oxide layer, wherein the second diode array and the first diode array are connected in parallel, A first conductive plug extends from the first end of the second diode array through the first spacer oxide layer to the first end of the first diode array, and connects the first electrode to the first end of the second diode array and the first end of the first diode array, A first highly doped region is located within the first end of the first diode array and surrounds the end of the first conductive plug. A static discharge protection structure is provided.

2. The first diode array is, A plurality of first doped regions of the first conductivity type, Multiple second doped regions of the second conductive type and Equipped with, The electrostatic discharge protection structure according to claim 1, wherein the plurality of first doped regions and the plurality of second doped regions are arranged alternately, and a PN junction is formed at the interface between each first doped region and each second doped region adjacent to each first doped region.

3. The second diode array described above is The plurality of third doped regions of the first conductivity type, The plurality of fourth doped regions of the second conductivity type and Equipped with, The electrostatic discharge protection structure according to claim 2, wherein the plurality of third doped regions and the plurality of fourth doped regions are arranged alternately, and a PN junction is formed at the interface between each third doped region and each fourth doped region adjacent to each third doped region.

4. A second conductive plug extending from the second end of the second diode array through the first spacer oxide layer to the second end of the first diode array, the second electrode connecting the second end of the second diode array and the second end of the first diode array, A second highly doped region is located within the second end of the first diode array and surrounds the end of the second conductive plug. The electrostatic discharge protection structure according to claim 1, further comprising:

5. The electrostatic discharge protection structure according to claim 1, wherein the first end of the first diode array is adjacent to the first polysilicon structure, and the second end of the first diode array is adjacent to the second polysilicon structure.

6. A second spacer oxide layer is placed on the second diode array and surrounds the second diode array. The electrostatic discharge protection structure according to claim 1, further comprising:

7. The electrostatic discharge protection structure according to claim 1, wherein the first oxide layer is adjacent to the second oxide layer, and the first diode array is arranged between the first spacer oxide layer, the first oxide layer, and the second oxide layer.

8. The electrostatic discharge protection structure according to claim 1, wherein each of the first diode array and the second diode array comprises a plurality of back-to-back diodes connected in series.

9. A low-concentration doped layer placed on the substrate, Displaced within the low-concentration doped layer and extending toward the substrate, the first trench structure comprises a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure, An interlayer dielectric layer disposed on the low-concentration doped layer, A source electrode connected to a source-doped region located within the low-concentration doped layer, A gate electrode connected to the first polysilicon structure, A static discharge protection structure disposed within the interlayer dielectric layer and A semiconductor power device comprising, The electrostatic discharge protection structure is The first diode array, A second diode array is positioned above the first diode array and connected in parallel with the first diode array between the source electrode and the gate electrode, A first spacer oxide layer is disposed between the first diode array and the second diode array. Equipped with, The aforementioned semiconductor power device is A first conductive plug extends through the second diode array and the first spacer oxide layer to the first diode array, and connects the source electrode to the first end of the first diode array and the first end of the second diode array, A first highly doped region is located within the first end of the first diode array and surrounds the end of the first conductive plug. A semiconductor power device that further incorporates these features.

10. The electrostatic discharge protection structure is A second spacer oxide layer is disposed on the second diode array and on the sidewall of the second diode array, and is adjacent to the first spacer oxide layer. The semiconductor power device according to claim 9, further comprising:

11. Each of the first diode array and the second diode array is, A plurality of first doped regions of the first conductivity type, Multiple second doped regions of the second conductive type and Equipped with, The semiconductor power device according to claim 9, wherein the plurality of second doped regions and the plurality of first doped regions are arranged alternately, and a PN junction is formed at the interface between each first doped region and each second doped region adjacent to each first doped region.

12. A second conductive plug extending from the second diode array and the first spacer oxide layer to the first diode array, the gate electrode connecting to the second end of the first diode array and the second end of the second diode array, A second highly doped region is located within the second end of the first diode array and surrounds the end of the second conductive plug. The semiconductor power device according to claim 9, further comprising:

13. Displaced within the low-concentration doped layer, adjacent to the first oxide layer, and comprising a body doped region in which the source doped region is located, A third high-concentration doped region is located within the body-doped region, A third conductive plug connected to the source electrode and extending through the interlayer dielectric layer and the source doped region to the body doped region, Furthermore, The semiconductor power device according to claim 9, wherein the third highly doped region surrounds one end of the third conductive plug.

14. A drain-doped region is disposed within the low-concentration doped layer, A fourth high-concentration doped region is located within the low-concentration doped region below the drain-doped region, A fourth conductive plug connected to the drain electrode of the semiconductor power device and extending into the low-concentration doped layer through the interlayer dielectric layer and the drain doped region, and Furthermore, The semiconductor power device according to claim 9, wherein the fourth highly doped region surrounds one end of the fourth conductive plug.

15. The semiconductor power device according to claim 9, wherein the dielectric breakdown voltage of the first diode array is substantially equal to the dielectric breakdown voltage of the second diode array, or the dielectric breakdown voltage of the first diode array is lower than the dielectric breakdown voltage of the first oxide layer.

16. A method for manufacturing semiconductor power devices, Forming a low-concentration doped layer on the substrate, To form a first opening, a second opening, and a third opening extending toward the substrate on the low-concentration doped layer, A first diode array is formed above the second and third openings, Forming a first spacer oxide layer surrounding the first diode array on the first diode array, Forming a second diode array on the first spacer oxide layer, A highly doped region is formed within the first end of the first diode array, The method involves forming a second conductive plug that extends through the second diode array and the first spacer oxide layer to the high-concentration doped region, wherein the high-concentration doped region surrounds the end of the second conductive plug. A first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure is formed within the first opening. The source-doped region, which is positioned between the first trench structure and the second opening, is formed within the low-concentration doped layer. Forming a source electrode connected to the source-doped region, To form a gate electrode connected to the first polysilicon structure It includes, A method wherein the first diode array and the second diode array are connected in parallel between the source electrode and the gate electrode.

17. A second spacer oxide layer is formed on the second diode array, surrounding the second diode array and adjacent to the first spacer oxide layer. Forming an interlayer dielectric layer on the low-concentration doped layer and It further includes, The method according to claim 16, wherein the source electrode and the gate electrode are formed on the interlayer dielectric layer.

18. To form a first conductive plug and a third conductive plug. It further includes, The method according to claim 17, wherein the first conductive plug extends through the interlayer dielectric layer and the first spacer oxide layer to reach the source-doped region, and the third conductive plug extends through the second spacer oxide layer, the second diode array, and the first spacer oxide layer to reach the first diode array.

19. The method according to claim 18, wherein the first conductive plug connects the source electrode to the source doped region, the second conductive plug connects the source electrode to the first diode array and the second diode array, and the third conductive plug connects the gate electrode to the first diode array and the second diode array.

20. Forming a drain-doped region within the low-concentration doped layer, To form a fourth conductive plug that extends through the interlayer dielectric layer and the first spacer oxide layer and reaches the drain-doped region, Forming a drain electrode and It further includes, The method according to claim 17, wherein the fourth conductive plug connects the drain electrode to the drain-doped region.

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