SiC bonded substrates and semiconductor devices

Abstract

This invention provides a highly reliable and yield-oriented SiC junction substrate and semiconductor device that maintains on-resistance at or above that of conventional support substrates. [Solution] A SiC junction substrate comprising a single-crystal SiC layer and a polycrystalline SiC layer, wherein the resistivity of the single-crystal SiC layer is 30 mΩ·cm or more and 1830 mΩ·cm or less, and the resistivity of the polycrystalline SiC layer is 1 mΩ·cm or more and 10 mΩ·cm or less.

Description

[Technical Field]

[0001] This invention relates to a SiC junction substrate and a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor with a broad band gap of 2.2 to 3.3 eV, and due to its excellent physical and chemical properties, it is being researched and developed as an environmentally resistant semiconductor material. In recent years, SiC has attracted attention as a material for power devices such as high-voltage, high-power electronic devices and high-frequency electronic devices, as well as for short-wavelength optical devices from blue to ultraviolet, and research and development has become active. However, the difficulty in manufacturing high-quality, large-diameter single crystals of SiC has hindered the practical application of SiC devices until now.

[0003] To address these issues, an improved Rayleigh method has been developed that uses a single-crystal SiC substrate as a seed crystal for sublimation recrystallization. This improved Rayleigh method allows for the growth of single-crystal SiC while controlling the crystal polymorphism (4H-SiC, 6H-SiC, 15R-SiC, etc.), carrier type, and impurity concentration. This technology significantly reduces the crystal defect density, leading to the practical application of Schottky barrier diodes (SBDs) and field-effect transistors (MOSFETs) on these substrates.

[0004] In SiC power devices, reducing on-resistance is particularly important from an energy-saving perspective. For example, in vertical power devices such as SBDs and MOSFETs, the on-resistance is determined by the sum of the electrical resistance components in the current path. Therefore, substrate resistance is reduced by either decreasing the resistivity (also called volume resistivity, measured in Ω·cm) of the support substrate or by shortening the current path length through a thinning grinding process called back grinding of the support substrate.

[0005] Typically, the resistivity range of n-type single-crystal SiC for power semiconductors, where single-crystal SiC is used alone as a support substrate, is controlled to a range of 15 mΩ·cm to 25 mΩ·cm, as described in Non-Patent Document 1, for example. Resistivity in semiconductors is determined by the carrier density, mobility, and elementary charge of free electrons, which are determined by the amount of nitrogen doping, a donor that supplies free electrons contributing to electrical conduction, and its activation rate. In particular, in single-crystal SiC, the nitrogen doping concentration is, for example, 5 × 10⁻⁶. 18 atoms / cm 3 From 1.5 × 10 19 atoms / cm 3 This range is considered to be 2-3 × 10⁻⁶. 19 atoms / cm 3 In the above cases, if double Shockley-type stacking faults are induced during activation annealing at around 1000°C or contact annealing after electrode formation, the resistance at that location will increase, raising concerns that it will significantly degrade the performance of the SiC power device. Furthermore, the upper limit of resistivity is set to approximately twice the lower limit, so as not to significantly degrade the on-resistivity of the SiC vertical power device.

[0006] Therefore, while increasing the nitrogen doping concentration can lower the resistance of the single-crystal SiC itself, it is desirable to control the resistivity of actual n-type single-crystal SiC within the higher end of the general specification range (15 mΩ·cm to 25 mΩ·cm) in order to avoid the risk of stacking fault formation. In other words, a lower nitrogen doping concentration is preferable from the viewpoint of improving crystal quality, resulting in relatively higher quality and reliability. However, when n-type single-crystal SiC is used alone as a support substrate for SiC power devices, the support substrate becomes highly resistive, leading to a trade-off where the on-resistance increases, which is a dilemma in single-crystal SiC manufacturing.

[0007] Under these circumstances, the improved Rayleigh process using single-crystal SiC substrates as seed crystals results in high manufacturing costs for single-crystal SiC substrates due to the slow crystal growth rate and the high processing costs involved in processing single-crystal SiC ingots into wafers, which primarily consist of cutting and polishing. This high manufacturing cost has been a factor hindering the practical application of SiC power devices, and there has been a strong demand for the development of technologies that can provide inexpensive SiC substrates for semiconductor device applications, especially for high-voltage and high-power electronic elements.

[0008] Therefore, a technology has been provided for manufacturing a semiconductor substrate (hereinafter referred to as a SiC junction substrate) that combines a low-cost support substrate with high-quality single-crystal SiC by using high-quality single-crystal SiC only for the device formation layer and fixing it to a support substrate (a material with sufficient strength, heat resistance, and cleanliness to withstand the device manufacturing process: for example, polycrystalline SiC) using a bonding method that does not involve the formation of an oxide film at the bonding interface (see, for example, Patent Document 1). In particular, SiC junction substrates using polycrystalline SiC as the support substrate have an advantage over single-crystal SiC substrates in that they can reduce costs while utilizing the characteristics of single-crystal SiC when applied to power devices. With the spread of single-crystal SiC substrates, attention is growing towards SiC junction substrates that can be manufactured at a lower cost.

[0009] In Patent Document 2, a method for manufacturing a SiC bonded substrate configured using a material having a thermal expansion coefficient close to that of single-crystalline SiC and a resistivity lower than that of single-crystalline SiC as a support substrate is disclosed. By configuring the support substrate using a material with low resistivity, the on-resistance can be made lower than when using n-type single-crystalline SiC alone as the support substrate, enabling low-power consumption operation. Specifically, it is described that the support substrate can be configured from materials mainly composed of highly doped polycrystalline SiC, highly doped amorphous SiC, metal tungsten and its carbides, metal molybdenum carbide, etc. Further, when an n-type drift layer is formed on a thick single-crystalline SiC substrate to form a SiC semiconductor device, a process of thinning the substrate by grinding or the like is performed to reduce the substrate resistance. However, in this embodiment, the process of thinning can be eliminated, and even if the substrate is thinned, the time required for grinding can be shortened by selecting a material with a lower hardness than single-crystalline SiC as the support substrate. That is, in the manufacturing method of these Patent Documents 2, as described above, cost reduction is achieved by reducing the usage amount of expensive and high-quality single-crystalline SiC substrates.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0011]

Non-Patent Document 1

Summary of the Invention

[0012] Patent Document 2 describes a method for manufacturing a SiC bonded substrate, stating that by constructing the support substrate using a material with a lower resistivity than the single-crystal SiC that forms the transfer layer, the on-resistivity can be lowered, enabling low-power operation. However, conventional methods have involved bonding a single-crystal SiC with a resistivity value (15 mΩ·cm to 25 mΩ·cm) used when a single-crystal SiC is used alone as the support substrate to the transfer layer. As a result, many through-helical dislocations occur due to the single-crystal SiC with such a resistivity value, making it impossible to provide a high-quality bonded substrate.

[0013] Furthermore, Patent Document 2 states that using SiC powder or bulk material sintered from amorphous SiC as a support substrate reduces process costs compared to forming the support substrate by physical vapor deposition (PVT) or chemical vapor deposition (CVD). For example, SiC powder that is readily available at low cost is thought to be made by crushing SiC crystals produced by the Acheson process, but the crystal system is α-type (6H-SiC), and even if high concentrations of nitrogen are used to reduce resistance, stacking faults occur in the crystal grain structure due to the thermal process in the manufacturing process of SiC power devices, resulting in the same problems as when using a support substrate made of single-crystal SiC. Also, sintering powdered SiC produced by PVT or CVD incurs additional process costs, so the aforementioned advantages cannot be obtained.

[0014] This invention was made in view of these problems, and aims to provide a SiC junction substrate and semiconductor device with high reliability and yield while maintaining on-resistance at or above that of conventional support substrates. [Means for solving the problem]

[0015] In light of the above circumstances, and through ingenuity, this invention has succeeded in creating an unprecedented low-resistance and high-reliability SiC junction substrate by using a higher-quality single-crystal SiC substrate as the transfer layer of a SiC junction substrate, even though it would normally not be marketable as a standalone single-crystal SiC substrate due to its inferior resistivity, and by using polycrystalline SiC, which has lower resistance than market-grade single-crystal SiC, as the support substrate. Furthermore, since the yield of this SiC junction substrate has been improved, this invention has been found to create new market value for high-quality single-crystal SiC, which has higher resistance than usual, and to reduce the amount of single-crystal SiC used when used as a SiC junction substrate.

[0016] In other words, the SiC junction substrate of the present invention comprises a single-crystal SiC layer and a polycrystalline SiC layer, wherein the resistivity of the single-crystal SiC layer is 30 mΩ·cm or more and 1830 mΩ·cm or less, and the resistivity of the polycrystalline SiC layer is 1 mΩ·cm or more and 10 mΩ·cm or less.

[0017] The SiC junction substrate of the present invention may include a single-crystal SiC epitaxial film layer laminated on the single-crystal SiC layer.

[0018] Furthermore, in order to solve the above problems, the semiconductor device of the present invention comprises the SiC junction substrate of the present invention. [Effects of the Invention]

[0019] The present invention makes it possible to provide a SiC junction substrate and semiconductor device with high reliability and yield while maintaining on-resistance at or above that of conventional support substrates. [Brief explanation of the drawing]

[0020] [Figure 1] This is a schematic perspective view of a SiC junction substrate. [Figure 2] This is a schematic perspective view of a SiC junction substrate equipped with a single-crystal SiC epitaxial film layer. [Figure 3] This is a schematic cross-sectional view of a MOSFET, an example of a semiconductor device. [Figure 4]This is a schematic cross-sectional view of a SiC single crystal growth apparatus before performing SiC single crystal growth by the sublimation recrystallization method. [Figure 5] This is a schematic cross-sectional view of a SiC single crystal growth apparatus after growing a SiC single crystal ingot.

Embodiments for Carrying Out the Invention

[0021] Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to this embodiment.

[0022] [SiC Bonded Substrate] The SiC bonded substrate of this embodiment includes the following single crystal SiC layer and polycrystalline SiC. Further, a single crystal SiC epitaxial film layer laminated on the single crystal SiC layer may be provided. For example, it can be used for applications such as manufacturing SBD and MOSFET which are SiC power devices.

[0023] 〈Single Crystal SiC Layer〉 The single crystal SiC layer is a layer serving as a base for growing a single crystal SiC epitaxial thin film, and can play a role as a base substrate for growing single crystal SiC to form an active layer in a SiC power device.

[0024] (Nitrogen Doping Concentration) The single crystal SiC layer has a nitrogen doping concentration of 3×10 15 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less, preferably 1×10 17 atoms / cm 3 or more and 1×10 18 atoms / cm 3The following is true: Because the nitrogen doping concentration of the single-crystal SiC layer is lower than that of commercially available single-crystal SiC substrates, the risk of stacking faults caused by dopants can be essentially eliminated. Furthermore, because there is less nitrogen impurity incorporated into the SiC single crystal, a relative improvement in crystal quality can be expected.

[0025] However, the nitrogen doping concentration is 3 × 10 15 atoms / cm 3 If the concentration is less than 1 × 10⁻¹⁰, the resistivity of the single-crystal SiC layer may become too high compared to when commercially available grade single-crystal SiC is used as the single-crystal SiC layer of a SiC junction substrate, potentially leading to a significant increase in the on-resistance of vertical SiC power devices. Furthermore, growth control may become difficult with a general-purpose modified Rayleigh process setup. Also, if the nitrogen doping concentration is less than 1 × 10⁻¹⁰, the resistivity of the single-crystal SiC layer may become excessively high, potentially leading to a significant increase in the on-resistance of vertical SiC power devices. 18 atoms / cm 3 If it's of the "ultra" grade, it will be comparable to commercially available single-crystal SiC, and therefore the aforementioned effects will not be obtained.

[0026] (Penetrating spiral dislocation) Furthermore, if the nitrogen doping concentration of the single-crystal SiC layer grown using, for example, the modified Rayleigh method is lower than that of commercially available single-crystal SiC, the concentration of impurities incorporated into the crystal is reduced. This allows for crystal growth without compromising crystal quality and suppresses the occurrence of threading helical dislocations (TSDs). For example, preferably, the threading helical dislocations are 250 per cm. 2 More preferably 100 pieces / cm 2 More preferably, 10 pieces / cm 2 The following is true: A low number of through-helical dislocations improves the reliability and yield of SiC power devices.

[0027] (Basal transposition) Furthermore, if the nitrogen doping concentration of the single-crystal SiC layer grown by, for example, the modified Rayleigh method is lower than that of commercially available single-crystal SiC, the concentration of impurities incorporated into the crystal will decrease, allowing for crystal growth without compromising crystal quality and suppressing the generation of basal plane dislocations. For example, preferably, the number of basal plane dislocations is 600 / cm². 2 More preferably 500 pieces / cm 2 More preferably, 400 pieces / cm 2 The following is true: A low number of basal plane dislocations improves the reliability and yield of SiC power devices.

[0028] (specific resistance) The resistivity of the single-crystal SiC layer in this embodiment is higher than that of commercially available single-crystal SiC. Specifically, the resistivity of the single-crystal SiC layer is 30 mΩ·cm or higher, preferably 1830 mΩ·cm or lower, more preferably 30 mΩ·cm or higher and 1000 mΩ·cm or lower, and more preferably 30 mΩ·cm or higher and 500 mΩ·cm or lower. As a result, the on-resistance of the vertical SiC power device can be sufficiently reduced compared to when a commercially available single-crystal SiC substrate is used alone as a support substrate. On the other hand, compared to a SiC junction substrate with a commercially available single-crystal SiC transfer layer, the on-resistance of the vertical SiC power device increases slightly, but the increase can be kept to 1% or less, so the increase in on-resistance is almost negligible.

[0029] Generally, a lower resistivity is considered desirable for a SiC junction substrate, and a resistivity of around 10 mΩ·cm for the polycrystalline substrate is preferable. When manufacturing a vertical SiC power device using a SiC junction substrate obtained by bonding a single-crystal SiC layer, which has a higher resistivity than commercially available single-crystal SiC, to a polycrystalline substrate with a resistivity of around 10 mΩ·cm, it is possible to set the resistivity of the single-crystal SiC layer to around 215 mΩ·cm in order to keep the increase in the on-resistivity of the vertical SiC power device within 1%. Furthermore, assuming that the resistivity of the polycrystalline substrate can be around 1 mΩ·cm, the maximum resistivity of the single-crystal SiC layer that can keep the increase in the on-resistivity of the manufactured vertical SiC power device within 1% is acceptable is up to 1830 mΩ·cm. When using a single-crystal SiC layer with such high resistivity, crystal defects such as through-helix dislocations and basal plane dislocations can also be reduced.

[0030] While using the single-crystal SiC layer in this embodiment alone as a support substrate is difficult for SiC semiconductor devices such as vertical SiC power devices due to its high resistivity, it can be used as a support substrate for SiC semiconductor devices when used in combination with a low-resistivity polycrystalline SiC substrate to form a SiC junction substrate.

[0031] (Thickness) The thickness of the single-crystal SiC layer is preferably 0.1 μm or more and less than 3.0 μm. A thickness within this range allows it to adequately serve as a base layer for forming a single-crystal SiC epitaxial film layer, while also providing significant cost advantages. Considering the strength of the single-crystal SiC layer and the ease of transfer to the polycrystalline SiC layer by forming and peeling off the hydrogen ion layer, the thickness is more preferably 0.4 μm or more and 1.0 μm or less, and even more preferably 0.5 μm or more and 0.9 μm or less.

[0032] However, if the thickness of the single-crystal SiC layer is less than 0.1 μm, for example, when considering its use as a substrate in the manufacturing of a single-crystal SiC epitaxial film layer by the CVD method, there is a high risk that the single-crystal SiC layer may disappear due to etch-back of the single-crystal SiC substrate during the initial stages of crystal growth. Furthermore, since the single-crystal SiC layer and the polycrystalline SiC layer are bonded and laminated, the thicker the single-crystal SiC layer is relative to the product thickness, the greater the stress between the two layers constituting the substrate, which may lead to greater warping of the SiC bonded substrate. In addition, if the thickness of the single-crystal SiC layer is thicker than 1 μm, the number of times the original single-crystal SiC substrate can be reused decreases, and the cost benefits may not be fully realized, so it is desirable that the thickness be 1 μm or less.

[0033] For single-crystal SiC layers, for example, single-crystal SiC fabricated by the modified Rayleigh process can be used. Furthermore, from the viewpoint of obtaining high-quality single-crystal SiC, high-quality single-crystal SiC epitaxial thin films can be effectively obtained by using single-crystal SiC manufactured by solution growth, high-temperature gas growth, CVD, or a combination thereof.

[0034] <Polycrystalline SiC layer> The polycrystalline SiC layer is a layer that supports the single-crystal SiC layer and can act as a handle component that protects the single-crystal SiC layer when handling the SiC junction substrate. Furthermore, in vertical SiC power devices, for example, the polycrystalline SiC layer is n + It functions as a layer. As a SiC semiconductor substrate, it needs a certain thickness and strength, and it can play a role in ensuring these.

[0035] (Nitrogen doping concentration) The polycrystalline SiC layer has lower resistance than the single-crystal SiC layer, and even lower resistance than commercially available single-crystal SiC, therefore the nitrogen doping concentration is 3 × 10⁻⁶. 19 atoms / cm 3 The above 2 x 10 20 atoms / cm 3The following is preferable: The nitrogen doping concentration of the polycrystalline SiC layer is 3 × 10⁻⁶ 19 atoms / cm 3 If the nitrogen doping concentration is less than 2 × 10, the resistivity of the polycrystalline SiC layer will increase, which may prevent the reduction in the on-resistance of the vertical SiC power device. 20 atoms / cm 3 As the density increases, the nitrogen solid solubility limit of 3C-SiC is reached, so nitrogen is not incorporated, and the resistivity plateaus. Although doping with nitrogen up to the solid solubility limit does not cause any particular problems in terms of electrical conductivity, it may worsen the processability of the crystal, so 5 × 10⁻¹⁶ is preferable. 19 atoms / cm 3 The above is 1 x 10 20 atoms / cm 3 The following applies:

[0036] (specific resistance) Furthermore, the resistivity of the polycrystalline SiC layer is linked to the range of nitrogen doping concentration, preferably being 1 mΩ·cm or more and 10 mΩ·cm or less, and more preferably 3 mΩ·cm or more and 5 mΩ·cm or less. This allows for a significant reduction in the on-resistance of the vertical SiC power device compared to using a commercially available single-crystal SiC substrate as the support substrate alone. On the other hand, compared to a SiC junction substrate with a commercially available single-crystal SiC transfer layer, the on-resistance of the vertical SiC power device increases slightly, but the increase can be kept to 1% or less, so the increase in on-resistance is almost negligible.

[0037] For the polycrystalline SiC layer, for example, polycrystalline SiC with an average grain size of 0.1 μm to 10 μm as viewed from the bonding surface (joint surface) where the single-crystal SiC layers are bonded can be used. Such an average grain size is common for polycrystalline SiC and is not difficult to obtain.

[0038] The thickness of the polycrystalline SiC layer is preferably 100 μm to 700 μm, and more preferably 150 μm to 550 μm, and even more preferably 350 μm, considering ease of handling and strength as a handle member.

[0039] The polycrystalline SiC used in the polycrystalline SiC layer can be any molded body mainly composed of polycrystalline 3C-SiC, and may also contain 4H, 6H, or 15-SiC. There are no particular limitations on the manufacturing method. Examples of manufacturing methods for polycrystalline SiC include atmospheric pressure sintering using a sintering aid, atmospheric pressure sintering, hot pressing, hot isostatic pressing (HIP), chemical vapor deposition (CVD), and reaction sintering (RS).

[0040] As long as the thickness ranges of the single-crystal SiC layer and the polycrystalline SiC layer are as described above, there is no problem with the SiC junction substrate having these stacked structures, but it is preferable that the thickness of the SiC junction substrate is between 101 μm and 551 μm.

[0041] In the SiC junction substrate of this embodiment, the single-crystal SiC layer and the polycrystalline SiC layer may be directly bonded and stacked. For example, by employing a method that uses a hydrogen atom ablation technique (also known as SmartCut®) to bond a thick single-crystal SiC substrate to a polycrystalline SiC layer, and then separating them to transfer a thin single-crystal SiC layer onto the polycrystalline SiC layer, a SiC junction substrate in which the single-crystal SiC layer and the polycrystalline SiC layer are directly bonded can be obtained.

[0042] <SiC bonded substrate 100> Figure 1 is a schematic perspective view of a SiC junction substrate 100, which is shown as an example of a SiC junction substrate in this embodiment. The SiC junction substrate 100 comprises a single crystal SiC layer 10 and a polycrystalline SiC layer 20, and has a structure in which the polycrystalline SiC layer 20 and the single crystal SiC layer 10 bonded thereto are stacked.

[0043] (Single-crystal SiC layer 10) The single-crystal SiC layer 10 is, for example, 0.1 μm to 1 μm thick and disc-shaped with the same diameter as the polycrystalline SiC layer 20. For example, it is formed as a 6-inch disc with a thickness of about 1 μm. The single-crystal SiC of the single-crystal SiC layer 10 can be composed of 4H-SiC crystal, 6H-SiC crystal, or 3C-SiC crystal. Note that 1 inch is equal to 25.4 mm.

[0044] (Polycrystalline SiC layer 20) As the polycrystalline SiC layer 20, for example, a layer formed from polycrystalline SiC deposited by the CVD method can be used, and a disc shape with a thickness of 100 μm to 550 μm and a diameter of 4 inches to 8 inches can be used. For example, it can be formed as a 6-inch disc with a thickness of about 350 μm. The polycrystalline SiC of the polycrystalline SiC layer 20 can be a mixture mainly composed of 3C-SiC crystals with either 4H-SiC crystals, 6H-SiC crystals, or 15-SiC.

[0045] If, for example, the surface 21 of the polycrystalline SiC layer 20 is the surface that bonds with the bonding surface 11 of the single-crystal SiC layer 10, then the opposite surface 22 of the surface 21 is the surface that does not bond with the single-crystal SiC layer 10. When forming a single-crystal SiC epitaxial thin film by CVD, the opposite surface 22 becomes the surface that contacts the susceptor. There is no particular difference between the surface 21 and the opposite surface 22; the opposite surface 22 may also be the surface that bonds with the bonding surface 11 of the single-crystal SiC layer 10. In this case, the surface 21 is the surface that does not bond with the single-crystal SiC layer 10, and the surface 21 becomes the surface that contacts the susceptor.

[0046] The crystal orientation of the surface 12 of the single-crystal SiC layer 10 is not particularly limited. However, for example, when using a disc-shaped wafer with the c-axis direction as the main plane and a 4° off-angle in the {11-20} direction, similar to commercially available single-crystal 4H-SiC substrates, as the single-crystal SiC layer 10, it is desirable to have the C-plane side as the opposite plane and the Si plane as the surface 12. That is, if the opposite plane is the bonding surface 11 that bonds with the polycrystalline SiC layer 20, then the surface 12 on the opposite side is the plane that does not bond with the polycrystalline SiC layer 20, and when forming a single-crystal SiC epitaxial thin film by CVD, the surface 12 becomes the plane on which the single-crystal SiC epitaxial thin film grows. Note that the surface 12 may also be the plane that bonds with the polycrystalline SiC layer 20. In this case, the opposite plane is the plane that does not bond with the polycrystalline SiC layer 20, and this opposite plane becomes the plane on which the single-crystal SiC epitaxial thin film grows.

[0047] <SiC bonded substrate 110> The SiC junction substrate of this embodiment may further comprise a single-crystal SiC epitaxial film layer laminated on a single-crystal SiC layer. Figure 2 is a schematic perspective view of a SiC junction substrate 110 comprising a single-crystal SiC epitaxial film layer 30. The single-crystal SiC epitaxial film layer 30 has the same crystal structure as the single-crystal SiC layer 10 that serves as the growth base, and a CVD method may be used for its formation. Surface 31 is the interface between the single-crystal SiC epitaxial film layer 30 and the single-crystal SiC layer 10, and the opposite surface 32 is the surface on which electrodes for SiC power devices are formed.

[0048] (Surface curvature) In this embodiment, the warpage of the SiC bonded substrate is preferably 56 m or more in terms of radius of curvature. Specifically, the warpage of the polycrystalline SiC layer can be measured, for example, as the warpage of the opposite surface 22, which is the surface not bonded to the single-crystal SiC layer 10 in Figure 1. Also, in Figure 2, the warpage of the opposite surface 22 can be measured. The radius of curvature can be measured using a laser interferometer or the like.

[0049] When the above-mentioned warp has a radius of curvature of 56m or more, it is possible to prevent defects in the lithography process and cracks or chips in the semiconductor substrate during handling. From the viewpoint of ensuring more stable productivity, the above-mentioned warp has a radius of curvature of preferably 142m or more, and more preferably 187m or more.

[0050] The SiC bonded substrate of this embodiment is a composite structure of single-crystal SiC and polycrystalline SiC. Since these are the same type of material, their coefficients of thermal expansion are almost the same, and therefore, warping due to thermal processes during manufacturing does not occur. However, warping of the SiC bonded substrate may occur due to the shape preparation process during the manufacturing process to shape the SiC bonded substrate into the desired form, so it is important to appropriately control this warping.

[0051] The processing methods required to create the shape of the SiC bonded substrate are not particularly limited. For example, in the case of polycrystalline SiC, a bulk molded polycrystalline SiC body is first obtained, and then a polycrystalline SiC layer is obtained through processing methods such as grinding with a diamond grinding wheel, polishing with a slurry containing diamond abrasive particles, or chemical mechanical polishing (CMP). Alternatively, the shape of the polycrystalline SiC may be controlled by combining the above processing methods after bonding polycrystalline SiC with single-crystal SiC to form a SiC bonded substrate.

[0052] [Manufacturing method for SiC bonded substrates] Next, regarding the SiC bonded substrate of this embodiment, an example of its manufacturing method will be described using the SiC bonded substrate 100 shown in Figure 1. The SiC bonded substrate 100 can be manufactured by a bonding process that bonds a polycrystalline SiC layer 20 to a separately prepared single-crystal SiC layer 10. It is desirable that these bonding methods satisfy conditions such as mechanically strong bonding across the entire bonding surface, thermal and chemical stability, and a simple bonding process, and that no dissimilar material is inserted as an intermediate layer. For example, from the viewpoint of bonding single-crystal SiC and polycrystalline SiC with different morphologies, a direct bonding method that does not use adhesive materials such as adhesives or low-melting-point metals may be used.

[0053] [Semiconductor devices] The semiconductor device of this embodiment comprises the SiC junction substrate of this embodiment. Examples of semiconductor devices include vertical power devices such as SBDs and MOSFETs. Figure 3 shows a schematic cross-sectional view of a MOSFET, which is an example of a semiconductor device.

[0054] The semiconductor device 150 is constructed by stacking, in order, a drain electrode 80, a polycrystalline SiC layer 20, a single-crystal SiC layer 10, a single-crystal SiC epitaxial film layer 30, and a semiconductor element component 50 formed on the single-crystal SiC epitaxial film layer 30.

[0055] Here, the semiconductor element components 50 are not particularly limited, but for example, a source electrode 51, a gate electrode 52, a gate insulating film 53, and N + It consists of source 54 and P well 55.

[0056] Furthermore, the semiconductor device 150 is a semiconductor device for vertical power devices in which the direction of current conduction is in the thickness direction of the substrate, and has a structure in which a drain electrode 80 is formed as a back electrode.

[0057] [Method for manufacturing SiC single crystal ingots] An example of a manufacturing method for the SiC single crystal ingot that forms the basis of the single crystal SiC layer in this embodiment will be described. The manufacturing method for the SiC single crystal ingot includes the following growth steps.

[0058] <Growth process> In the growth process, a SiC single crystal is grown on a seed substrate 200 made of single-crystal SiC, for example, by sublimation recrystallization, to produce a SiC single-crystal ingot. Figure 4 is a schematic cross-sectional view of the SiC single-crystal growth apparatus 300 before SiC single-crystal growth is performed by sublimation recrystallization. The SiC single-crystal growth apparatus 300 is not limited to its heating method and may use either high-frequency induction heating or resistance heating. In the example shown in Figure 4, an example of high-frequency induction heating is shown.

[0059] The base 40 of the seed substrate 200 is fixed to the graphite crucible lid 310, and the graphite crucible lid 310 is held on top of the graphite crucible 320, which is made of graphite. The method of holding the components such as the base 40, graphite crucible 320, and graphite crucible lid 310 is not particularly limited as long as it does not cause displacement of these components during the growth of the SiC single crystal ingot. For example, these components may be fixed using an adhesive containing carbon filler, or the structure of the components may be such that each component is fixed by the structural design of the components.

[0060] The graphite crucible 320 is filled with SiC powder 330, which serves as a precursor for growing SiC single crystal ingots. The form of the SiC powder 330 is not limited; for example, SiC powder formed by the Acheson method or CVD method, then crushed, washed, and classified can be used. However, it is preferable that the nitrogen content in the SiC powder used for crystal growth be 0.1 ppm to 50 ppm, preferably 0.5 ppm to 10 ppm. Using the SiC powder, by using argon or a mixed gas of hydrogen and nitrogen with a nitrogen gas ratio of 0% to 5%, the nitrogen uptake amount of the grown single crystal SiC ingot is increased to 1 × 10⁻¹⁶. 17 atoms / cm 3 The above 3 x 10 18 atoms / cm 3 The nitrogen doping concentration can be controlled as follows: If the amount of nitrogen in the SiC powder is greater than 50 ppm, the amount of nitrogen incorporated into the grown single-crystal SiC ingot will be 3 × 10⁻¹⁰ even when the nitrogen gas ratio in the mixed gas of argon and nitrogen gas is set to 0%. 18 atoms / cm 3 Because the amount becomes greater than this, it may be unsuitable as a single-crystal SiC layer in this embodiment. If the nitrogen content in the SiC powder is less than 0.1 ppm, the manufacturing cost when synthesizing the SiC powder becomes extremely high, so it is preferable to avoid this. With this manufacturing method, the nitrogen doping concentration of the single-crystal SiC can be controlled by balancing the nitrogen gas that serves as the nitrogen source and the nitrogen concentration contained in the SiC raw material, so that a single-crystal SiC ingot that will serve as the basis for the single-crystal SiC layer in this embodiment can be obtained.

[0061] The graphite crucible 320 is equipped with a SiC sublimation gas transport unit 340 that transports sublimation gas generated from the SiC powder 330 to the seed substrate 200. The SiC single crystal growth apparatus 300 may also be provided with a tapered guide 350 to control the shape of the growing SiC single crystal ingot and the rectification of the SiC sublimation gas. The shape and holding method of the tapered guide 350 are not limited; for example, it may be shaped to increase in diameter at a constant rate from top to bottom of the graphite crucible 320, that is, in the growth direction of the growing SiC single crystal ingot.

[0062] The graphite crucible 320 and the graphite crucible lid 310 are fixed by an insulating material 360 that covers the body, bottom, and lid from the outside. The insulating material 360 is made of a material that can withstand the growth temperature of SiC single crystal ingots, which is 2000°C to 2400°C, and molded insulating material made of carbon felt or a molded body thereof is used. In the SiC single crystal growth apparatus 300, the insulating material 360 is housed in a cylindrical quartz tube 370 and has a high-frequency coil 380 on its outer circumference.

[0063] When growing SiC single crystals, a constant amount of argon gas is flowed into the graphite crucible 320 as an inert gas, while the inside of the graphite crucible 320 is reduced in pressure using a vacuum pump, and the graphite crucible 320 is heated under these conditions.

[0064] Examples of manufacturing conditions for SiC single crystal ingots include setting the growth temperature to 2000°C or higher and 2300°C or lower, the growth pressure to 1 Torr or higher and 10 Torr or lower, using argon or a mixed gas of hydrogen and nitrogen with a nitrogen gas ratio of 0% or higher and 5% or lower, and setting the nitrogen concentration in the SiC raw material used for crystal growth to 0.1 ppm or higher and 50 ppm or lower.

[0065] Figure 5 is a schematic cross-sectional view of the SiC single crystal growth apparatus 300 after growing a SiC single crystal ingot 500. The SiC single crystal growth layer 400 is a SiC single crystal grown by the growth process, and the SiC polycrystalline attachment growth section 410 is a SiC polycrystal that has grown again after sublimation gas generated from the raw material SiC powder 330 by the growth process adheres to the graphite crucible lid 310.

[0066] Furthermore, the growth process may involve the modified Rayleigh process, or the sublimation recrystallization method derived from the modified Rayleigh process. For example, any of the following methods may be used: PVT (Physical Vapor Transport), M-PVT (Modified-PVT), CF-PVT (Continuous Feeding PVT), HT-CVD (High Temperature Chemical Vapor Deposition), H-CVD (Halogenated-CVD), or SS (Sublimation Sandwich).

[0067] An example of a SiC single crystal ingot 500 obtained by the growth process is a SiC single crystal ingot 500 comprising a single crystal SiC layer 10 described in this embodiment and a SiC single crystal growth layer 400 grown on the single crystal SiC layer 10.

[0068] <Cutting process> This process involves cutting out at least a portion of the SiC single crystal growth layer 400 obtained in the growth process so that it is separate from at least a portion of the base 40 to obtain a SiC single crystal ingot 500.

[0069] The SiC single crystal growth layer 400 can be cut out by removing the SiC single crystal growth layer 400, along with the graphite crucible lid 310, from the SiC single crystal growth apparatus 300 and using a wire electrical discharge machine or the like. Examples of cut-out portions include the interface between the seed substrate 200 and the SiC single crystal growth layer 400, and desired portions of the SiC single crystal growth layer 400. By slicing these portions, a SiC single crystal ingot 500 can be cut out. It is important that the SiC single crystal ingot 500 is processed so as not to include the SiC polycrystalline attached growth portion 410.

[0070] <Other processes> The method for manufacturing seed substrates for SiC single crystal ingots according to this embodiment may include steps other than those described above. For example, steps to prepare for the growth process include attaching the base 40 to the graphite crucible lid 310, creating a reduced-pressure atmosphere inside the graphite crucible 320 using a vacuum pump while flowing a certain amount of argon gas as an inert gas into the graphite crucible 320, and heating the graphite crucible 320 under reduced pressure.

[0071] [Manufacturing method for SiC bonded substrates] The manufacturing method of the SiC junction substrate of this embodiment includes a transfer step of transferring a SiC single crystal thin film from the SiC single crystal ingot cut out in the above cutting step to a SiC polycrystalline substrate.

[0072] Specifically, a delamination technique using hydrogen atom ablation (also known as SmartCut®) can be used. One method involves first bonding a SiC single crystal ingot to a SiC polycrystalline substrate (bonding step), then separating a thin sheet of SiC single crystal from the SiC single crystal ingot, and transferring the thin sheet of SiC single crystal substrate to the SiC polycrystalline substrate (transfer step).

[0073] Furthermore, the manufacturing method of the SiC bonded substrate in this embodiment may include, in addition to the bonding and transfer processes described above, a polishing process for the bonding surface, a phosphorus ion implantation process, a hydrogen ion implantation process, and the like. [Examples]

[0074] The present invention will be further described below with reference to examples, but it is not limited in any way to the following examples.

[0075] [Example 1] <Preparation of 500 SiC single crystal ingots> In Example 1, a SiC single crystal was used as the seed substrate 200, and a SiC single crystal ingot was fabricated using the modified Rayleigh method. Specifically, a wafer-shaped SiC single crystal with a diameter of 6 inches and a thickness of 0.5 mm was used as the seed substrate 200. A carbonized adhesive layer was formed using carbon adhesive by firing, and the seed substrate 200 was attached and fixed to the base 40. In the process of growing the SiC single crystal ingot using the modified Rayleigh method (growth process), a high-frequency induction heating type SiC single crystal growth apparatus 300 was used. The growth temperature for growing the SiC single crystal ingot was set to 2300°C. Crystals were grown by flowing a fixed amount of a mixed gas of argon gas as an inert gas and N2 gas as a dopant into a graphite crucible 320, while heating the crucible 320 under reduced pressure of 600 Torr using a vacuum pump to raise the temperature inside the crucible 320 to 2300°C, then reducing the pressure to 2.5 Torr, and maintaining the pressure. The N2 gas concentration in the mixed gas of argon gas and N2 gas was set to 0.1 volume%. The growth time for SiC single crystal ingot 500 was 150 hours, and a 4H-SiC single crystal ingot with an effective length and thickness of 15 mm was obtained. Here, effective length refers to the growth thickness from the surface of the seed crystal to the point where a SiC single crystal ingot 500 with a diameter equivalent to that of the seed crystal was obtained.

[0076] <Fabrication of single-crystal SiC substrates> The SiC single crystal ingot 500 and seed substrate 200 were separated from the base, and multiple wafer-shaped SiC single crystals were cut using a wire saw to a thickness of 0.7 to 5.2 mm. The front and back surfaces were then ground and polished. The crystal growth surface of the SiC single crystal ingot 500 was the C-plane, and the bonding surface (joining surface) with the polycrystalline SiC layer 20 was the Si-plane. The C-plane was polished using CMP to obtain a single-crystal SiC substrate.

[0077] (Measurement of nitrogen doping concentration) The nitrogen doping concentration in single-crystal SiC substrates was measured using secondary ion mass spectrometry (SIMS).

[0078] (Measurement of resistivity) The resistivity of a single-crystal SiC substrate was measured using the eddy current method.

[0079] Table 1 shows the nitrogen doping concentration, resistivity, and N2 gas concentration in a mixed gas of argon and N2 for single-crystal SiC substrates.

[0080] <Fabrication of polycrystalline SiC layer 20> A polycrystalline SiC film with a thickness of 2.0 to 5.5 mm was deposited on the surface of a carbon-based disc substrate using chemical vapor deposition (CVD) with a deposition apparatus. Methylchlorosilane was used as the raw material gas, and hydrogen and nitrogen gases were used as carrier gases. The growth temperature in this chemical vapor deposition method was 1400°C. Subsequently, the substrate was heated and removed in an atmospheric atmosphere at 1000°C by combustion, and a 6-inch diameter disc-shaped polycrystalline SiC film was fabricated. The polycrystalline SiC film was ground using a surface grinder and polished using a double-sided polishing apparatus to obtain a polycrystalline SiC substrate which would become the polycrystalline SiC layer 20.

[0081] (Measurement of resistivity) The resistivity of a polycrystalline SiC substrate was measured using the eddy current method.

[0082] (Measurement of film thickness) The film thickness of a polycrystalline SiC substrate was measured at 10 points using a non-contact film thickness gauge, and the average film thickness was calculated.

[0083] Table 2 shows the average resistivity and film thickness of polycrystalline SiC substrates.

[0084] <Fabrication of SiC junction substrate 100> Using the manufactured single-crystal SiC substrate and polycrystalline SiC layer 20, a SiC junction substrate 100 was fabricated using a delamination technique by hydrogen atom ablation (also known as SmartCut®).

[0085] Hydrogen ions were implanted into the bonding surface of the single-crystal SiC substrate to be bonded with the polycrystalline SiC layer 20, forming a hydrogen ion implantation layer at a depth of 1.0 μm from the bonding surface. The SiC single-crystal substrate and the polycrystalline SiC layer 20 were attracted by an electrostatic chuck and set in the chamber. Next, the electrostatic chuck was moved to align the relative positions of the single-crystal SiC substrate and the polycrystalline SiC layer 20 so that the two substrates could contact each other in the correct position at room temperature. Next, the chamber was moved 2 × 10⁻¹⁰ -6 The chamber was subjected to a vacuum of Pa. Next, a neutral argon atom beam was uniformly irradiated onto the entire surface of the single-crystal SiC substrate and the entire surface of the polycrystalline SiC layer 20 using a FAB gun to remove the oxide film and adsorbed layer on both surfaces, exposing the bonding bonds and activating them. Then, while maintaining a vacuum at room temperature, the surface of the single-crystal SiC substrate and the surface of the polycrystalline SiC layer 20 were brought into contact under vacuum within the chamber by moving an electrostatic chuck, thereby directly bonding them by covalent bonding to obtain a SiC bonded substrate.

[0086] Next, using a furnace, the bonded substrate was heated to 1000°C in an inert atmosphere filled with argon gas to form a microbubble layer in the hydrogen ion implantation layer. The single-crystal SiC substrate was then separated by the microbubble layer, and a thin, plate-like single-crystal SiC layer 10 with a thickness of 1.0 μm was transferred to the polycrystalline SiC layer 20.

[0087] The surface of the single-crystal SiC layer 10, exposed by the transfer process, was smoothed by CMP polishing. This resulted in obtaining a SiC junction substrate 100.

[0088] (Measurement of film thickness of single-crystal SiC layer 10) The film thickness of the single-crystal SiC layer 10 was measured at 10 points using a non-contact film thickness gauge, and the average film thickness was calculated.

[0089] (Measurement of threading helical dislocations in single-crystal SiC layer 10) Using an X-ray topography system (XRTmicron) manufactured by Rigaku Corporation, through image analysis of measurement images obtained from the 11-28 diffraction plane of 4H-SiC as a reflection measurement, the threading helical dislocations in the single-crystal SiC layer 10 were identified, and 1 cm 2 The number of displacements per unit was measured.

[0090] (Measurement of basal plane dislocations in single-crystal SiC layer 10) Using an X-ray topography system (XRTmicron) manufactured by Rigaku Corporation, basal plane dislocations of the single-crystal SiC layer 10 were identified by image analysis of measurement images obtained from the 11-28 diffraction plane of 4H-SiC as a reflection measurement. 2 The number of displacements per unit was measured.

[0091] Table 2 shows the average thickness, through-helic dislocations, and basal plane dislocation measurements for the single-crystal SiC layer 10.

[0092] (Simulation of 150 semiconductor devices) A SiC junction substrate 100 structure was formed as a simulation model. The SiC junction substrate 100 was used as a support substrate for a semiconductor device, and a single-crystal SiC epitaxial film layer 30 on the surface of the single-crystal SiC substrate was made 10 μm thick. A circuit pattern was formed on the surface of the single-crystal SiC epitaxial film layer 30 as a component 50 of the semiconductor device. The thickness of the polycrystalline SiC layer 20 was 180 μm. A drain electrode 80 was formed as a back electrode, and a MOSFET model was created as the semiconductor device 150.

[0093] (Simulation of the on-resistance of 150 semiconductor devices) The on-resistance of semiconductor device 150 can be calculated as the sum of the resistances of the polycrystalline SiC layer and the single-crystal layer, with drift resistance, buffer layer resistance, channel resistance, and other resistances (including electrode and interface resistances) as common elements. Here, the measured drift resistance is 0.921 mΩ·cm. 2 The buffer layer resistance is 0.0075 mΩ·cm. 2 The channel resistance is 0.660 mΩ·cm. 2The resistance of the polycrystalline SiC layer was calculated from the resistivity and thickness of the polycrystalline SiC. The resistance of the single-crystal SiC layer was calculated from the resistivity and thickness of the single-crystal SiC.

[0094] (Evaluation of the yield of 150 semiconductor devices) The yield of semiconductor device 150 was calculated using a Poisson distribution, where D is the defect density and A is the chip area, and Y = exp(-DA). Here, the defect density considered the contributions of through-helix dislocations and basal plane dislocations. Among the through-helix dislocations, those with a large edge component formed by the merging of a through-helix dislocation and multiple through-edge dislocations during crystal growth become killer defects that generate reverse bias leakage current; however, the killer defect rate of the through-helix dislocation density was set at 0.1%. Furthermore, since 99.99% of basal plane dislocations are converted into through-edge dislocations that do not have adverse effects under the assumption of epitaxial growth, the killer defect rate of basal plane dislocations was set at 0.01%. The chip area was set to 0.5 cm square.

[0095] Table 2 shows the average thickness, on-resistance measurement results, and yield evaluation results for 150 semiconductor devices.

[0096] [Example 2] Except for setting the N2 gas concentration in the mixed gas of argon and N2 gas to 1 volume%, a SiC single crystal ingot 500 was prepared in the same manner as in Example 1, and a SiC junction substrate 100 and a semiconductor device were fabricated. Measurements were also performed in the same manner as in Example 1.

[0097] [Example 3] Except for setting the N2 gas concentration in the mixed gas of argon and N2 gas to 1.5 volume%, a SiC single crystal ingot 500 was prepared in the same manner as in Example 1, and a SiC junction substrate 100 and a semiconductor device were fabricated. Measurements were also performed in the same manner as in Example 1.

[0098] [Example 4] Except for setting the N2 gas concentration in the mixed gas of argon and N2 gas to 2 volume%, a SiC single crystal ingot 500 was prepared in the same manner as in Example 1, and a SiC junction substrate 100 and a semiconductor device were fabricated. Measurements were also performed in the same manner as in Example 1.

[0099] [Comparative Example 1] The SiC junction substrate in Comparative Example 1 is an existing device support substrate used in the manufacture of MOSFETs, and Comparative Example 1 is an example for comparing the on-resistance and yield in Examples 1 to 4.

[0100] In Comparative Example 1, a SiC single crystal ingot 500 was prepared in the same manner as in Example 1, except that the N2 gas concentration in the mixed gas of argon gas and N2 gas was set to 5 volume%, and a SiC junction substrate 100 and a semiconductor device were fabricated. Measurements were also performed in the same manner as in Example 1.

[0101] [Comparative Example 2] Comparative Example 2 is an example in which a single-crystal SiC substrate is used instead of a SiC junction substrate as a support substrate for the device. The single-crystal SiC substrate in Comparative Example 2 is an existing device substrate used in the manufacture of MOSFETs, and Comparative Example 2 is an example for comparing the on-resistance and yield in Examples 1 to 4.

[0102] In Comparative Example 2, a single-crystal SiC substrate with an average film thickness of 350 μm was fabricated using a SiC single-crystal ingot 500 prepared in the same manner as in Comparative Example 1, by the same method as in Example 1. This single-crystal SiC substrate was used as a support substrate for a semiconductor device, and a MOSFET was manufactured as a semiconductor device by forming a SiC single-crystal epitaxial layer, forming a circuit pattern, protecting it with resin, grinding the back surface, and forming a drain electrode, in the same manner as the manufacturing method of semiconductor device 150.

[0103] [Comparative Example 3] Comparative Example 3 is an example in which a single-crystal SiC substrate is used instead of a SiC junction substrate as a device support substrate. The single-crystal SiC substrate in Comparative Example 3 has a nitrogen doping concentration equivalent to that of the single-crystal SiC layer of the present invention, but it is a substrate with a low nitrogen doping concentration for use as a device substrate in the manufacture of MOSFETs. When the single-crystal SiC substrate of Comparative Example 3 is used alone as a device support substrate, the on-resistance of the MOSFET increases, so this example is for comparing the on-resistance and yield with Examples 1 to 4.

[0104] In Comparative Example 3, a single-crystal SiC substrate with an average film thickness of 350 μm was fabricated using a SiC single-crystal ingot 500 prepared in the same manner as in Example 4, by the same method as in Example 1. This single-crystal SiC substrate was used as a support substrate for a semiconductor device, and a MOSFET was manufactured as a semiconductor device by forming a SiC single-crystal epitaxial layer, forming a circuit pattern, protecting it with resin, grinding the back surface, and forming a drain electrode, in the same manner as the manufacturing method of semiconductor device 150.

[0105] Similar to Example 1, the conditions and results for Examples 2-4 and Comparative Examples 1-3 are shown in Tables 1 and 2. Furthermore, the on-resistance values ​​are shown using the on-resistance of Comparative Example 1 or Comparative Example 2 as a baseline, and the increase or decrease in the on-resistance of Examples 1-4, etc., from these baselines is indicated in [Comparison with Comparative Example 1 (%)] and [Comparison with Comparative Example 2 (%)].

[0106] [Table 1]

[0107] [Table 2]

[0108] [Results and Discussion] The results from Examples 1 to 4 showed that when producing SiC single crystal ingot 500, increasing the N2 gas concentration in the mixed gas of argon and N2 gas increased the nitrogen doping concentration and decreased the resistivity, while simultaneously increasing the number of through-helix dislocations and basal plane dislocations.

[0109] As shown in Comparative Example 3, it was clear, in comparison with Comparative Example 2, that using the single-crystal SiC substrates of Examples 1-4 alone as support substrates for semiconductor devices instead of SiC junction substrates increased the on-resistance of the MOSFETs. The support substrate in Comparative Example 3 was unsuitable for use as a substrate for semiconductor device applications.

[0110] However, as shown in Examples 1 to 4, even a single-crystal SiC substrate similar to that in Comparative Example 3 can be combined with a polycrystalline SiC substrate to form a SiC junction substrate, and this can be used as a support substrate for semiconductor devices. For example, compared to Comparative Example 2, which is already in practical use as a support substrate for semiconductor devices, Examples 1 to 4 all showed lower on-resistance and yields that were equal to or better than those of the Comparative Example 2.

[0111] On the other hand, the SiC junction substrate of Comparative Example 1 is a commercially available support substrate for semiconductor devices. While the on-resistance of Examples 1 to 4 varied from 0% to 0.66% compared to Comparative Example 1, with some examples showing a slight increase, all of them exhibited lower on-resistance than the commercially available Comparative Example 2, and were capable of performing sufficiently as MOSFETs. Furthermore, the yield for Examples 1 to 4 was equivalent to or better than that for Comparative Example 1.

[0112] These results demonstrate that even single-crystal SiC substrates, which were previously impractical as support substrates for semiconductor devices due to their high resistivity, can be processed into SiC junction substrates comprising single-crystal SiC layers and polycrystalline SiC layers. This SiC junction substrate can then be fully utilized as a support substrate for semiconductor devices.

[0113] In the conventional market, there was no incentive to use single-crystal SiC substrates with higher resistivity than the single-crystal SiC substrate of Comparative Example 2, which is already in practical use, for semiconductor device applications. Therefore, the idea of ​​applying the single-crystal SiC substrates of Examples 1-4, which have higher resistivity than Comparative Example 2, as support substrates for semiconductor devices was not considered. However, these results clearly demonstrate that even single-crystal SiC substrates with higher resistivity than Comparative Example 2 can be effectively utilized as support substrates for semiconductor devices by using them to create SiC junction substrates. [Explanation of Symbols]

[0114] 10: Single-crystal SiC layer, 11: Junction surface, 12: Surface, 20: Polycrystalline SiC layer, 21: Surface, 22: Opposite surface, 30: Single-crystal SiC epitaxial film layer, 31: Surface, 32: Opposite surface, 40: Base, 50: Component, 51: Source electrode, 52: Gate electrode, 53: Gate insulating film, 54: N + Source, 55: P-well, 80: Drain electrode, 100: SiC junction substrate, 110: SiC junction substrate, 150: Semiconductor device, 200: Seed substrate, 300: SiC single crystal growth apparatus, 310: Graphite crucible lid, 320: Graphite crucible, 330: SiC powder, 340: SiC sublimation gas transport section, 350: Tapered guide, 360: Insulation material, 370: Quartz tube, 380: High-frequency coil, 400: SiC single crystal growth layer, 410: SiC polycrystalline adhesion growth section, 500: SiC single crystal ingot

Claims

1. A single-crystal SiC layer, A polycrystalline SiC layer is provided, The resistivity of the single-crystal SiC layer is 30 mΩ·cm or more and 1830 mΩ·cm or less. A SiC junction substrate in which the resistivity of the polycrystalline SiC layer is 1 mΩ·cm or more and 10 mΩ·cm or less.

2. The SiC junction substrate according to claim 1, comprising a single-crystal SiC epitaxial film layer laminated on the single-crystal SiC layer.

3. A semiconductor device comprising a SiC junction substrate as described in claim 2.

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