Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing a decrease in breakdown voltage of a transistor, and a manufacturing method thereof.SOLUTION: A semiconductor device 100 includes: a substrate 1; a groove 2 formed on a main surface of the substrate 1; a gate insulating film 3 disposed on an internal surface of the groove 2; a gate electrode 4 formed inside the groove 2 via the gate insulating film 3; a drift region 5 formed in contact with a side of the groove 2; a well region 6 formed in contact with the side of the groove 2 and the drift region 5; a source region 7 formed in contact with the side of the groove 2 and the well region 6; a source electrode 12 electrically connected to the source region 7; a drain region 8 formed in contact with the drift region 5; a drain electrode 13 electrically connected to the drain region 8; and an anode electrode 10 electrically connected to the source electrode 12, the anode electrode being in contact with the drift region 5. The anode electrode 10 is formed on the well region 6 or on the source region 7 in a plan view of the main surface of the substrate 1.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Conventionally, a semiconductor device is known in which a trench formed inside to form a gate electrode and a trench formed inside to form a Schottky barrier diode are provided adjacent to each other, and a channel region is provided between the gate electrode and the electrode of the Schottky barrier diode (Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the adjacent trench structure described in Patent Document 1, due to the voltage applied to the electrode of the Schottky barrier diode, a depletion layer spreads from the Schottky diode to the channel region, which may reduce the breakdown voltage of the transistor.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that can suppress a decrease in the breakdown voltage of a transistor.

Means for Solving the Problems

[0006] A semiconductor device according to one aspect of the present invention comprises a substrate, a first groove formed on the main surface of the substrate, a gate insulating film disposed on the inner wall surface of the first groove, a gate electrode formed inside the first groove via the gate insulating film, a drift region of a first conductivity type formed in contact with the main surface and the side surface of the first groove, a well region of a second conductivity type formed in contact with the main surface, the side surface of the first groove and the drift region, a source region of a first conductivity type formed in contact with the main surface, the side surface of the first groove and the well region, a source electrode electrically connected to the source region, a drain region of a first conductivity type formed in contact with the drift region, a drain electrode electrically connected to the drain region, and an anode electrode electrically connected to the source electrode and in contact with the drift region, forming a unipolar diode with the drift region, wherein the anode electrode is formed on the well region or the source region in a plan view of the main surface. The substrate has an impurity concentration lower than the drift region. [Effects of the Invention]

[0007] According to the present invention, it is possible to suppress the breakdown voltage of the transistor. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view of a semiconductor device 100 according to the first embodiment of the present invention. [Figure 2] Figure 2 shows a cross-sectional view of AA in Figure 1. [Figure 3] Figure 3 shows a cross-sectional view of BB in Figure 1. [Figure 4] Figure 4 shows a cross-sectional view of the CC shown in Figure 1. [Figure 5] Figure 5 is a diagram illustrating a method for manufacturing a semiconductor device 100 according to a first embodiment of the present invention. [Figure 6] Figure 6 illustrates a method for manufacturing a semiconductor device 100 according to a first embodiment of the present invention. [Figure 7] Figure 7 illustrates a method for manufacturing a semiconductor device 100 according to a first embodiment of the present invention. [Figure 8]Figure 8 is a plan view of a semiconductor device 100 according to a second embodiment of the present invention. [Figure 9] Figure 9 shows a cross-sectional view of the DD shown in Figure 8. [Figure 10] Figure 10 illustrates a method for manufacturing a semiconductor device 100 according to a second embodiment of the present invention. [Figure 11] Figure 11 is a diagram illustrating a method for manufacturing a semiconductor device 100 according to a second embodiment of the present invention. [Figure 12] Figure 12 illustrates a method for manufacturing a semiconductor device 100 according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals and their descriptions are omitted. In the following description, the definitions of "top" and "bottom" such as "top surface" and "bottom surface" are merely matters of representation on the illustrated cross-sectional view. For example, if the orientation of the semiconductor device is changed by 90° and observed, the designations "top" and "bottom" become "left" and "right," and of course, if it is changed by 180° and observed, the relationship between the designations "top" and "bottom" will be reversed. In this embodiment, the N type is described as the first conductivity type and the P type as the second conductivity type, but the P type may be described as the first conductivity type and the N type as the second conductivity type.

[0010] (First Embodiment) (Configuration of a semiconductor device) The configuration of the semiconductor device 100 according to the first embodiment will be described with reference to Figures 1 to 4. Figure 1 shows a plan view of the semiconductor device 100. Figure 2 shows a cross-sectional view AA of Figure 1. Figure 3 shows a cross-sectional view BB of Figure 1. Figure 4 shows a cross-sectional view CC of Figure 1. As shown in Figures 1 to 4, the semiconductor device 100 comprises a substrate 1, a plurality of grooves 2, a gate insulating film 3, a gate electrode 4, a drift region 5, a well region 6, a source region 7, a drain region 8, an anode electrode 10, a source electrode 12, and a drain electrode 13. However, for the sake of explanation, the source electrode 12 and the drain electrode 13 are omitted from Figure 1.

[0011] Substrate 1 is a semi-insulating substrate made of silicon carbide. The resistivity of the semi-insulating substrate is several kΩ / cm or more. Although there are multiple polytypes (crystalline polymorphs) of silicon carbide, in this embodiment it will be described as the representative 4H. As shown in Figure 2, substrate 1 has grooves 2 (first grooves) formed on the main surface (top surface) so as to extend in one direction (X axis direction). In Figure 1, three grooves 2 are formed, but this is just an example and is not limited to three. As shown in Figures 1 to 4, a well region 6 (P type), a drift region 5 (N type), a drain region 8 (high concentration N type), and a source region 7 (high concentration N type) are formed on the main surface of substrate 1.

[0012] As shown in Figure 2, a gate insulating film 3 is formed on the inner wall surface of the groove 2. A gate electrode 4 is formed via the gate insulating film 3 so as to fill the inside of the groove 2. The gate electrode 4 is also in contact with the source region 7, the well region 6, and the drift region 5 via the gate insulating film 3. The drift region 5 is formed to be in contact with the main surface of the substrate 1 and the side surface of the groove 2. The well region 6 is formed to be in contact with the main surface of the substrate 1, the side surface of the groove 2, and the drift region 5. As shown in Figures 2 and 4, the depth of the gate electrode 4 in the vertical direction (Z-axis direction) is deeper than the depth of the drift region 5, and the end (bottom surface) of the gate electrode 4 is in contact with the substrate 1.

[0013] As shown in FIGS. 1 to 3, a source electrode 12 is formed which is electrically connected to the source region 7, the well region 6, and the opening formed in the interlayer insulating film 14. The source region 7 is formed so as to contact the main surface of the substrate 1, the side surface of the groove 2, and the well region 6. As shown in FIG. 3, the anode electrode 10 is electrically connected to the source electrode 12 and is formed so as to be surrounded by the well region 6 or the source region 7 in a plan view of the main surface of the substrate 1. In FIG. 1, the left-right direction (Y-axis direction) of the anode electrode 10 is formed so as to be surrounded by the well region 6, and the up-down direction (X-axis direction) is formed so as to be surrounded by the well region 6, but it is not limited thereto. The anode electrode 10 may be formed so that the up-down direction and the left-right direction are surrounded by the well region 6 in a plan view of the main surface of the substrate 1, or may be formed so that the up-down direction and the left-right direction are surrounded by the source region 7. In other words, the anode electrode 10 may be formed on the well region 6 or the source region 7 in a plan view of the main surface of the substrate 1.

[0014] The drain region 8 is formed so as to contact the drift region 5. The drain electrode 13 is formed so as to be electrically connected to the drain region 8. Also, the drain electrode 13 is formed away from the source electrode 12. The anode electrode 10 is formed on the main surface of the substrate 1. As shown in FIG. 3, the anode electrode 10 contacts the drift region 5 at the back surface of the anode electrode 10 (directly below the anode electrode 10) and forms a Schottky junction with the drift region 5. The anode electrode 10 forms a unipolar type diode with the drift region 5. Also, as shown in FIG. 3, in the horizontal direction (X-axis direction) of the main surface of the substrate 1, a well region 6 is formed between the interface between the anode electrode 10 and the drift region 5 (the surface that contacts the drift region 5 directly below the anode electrode 10) and the drain region 8.

[0015] (Operation example of semiconductor device) The basic operation of the semiconductor device 100 will be described. The semiconductor device 100 functions as a transistor by controlling the potential of the gate electrode 4 with a positive potential applied to the drain electrode 13 with reference to the potential of the source electrode 12. That is, when the voltage between the gate electrode 4 and the source electrode 12 is made equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel region of the well region 6 on the side of the gate electrode 4, and thus it is in the on state, and current flows from the drain electrode 13 to the source electrode 12. On the other hand, when the voltage between the gate electrode 4 and the source electrode 12 is made lower than the predetermined threshold voltage, the inversion layer disappears and it is in the off state, and the current is cut off.

[0016] The operation (current flow) of the semiconductor device 100 when it is off will be described. When a positive voltage is applied to the source electrode 12 and a negative voltage is applied to the drain electrode 13 (when the MOSFET is off), a depletion layer extends from the pn junction between the well region 6 and the drift region 5 and the interface between the anode electrode 10 and the drift region 5. At this time, since the anode electrode 10 is closer to the drift region 5 than the gate electrode 4, the depletion layer extending from the anode electrode 10 can cover the gate electrode 4, and it becomes possible to relieve the electric field concentration at the end of the gate electrode 4. At this time, since the pn junction interface covers the end of the anode electrode 10, the electric field concentration at the end of the anode electrode 10 is relieved and the leakage current is reduced.

[0017] (Method of manufacturing a semiconductor device) Next, an example of a manufacturing method for the semiconductor device 100 will be described with reference to Figures 5-7. First, as shown in Figure 7, a semi-insulating substrate (substrate 1) made of silicon carbide with a low impurity concentration is ion-implanted to form P-type well regions 6, N-type drift regions 5, high-concentration N-type drain regions 8, and high-concentration N-type source regions 7 in areas patterned with a mask material. In the ion implantation process, nitrogen can be used as the N-type impurity, and aluminum or boron can be used as the P-type impurity. At this time, by performing ion implantation with the substrate temperature heated to about 600°C, the occurrence of crystal defects in the implanted regions can be suppressed. The drift regions 5 and well regions 6 preferably have a concentration of 1E15 / cm³ to 1E19 / cm³. Next, the ion-implanted impurities are activated by heat treatment. A heat treatment temperature of about 1700°C can be used, and argon or nitrogen can preferably be used as the atmosphere.

[0018] Next, as shown in Figure 6, a patterned mask material is formed, and grooves 2 are formed by dry etching. Then, as shown in Figure 7, the gate insulating film 3 and gate electrode 4 are formed inside grooves 2. The gate insulating film 3 can be formed by thermal oxidation or deposition. As an example of the conditions for thermal oxidation, the substrate 1 is heated to about 1100°C in an oxygen atmosphere, so that a silicon oxide film is formed in all parts of the substrate that come into contact with oxygen. After forming the gate insulating film 3, annealing at about 1000°C in an atmosphere of nitrogen, argon, N2O, etc. may be performed to reduce the interface state at the interface between the well region 6 and the gate insulating film 3. It is also possible to form the gate insulating film 3 by thermal oxidation in an NO or N2O atmosphere. In that case, a temperature of 1100°C to 1400°C is preferable. The thickness of the formed gate insulating film 3 is preferably several tens of nanometers.

[0019] Next, the gate electrode 4 is deposited. Polysilicon is commonly used as the material for the gate electrode 4, and this explanation will use polysilicon. Vacuum CVD may be used as the method for depositing polysilicon. The thickness of the deposited polysilicon should be greater than half the width of the groove 2, completely filling the groove 2 with polysilicon. For example, if the width of the groove 2 is 2 μm, the thickness of the polysilicon should be greater than 1 μm. After depositing the polysilicon, annealing in POCl3 at 950°C forms N-type polysilicon, giving conductivity to the gate electrode 4. Next, the interlayer insulating film 14 is deposited. An example of the interlayer insulating film 14 is a silicon oxide film, but it is not limited to this, and a silicon nitride film may also be used.

[0020] Next, a contact hole is formed at the interface between the anode electrode 10 and the drift region 5, using the patterned resist material as a mask. Then, the metal material that will become the anode electrode 10 is deposited on the main surface of the substrate 1. The metal material is deposited on the main surface of the substrate 1 while leaving the resist film used as the mask material for the contact hole. Next, the substrate 1 that has undergone each of the above processes is immersed in, for example, acetone to perform a lift-off treatment that removes the resist film and the metal material on the resist film. For example, titanium, molybdenum, nickel, etc., can be used for the anode electrode 10.

[0021] Next, source electrode contact holes and drain electrode contact holes are formed in the interlayer insulating film 14 by patterning with a resist and dry etching. Then, a metallic material, such as aluminum, is deposited on the main surface of the substrate 1 to fill the contact holes, and the source electrode 12 and drain electrode 13 are formed by patterning. Metal wiring is commonly used as the electrode material. The metal can be Ti, Ni, or Mo. Alternatively, a multilayer metal made of Ti, Ni, Ag, etc., may also be used.

[0022] (Effects and Benefits) As described above, the semiconductor device 100 according to the first embodiment provides the following effects and advantages.

[0023] The semiconductor device 100 includes a substrate 1, a first groove (groove 2) formed on the main surface of the substrate 1, a gate insulating film 3 disposed on the inner wall surface of the first groove, a gate electrode 4 formed inside the first groove via the gate insulating film 3, a drift region 5 of a first conductivity type formed to be in contact with the main surface of the substrate 1 and the side surface of the first groove, a well region 6 of a second conductivity type formed to be in contact with the main surface of the substrate 1, the side surface of the first groove, and the drift region 5, a source region 7 of a first conductivity type formed to be in contact with the main surface of the substrate 1, the side surface of the first groove, and the well region 6, a source electrode 12 electrically connected to the source region 7, a drain region 8 of a first conductivity type formed to be in contact with the drift region 5, a drain electrode 13 electrically connected to the drain region 8, and an anode electrode 10 electrically connected to the source electrode 12 and in contact with the drift region 5, forming a unipolar diode with the drift region 5. The anode electrode 10 is formed on the well region 6 or the source region 7 in a plan view of the main surface of the substrate 1. In the semiconductor device 100, since the anode electrode 10 is formed away from the drain region 8, the channel near the drift region 5 is not depleted, the threshold voltage drop when integrated is suppressed, and the breakdown voltage of the transistor is suppressed. Furthermore, since the anode electrode 10 is adjacent to the well region 6 or source region 7 connected to the source electrode 12, the electric field concentration at the end of the anode electrode 10 when a reverse diode voltage is applied is mitigated, making it possible to reduce leakage current.

[0024] The substrate 1 may be semi-insulating or insulating. This makes it possible to reduce leakage current from the electrodes formed on the main surface of the substrate 1 to the back surface.

[0025] The substrate 1 may be formed of silicon carbide. This improves the drain and source breakdown voltage.

[0026] The anode electrode 10 and gate electrode 4 may be formed from polysilicon. This improves the ability of the electrodes to be embedded in the groove.

[0027] When manufacturing the semiconductor device 100, the anode electrode 10 and the gate electrode 4 may be formed at the same time. This makes it possible to reduce the manufacturing time.

[0028] (Second Embodiment) (Configuration of a semiconductor device) The configuration of the semiconductor device 100 according to the second embodiment will be described with reference to Figures 8-9. The difference between the second embodiment and the first embodiment is that a groove 9 (second groove) is formed, and the anode electrode 10 is formed inside this groove 9. The position where the groove 9 is formed is the same position where the anode electrode 10 is formed in the first embodiment. Components that overlap with the first embodiment are denoted by reference numerals and their explanations are omitted. The following explanation will focus on the differences. For the sake of explanation, the source electrode 12 and drain electrode 13 are not shown in Figures 8-9.

[0029] Figure 8 shows a plan view of the semiconductor device 100. Figure 9 shows a DD cross-sectional view of Figure 1. As shown in Figure 9, the groove 9 is formed on the main surface of the substrate 1. In Figure 9, two grooves 9 are formed, but this is just an example and is not limited to two. As shown in Figure 9, the depth of the groove 9 is greater than the depth of the drift region 5. Also, the depth of the groove 9 is greater than the depth of the well region 6. The anode electrode 10 is formed inside the groove 9 so as to be embedded. At the interface between the side surface of the groove 9 and the drift region 5, which is formed deeper than the well region 6, the anode electrode 10 forms a heterojunction diode with the drift region 5.

[0030] (Example of semiconductor device operation) The basic operation of the semiconductor device 100 will now be described. The semiconductor device 100 functions as a transistor by controlling the potential of the gate electrode 4 while a positive potential is applied to the drain electrode 13, with the potential of the source electrode 12 as a reference. That is, when the voltage between the gate electrode 4 and the source electrode 12 is raised above a predetermined threshold voltage, an inversion layer is formed in the channel region of the well region 6 on the side of the gate electrode 4, causing it to turn on, and current flows from the drain electrode 13 to the source electrode 12. On the other hand, when the voltage between the gate electrode 4 and the source electrode 12 is raised below a predetermined threshold voltage, the inversion layer disappears, causing it to turn off and interrupting the current.

[0031] The operation (current flow) of the semiconductor device 100 when it is off will be explained. When a positive voltage is applied to the source electrode 12 and a negative voltage is applied to the drain electrode 13 (when the MOSFET is off), a depletion layer extends from the pn junction between the well region 6 and the drift region 5 and from the interface between the anode electrode 10 and the drift region 5. At this time, the groove 9 containing the anode electrode 10 is formed deeper than the drift region 5, and since the depth-direction end is in a substrate with a low impurity concentration, electric field concentration at the depth-direction end is mitigated, making it possible to suppress the breakdown voltage of the transistor. Furthermore, when it is on, current flows from the source side to the drain side via a parasitic Schottky diode formed on the side of the groove 9, without going through the parasitic pn diode formed in the well region 6 and the drift region 5. In other words, when it is on, only the parasitic Schottky diode among the body diodes formed in the substrate 1 operates, and the parasitic pn diode does not operate. Therefore, aging degradation due to the parasitic pn diode turning on and operating bipolar does not occur.

[0032] (Method of manufacturing semiconductor devices) Next, an example of a manufacturing method for the semiconductor device 100 will be described with reference to Figures 10-12. First, as shown in Figure 10, well regions 6, drift regions 5, drain regions 8, and source regions 7 are formed by ion implantation in a semi-insulating substrate (substrate 1) made of silicon carbide with a low impurity concentration, in the areas patterned with a mask material. Next, as shown in Figure 11, a patterned mask material is formed, and grooves 2 and 9 are formed by dry etching.

[0033] Next, as shown in Figure 12, a gate insulating film 3 is formed inside grooves 2 and 9. Then, a resist is applied to the main surface of the substrate 1, and only the area of ​​groove 9 is opened by photolithography. Then, the gate insulating film 3 formed inside groove 9 is removed by wet etching. Next, the gate electrode 4 and anode electrode 10 are deposited. An example of a material is polysilicon. Vacuum CVD may be used as the method for depositing polysilicon. The thickness of the deposited polysilicon should be greater than half the width of the groove, so that the groove is completely filled with polysilicon. For example, if the width of the groove is 2 μm, the thickness of the polysilicon should be greater than 1 μm. After polysilicon deposition, boron is doped by ion implantation and annealed at 950°C to form P-type polysilicon, which gives conductivity to the gate electrode 4 and anode electrode 10.

[0034] Next, polysilicon is removed from the main surface of substrate 1 by anisotropic etching, leaving polysilicon only inside grooves 2 and 9. Then, an interlayer insulating film is deposited. An example of an interlayer insulating film is a silicon oxide film, but it is not limited to this; a silicon nitride film may also be used. Then, source electrode contact holes, drain electrode contact holes, anode electrode contact holes, and gate electrode contact holes are formed in the interlayer insulating film by patterning with a resist and dry etching. Next, a metallic material, such as aluminum, is deposited on the main surface of substrate 1, filling the contact holes formed in the interlayer insulating film, and the source electrode 12, drain electrode 13, and gate wiring are formed by patterning. Metal wiring is commonly used as the electrode material. The metal may be Ti, Ni, or Mo. Alternatively, a multilayer metal composed of Ti, Ni, Ag, etc., may also be used.

[0035] (Effects and Benefits) As described above, the semiconductor device 100 according to the second embodiment provides the following effects and advantages. Effects and advantages common to the first embodiment are omitted.

[0036] The semiconductor device 100 further includes a second groove (groove 9) formed on the main surface of the substrate 1. The anode electrode 10 is formed inside the second groove. This shortens the current path in the drift region 5 and reduces the drift resistance.

[0037] As shown in Figure 9, the depth of the second groove (groove 9) is greater than the depth of the well region 6. This allows the sides of the second groove to also form a diode with the drift region 5, thereby improving the current capacity of the diode.

[0038] Substrate 1 has a lower impurity concentration than drift region 5, and the depth of the second groove (groove 9) is greater than the depth of drift region 5. This reduces electric field concentration at the depth-direction end of the anode electrode 10, improving the diode breakdown voltage.

[0039] As described above, embodiments of the present invention have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure. [Explanation of Symbols]

[0040] 1 Substrate, 2,9 Grooves, 3 Gate insulating film, 4 Electrode, 5 Drift region, 6 Well region, 7 Source region, 8 Drain region, 10 Anode electrode, 11 Field relaxation region, 12 Source electrode, 13 Drain electrode, 14 Interlayer insulating film

Claims

1. circuit board and A first groove formed on the main surface of the substrate, A gate insulating film disposed on the inner wall surface of the first groove, A gate electrode formed inside the first groove via the gate insulating film, A first conductive drift region formed so as to be in contact with the main surface and the side surface of the first groove, A second conductive well region formed to be in contact with the main surface, the side surface of the first groove, and the drift region, A first conductive source region formed to be in contact with the main surface, the side surface of the first groove, and the well region, A source electrode electrically connected to the source region, A drain region of the first conductivity type formed in contact with the drift region, A drain electrode electrically connected to the drain region, The system comprises an anode electrode that is electrically connected to the source electrode and in contact with the drift region, and that forms a unipolar diode with respect to the drift region, The anode electrode is formed on the well region or the source region in a plan view of the main surface. The substrate has an impurity concentration lower than that of the drift region. A semiconductor device characterized by the following features.

2. The substrate further comprises a second groove formed on the main surface of the substrate, The anode electrode is formed inside the second groove. The semiconductor device according to feature 1.

3. The depth of the second groove is greater than the depth of the well region. The semiconductor device according to claim 2.

4. The depth of the second groove is greater than the depth of the drift region. The semiconductor device according to claim 2 or 3, characterized by the features described above.

5. The substrate is semi-insulating or insulating. A semiconductor device according to any one of claims 1 to 4.

6. The substrate is formed of silicon carbide. A semiconductor device according to any one of claims 1 to 5.

7. The anode electrode and the gate electrode are formed of polysilicon. A semiconductor device according to any one of claims 1 to 6.

8. The anode electrode and the gate electrode are formed together. The method for manufacturing a semiconductor device according to claim 7.

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