Semiconductor device, and method for manufacturing a semiconductor device.

Abstract

The present invention prevents defective embedding of metal in a semiconductor device in which through-vias are formed.　The semiconductor device according to the present invention comprises a substrate, an etching stopper layer, a die, and an isolation film. In this semiconductor device, a rewiring layer is formed on the substrate. The etching stopper layer is formed on a joining surface of the rewiring layer. The die is joined to a partial region of the joining surface with the etching stopper layer therebetween. The isolation film covers the die and the etching stopper layer.

Description

Technical Field

[0001] The present technology relates to semiconductor devices. More specifically, it relates to semiconductor devices having a stacked structure and a method of manufacturing semiconductor devices.

Background Art

[0002] In recent years, due to the high functionality of devices, the development of a technique for stacking devices having different functions fabricated on separate semiconductor substrates has been underway. When stacking these, it is necessary to electrically connect the upper and lower devices after joining the semiconductor substrates. For example, a semiconductor device has been proposed in which wafers and dies each including a semiconductor substrate are stacked, and the devices on the wafer and the die are electrically connected by through vias (see, for example, Patent Document 1). When manufacturing this semiconductor device, after stacking the dies, an isolation film including an etching stopper layer is formed, and then through vias are formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-described conventional technology, it is easy to stack a large number of dies by a via last process. However, in the above-described semiconductor device, when performing additional etching after etching up to the etching stopper layer, the additional etched portion bulges and becomes arcuate, and there is a risk of poor metal filling in the arcuate portion when forming through vias.

[0005] The present technology has been created in view of such a situation, and an object thereof is to prevent poor metal filling in a semiconductor device in which through vias are formed. [Means for solving the problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a semiconductor device comprising a substrate on which a redistribution layer is formed, an etching stopper layer formed on the bonding surface of the redistribution layer, a die bonded to a portion of the bonding surface via the etching stopper layer, and an isolation film covering the die and the etching stopper layer, as well as a method for manufacturing the same. This has the effect of preventing metal embedding defects.

[0007] Furthermore, in this first aspect, the substrate may further include a substrate-side via that penetrates the isolation film and the etching stopper layer and has one end connected to the wiring in the redistribution layer, and a die-side via that penetrates the isolation film, the die, and the etching stopper layer and has one end connected to the wiring in the redistribution layer. This results in the substrate being electrically connected to the die, and the substrate being electrically connected to the outside.

[0008] Furthermore, in this first aspect, the die-side via may be formed at a location that does not correspond to the end of the die. This results in the die and the substrate being electrically connected at a location that does not correspond to the end.

[0009] Furthermore, in this first aspect, the die-side via may be formed at the end of the die. This results in a reduction in the die-side area of ​​the through-via and the die-side electrode pad area.

[0010] Furthermore, in this first aspect, the etching rate when etching the etching stopper layer with a predetermined etching gas may be lower than the etching rate when etching the isolation film with the etching gas. This results in the etching stopping at the etching stopper layer when etching the isolation film.

[0011] Furthermore, in this first aspect, the isolation film is a silicon oxide film, and the etching stopper layer may be a layer of silicon nitride, silicon carbide, or silicon carbonitride. This results in the etching stopping at the etching stopper layer when etching the isolation film.

[0012] Furthermore, a second aspect of this technology is a semiconductor device comprising a substrate on which a redistribution layer is formed, a die bonded to a portion of the bonding surface of the redistribution layer, a first isolation film covering the die and the redistribution layer, a second isolation film, and an etching stopper layer formed between the first and second isolation films and having a step near the end of the die, and a method for manufacturing the same. This has the effect of preventing metal embedding defects.

[0013] Furthermore, in this second aspect, the substrate may further include vias that penetrate the first and second isolation films and the etching stopper layer, with one end connected to the wiring in the redistribution layer, and die-side vias that penetrate the first and second isolation films, the etching stopper layer, and the die, with one end connected to the wiring in the redistribution layer. This results in the substrate being electrically connected to the die, and the substrate being electrically connected to the outside.

[0014] Furthermore, in this second aspect, the die-side via may be formed at a location that does not correspond to the end of the die. This results in the die and the substrate being electrically connected at a location that does not correspond to the end.

[0015] Furthermore, in this second aspect, the die-side via may be formed at the end of the die. This results in a reduction in the die-side area of ​​the through-via and the die-side electrode pad area. [Brief explanation of the drawing]

[0016] [Figure 1] A cross-sectional view showing a configuration example of a wafer in the first embodiment of the present technology. [Figure 2] A cross-sectional view showing a configuration example of a wafer in a comparative example. [Figure 3] An example of a cross-sectional view of a wafer with sidewalls formed in a comparative example. [Figure 4] A diagram for explaining the procedure up to the embedding of metal in a comparative example. [Figure 5] An example of a cross-sectional view of a wafer with embedding failure in a comparative example. [Figure 6] A diagram for explaining the procedure up to the CMP (Chemical Mechanical Polishing) of the isolation film in the first embodiment of the present technology. [Figure 7] A diagram for explaining the procedure up to the etching of the redistribution layer on the die side in the first embodiment of the present technology. [Figure 8] A diagram for explaining the procedure up to the embedding and CMP of metal in the first embodiment of the present technology. [Figure 9] A flowchart showing an example of a method for manufacturing a semiconductor device in the first embodiment of the present technology. [Figure 10] A diagram for explaining the procedure up to the CMP of the isolation film in the second embodiment of the present technology. [Figure 11] A diagram for explaining the procedure up to the removal of the etching stopper layer in the second embodiment of the present technology. [Figure 12] A diagram for explaining the procedure up to the embedding and CMP of metal in the second embodiment of the present technology. [Figure 13] A cross-sectional view showing a configuration example of a wafer in the third embodiment of the present technology. [Figure 14] A diagram for explaining the procedure up to the formation of the etching stopper layer in the third embodiment of the present technology. [Figure 15]This is a diagram for explaining the procedure up to the etching of the substrate in the third embodiment of the present technology. [Figure 16] This is a diagram for explaining the procedure up to the metal embedding and CMP in the third embodiment of the present technology. [Figure 17] This is a flowchart showing an example of a method for manufacturing a semiconductor device in the third embodiment of the present technology. [Figure 18] This is a diagram for explaining the procedure up to the formation of an etching stopper layer in the fourth embodiment of the present technology. [Figure 19] This is a diagram for explaining the procedure up to the etching of the substrate in the fourth embodiment of the present technology. [Figure 20] This is a diagram for explaining the procedure up to the metal embedding and CMP in the fourth embodiment of the present technology. [Figure 21] This is a block diagram showing a schematic configuration example of a vehicle control system. [Figure 22] This is an explanatory diagram showing an example of the installation position of an imaging unit.

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First Embodiment (Example in which an etching stopper layer is formed on the bonding surface) 2. Second Embodiment (Example in which an etching stopper layer is formed on the bonding surface and through vias are provided at the ends of the die) 3. Third Embodiment (Example in which a step is provided in the etching stopper layer) 4. Fourth Embodiment (Example in which a step is provided in the etching stopper layer and through vias are provided at the ends of the die) 5. Application Example to a Moving Body

[0018] <1. First Embodiment> [Example of Wafer Configuration] Figure 1 is a cross-sectional view showing an example configuration of a wafer 100 in a first embodiment of this technology. This wafer 100 includes a plurality of substrates 110. The dotted parallelograms in the figure represent the substrates 110. A redistribution layer 120 is formed on each substrate 110. Hereinafter, the direction from the substrate 110 to the redistribution layer 120 will be referred to as the "up" direction. The entire upper surface of the redistribution layer 120 will be referred to as the "bonding surface". Wirings 121, 122, etc., are routed on this redistribution layer 120.

[0019] Furthermore, a die 140, which includes a laminated substrate 142 and a redistribution layer 141, is laminated onto the wafer 100, which includes the substrate 110 and the redistribution layer 120. The substrate 110 on the wafer side and the substrate 142 on the die side are rectangular when viewed from above, and the area of ​​the substrate 110 on the wafer side is larger than that of the substrate 142 on the die side.

[0020] An etching stopper layer 130 is formed on the bonding surface of the redistribution layer 120. The die 140 is bonded to a portion of the bonding surface of the redistribution layer 120 via this etching stopper layer 130. In the figure, the region from coordinate X1 to coordinate X2 indicates the region to which the die 140 is bonded. On the die 140, the redistribution layer 141 is on the underside of the substrate 142, and this redistribution layer 141 is bonded to the bonding surface via the etching stopper layer 130. Wiring 143 and the like are also wired on the redistribution layer 141.

[0021] Furthermore, the tops of the die 140 and the etching stopper layer 130 are covered with an isolation film 151. Since the area of ​​the die 140 is smaller than that of the substrate 110 on the wafer side, the top and sides of the die 140 are covered with the isolation film 151.

[0022] Furthermore, the die 140 is electrically connected to the outside by a through-via 161. This through-via 161 penetrates the isolation film 151 on the top of the die 140 and the substrate 142 on the die side, with one end connected to the wiring 143 on the die side and the other end exposed on the upper surface of the isolation film 151.

[0023] Furthermore, the die 140 and the wafer 100 are electrically connected by a through via 162. This through via 162 penetrates the isolation film 151 on the upper part of the die 140, the die 140, and the etching stopper layer 130. One end of the through via 162 is connected to the wiring 121 on the wafer side, and the other end is exposed on the upper surface of the isolation film 151. The through via 162 is formed in a location that does not correspond to the edge of the die 140. In the figure, coordinates X1 and X2 correspond to the edge of the die 140. Note that the through via 162 is an example of a die-side via as described in the claims.

[0024] Furthermore, the wafer 100 is electrically connected to the outside by a through-via 163. This through-via 163 penetrates the isolation film 151 and etching stopper layer 130 on the side of the die 140, with one end connected to the wiring 122 on the wafer side and the other end exposed on the upper surface of the isolation film 151. Note that the through-via 163 is an example of a substrate-side via as described in the claims.

[0025] Here, the etching stopper layer 130 is a layer that stops etching when etching the isolation film 151, and has a different composition from the isolation film 151. As the material for this etching stopper layer 130, a material is used in which the etching rate when etching with a certain etching gas is lower than the etching rate when etching the isolation film 151 with that etching gas. For example, if a silicon oxide film is used as the isolation film 151, then one of the following layers, silicon nitride (SiN), silicon carbide (SiC), or silicon carbonitride (SiCN), is used as the etching stopper layer 130.

[0026] Furthermore, the etching stopper layer 130 is thinner than the isolation film 151. For example, the etching stopper layer 130 has a thickness of 50 nanometers (nm), and the isolation film 151 has a thickness of 5000 nanometers (nm).

[0027] The wafer 100 illustrated in the figure is divided into multiple wafer-level semiconductor packages by dicing. These semiconductor packages are then mounted on various semiconductor devices, such as solid-state image sensors.

[0028] Here, we consider a wafer in which the etching stopper layer 130 is not formed on the bonding surface, but rather on the upper part of the bonding surface, as a comparative example.

[0029] Figure 2 is a cross-sectional view showing one example configuration of wafer 100 in a comparative example. Details of this comparative example are described in Patent Document 1. In the comparative example, the etching stopper layer 130 is not formed on the bonding surface, but is formed on the upper part of the bonding surface. More specifically, the bonding surface of the redistribution layer 120 and the upper and side surfaces of the die 140 are covered with an isolation film 151. An etching stopper layer 130 is formed on the upper surface of this isolation film 151, and the upper surface of the etching stopper layer 130 is covered with an isolation film 152.

[0030] Furthermore, the etching stopper layer 130 in the comparative example has no steps. On the other hand, there is a step between the die 140 and the surrounding bonding surface. As a result, the distance d1 from the top surface of the die 140 to the etching stopper layer 130 and the distance d2 from the surrounding bonding surface of the die 140 to the etching stopper layer 130 are different values.

[0031] When manufacturing the comparative example wafer 100, the manufacturing system joins the die 140 and sequentially forms an isolation film 151, an etching stopper layer 130, and an isolation film 152. The manufacturing system then etches the upper isolation film 152 up to the etching stopper layer 130 to form openings 211, 212, and 213 (not shown). Openings 211 and 212 are formed on the top of the die 140, and opening 213 is formed on the wafer side around the die 140. Subsequently, the manufacturing system etches the exposed etching stopper layer 130 and etches the isolation films 151 below each of the openings 211 to 213 down to the redistribution layer 141 to form sidewalls 171 to 173.

[0032] Figure 3 is an example of a cross-sectional view of a wafer in which the sidewall 171 etc. have been formed in the comparative example. The dashed line in the figure indicates the plane at which the distance from the etching stopper layer 130 is d2. The openings 211 and 212 on the die side are etched up to the redistribution layer 141. On the other hand, the etching of the opening 213 on the wafer side stops at the dashed line in the middle of the isolation film 151.

[0033] Figure 4 is a diagram illustrating the procedure up to the metal embedding in the comparative example. In Figure 4, a shows a cross-sectional view of the area enclosed by the dotted line near the opening 213 illustrated in Figure 3.

[0034] As illustrated in Figure 4b, the manufacturing system etches the isolation film 152 and redistribution layer 120 below the opening 213 down to the wiring 122. Because the formation of the sidewall 173 stops at the dashed line, the area where additional etching is performed may become bowed.

[0035] As illustrated in figure c, the manufacturing system forms a metal (such as copper) seed layer 160 by BM (Balanced Magnetron) sputtering. Then, as illustrated in figure d, the manufacturing system fills the opening 213 with this metal by electroplating to form through vias 163. If there is a curved portion during this electroplating process, the metal may not fill into that portion, increasing the likelihood of step breakage. This poor metal filling can result in poor electrical connections between the wafer 100 and the outside.

[0036] Figure 5 shows an example of a cross-sectional view of wafer 100 in the comparative example where an embedding defect occurred. In the comparative example, depending on the conditions, an embedding defect may not occur as illustrated in Figure 2, but it may also occur as illustrated in Figure 5.

[0037] In contrast, as illustrated in Figure 1, the wafer 100 of the first embodiment, in which an etching stopper layer 130 is formed on the bonding surface, can prevent metal embedding defects during manufacturing. Next, the manufacturing method of the wafer 100 of the first embodiment will be described.

[0038] [Wafer manufacturing method] Figure 6 is a diagram illustrating the procedure up to CMP of the isolation film 151 in the first embodiment of this technology. As illustrated in figure a, the manufacturing system forms a 50 nanometer (nm) silicon nitride layer as an etching stopper layer 130 on the bonding surface of the redistribution layer 120 on the wafer side. The manufacturing system also manufactures a rectangular die 140 when viewed from above.

[0039] As illustrated in figure b, the manufacturing system directly bonds the die 140 to the redistribution layer 120 on the wafer side via the etching stopper layer 130. Alternatively, the die 140 can be bonded using a thin adhesive instead of direct bonding. In this case, the die 140 was made 300 micrometers (μm) thick for ease of handling, but if the transistor can operate after bonding, the thinner it is possible will make subsequent processes easier. For this reason, the manufacturing system grinds it down to a thickness of 1 micrometer (μm) using a grinder and polishes the top surface of the substrate 142 so that it is flat.

[0040] Then, as illustrated in figure c, the manufacturing system deposits a 5000 nanometer (nm) silicon oxide film as an isolation film 151 from the top surface of the die 140. This isolation film 151 on the top of the die 140 is higher than its surroundings by the thickness of the die 140.

[0041] Therefore, the manufacturing system applies a resist agent and exposes it to light to create an opening only at the top of the die 140, and then etches the isolation film 151 by dry etching.

[0042] This makes it possible to make the height of the isolation film 151 on the top of the die 140 and the surrounding portion of the isolation film 151 approximately the same, as illustrated in figure d. Subsequently, the manufacturing system performs CMP to eliminate any steps on the upper surface of the isolation film 151 and flatten it.

[0043] Figure 7 is a diagram illustrating the procedure up to etching the redistribution layer 141 on the die side in the first embodiment of this technology.

[0044] After the upper surface of the isolation film 151 is planarized, the manufacturing system applies a resist agent and exposes it, as illustrated in figure a, to create openings only in the through-via portions, and then etches the isolation film 151 by dry etching. This forms openings 211 to 213. At this time, the etching of the isolation film 151 stops at the silicon substrate 142 on the die side and at the etching stopper layer 130 on the wafer side. Unlike the third embodiment and comparative examples described later, in the first embodiment, the etching of the isolation film can be performed in a single step.

[0045] On the die side, the silicon substrate 142 is exposed, so the manufacturing system selects a gas to etch only the silicon and etches the substrate 142, as exemplified in figure b. Once the etching of the silicon is complete, silicon oxide is deposited as sidewalls 171 to 173 on the side walls of the openings 211 to 213 to insulate the metal that will fill those openings.

[0046] Subsequently, as illustrated in figure c, the manufacturing system etches the redistribution layer 141 by filling the die-side openings 211 and others with resist 220, leaving openings 212 and 213 corresponding to through-vias 162 and 163 that penetrate to the wafer side. At opening 212, the silicon oxide redistribution layer 141 is exposed, but its etching is stopped by the etching stopper layer 130.

[0047] As illustrated in the figure, by forming an etching stopper layer 130 on the bonding surface, it becomes unnecessary to stop the etching process midway through when etching the isolation film 151, as in the comparative example. This prevents the formation of arc-shaped portions during etching and prevents metal embedding defects.

[0048] Figure 8 is a diagram illustrating the procedure from metal embedding to CMP in the first embodiment of this technology.

[0049] As illustrated in Figure a, the manufacturing system removes the resist 220. Then, as illustrated in Figure b, the manufacturing system etches the redistribution layers 141 and 120 down to the electrode pads (not shown) on the wirings 143, 121, and 122.

[0050] Then, as illustrated in figure c, through vias 161 to 163 are formed. At this time, the manufacturing system creates a laminated structure by depositing titanium nitride and titanium, each to a thickness of 50 nanometers (nm), as a diffusion-blocking film to prevent the diffusion of metal (copper), and then deposits a thin film of copper to a thickness of 100 nanometers (nm) on top of it by sputtering. After that, the manufacturing system fills the openings 211 to 213 with copper by electroplating, and then removes the copper and diffusion-blocking layer covering the surface by CMP to obtain the shape shown in figure c.

[0051] Figure 9 is a flowchart showing an example of a semiconductor device manufacturing method in the first embodiment of this technology. The semiconductor device manufacturing system forms an etching stopper layer 130 on the bonding surface of the redistribution layer 120 on the wafer side (step S901), and bonds a die 140 to the bonding surface via the etching stopper layer 130 (step S902). Step S901 is an example of the etching stopper layer formation procedure described in the claims, and step S902 is an example of the bonding procedure described in the claims.

[0052] The manufacturing system then deposits an isolation film 151 that covers the die 140 and the etching stopper layer 130, and performs CMP (step S903). The manufacturing system etches the isolation film 151 to form openings 211 to 213 (step S904). The openings 211 and 212 on the die side penetrate the isolation film 151 and reach the die 140, while the opening 213 on the wafer side penetrates the isolation film 151 and reaches the etching stopper layer 130.

[0053] The opening 212 is an example of a die-side opening as described in the claims, and the opening 213 is an example of a substrate-side opening as described in the claims. Step S903 is an example of an isolation film deposition procedure as described in the claims.

[0054] Next, the manufacturing system etches the substrate 142 of the die 140 exposed at the openings 211 and 212 (step S905), and etches the redistribution layer 141 exposed at the opening 212 down to the etching stopper layer 130 (step S906).

[0055] The manufacturing system removes the etching stopper layer 130 exposed at openings 212 to 213 (step S907) and etches the exposed redistribution layer 120 (step S908).

[0056] The manufacturing system then forms through vias 161 to 163 by embedding metal (copper) into the openings 211 to 213 or by CMP (step S909). Step S909 is an example of the via formation procedure described in the claims.

[0057] The manufacturing system produces multiple semiconductor packages by dicing (step S910), and then manufactures a semiconductor device by mounting these semiconductor packages (step S911).

[0058] Thus, according to the first embodiment of this technology, since an etching stopper layer 130 is formed on the bonding surface, it is no longer necessary to stop the etching process midway when etching the isolation film 151, and the formation of a curved portion is eliminated. This prevents defects in metal embedding.

[0059] <2. Second Embodiment> In the first embodiment described above, the through via 162 on the die side was formed at a position away from the edge of the die 140. However, with this configuration, it is difficult to further reduce the area of ​​the through via 162 on the die side and the area of ​​the electrode pad on the die side. The wafer 100 in this second embodiment differs from the first embodiment in that the through via 162 is formed at the edge of the die 140.

[0060] Figure 10 is a diagram illustrating the procedure up to CMP of the isolation film 151 in a second embodiment of this technology. Each step up to CMP of the isolation film 151 in this second embodiment is the same as in the first embodiment.

[0061] Figure 11 is a diagram illustrating the procedure for removing the etching stopper layer 130 in a second embodiment of the present technology. In this second embodiment, as illustrated in figure a, the manufacturing system forms an opening 212 at the end of the die 140. Part of the opening 212 reaches the substrate 142 of the die 140, and the remainder reaches the etching stopper layer 130. The positions of the openings 211 and 213 in the second embodiment are the same as in the first embodiment.

[0062] The manufacturing system etches the silicon substrate 142 as illustrated in figure b, and removes the etching stopper layer 130 as illustrated in figure c.

[0063] Figure 12 is a diagram illustrating the procedure from metal embedding to CMP in a second embodiment of this technology.

[0064] The manufacturing system etches the redistribution layers 141 and 120 up to the respective electrode pads of wirings 143, 144, 121, and 122, as illustrated in figure a. The manufacturing system then forms through vias 161 to 163 by embedding metal (copper) or by CMP, as illustrated in figure b.

[0065] By opening the end of the die 140 to form through vias 162, the die-side area of ​​the through vias 162 and the area of ​​the electrode pads on the die side can be reduced compared to the first embodiment. This improves the flexibility of wiring within the die and allows for a reduction in die size. Furthermore, it eliminates the need to fill the die-side openings 211 and other openings with resist 220.

[0066] Thus, according to the second embodiment of this technology, since through vias 162 are formed at the end of the die 140, the area of ​​the through vias 162 on the die side and the area of ​​the electrode pads on the die side can be reduced.

[0067] <3. Third Embodiment> In the first embodiment described above, an etching stopper layer 130 was formed on the bonding surface of the redistribution layer 120, but the position of the etching stopper layer 130 is not limited to the bonding surface. The wafer 100 of this third embodiment differs from the first embodiment in that a stepped etching stopper layer 130 is formed on the upper part of the bonding surface.

[0068] Figure 13 is a cross-sectional view showing an example configuration of a wafer 100 in a third embodiment of this technology. In this third embodiment, the etching stopper layer 130 is not formed on the bonding surface of the redistribution layer 120, but is formed between the isolation film 151 and the isolation film 152 on the bonding surface. Furthermore, a step is provided in the etching stopper layer 130 at coordinate X3 near the edge of the die 140. This step is formed such that the height of the etching stopper layer 130 on the die side is higher than the etching stopper layer 130 on the wafer side. Due to this step, the distance from the substrate 142 on the die side to the etching stopper layer 130 and the distance from the redistribution layer 120 to the etching stopper layer 130 become approximately the same value d3.

[0069] The through-via 163 on the wafer side penetrates the isolation films 151 and 152 and the etching stopper layer 130, with one end connected to the wiring 122 in the redistribution layer 120. Similarly, the through-via 162 on the die side penetrates the isolation films 151 and 152, the etching stopper layer 130 and the die 140, with one end connected to the wiring 121 in the redistribution layer 120. The through-via 161 on the die side penetrates the isolation films 151 and 152, the etching stopper layer 130 and the substrate 142, with one end connected to the wiring 143 in the redistribution layer 141.

[0070] Furthermore, the distance from the top surface of the redistribution layer 141 to the electrode pad in the redistribution layer 120 and the distance from the etching stopper layer 130 to the electrode pad in the redistribution layer 120 are approximately the same value d4. As a result, the processing amount of the insulating film (redistribution layer and isolation film) is consistent, making processing easier.

[0071] The isolation membrane 151 is an example of the first isolation membrane described in the claims, and the isolation membrane 152 is an example of the second isolation membrane described in the claims.

[0072] Figure 14 is a diagram illustrating the procedure for forming the etching stopper layer 130 in a third embodiment of the present technology. As illustrated in figure a, the manufacturing system produces a rectangular die 140 when viewed from above. The etching stopper layer 130 is not formed on the bonding surface on the wafer side.

[0073] As illustrated in figure b, the manufacturing system directly bonds the die 140 to the redistribution layer 120 on the wafer side. Alternatively, the die 140 can be bonded using a thin adhesive instead of direct bonding.

[0074] Then, as illustrated in figure c, the manufacturing system deposits a 5000 nanometer (nm) silicon oxide film as an isolation film 151 from the top surface of the die 140.

[0075] Furthermore, as illustrated in figure d, the manufacturing system forms a 50 nanometer (nm) silicon nitride layer as an etching stopper layer 130.

[0076] Figure 15 is a diagram illustrating the procedure up to etching the substrate 142 in a third embodiment of this technology.

[0077] As illustrated in figure a, the manufacturing system deposits a 5000 nanometer (nm) silicon oxide layer as an isolation film 152 to cover the etching stopper layer 130. At this time, the isolation film 152 on top of the die 140 is higher than its surroundings by the thickness of the die 140.

[0078] Therefore, the manufacturing system applies a resist agent and exposes it to light, leaving only the top of the die 140 open, and then etches the isolation film 152 by dry etching.

[0079] This makes it possible to make the height of the isolation film 152 on the top of the die 140 and the surrounding part of the isolation film 152 nearly the same. Subsequently, the manufacturing system performs CMP to eliminate any steps on the upper surface of the isolation film 152 and flatten it.

[0080] As illustrated in figure b, after planarization, the manufacturing system applies a resist agent and exposes it to create an open shape only in the through-via area, and then etches the isolation film 152 by dry etching. This forms the openings 211 to 213. The thickness of the isolation film 152 differs between the top of the die 140 and the rest of the die, but etching of the top of the die 140 is stopped by the etching stopper layer 130 until the etching of the thicker part is completed.

[0081] The manufacturing system removes the resist and etches only the etching stopper layer 130 exposed at openings 211 to 213 with a different gas, and then removes the etching stopper layer 130. Then, the manufacturing system etches the isolation film 151 exposed at openings 211 to 213. At this time, due to the step of the etching stopper layer 130, the thickness of the etching stopper layer 130 (e.g., 300 nanometers) is the same on the top of the die 140 and around it. Therefore, when the etching reaches the redistribution layer 120, the substrate 142 on the die side is exposed.

[0082] On the die side, the silicon substrate 142 is exposed, so the manufacturing system selects a gas to etch only the silicon and etches the substrate 142, as illustrated in c in the figure.

[0083] As illustrated in the figure, by providing a step in the etching stopper layer 130, when etching the isolation film 151 after removing the etching stopper layer 130, it becomes unnecessary to stop the etching on the wafer side midway, as in the comparative example. This prevents the formation of a curved portion during etching and prevents metal embedding defects.

[0084] Figure 16 is a diagram illustrating the procedure from metal embedding to CMP in a third embodiment of this technology.

[0085] As illustrated in Figure a, the manufacturing system deposits silicon oxide as sidewalls 171 to 173 on the side walls of the openings 211 to 213 to insulate the metal that will fill those openings. Then, as illustrated in Figure b, the manufacturing system etches the redistribution layers 141 and 120 down to the electrode pads (not shown) on the wirings 143, 121 and 122.

[0086] Then, as illustrated in figure c, through vias 161 to 163 are formed.

[0087] Figure 17 is a flowchart showing an example of a semiconductor device manufacturing method in a third embodiment of the present technology. The manufacturing system bonds a die 140 to the bonding surface of the redistribution layer 120 on the wafer side (step S921), and deposits an isolation film 151 that covers the die 140 and the redistribution layer 120 (step S922). Step S921 is an example of the first isolation film deposition procedure described in the claims.

[0088] The manufacturing system then forms an etching stopper layer 130 having a step near the end of the die 140 (step S923), deposits an isolation film 152 covering the etching stopper layer 130, and performs CMP (step S924). Step S924 is an example of the second isolation film deposition procedure described in the claims.

[0089] The manufacturing system etches the isolation film 152 to form openings 211 to 213 (step S925). The die-side openings 211 and 212 penetrate the isolation film 151 and reach the die-side etching stopper layer 130, while the wafer-side opening 213 penetrates the isolation film 151 and reaches the wafer-side etching stopper layer 130.

[0090] The manufacturing system removes the etching stopper layer 130 exposed at openings 211 to 213 (step S926) and etches the exposed substrate 142 (step S927). Furthermore, the manufacturing system etches the exposed redistribution layer 141 and redistribution layer 120 (step S928).

[0091] The manufacturing system then forms through vias 161 to 163 by embedding metal (copper) into the openings 211 to 213 or by CMP (step S929).

[0092] The manufacturing system produces multiple semiconductor packages by dicing (step S930), and then manufactures a semiconductor device by mounting these semiconductor packages (step S931).

[0093] Thus, according to the third embodiment of this technology, since a step is provided in the etching stopper layer 130, when etching the isolation film 151 after removing the etching stopper layer 130, it is no longer necessary to stop the etching on the wafer side midway. As a result, a curved portion does not occur during etching, and metal embedding defects can be prevented.

[0094] <4. Fourth Embodiment> In the third embodiment described above, the through via 162 on the die side was formed at a position away from the edge of the die 140. However, with this configuration, it is difficult to further reduce the area of ​​the through via 162 on the die side and the area of ​​the electrode pad on the die side. The wafer 100 in this fourth embodiment differs from the third embodiment in that the through via 162 is formed at the edge of the die 140.

[0095] Figure 18 is a diagram illustrating the procedure for forming the etching stopper layer 130 in the fourth embodiment of this technology. Each step in forming the etching stopper layer 130 in this fourth embodiment is the same as in the third embodiment.

[0096] Figure 19 is a diagram illustrating the procedure up to etching the substrate 142 in the fourth embodiment of this technology.

[0097] As illustrated in figure a, the manufacturing system deposits a 5000 nanometer (nm) silicon oxide layer as an isolation film 152 to cover the etching stopper layer 130. The manufacturing system performs dry etching and CMP to eliminate any steps on the upper surface of the isolation film 152 and flatten it.

[0098] As illustrated in Figure b, the manufacturing system forms an opening 212 at the end of the die 140. Part of the opening 212 reaches the substrate 142 of the die 140, and the remainder reaches the etching stopper layer 130. The positions of the openings 211 and 213 in the fourth embodiment are the same as in the third embodiment.

[0099] The manufacturing system removes the etching stopper layer 130 and etches the isolation film 151 exposed at the openings 211 to 213.

[0100] Then, as illustrated in figure c, the manufacturing system selects a gas to etch only silicon and performs etching of the substrate 142.

[0101] Figure 20 is a diagram illustrating the procedure from metal embedding to CMP in a second embodiment of this technology.

[0102] The manufacturing system etches the redistribution layers 141 and 120 up to the respective electrode pads of wirings 143, 144, 121, and 122, as illustrated in figure a. The manufacturing system then forms through vias 161 to 163 by embedding metal (copper) or by CMP, as illustrated in figure b.

[0103] By opening the end of the die 140 to form a through via 162, the area of ​​the through via 162 on the die side and the area of ​​the electrode pad on the die side can be reduced compared to the third embodiment. This improves the flexibility of wiring within the die and allows for a reduction in the die size.

[0104] Thus, according to the fourth embodiment of this technology, since through vias 162 are formed at the end of the die 140, the area of ​​the through vias 162 on the die side and the area of ​​the electrode pads on the die side can be reduced.

[0105] <5. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0106] Figure 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0107] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0108] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0109] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0110] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0111] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0112] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0113] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0114] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0115] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0116] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 21, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0117] Figure 22 shows an example of the installation position of the imaging unit 12031.

[0118] In Figure 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0119] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0120] Figure 22 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0121] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0122] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0123] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0124] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0125] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, a semiconductor device manufactured from the wafer 100 in Figure 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it becomes possible to prevent metal embedding defects and improve the reliability of the system.

[0126] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0127] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0128] Furthermore, this technology can also be configured as follows. (1) A substrate on which a redistribution layer has been formed, An etching stopper layer formed on the bonding surface of the redistribution layer, A die bonded to a portion of the bonding surface via the etching stopper layer, The die and the etching stopper layer are covered by an isolation film. A semiconductor device equipped with the following. (2) A substrate-side via that penetrates the isolation film and the etching stopper layer and has one end connected to a wiring in the redistribution layer, The die-side via penetrates the isolation film, the die, and the etching stopper layer, with one end connected to the wiring in the redistribution layer. The semiconductor device according to (1) further comprising the above. (3) The die-side via is formed in a location that does not correspond to the end of the die. The semiconductor device described in (2) above. (4) The die-side via is formed at the end of the die. The semiconductor device described in (2) above. (5) The etching rate when etching the etching stopper layer with a predetermined etching gas is lower than the etching rate when etching the isolation film with the etching gas. A semiconductor device as described in any of (1) to (4) above. (6) The isolation film is a silicon oxide film, The etching stopper layer is a layer of silicon nitride, silicon carbide, or silicon carbonitride. The semiconductor device described in (5) above. (7) A substrate on which a redistribution layer has been formed, A die bonded to a portion of the bonding surface of the aforementioned redistribution layer, A first isolation film covering the die and the redistribution layer, A second isolation membrane, An etching stopper layer formed between the first and second isolation films, having a step near the end of the die, A semiconductor device equipped with the following. (8) A substrate-side via that penetrates the first and second isolation films and the etching stopper layer and has one end connected to a wiring in the redistribution layer, The die-side vias penetrate the first and second isolation films, the etching stopper layer, and the die, with one end connected to the wiring in the redistribution layer. The semiconductor device according to (7) further comprising: (9) The die-side via is formed in a location that does not correspond to the end of the die. The semiconductor device described in (8) above. (10) The die-side via is formed at the end of the die. The semiconductor device described in (8) above. (11) Etching stopper layer formation procedure for forming an etching stopper layer on the bonding surface of a redistribution layer formed on a substrate, A bonding procedure comprising bonding a die to a portion of the bonding surface via the etching stopper layer, An isolation film deposition procedure for forming an isolation film that covers the die and the etching stopper layer, and A method for manufacturing a semiconductor device comprising the above. (12) A bonding procedure for bonding a die to a portion of the bonding surface of a redistribution layer formed on a substrate, A first isolation film deposition procedure for depositing a first isolation film that covers the die and the redistribution layer, An etching stopper layer formation procedure for forming an etching stopper layer having a step near the end of the die, A second isolation film deposition procedure for depositing a second isolation film that covers the etching stopper layer, and A method for manufacturing a semiconductor device comprising the above. [Explanation of Symbols]

[0129] 100 wafers 110, 142 boards 120, 141 redistribution layer Wiring 121, 122, 143, 144 130 Etching stopper layer 140 Dies 151, 152 Isolation membrane 160 seed layers 161-163 Through-beer 171-173 Sidewall 211-213 Opening 220 Resist

Claims

1. A substrate on which a redistribution layer has been formed, A die bonded to a portion of the bonding surface of the aforementioned redistribution layer, A first isolation film covering the die and the redistribution layer, A second isolation membrane, An etching stopper layer formed between the first and second isolation films, having a step near the end of the die, A semiconductor device equipped with the following.

2. A substrate-side via, having one end connected to a wiring in the redistribution layer, penetrates the first and second isolation films and the etching stopper layer, The die-side vias penetrate the first and second isolation films, the etching stopper layer, and the die, with one end connected to the wiring in the redistribution layer. The semiconductor device according to claim 1, further comprising:

3. The die-side via is formed at a location that does not correspond to the end of the die. The semiconductor device according to claim 2.

4. The die-side via is formed at the end of the die. The semiconductor device according to claim 2.

5. A bonding procedure for bonding a die to a portion of the bonding surface of a redistribution layer formed on a substrate, A first isolation film deposition procedure for depositing a first isolation film that covers the die and the redistribution layer, An etching stopper layer formation procedure for forming an etching stopper layer having a step near the end of the die, A second isolation film deposition procedure for depositing a second isolation film that covers the etching stopper layer, A method for manufacturing a semiconductor device comprising the above.

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