High-frequency circuit device and detection system

Abstract

To suppress parasitic oscillation.SOLUTION: There is provided, a high-frequency circuit device that comprises: a chip that includes a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground; and a package substrate that includes a base material having a top face and a rear face opposite to the top face, and on which the chip is arranged. The high-frequency circuit device has: a shunt path arranged on the top face of the package substrate, consisting of a package signal conductor electrically connected with the signal conductor, a package first ground electrically connected with the chip ground, and a shunt element electrically connected with the package signal conductor and the package first ground; and a package second ground arranged in the base material and / or on the rear face of the package substrate. A part of the base material, a part of the shunt path, and the package second ground configure a capacity structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to high-frequency circuit devices and detection systems for handling electromagnetic waves. In particular, it relates to antenna devices for transmitting or receiving electromagnetic waves. [Background technology]

[0002] There are high-frequency circuit devices that handle electromagnetic waves (hereinafter simply referred to as "terahertz waves") that include at least a portion of the frequency band from millimeter waves to terahertz waves (30 GHz to 30 THz). As an example of a high-frequency circuit device, Patent Document 1 discloses an oscillator that integrates a negative resistance element and a resonant circuit on a semiconductor chip.

[0003] The high-frequency circuit device described in Patent Document 1 uses a resonant tunneling diode (RTD) as a negative resistance element and has a circuit that supplies a bias voltage to the negative resistance element (hereinafter simply referred to as the "voltage bias circuit"). Patent Document 1 discloses a technique to suppress parasitic low-frequency oscillations other than terahertz waves (hereinafter simply referred to as "parasitic oscillations") by electrically connecting a shunt element, which consists of a resistive element and a capacitive element connected in series, in parallel with this voltage bias circuit. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-136910 [Overview of the project] [Problems that the invention aims to solve]

[0005] Improving the layout of resistive and capacitive elements constituting a shunt element on the circuit board surface is limited by inductance constraints due to physical distance. Specifically, when designing a shunt element in a lumped-element circuit, controlling the inductance becomes difficult due to constraints on element size and board design rules, resulting in an increase in impedance above 10 MHz, for example. As a result, the likelihood of parasitic oscillations occurring in the frequency range above 10 MHz increases.

[0006] Therefore, in high-frequency circuit devices targeting terahertz waves, there is a need to suppress the rise in circuit impedance and inhibit parasitic oscillations in frequency ranges where control with lumped-element circuits is difficult.

[0007] This invention has been made in view of the above problems, and aims to suppress parasitic oscillations. [Means for solving the problem]

[0008] A first aspect of the present invention is a high-frequency circuit device comprising a chip including a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground, and a package substrate on which the chip is arranged, the package substrate comprising a base material having an upper surface and a back surface opposite to the upper surface, wherein the package substrate has a shunt path composed of a package signal conductor electrically connected to the signal conductor, a package first ground electrically connected to the chip ground, and a shunt element electrically connected to the package signal conductor and the package first ground, and a package second ground arranged in the interior of the base material and on at least one of the back surface of the package substrate, wherein a part of the base material, a part of the shunt path, and the package second ground constitute a capacitive structure. [Effects of the Invention]

[0009] According to the present invention, parasitic oscillations can be suppressed. [Brief explanation of the drawing]

[0010] [Figure 1] Top view and cross-sectional view of a high-frequency circuit device according to the first embodiment [Figure 2] Top view and cross-sectional view of a high-frequency circuit device according to a modification of the first embodiment [Figure 3] Equivalent circuit diagram of a high-frequency circuit device according to the first embodiment [Figure 4] Equivalent circuit diagram of a high-frequency circuit device with a conventional configuration [Figure 5] Top view and back view of a high-frequency circuit device according to the second embodiment [Figure 6] Cross-sectional view of a high-frequency circuit device according to the second embodiment [Figure 7] Cross-sectional view of a high-frequency circuit device according to the second embodiment [Figure 8] Equivalent circuit diagram of a high-frequency circuit device according to the second embodiment [Figure 9] Analysis example of a high-frequency circuit device according to the second embodiment [Figure 10] Graph showing the measurement results of parasitic oscillation of a high-frequency circuit device according to the second embodiment [Figure 11] Cross-sectional view of a high-frequency circuit device according to a modification of the second embodiment [Figure 12] Cross-sectional view of a high-frequency circuit device according to the third embodiment [Figure 13] Cross-sectional view of a high-frequency circuit device according to a modification of the third embodiment [Figure 14] Cross-sectional view of a high-frequency circuit device according to the fourth embodiment [Figure 15] Cross-sectional view of a high-frequency circuit device according to the fifth embodiment

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.

[0012] (First Embodiment) The high-frequency circuit device according to the first embodiment will be described with reference to FIGS. 1 to 4.

[0013] Figure 1 shows a schematic configuration of the high-frequency circuit device according to this embodiment. Figure 1(a) is a top view, and Figure 1(b) is a cross-sectional view taken along line A-A'.

[0014] The high-frequency circuit device 100 according to this embodiment consists of a package 192, a chip 191 mounted on the package 192, and a voltage bias circuit 180 that drives the chip 191 via the package 192.

[0015] As shown in Figure 1(a), a rectangular chip 191 is mounted on the package substrate 112 that constitutes the package 192, with a high-frequency element 101 and a high-frequency circuit 102 associated with the high-frequency element 101 arranged on it.

[0016] Chip 191 is mounted in a cavity 110 provided in package 192. The high-frequency element 101 is an active element such as a transistor or diode that operates with terahertz waves. The high-frequency circuit 102 is a circuit of passive elements such as a filter or antenna that targets terahertz waves. Many high-frequency circuits 102 are composed of distributed-parameter circuits. Terahertz waves are electromagnetic waves (hereinafter simply referred to as "terahertz waves") that include at least a portion of the frequency band from millimeter waves to terahertz waves (30 GHz to 30 THz).

[0017] Furthermore, the chip 191 may have an in-chip shunt element to stabilize the operation of the high-frequency element 101 and the high-frequency circuit 102. For example, the in-chip shunt element is composed of a chip resistor element 128 and a chip capacitance element 127. Also, a bias voltage is supplied to the chip 191. The chip 191 may be provided with a chip signal pad (chip-side signal pad) 106 to which pressure is applied, and a chip ground pad (not shown) to which a ground voltage is applied to the chip 191. The chip signal pad 106 and the chip ground pad are made of a conductor. In the following description, pads, grounds, patterns, etc., will be assumed to be made mainly of a conductor. The chip signal pad 106 and the chip ground pad are for making an electrical connection between the chip 191 and an external circuit, for example, for supplying a predetermined voltage from the outside. They may also be for supplying a predetermined voltage to an external circuit. In this embodiment, the predetermined voltage may be a ground voltage, a power supply voltage, a voltage from a voltage bias circuit, etc. The high-frequency element 101 and the high-frequency circuit 102 are arranged approximately in the center of the chip 191, and the chip capacitive element 127, which will be described later, is arranged adjacent to them.

[0018] Figure 1(b) is a cross-sectional view taken along the line A-A' in Figure 1(a). In addition to the configuration described above, the chip 191 has at least a dielectric layer 104, a chip signal pattern (chip signal conductor) 105, a chip ground 103, a semiconductor substrate 109, and a backside chip ground 107. The dielectric layer 104 is composed of a first dielectric layer 104a and a second dielectric layer 104b.

[0019] The chip signal pattern 105 is positioned between the first dielectric layer 104a and the second dielectric layer 104b. The high-frequency circuit 102 and the chip signal pattern 105 are electrically connected via the signal through conductor 120.

[0020] The chip signal pattern 105 is electrically connected to the chip signal pad 106. Alternatively, a portion of the chip signal pattern 105 is the chip signal pad 106.

[0021] The high-frequency element 101 is electrically connected to the high-frequency circuit 102 and the chip ground 103. The chip ground 103 is electrically connected to the back surface chip ground 107 via the chip ground through-conductor 108. For example, a chip ground pad (not shown) is provided on the same surface as the chip signal pad 106. The chip ground pad (not shown) is electrically connected to the package-side ground pad. The chip ground pad (not shown) is electrically connected to the chip ground 103.

[0022] For example, the chip capacitance element 127 is composed of a part of the conductive chip shunt pattern (chip shunt conductor) 137, a part of the second dielectric layer 104b, and a part of the chip ground 103. The chip capacitance element 127 is positioned adjacent to the high-frequency circuit 102. Also, in Figure 1(a), by positioning the chip capacitance element 127 to surround the high-frequency circuit 102, the area of ​​the chip capacitance element 127 on the chip 191 can be increased, and a larger capacitance can be secured.

[0023] Furthermore, the chip capacitance elements 127 are arranged so that the high-frequency circuit 102 is sandwiched between them, dividing the chip 191 into two opposing sides (the right and left sides of the chip 191 in Figure 1(a)). This allows for the placement of chip resistors 128, chip signal patterns 105, chip signal pads 106, etc., in the area where the chip capacitance elements 127 are not placed (the upper side of the chip 191 in Figure 1(a)), thus reducing the chip size of the chip 191.

[0024] The chip capacitance element 127 can use a MIM (Metal-Insulator-Metal) capacitance, in which an insulating layer is sandwiched between metal layers. The metal layer can be a wiring layer within the chip 191, and the insulating layer can be an insulating layer or dielectric layer that forms the high-frequency circuit 102. According to this embodiment, as shown in Figure 1(b), a chip ground 103 is used as one electrode of the MIM capacitance, and the chip ground 103 has a chip ground through conductor 108. It is connected to the back surface chip ground 107, to which the ground voltage is applied. The ground voltage may also be applied from a chip ground pad (not shown). In this case, the chip ground pad is electrically connected to the chip ground 103 via the chip ground through conductor 108.

[0025] A portion of the chip shunt pattern 137 is used as the other electrode of the MIM capacitor via the second dielectric layer 104b. Alternatively, the other electrode of the MIM capacitor may be connected to the chip resistive element 128 via wiring or through-conductors (not shown). By configuring the MIM capacitor as the chip capacitive element 127, a capacitor can be formed within the chip 191 using a simple manufacturing process.

[0026] The configuration of the chip capacitance element 127 is not limited to this. In addition to the above configuration, it is also possible to form the capacitance on a separate substrate from the chip 191 and attach it to the front or back surface of the chip 191. This configuration makes it possible to incorporate a larger capacitance element.

[0027] As shown in Figure 1, one terminal of the chip resistor element 128 is connected to a chip shunt pattern 137, which is one terminal of the chip capacitance element 127, via wiring and a through conductor (not shown). The other terminal of the chip resistor element 128 is connected to a chip signal pad 106 via a chip signal pattern 105. The chip resistor element 128 and the chip capacitance element 127 are connected in series between the chip signal pattern 105 and the chip ground 103. It is preferable to place the chip resistor element 128 near the chip capacitance element 127 for easy connection. Alternatively, the chip resistor element 128 may be placed overlapping the chip capacitance element 127. The chip signal pattern 105 applies a bias voltage to the high-frequency circuit 102.

[0028] The chip resistor element 128 and the chip capacitance element 127 function as shunt elements for the high-frequency circuit 102. More specifically, the chip resistor element 128 and the chip capacitance element 127, which are shunt elements, constitute a snubber circuit. In this embodiment, the chip resistor element 128 is connected to the chip signal pad 106 side and the chip capacitance element 127 is connected to the chip ground 103 side, but the connection relationship may be reversed. In Figure 1, there are two sets of chip resistor elements 128 and chip capacitance elements 127, but the number of sets is not limited to this. At the frequency of the parasitic oscillation to be suppressed, the resistance component of the shunt element should be smaller than the absolute value of the resistance component of the high-frequency element 101 that constitutes the high-frequency circuit 102.

[0029] Furthermore, the chip resistor element 128 may be constructed using a wiring resistor. This reduces the number of components used in the chip 191, thereby enabling miniaturization of the chip 191. Also, the shunt element may be composed of either the chip resistor element 128 or the chip capacitance element 127. When the shunt element includes the chip capacitance element 127, it is possible to suppress not only parasitic oscillations but also power consumption by cutting DC current using the impedance frequency characteristics.

[0030] The high-frequency element 101 is an element that operates in the terahertz wave region. The material of the semiconductor substrate 109 is selected according to the structure of the high-frequency element 101. For example, the semiconductor substrate 109 can be a silicon substrate or an InP substrate, which is a compound semiconductor. In addition, the dielectric layer 104 is composed of The first dielectric layer 104a and the second dielectric layer 104b should preferably be made of materials that exhibit low loss with respect to terahertz waves. For example, materials such as BCB (Benzocyclobutene), silicon oxide, and silicon nitride can be used. However, the types of materials are not limited to these.

[0031] In Figure 1, package 192 comprises a resistive element 121 and a capacitive element 122 that constitute the shunt element 140. Package 192 also provides the chip-side signal of chip 191. The package includes a package-side signal pad 118 for connecting to pad 106, and a package-side ground pad 113 for connecting to a chip-side ground pad (not shown) of the chip 191.

[0032] The package-side signal pad 118 and package-side ground pad 113 are for electrical connection to an external circuit. The package-side signal pad 118 and package-side ground pad 113 are made of a conductive material. In this case, the external circuit is the chip 191.

[0033] Package 192 also includes a bias connection terminal 181 to which a bias voltage is supplied from a voltage bias circuit 180, and a ground connection terminal 182 to which a ground voltage is supplied. To miniaturize package 192, it is preferable to use surface mount devices (SMDs) as the resistive element 121 and the capacitive element 122. Since the wiring placed in package 192 also has resistance, the wiring resistance included in the shunt element 140 may be used as the resistive element 121. This reduces the number of components used in package 192 and enables miniaturization of package 192.

[0034] The voltage bias circuit 180 is connected from outside the package 192 via the bias connection terminal 181 and the ground connection terminal 182. Alternatively, the voltage bias circuit 180 may be placed on the package 192 or on the chip 191.

[0035] The chip-side signal pad 106 of the chip 191 and the package-side signal pad 118 of the package 192 are connected by a bonding wire 117. To reduce the inductance of the bonding wire 117, it is preferable to place the chip-side signal pad 106 and the package-side signal pad 118 close to each other and shorten the length of the bonding wire 117. To shorten the bonding wire 117, the chip-side signal pad 106 can be placed at the end of the chip 191. Alternatively, the chip-side signal pad 106 and the package-side signal pad 118 can be placed opposite each other across the edge of the chip 191. The inductance of the bonding wire 117 can also be controlled by the number of wires or the wire diameter. At terahertz waves and the frequencies of parasitic oscillations to be suppressed, the resistance component of the bonding wire 117 is designed to be sufficiently smaller than the absolute value of the resistance component of the high-frequency elements 101 that constitute the high-frequency circuit 102.

[0036] In Figure 1, package 192 has a package ground 115 on its back side. The package ground 115 is at the same potential as the package-side ground pad 113 and the ground connection terminal 182. The chip ground 107 on the back side of chip 191 is electrically connected to the package ground 115 via a conductive layer 111. A low-resistance die bonding material can be used for the conductive layer 111. Through this connection, package 192 supplies ground voltage to chip 191. Alternatively, the ground voltage from package 192 may be supplied to a chip-side ground pad (not shown) via the package-side ground pad 113.

[0037] One terminal of the resistive element 121 is connected to one terminal of the capacitive element 122 via a conductive package intermediate wiring pattern (package intermediate wiring conductor) 124. In other words, the resistive element 121 and the capacitive element 122 are connected in series. Therefore, it is preferable to place the resistive element 121 and the capacitive element 122 in close proximity to each other. More preferably, one terminal of the resistive element 121 is placed adjacent to one terminal of the capacitive element 122. This allows the length of the package intermediate wiring pattern 124 to be shortened, thereby reducing the inductance.

[0038] The other terminals of the resistor element 121 are connected to the package signal pattern, which is a conductor (package signal conductor). The package-side signal pad 118 and the bias connection terminal 181 are connected via 123. The other terminal of the capacitive element 122 is connected to the package-side ground pad 113 and the ground connection terminal 182 via the package first ground 125. It is preferable that the direction in which one terminal and the other terminal of the resistive element 121 and one terminal and the other terminal of the capacitive element 122 are aligned is the same as the direction in which the package-side signal pad 118 and the package-side ground pad 113 are aligned. This arrangement allows for shorter wiring and reduced inductance.

[0039] The shunt element 140 consists of a resistor 121 and a capacitor 122 connected in series, and functions as a shunt element for the chip 191, which includes the high-frequency circuit 102. More specifically, the resistor 121 and the capacitor 122, which constitute the shunt element, form a snubber circuit. In this embodiment, the resistor 121 is connected to the package signal pattern 123 side, and the capacitor 122 is connected to the package first ground 125 side. However, this connection relationship may be reversed. There may also be multiple shunt elements 140. At the frequency of the parasitic oscillation to be suppressed, it is preferable that the resistance component of the shunt element 140 is smaller than the absolute value of the resistance component of the high-frequency element 101 that constitutes the high-frequency circuit 102 of the chip 191. Furthermore, the shunt element 140 may consist of either the resistor 121 or the capacitor 122. When the shunt element 140 includes the capacitor 122, it is possible not only to suppress parasitic oscillations but also to reduce power consumption by cutting DC current using the impedance frequency characteristics.

[0040] The package substrate 112 constituting the package 192 can be made of a substrate used for printed circuit boards, such as a glass composite substrate, a glass epoxy substrate, or a fluorine substrate. Furthermore, the package substrate 112 can be made of an aluminum oxide (Al2O3) substrate or an aluminum nitride (AlN) substrate. Substrate, LTCC (Low Temperature Co-fired Ceramics) Substrates used for ceramic circuit boards such as substrates can be applied. Preferably, a substrate with low loss to terahertz waves is used for the package substrate 112.

[0041] Regarding the positional relationship of the components of the high-frequency circuit device 100, it is preferable to position the shunt element of chip 191 between the high-frequency circuit 102 and the voltage bias circuit 180. Furthermore, it is preferable to position the shunt element 140 of package 192 between the shunt element of chip 191 and the voltage bias circuit 180. Details of a device using multiple shunt elements are disclosed, for example, in Japanese Patent Application Publication No. 2020-136910. Multiple shunt elements are used here. This makes it possible to suppress parasitic oscillations over a wide frequency band.

[0042] Our research indicates that when designing shunt elements in lumped-element circuits, inductance control becomes difficult at certain frequencies due to constraints on element size and substrate design rules. For example, an increase in circuit impedance is expected above 10 MHz, making it desirable to improve circuit stability at this frequency (above 10 MHz).

[0043] Therefore, in this embodiment, the high-frequency circuit device 100 has the following configuration. As described above, the chip 191 has at least a high-frequency element 101, a high-frequency circuit 102, a chip signal pattern 105, and a chip ground 103. The package 192 includes a substrate having an upper surface and a back surface opposite to the upper surface, and has at least a package substrate 112 on which the chip 191 is arranged. Furthermore, as shown in Figure 1(b), the package 192 is characterized by having a capacitive structure 126 in the thickness direction of the package substrate 112 near the side connected to the chip 191.

[0044] The capacitance structure 126 will now be described. In Figure 1(b), the capacitance structure 126 consists of a part of the base material of the package substrate 112, a part of the shunt path 130, and a part of the package second gland 114.

[0045] The shunt path 130 is defined as a path that includes the package signal pattern 123, the resistive element 121 constituting the shunt element 140, the package intermediate wiring pattern 124, the capacitive element 122 constituting the shunt element 140, and the package first ground 125. The shunt path 130 can also be defined as a path through which current flows. The shunt path 130 is located on the upper surface of the package substrate 112. The package signal pattern 123 is electrically connected to the chip signal pattern 105. The package first ground 125 is electrically connected to the chip ground 103. The shunt element 140 is electrically connected to the package signal pattern 123 and the package first ground 125.

[0046] The package second ground 114 is a conductor located on the back side of the package substrate 112 that constitutes the package 192. Here, the package second ground 114 is electrically connected to the package ground 115 via a ground connection pattern (ground connection conductor) 183. The ground connection pattern 183 is a fine wire pattern of conductors. For example, a fine wire pattern of conductors can be considered an inductor, and its impedance increases as the frequency increases. In other words, the impedance at a desired frequency can be adjusted. By utilizing this characteristic, the package ground 115 and the package second ground 114 are electrically isolated by the ground connection pattern 183 in any band from the parasitic oscillation frequency to the terahertz wave frequency. The ground connection pattern 183 may also be a filter composed of a distributed constant circuit.

[0047] Furthermore, the package second ground 114 is electrically connected to the package first ground 125 via a package ground through-conductor 116 located inside the package substrate 112. Depending on the shape of the package ground through-conductor 116, inductive and capacitive components can be imparted to it. In other words, the impedance at a desired frequency can be adjusted. By utilizing this characteristic, for example, the package first ground 125 and the package second ground 114 are electrically isolated in a frequency band ranging from parasitic oscillation frequencies to terahertz waves. By electrically isolating each ground in the target frequency range, unwanted signals transmitted through the grounds can be suppressed, thereby stabilizing the operation of the high-frequency circuit device 100. By configuring a portion of the base material of the package substrate 112 to sandwich the conductor of the shunt path 130 and the package second ground 114, capacitance Cs and admittance Gs can be imparted near the connection between the chip 191 and the package 192, as shown in Figure 1(b). In this embodiment, the capacitance structure 126 is used as a shunt element, and the capacitance obtained therefrom is used to suppress parasitic oscillations.

[0048] The through-conductors described above, such as the chip ground through-conductor 108, package ground through-conductor 116, and signal through-conductor 120, are formed by creating through-holes in the material and then forming an insulating film on the inner wall of the through-holes to electrically isolate them. These through-conductors are then formed by filling the through-holes with copper or a similar material that has low electrical resistance and can be easily electrode-formed by electrolytic plating. These through-conductors may also be smoothed using CMP (Chemical Mechanical Polishing) or other processes. For example, after forming the through-conductors, pads may be formed to electrically connect them to external wiring.

[0049] The capacitance obtained by the capacitance structure 126 can also be adjusted by the distance between the conductor of the shunt path 130 and the package second ground 114. For example, as shown in Figure 2(b), the package second ground 114 may be placed inside the substrate of the package substrate 112. In Figure 2(b), the package second ground 114 is electrically connected to the package first ground 125 and the package ground 115 via the package ground through conductor 116. At this time, in a band from the parasitic oscillation frequency to the terahertz wave frequency, The package first ground 125, the package second ground 114, and the package ground 115 are electrically isolated in the thickness direction of the substrate of the package substrate 112. By placing the package second ground 114 inside the substrate of the package substrate 112, the degree of freedom for adjusting the capacitance of the capacitive structure 126 is increased. As a result, the controllability of parasitic oscillation suppression is improved.

[0050] As shown in Figures 1 and 2, a portion of the shunt path 130, a portion of the package's first ground 125, and a portion of the package's second ground 114 overlap when viewed from the shunt path 130. Therefore, it can also be said that the capacitive structure 126, which is a shunt element, and the shunt element 140, which is made up of SMD components, overlap when viewed from the shunt path 130. By arranging multiple shunt elements in this way, the length of the wiring required for the circuit can be shortened, making it easier to suppress parasitic oscillations. In addition, since multiple shunt elements can be arranged in overlapping order, it is easier to miniaturize the entire circuit, which also contributes to miniaturizing the package 192.

[0051] Furthermore, in Figures 1 and 2, in order to use the capacitive structure 126 as a shunt element, the distance L between the high-frequency element 101 and the package ground penetrating conductor 116 is the wavelength λ sig and wavelength λ para between λ sig ≤L ≤λ para It is preferable that the following relationship is satisfied. Here, wavelength λ sig λ is the effective wavelength of the high-frequency signal of the high-frequency circuit 102, and the wavelength λ parais the effective wavelength of the parasitic oscillation generated in the shunt path 130. The distance L is, for example, the length along the current path from the end of the high-frequency element 101 (the end of the array antenna; the end of the element close to the electrode pad) to the center of the package ground via-conductor 116. Since the effective wavelength of the parasitic oscillation is long, even if there is an error in the position of the start or end point of the distance L, the influence is small.

[0052] FIG. 3 is a diagram showing an example of the equivalent circuit of the present embodiment. Specifically, it is an example of the equivalent circuit of FIG. 1. In FIG. 3, r 101 is the absolute value of the negative resistance of the high-frequency element 101. Generally, when the combined resistance of the circuit connected in parallel to the high-frequency element 101 is R, when the relationship of r 101 <R is satisfied, the subsequent circuit becomes unstable and is likely to generate parasitic oscillation. The chip 191 is connected to the package 192 via the chip-side signal pad 106 and the conductive layer 111. Z 102 is the combined impedance of the high-frequency circuit 102. R 128 is the resistance of the chip resistance element 128. C 127 is the capacitance (capacitance) of the chip capacitance element 127. R 128 and C 127 constitute a snubber circuit which is a shunt element, suppresses the influence of the circuit of the package 192 as seen from the high-frequency circuit 102, and suppresses parasitic oscillation on the high-frequency side from, for example, several GHz to several hundred GHz.

[0053] The chip-side signal pad 106 of the chip 191 and the package-side signal pad 118 of the package 192 are connected via the bonding wire 117. L 117 is the inductance of the bonding wire 117.

[0054] Regarding the package 192, L lineThis expresses the influence of circuits and wiring in the shunt path 130 as inductance. The wiring in the shunt path 130 includes the package signal pattern 123, the package intermediate wiring pattern 124, the package first ground 125, etc. As described above, in this embodiment, the capacitive structure 126 is formed by a part of the base material of the package substrate 112, a part of the shunt path 130, and the package second ground 114. S This is the capacitance of the capacitive structure 126. G S This is admittance, which is the reciprocal of the resistive component of the capacitive structure 126.

[0055] The package second ground 114, which defines the reference potential of the capacitive structure 126, is electrically connected to the package first ground 125 via the package ground through-conductor 116. The package first ground 125 is also connected to the chip 191 via the ground connection pattern 183. It is electrically connected to the conductive layer 111. Although the potentials of these grounds are the same in DC terms, they are AC-disconnected depending on the frequency, suppressing unwanted noise and signals from coupling to the circuit via the ground. Capacitive structure 126 C S and G S This is a shunt element. C of capacitive structure 126 S and G S This is mainly due to the inductor L caused by the circuit and wiring of the shunt path 130. line The effects of parasitic oscillations are suppressed, and the impedance of the shunt path 130 is adjusted to a low impedance (impedance below a predetermined value) within a desired frequency range. This frequency range is, for example, the range from 10 MHz to 10 GHz (mid-frequency range), and by setting the impedance of the shunt path 130 to a low impedance in the intermediate frequency range, parasitic oscillations in the intermediate frequency range are suppressed.

[0056] The shunt path 130 contains a shunt element 140 made of SMD components. 121 This is the resistance of the resistive element 121 that constitutes the shunt element 140. 122 R is the capacitance of the capacitive element 122 that constitutes the shunt element 140.121 and C 122 This constitutes a snubber circuit, which is a shunt element, and suppresses the influence of the voltage bias circuit 180 from the perspective of the circuit in package 192. And R 121 and C 122 The snubber circuit, composed of these components, suppresses parasitic oscillations on the low-frequency side, for example, below several hundred MHz. The package 192 and the voltage bias circuit 180 are connected to the bias connection terminal 181 via the ground connection terminal 182.

[0057] Figure 4 shows an example of an equivalent circuit of a conventional configuration (for example, Japanese Patent Publication No. 2020-136910). As is clear from the comparison of Figure 3 and Figure 4, the conventional configuration lacks a shunt element provided by the capacitive structure 126, making impedance adjustment in the mid-frequency range difficult. Furthermore, depending on the circuit configuration and layout, the inductor L line Parasitic oscillations may occur as a result.

[0058] By using multiple shunt elements in this way, it becomes easier to suppress parasitic oscillations over a wide frequency band. In particular, the capacitive structure 126 makes it possible to suppress parasitic oscillations at medium frequencies, which were previously difficult to suppress, thus further stabilizing the circuit.

[0059] (Second embodiment) A high-frequency circuit device according to the second embodiment will be described with reference to Figures 5 to 7. Note that explanations of parts common to the preceding explanations will be omitted. Figures 5 to 7 show the schematic configuration of the high-frequency circuit device 100 according to this embodiment. Figure 5(a) is a top view. Figure 5(b) is a rear view. Figure 6(a) is a cross-sectional view taken along line A-A' in Figure 5(a). Figure 6(b) is a cross-sectional view taken along line B-B' in Figure 5(a). Figure 7 is a cross-sectional view taken along line C-C' in Figure 5(a). The high-frequency circuit device according to this embodiment shows an example of an antenna device for transmitting or receiving terahertz waves 193.

[0060] The chip 191 in Figure 6(a) differs from the first embodiment in the following configuration. The high-frequency element 101 is a negative resistance element that has gain with respect to terahertz waves 193. The high-frequency circuit 102 is an antenna for transmitting or receiving terahertz waves 193. The antenna can be considered a resonant circuit and also acts as an impedance converter with respect to the atmosphere. In particular, in this embodiment, the chip 191 has multiple high-frequency elements 101, and one antenna is connected to each high-frequency element 101. In this embodiment, the multiple antennas are also called an array antenna. In this embodiment, power combining of terahertz waves 193 is performed by the antenna array. As shown in Figure 5(a), the number of chip-side signal pads 106 and chip-side ground pads 133 differs from the first embodiment, with four of each being arranged. The chip-side signal pads 106 are electrically connected to the package signal pattern 123 of the package 192 via bonding wires 117. The chip-side ground pad 133 is connected to the package first ground 125 of the package 192 via the bonding wire 117.

[0061] Details of the high-frequency element 101 and the high-frequency circuit 102 will be explained. As an array antenna which is the high-frequency circuit 102, 20 to 40 antennas are arranged. Figure 5(a) shows an example in which 36 antennas are arranged in a matrix. Note that the arrangement layout is not limited to this. Typically, in an antenna array intended for power combining, the spacing between individual antennas is set to be less than or equal to the wavelength obtained by converting the oscillating electromagnetic wave to its wavelength in a vacuum, or an integer multiple of the wavelength, more preferably less than or equal to half a wavelength. In this embodiment, the antennas are arranged so that the spacing between them is less than or equal to half a wavelength of the transmitted electromagnetic wave, the terahertz wave 193.

[0062] In the antenna array, a resonant circuit is configured to control the oscillation frequency by a microstrip resonator consisting of a metal layer (corresponding to the high-frequency circuit 102) that forms part of the antenna, a dielectric layer 104, and a chip ground 103 that is a conductor and also forms part of the antenna. The antenna consists of this resonant circuit and a negative resistance element, which is a high-frequency element 101. A bias voltage line (not shown) is connected to the metal layer via a signal-through conductor 120, and a bias voltage is applied to the negative resistance element. The bias voltage line is connected to the chip-side signal pad 106. The negative resistance element generates electromagnetic wave gain to maintain oscillation. Individual antennas need to oscillate in phase and synchronously, and are designed to be close to the oscillation frequency ω0. Therefore, it is preferable that the shapes of the individual antennas, including the half-wavelength resonators, are similar to each other. In this embodiment, an example of a patch-shaped antenna is shown, but the antenna shape is not limited to this. It is also preferable to use negative resistance elements with similar shapes and characteristics. A configuration in which the antenna also serves as a resonant circuit for oscillating electromagnetic waves, and negative resistance elements for supplying power to the resonant circuit are integrated, is also called an active antenna. In particular, the configuration of this embodiment is an active antenna array in which multiple active antennas are arranged in a matrix.

[0063] Each active antenna has a microstrip line (not shown) for synchronization in phase, and adjacent active antennas are coupled by the microstrip line. In this embodiment, this microstrip line is also called a coupling line for synchronizing and oscillating individual active antennas in phase with each other.

[0064] It is preferable to select a coupling line (not shown) such that the length from one end to the other is 2π in electrical length at the synchronized oscillation frequency ω0. An electrical length of 2π corresponds to the effective oscillation wavelength λ0, calculated using the effective dielectric constant of the surrounding structure. The reason for selecting an electrical length of 2π is to synchronize adjacent active antennas in phase and cause them to oscillate. If adjacent active antennas are to be synchronized in opposite phase, the electrical length may be π or 3π. Synchronization of adjacent active antennas is possible even if the coupling line length is not exactly 2π. Depending on the magnitude of the coupling between elements formed by the coupling line, an electrical length of approximately 2π ± 10% is typically within the acceptable range. This acceptable range is wider than that of a configuration in which adjacent active antennas are coupled in space without using a coupling line. The electrical length of the coupling line can be easily confirmed using an electromagnetic field simulator, etc.

[0065] A portion of the oscillation output of one active antenna is input to the adjacent active antenna via a coupling line in approximately the same phase. Similarly, a portion of the oscillation output of the other active antenna is input to the adjacent active antenna via a coupling line in approximately the same phase. In this embodiment of the active antenna array, a coupling line is introduced to realize such mutual injection synchronization phenomena between adjacent active antennas.

[0066] As an example of a coupling line in this embodiment, a coupling line (not shown) is capacitively coupled to a metal layer which is part of the resonant structure. For example, the coupling line (not shown) has an insulating layer (not shown) sandwiched between the metal layer and the coupling line, forming a metal-insulator-metal (MIM) region, and capacitance is formed through the insulating layer, so it is DC open. As a result, in the bandwidth of the oscillation frequency ω0, between active antennas The coupling size can be kept large, just as with direct coupling. Furthermore, in the low-frequency region smaller than ω0, the coupling size decreases, ensuring isolation between active antennas. Moreover, in the low-frequency region smaller than ω0, the coupling line, which is an open-ended microstrip line, becomes a capacitive element. From the perspective of the high-frequency element 101, which is a negative resistive element, on the high-frequency circuit 102 side, which is a metal layer with an antenna pattern, the coupling line is a capacitive element and can function as a shunt element, for example. Therefore, the resonant frequency that is a concern in the low-frequency region is not generated. Consequently, it becomes possible to suppress parasitic oscillations in the low-frequency region.

[0067] In chip 191, arranging the active antennas in a matrix and coupling adjacent active antennas according to the coupling line conditions is preferable because it not only increases the combined power but also provides sharp directivity.

[0068] In Figures 5(a) and 7, the high-frequency circuit 102, which consists of multiple metal layers, is commonly connected within the chip 191 via a strip conductor (not shown) and connected to a chip-side signal pad 106 to which a bias voltage is applied. The chip ground 103 is also connected within the chip 191 to a chip-side ground pad 133 to which a ground voltage is applied. With this configuration, when a voltage is applied to the chip-side signal pad 106 and the chip-side ground pad 133, a bias voltage is applied across the high-frequency element 101, which is a negative resistance element.

[0069] As the negative resistance element, a resonant tunneling diode (RTD) lattice-matched to the InP substrate can be used. Note that, in addition to resonant tunneling diodes, Esaki diodes and Gunn diodes may also be used as the negative resistance element. The resonant tunneling diode is constructed, for example, with a multiple quantum well structure of InGaAs / InAlAs and InGaAs / AlAs on the InP substrate, and an electrical contact layer of n-InGaAs. As the multiple quantum well structure, for example, a triple-barrier structure is used. More specifically, a semiconductor multilayer structure of AlAs(1.3nm) / InGaAs(7.6nm) / InAlAs(2.6nm) / InGaAs(5.6nm) / AlAs(1.3nm) is used. It is constructed as a layered structure. Of these, InGaAs is the well layer, and lattice-matched InAlAs and mismatched AlAs are barrier layers. These layers are intentionally undoped, meaning they are not carrier-doped. In such a multiple quantum well structure, the electron concentration is 2 × 10⁻¹⁶ 18 cm -3 It is sandwiched between electrical contact layers made of n-InGaAs. In the current-voltage (I / V) characteristics of this structure between electrical contact layers, the peak current density is 280 kA / cm². 2 It is approximately 0.7V The negative resistance region extends from approximately 0.9V. The diode configuration consists of a mesa with a diameter of 2μm. In this structure, a peak current of 10 mA and a negative resistance of -20 Ω are obtained. Considering the reactance due to the junction capacitance of a 2 μm diameter resonant tunnel diode connected to the bottom of the antenna pattern composed of metal layers, the oscillation frequency is approximately 0.3 to 0.6 THz.

[0070] Generally, at the frequency of the parasitic oscillation to be suppressed, the impedance of the circuit including the transmission line as seen from the negative resistive element is equal to the absolute value of the negative differential resistance (for example, r in Figures 3 and 4). 101When the impedance is less than 10 times the negative resistance element, the magnitude of the losses due to the transmission line cannot be ignored compared to the gain of the negative resistance element. In other words, because power needs to be supplied from the negative resistance element to the circuit to compensate for the lost power, the power contributing to oscillation becomes relatively small, and the oscillation of the parasitic oscillation cannot be maintained. Preferably, the impedance of the circuit including the transmission line is r 101 It is equivalent to, and more preferably, r 101 It is a value smaller than that. For example, when the chip 191 is 3mm square to 4mm square, 20 to 40 antennas can be arranged in the high-frequency circuit 102, and the combined resistance value of the negative resistance of the high-frequency elements 101 will be at most 1Ω, i.e., 1Ω or less. Therefore, if the circuit design of the package 192, including the shunt element, is carried out with this value as the target for the target frequency range, parasitic oscillations can be suppressed. For example, package By setting the impedance of signal pattern 123 to 1Ω or less, parasitic oscillations can be easily suppressed. Here, the predetermined value is, for example, 1Ω.

[0071] Next, we will describe package 192 with reference to Figures 5 to 7. Package 192 differs from the first embodiment in the following configuration.

[0072] The external dimensions of the package 192 are approximately 10 x 8 mm, and the thickness of the package substrate 112 is approximately 1 mm. The package substrate 112 is an aluminum nitride substrate. A package second ground 114 is located at the bottom surface of the cavity 110 that houses the chip 191 provided on the package substrate 112. The back surface chip ground 107 and the package second ground 114 are electrically connected at the bottom surface of the cavity 110.

[0073] In Figure 5(a), the package 192 has four shunt paths 130, and along each shunt path 130, a shunt element 140 consisting of a resistive element 121 and a capacitive element 122 is arranged. Two resistive elements 121 are arranged in parallel. As a result, four shunt elements 140 are connected in parallel to the high-frequency element 101, which is a negative resistive element, and the impedance of the combined shunt element 140 can be reduced. Therefore, parasitic oscillations are easily suppressed and the circuit is stabilized. The number of shunt paths 130 is not limited to this.

[0074] Package 192 has a package float wiring pattern (package float wiring conductor) 135 which is a conductor. The package float wiring pattern is in a state where its potential is not determined on its own, that is, it is electrically floating. The package float wiring pattern 135 also serves as a spare wiring and can be used, for example, as a terminal to connect to an external circuit when the types of control signals of the chip 191 increase. Alternatively, the package float wiring pattern 135 is space for expanding the circuitry inside package 192. Alternatively, the package float wiring pattern 135 may be used as a place to manage the lot number of package 192.

[0075] In Figure 5(b), package 192 has a bias connection terminal 181 and a ground connection terminal 182 on its back surface. For example, it can be mounted to an external circuit using the bias connection terminal 181 and ground connection terminal 182, similar to a general SMD component. The bias connection terminal 181 may have a signal pin 131 which is a rod-shaped conductor. The ground connection terminal 182 may have a ground pin 132 which is a rod-shaped conductor. In this case, package 192 can be treated like a DIP (Dual Inline Package) package, making it easy to connect to an external circuit. The configuration of these connection terminals can be appropriately changed according to the connection specifications of the external circuit. With this connection configuration, for example, impedance management of the connection part with the voltage bias circuit 180 becomes easier, and circuit stabilization can be expected.

[0076] Figure 6(a) is a cross-sectional view along line A-A' in Figure 5(a), and Figure 6(b) is a cross-sectional view along line B-B' in Figure 5(a). The package 192 of this embodiment differs from the first embodiment in that it has an inner package signal pattern (inner package signal conductor) 119 and an inner package ground 136 that are layered inside the package substrate 112. For example, the inner package signal pattern 119 is positioned so as to overlap a portion of the package signal pattern 123 when viewed from the perspective of the package signal pattern 123. Similarly, the inner package ground 136 is positioned so as to overlap a portion of the package first ground 125 when viewed from the perspective of the package first ground 125. Also, in a cross-section perpendicular to the upper surface of the package substrate 112, or in a perpendicular direction, at least a portion of the inner package signal pattern 119 is positioned so as to overlap at least a portion of the package signal pattern 123. Similarly, At least a portion of the inner layer ground 136 is positioned to overlap with at least a portion of the package first ground 125. Also, in a plan view, at least a portion of the package inner layer signal pattern 119 is positioned to overlap with at least a portion of the package signal pattern 123. At least a portion of the package inner layer ground 136 is positioned to overlap with at least a portion of the package first ground 125. Here, a plan view refers to, for example, a projection of each component perpendicular to the package substrate 112.

[0077] As shown in Figure 6(b), the package inner layer signal pattern 119 is connected to the package signal pattern 123 and the ground connection terminal 182 via the package signal through conductor 129. The package inner layer ground 136 is connected to the package first ground 125, package second ground 114, package ground 115, and ground connection terminal 182 via the package ground through conductor 116. For example, by placing the package inner layer ground 136 below the package first ground 125, the impedance of the ground layer can be lowered, and the ground of the circuit is strengthened. As a result, the circuit is stabilized. Furthermore, beneath the chip 191, the package inner layer signal pattern 119 is sandwiched between the package second ground 114 and package ground 115, which are grounds at the same potential. This suppresses the coupling of unwanted signal noise transmitted through the package inner layer signal pattern 119 to the chip 191. As a result, the circuit is stabilized.

[0078] Figure 7 is a cross-sectional view of the line C-C' in Figure 5(a), and is a cross-sectional view of the capacitive structure 126 along the shunt path 130. The chip signal pattern 105 and the package signal pattern 123 are electrically connected via bonding wires 117. The capacitive structure 126 differs from the first embodiment in that it has a package inner layer signal pattern 119. The package inner layer signal pattern 119 is located inside the substrate of the package substrate 112, and is positioned so that, when viewed from the package signal pattern 123 (in a direction perpendicular to the upper surface of the package substrate 112), a portion of the package signal pattern 123 overlaps with it. Also, in a plan view, at least a portion of the package inner layer signal pattern 119 is positioned so that at least a portion of the package signal pattern 123 overlaps with it. By arranging the signal patterns in parallel, the impedance of the wiring can be reduced, and parasitic oscillations can be easily suppressed. The package signal pattern 123 and the package inner layer signal pattern 119 are preferably arranged so that they overlap, for example, around the shunt path 130.

[0079] Figure 8 shows an example of an equivalent circuit diagram of this embodiment. Unlike the equivalent circuit in Figure 3, the equivalent circuit diagram in Figure 8 shows the inductor L of the upper circuit including the package signal pattern 123 for the shunt path 130. line In contrast, the inductor L of the inner layer circuit including the package inner layer signal pattern 119 line2 These are connected in parallel. This reduces the overall inductance of the circuit. This can be achieved. Furthermore, by having multiple capacitive structures 126 and shunt elements 140, the overall inductance of the circuit can be reduced. As a result, parasitic oscillations can be easily suppressed, and circuit stabilization can be achieved.

[0080] Figure 9 shows an example of impedance analysis of package 192 in this embodiment. Figure 9(a) is the analysis model. To analyze the impedance as seen from the chip 191 side, an analysis port is provided at the location of chip 191. Also, the voltage bias circuit 180 is disconnected, and the bias connection terminal 181 and ground connection terminal 182 are open.

[0081] Figure 9(b) is a graph of the analysis results, with the real part of the impedance plotted in graph 91 on the left and the imaginary part of the impedance plotted in graph 92 on the right. The horizontal axis represents frequency, and the vertical axis represents impedance. Here, the results for the presence or absence of the capacitive structure 126 and the difference in the thickness of the substrate, which is part of the package substrate 112 that constitutes the capacitive structure 126, are plotted. According to the analysis, adding the capacitive structure 126 reduces (lowers) the values ​​of both the real and imaginary parts of the impedance. It can be seen that this is being done. In detail, it was confirmed that the impedance of the shunt path 130 can be reduced to 1Ω or less in the frequency band (frequency range) of 10MHz to 10GHz. Furthermore, it was confirmed that the impedance of the shunt path 130 can be controlled by changing the substrate thickness of the package substrate 112 that constitutes the capacitive structure 126.

[0082] Figure 10 is a graph showing the measurement results of parasitic oscillation to confirm the effect of the capacitance structure 126. Figure 10(a) is the time waveform, with time on the horizontal axis and voltage on the vertical axis. Figure 10(b) is the frequency response, with frequency on the horizontal axis and amplitude on the vertical axis. Figure 10 compares the results with and without the capacitance structure 126. According to Figure 10, parasitic oscillation at approximately 200 MHz is observed without the capacitance structure 126, but it can be seen that this parasitic oscillation is suppressed by adding the capacitance structure 126.

[0083] The capacitance structure 126 of this embodiment is not limited to the structure described above. Figure 11 is a cross-sectional view of a modified example of this embodiment along the line C-C' in Figure 5(a). For example, as shown in Figure 11(a), the capacitance structure 126 may not have internal layer wiring such as the package internal layer signal pattern 119 or package internal layer ground 136 above the package second ground 114. Also, as shown in Figure 11(b), the capacitance of the capacitance structure 126 can be adjusted by overlapping a part of the package internal layer ground 136 and a part of the package signal pattern 123 when viewed from the package signal pattern 123 side. Furthermore, as shown in Figure 11(c), the capacitance structure 126 may have internal layer wiring in multiple layers above the package second ground 114.

[0084] (Third embodiment) A high-frequency circuit device according to the third embodiment will be described with reference to Figures 12 and 13. Note that explanations of parts common to the preceding descriptions will be omitted. This embodiment is a modified version of the embodiments described so far.

[0085] Figure 12 is a cross-sectional view of this embodiment taken along the line A-A' in Figure 1(a). In previous embodiments, the chip 191 was placed inside a cavity 110 provided in the package 192, but in this embodiment, the cavity 110 is eliminated, and the chip 191 is mounted on the side of the package 192 on which the shunt element 140 is mounted.

[0086] The configuration of this embodiment is not limited to this. For example, as shown in Figure 13(a), the package 192 may have internal wiring such as the package internal ground 136 and package internal signal pattern 119 described above. Also, as shown in Figure 13(b), a configuration is possible in which the capacitance of the capacitive structure 126 is adjusted by the package signal pattern 123 and the package internal ground 136. Furthermore, as shown in Figure 13(c), the package substrate 112 may have internal wiring in multiple layers in the thickness direction.

[0087] (Fourth embodiment) A high-frequency circuit device according to the fourth embodiment will be described with reference to Figure 14. Note that explanations of parts common to the previous descriptions will be omitted. This embodiment is a modification of the embodiments described so far. As shown in Figure 14, this embodiment differs in that lumped element components are arranged in the thickness direction of the package substrate 112 in a portion of the region from the chip 191 to the shunt path 130. For example, in Figure 14(a), a capacitor, which is a lumped element 141, is mounted in the thickness direction laterally to the chip 191. In Figure 14(a), one terminal of the lumped element 141 is connected to the package's second ground 114, and the other terminal is connected to the chip-side signal pad 106 and the package-side signal pad 118 by a bonding wire 117. Also, as shown in Figure 14(b), the chip 191 can be mounted on the lumped element 141. Figure 14 In (b), one terminal of the lumped element 141 is connected to the inner layer signal pattern 119 of the package, and the other terminal is connected to the back surface chip ground 107 of the chip 191 via the conductive layer 111. Note that the lumped element 141 may also be a lumped element circuit.

[0088] With this configuration, the circuit can be configured in the thickness direction of the package substrate 112, so the number of circuits incorporated into the package 192 can be increased without changing the size of the package 192. In other words, it becomes easier to increase the integration density of the circuits. Furthermore, while the dielectric material of the capacitive structure 126 has been limited to the dielectric material of the base material of the package substrate 112 until now, this configuration allows different dielectric materials to be used as the capacitive structure 126, increasing the degree of freedom in circuit adjustment.

[0089] (Fifth embodiment) A high-frequency circuit device according to the fifth embodiment will be described with reference to Figure 15. Note that explanations of parts common to the previous descriptions will be omitted. This embodiment is a modification of the embodiments described so far.

[0090] In this embodiment, as shown in Figure 15, a sealing layer 134 is further provided to seal part or all of the upper surface of the chip 191 and the upper surface of the package substrate 112. The sealing layer 134 uses a transparent resin material that has low loss to terahertz waves 193. By sealing the area around the heat-generating chip 191 with the sealing layer 134, the amount of heat generated by the chip 191 can be diffused over a wide area along the sealing layer 134. As a result, heat dissipation from the chip 191 is improved and thermal damage to the high-frequency elements 101 constituting the chip 191 can be suppressed.

[0091] (Other embodiments) Preferred embodiments and examples of the present invention have been described above, but the present invention is not limited to these embodiments and examples, and various modifications and changes are possible within the scope of its gist. For example, although the above embodiments and examples are described assuming that the carrier is an electron, the invention is not limited to this, and holes may also be used. Furthermore, the substrate and dielectric materials can be selected according to the application, and semiconductors such as silicon, gallium arsenide, indium arsenide, and gallium phosphide, or resins such as glass, ceramics, polytetrafluoroethylene, and ethylene terephthalate can be used. Note that the above-mentioned structures and materials in each embodiment and example may be appropriately selected according to the desired frequency, etc.

[0092] Furthermore, in the embodiments and examples described above, a square patch antenna is used as the terahertz wave resonator. However, the shape of the resonator is not limited to this, and for example, a resonator with a structure using polygons such as rectangles and triangles, or patch conductors such as circles and ellipses may also be used.

[0093] Furthermore, the number of differential negative resistance elements integrated into the semiconductor device is not limited to one; a resonator with multiple differential negative resistance elements is also possible. Similarly, the number of transmission lines is not limited to one; a configuration with multiple transmission lines is also acceptable.

[0094] Furthermore, the above has described a double-barrier RTD made of InGaAs / AlAs grown on an InP substrate. However, the RTD is not limited to these structures or material systems, and other structures and material combinations may also be used. For example, an RTD with a triple-barrier quantum well structure or an RTD with a quadruple or more multi-barrier quantum well structure may be used.

[0095] Additionally, any of the following combinations may be used as materials for the RTD. • GaAs / AlGaAs and GaAs / AlAs formed on a GaAs substrate, In GaAs / GaAs / AlAs InGaAs / InAlAs, InGaAs / AlAs, InGaAs / AlGaAsSb formed on an InP substrate InAs / AlAsSb and InAs / AlSb formed on an InAs substrate • SiGe / SiGe formed on a Si substrate

[0096] Furthermore, the high-frequency circuit device described in the above embodiments and examples can be used as an oscillator in the detection system. The detection system may, for example, use the high-frequency circuit device as an oscillator, have a receiver that receives high frequencies from the oscillator, and a processing circuit that processes the signals from the receiver. The detection system may also be, for example, a terahertz wave imaging system. In the detection system, the high-frequency circuit device may also be used as a receiver, or it may be used as both an oscillator and a receiver. [Explanation of symbols]

[0097] 100: High-frequency circuit device 101: High-frequency element 102: High-frequency circuit 103: Chip ground 105: Chip signal pattern 112: Package substrate 114: Package 2nd Ground 123: Package Signal Pattern 125: Package 1st ground 126: Capacity structure 130: Shunt pathway 140: Shunt element 191: Chip

Claims

1. A chip including a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground, A package substrate comprising a base material having an upper surface and a back surface opposite to the upper surface, on which the chip is arranged, In a high-frequency circuit device equipped with, A shunt path comprising a package signal conductor electrically connected to the signal conductor, a package first ground electrically connected to the chip ground, and a shunt element electrically connected to the package signal conductor and the package first ground, arranged on the upper surface of the package substrate, The package substrate has a second package ground disposed inside the base material and on at least one of the back surfaces, A portion of the substrate, a portion of the shunt path, and the second package gland constitute a capacitive structure. A high-frequency circuit device characterized by the following features.

2. Due to the capacitive structure, the frequency range in which the impedance of the shunt path is below a predetermined value is between 10 MHz and 10 GHz. The high-frequency circuit device according to feature 1.

3. In the range of 10 MHz to 10 GHz, the impedance of the shunt path is 1 Ω or less. The high-frequency circuit device according to feature 2.

4. The package further comprises a package gland arranged on the back surface of the aforementioned package substrate. A high-frequency circuit device according to any one of claims 1 to 3.

5. The chip further comprises a chip ground through conductor and a back surface chip ground. The chip ground through-conductor connects the chip ground located on the upper surface of the chip and the back surface chip ground located on the back surface of the chip. The aforementioned back surface chip gland is connected to the package second gland or the package gland of the package substrate via a conductive layer. The high-frequency circuit device according to feature 4.

6. The package further includes a package ground through-conductor that connects the first package ground and the second package ground. The effective wavelength of the high-frequency signal of the aforementioned high-frequency circuit is wavelength λ ｓｉｇ The effective wavelength of the parasitic oscillation generated in the shunt path is defined as wavelength λ. ｐａｒａ In this case, the distance L between the high-frequency element and the package ground penetrating conductor is l ｓｉｇ ≦L≦λ ｐａｒａ That is, A high-frequency circuit device according to any one of claims 1 to 5.

7. The package substrate further comprises an inner layer signal conductor located inside the base material of the package substrate, in a position where it partially overlaps with the package signal conductor in a direction perpendicular to the upper surface of the package substrate. A high-frequency circuit device according to any one of claims 1 to 6.

8. With respect to the aforementioned shunt path, a portion of the shunt path, a portion of the first package ground, and a portion of the second package ground are arranged to overlap. A high-frequency circuit device according to any one of claims 1 to 7.

9. The package substrate further has a cavity for housing the chip, At the bottom surface of the cavity, the back surface chip ground located on the back surface of the chip and the package second ground are electrically connected. A high-frequency circuit device according to any one of claims 1 to 8.

10. The signal conductor and the package signal conductor are electrically connected via a wire. A high-frequency circuit device according to any one of claims 1 to 9.

11. In a portion of the region from the chip to the shunt path, lumped element elements are arranged in the thickness direction of the package substrate. A high-frequency circuit device according to any one of claims 1 to 10.

12. The package further comprises a sealing layer that seals the upper surface of the chip and part or all of the upper surface of the package substrate. A high-frequency circuit device according to any one of claims 1 to 11.

13. The chip is placed on the upper surface of the substrate. A high-frequency circuit device according to any one of claims 1 to 12.

14. The aforementioned high-frequency element is a negative resistive element, The aforementioned high-frequency circuit is an antenna that transmits or receives terahertz waves. A high-frequency circuit device according to any one of claims 1 to 13.

15. A high-frequency circuit device according to any one of claims 1 to 14 is used as an oscillator. A receiver that receives high-frequency signals from the aforementioned transmitter, A detection system having a processing circuit for processing the signal from the receiver.

Images