Method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Abstract

To provide a manufacturing method of a nitride semiconductor device and a nitride semiconductor device capable of suppressing diffusion of Ga into a SiO2 film used as a gate insulating film.SOLUTION: A manufacturing method of a nitride semiconductor device includes the steps of forming a silicon oxide film as a gate insulating film on a gallium nitride layer, subjecting the silicon oxide film and the gallium nitride layer to high-temperature heat treatment at treatment temperature of 800°C or more and 1200°C or less, and forming an electrode on the silicon oxide film subjected to the high-temperature heat treatment, and the high-temperature heat treatment is performed in atmosphere containing nitrogen gas at pressure higher than the decomposition pressure of the gallium nitride layer.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Background Art

[0002] Conventionally, a vertical MOSFET using gallium nitride (GaN) has been known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to realize a GaN-MOSFET with excellent reliability, it is desirable to use a silicon oxide film (SiO2 film) having excellent breakdown voltage as a gate insulating film. However, as a method for forming the SiO2 film, after deposition by plasma film formation or the like, heat treatment at a high temperature is required. However, since the diffusion coefficient of gallium (Ga) in the SiO2 film is large, when high-temperature heat treatment is performed, Ga diffuses into the SiO2 film and easily forms charges. When charges are formed in the SiO2 film, the threshold value of the GaN-MOSFET may decrease, or the insulation characteristics of the SiO2 film itself may deteriorate.

[0005] The present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of suppressing the diffusion of Ga into the SiO2 film used as a gate insulating film.

Means for Solving the Problems

[0006] To solve the above problems, a method for manufacturing a nitride semiconductor device according to one aspect of the present invention comprises the steps of: forming a silicon oxide film as a gate insulating film on a gallium nitride layer; performing a high-temperature heat treatment on the silicon oxide film and the gallium nitride layer at a treatment temperature of 800°C to 1200°C; and forming an electrode on the silicon oxide film that has undergone the high-temperature heat treatment. The high-temperature heat treatment is performed in an atmosphere containing nitrogen gas at a pressure higher than the decomposition pressure of the gallium nitride layer. i, nitrogen molecules (N) that are solid-dissolved in the silicon oxide film 2 ) Concentration is 1 × 10 17 cm -3 The above 1.5 × 10 19 cm -3 Set the processing temperature and the nitrogen gas pressure as follows: . A nitride semiconductor device according to one aspect of the present invention comprises a gallium nitride layer, a gate insulating film provided on the gallium nitride layer, and an electrode provided on the gate insulating film. The gate insulating film includes a silicon oxide film. The concentration of nitrogen molecules (N2) solidly dissolved in the silicon oxide film is 1 × 10⁻⁶ 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies: [Effects of the Invention]

[0007] According to one aspect of the present invention, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device that can suppress the diffusion of Ga into an SiO2 film used as a gate insulating film. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing an example of the configuration of a GaN semiconductor device according to Embodiment 1 of the present invention. [Figure 2] Figure 2 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device according to Embodiment 1. [Figure 3A] Figure 3A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 1 in order of steps. [Figure 3B]Figure 3B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 1 in order of steps. [Figure 3C] Figure 3C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 1 in order of steps. [Figure 3D] Figure 3D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 1 in order of steps. [Figure 4] Figure 4 is a graph showing the equilibrium vapor pressure curve of GaN. [Figure 5] Figure 5 is a graph showing an example of a high-temperature heat treatment sequence according to Embodiment 1. [Figure 6] Figure 6 is a plan view showing an example of the configuration of a GaN semiconductor device according to Embodiment 2 of the present invention. [Figure 7] Figure 7 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device according to Embodiment 2. [Figure 8] Figure 8 is a plan view showing an example of the configuration of a GaN semiconductor device according to Embodiment 3 of the present invention. [Figure 9] Figure 9 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device according to Embodiment 3. [Figure 10] Figure 10 is a cross-sectional view showing a modified example 1 of the vertical MOSFET according to Embodiment 3. [Figure 11] Figure 11 is a cross-sectional view showing a modified example 2 of the vertical MOSFET according to Embodiment 3. [Figure 12] Figure 12 is a cross-sectional view showing a modified example 3 of the vertical MOSFET according to Embodiment 3. [Modes for carrying out the invention]

[0009] Embodiments of the present invention are described below. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each device and component, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0010] In the following explanation, the positive Z-axis direction may be referred to as "up," and the negative Z-axis direction as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0011] In the following explanation, the + and - prefixes attached to p and n, which indicate the conductivity type of a semiconductor region, mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - prefixes. However, even if two semiconductor regions are labeled p and p (or n and n), this does not mean that the impurity concentrations of each semiconductor region are exactly the same.

[0012] <Embodiment 1> (Example configuration) Figure 1 is a plan view showing an example configuration of a gallium nitride semiconductor device (an example of the "nitride semiconductor device" of the present invention; hereinafter referred to as a GaN semiconductor device) 1 according to Embodiment 1 of the present invention. Figure 2 is a cross-sectional view showing an example configuration of a GaN semiconductor device 1 according to Embodiment 1. Figure 2 shows a cross-section obtained by cutting the plan view shown in Figure 1 along the line X1-X'1 parallel to the X-axis direction.

[0013] As shown in FIGS. 1 and 2, the GaN semiconductor device 1 according to Embodiment 1 includes a gallium nitride substrate (hereinafter, GaN substrate) 10 and a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 20 provided on the GaN substrate 10. The GaN substrate 10 has, for example, a GaN single crystal substrate 11, an n-type GaN layer 12 provided on the GaN single crystal substrate 11, and a p-type GaN layer 13 (an example of the "gallium nitride layer" of the present invention) provided on the n-type GaN layer 12.

[0014] The GaN single crystal substrate 11 is, for example, an n+-type c-plane GaN single crystal substrate. The n-type impurities contained in the GaN single crystal substrate 11 are one or more of Si (silicon), O (oxygen), and Ge (germanium). For example, the GaN single crystal substrate 11 contains Si as an n-type impurity, and the impurity concentration of Si in the GaN single crystal substrate 11 is 5×10 17 cm -3 or more. The thickness of the GaN single crystal substrate 11 is, for example, 350 μm.

[0015] The GaN single crystal substrate 11 may be a low-dislocation free-standing substrate with a dislocation density of less than 1×10 7 cm -2 If the GaN single crystal substrate 11 is a low-dislocation free-standing substrate, the dislocation density of the GaN layer 13 formed on the GaN single crystal substrate 11 also becomes low. Also, by using a low-dislocation free-standing substrate, even when a large-area power device is formed on the GaN substrate 10, the leakage current in the power device can be reduced. Thereby, the manufacturing apparatus can manufacture the power device with a high yield. Also, in heat treatment, it is possible to prevent the ion-implanted impurities from diffusing deeply along the dislocations.

[0016] The GaN layer 12 is a layer epitaxially grown on the surface of the GaN single crystal substrate 11 and contains, for example, Si as an n-type impurity. Si is doped during the epitaxial growth process of the GaN layer 12. The donor concentration (for example, Si concentration) in the GaN layer 12 is, for example, 5×1015 cm -3 The above 5 x 10 16 cm -3 The following are typical examples, such as 2 × 10 16 cm -3 The thickness of the GaN layer 12 is, for example, 1 μm or less.

[0017] The GaN layer 13 is a layer epitaxially grown on the surface of the GaN layer 12 and contains Mg (magnesium) as a p-type impurity. The Mg is doped during the epitaxial growth process of the GaN layer 13. The concentration of Mg in the GaN layer 13 is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 18 cm -3 The following is a typical example, 1 × 10 17 cm -3 The thickness of the GaN layer 13 is, for example, 4 μm.

[0018] The configuration of the GaN substrate 10 is not limited to the above. For example, the n-type GaN layer 12 may be absent, and a p-type GaN layer 13 may be directly provided on the n+-type GaN single crystal substrate 11. Alternatively, the GaN substrate 10 may consist only of a Mg-doped p-type single crystal GaN layer. In other words, the GaN substrate 10 may be a Mg-doped p-type GaN single crystal substrate.

[0019] The lateral MOSFET 20 comprises a gate insulating film 21 provided on a Mg-doped p-type GaN layer 13, a gate electrode 22 (an example of the "electrode" in the present invention) provided on the gate insulating film 21, an n+-type source region 23 provided on the GaN layer 13, an n+-type drain region 24 provided on the GaN layer 13, a source electrode 25 provided above the GaN layer 13 and in contact with the source region 23, and a drain electrode 26 provided above the GaN layer 13 and in contact with the drain region 24.

[0020] The gate insulating film 21 is, for example, an SiO2 film. The thickness of the SiO2 film that is the gate insulating film 21 is, for example, 100 nm. Alternatively, the gate insulating film 21 may be a multilayer film including an SiO2 film. For example, the gate insulating film 21 may include an SiO2 film provided on the GaN layer 13 and another insulating film provided on the SiO2 film. Examples of the other insulating film include one or more of the following: an Al2O3 film, a SiON film, an AlSiO film, and an AlON film.

[0021] The gate electrode 22 is adjacent to the channel region via a gate insulating film 21. The gate electrode 22 is made of, for example, aluminum (Al) and has a thickness of 200 nm. Alternatively, the gate electrode 22 may be made of a material other than Al. For example, the gate electrode 22 may be made of polysilicon doped with metals such as Ti, Ni, or W, or with impurities, or it may be made of silicides such as WSi or NiSi. The source region 23 and drain region 24 are provided in the GaN layer 13 below both sides of the gate electrode 22. The source region 23 and drain region 24 are, for example, n+ type impurity implantation layers. The source region 23 and drain region 24 are implanted with 1 × 10⁻¹⁶ Si as n-type impurities. 19 cm -3 The above 5 x 10 20 cm -3 It contains the following concentrations.

[0022] As shown in Figure 2, the source electrode 25 is in contact with the source region 23 and the p-type GaN layer 13 through an opening h1 provided in the gate insulating film 21. This allows the potential of the p-type GaN layer 13 to be fixed at the potential of the source electrode 25. The drain electrode 26 is in contact with the drain region 24 through an opening h2 provided in the gate insulating film 21. The drain electrode 26 is not in contact with the p-type GaN layer 13.

[0023] The source electrode 25 and drain electrode 26 are made of Al or Al-Si alloy, Ni, Ni alloy, Ti-Al alloy, Ni-Au alloy, etc. The source electrode 25 may also have a barrier metal layer between it and the source region 23. The drain electrode 26 may also have a barrier metal layer between it and the drain region 24. The barrier metal layer may be made of Ti (titanium). That is, the source electrode 25 and drain electrode 26 may be a stack of Ti layers and Al layers, or a stack of Ti layers and Al-Si alloy layers. The source electrode 25 may also be an electrode that serves as a source pad (not shown), or it may be an electrode provided separately from the source pad. The drain electrode 26 may also be an electrode that serves as a drain pad (not shown), or it may be an electrode provided separately from the drain pad.

[0024] The source electrode 25 may be directly connected to the p-type GaN layer 13, or it may be indirectly connected via a p-type layer (not shown). This allows the potential of the p-type GaN layer 13 to be fixed at the potential of the source electrode 25. Furthermore, the portion of the source electrode 25 that is in contact with the source region 23 and the portion that is in contact with the p-type GaN layer 13 (i.e., the portion that functions as a body electrode) may be made of the same material or of different materials.

[0025] Furthermore, Figure 2 shows an example in which the source electrode 25 also serves as the body electrode connected to the p-type GaN layer 13 (i.e., they are integrated), but the embodiments of the present invention are not limited to this. The GaN semiconductor device 1 may also have a body electrode connected to the p-type GaN layer 13 in addition to the source electrode 25. In this case as well, the source electrode 25 and the body electrode may be made of the same material or of different materials.

[0026] (Manufacturing method) Next, a method for manufacturing the GaN semiconductor device 1 will be described. Figures 3A to 3D are cross-sectional views showing the manufacturing method of the GaN semiconductor device 1 according to Embodiment 1 in order of steps. The GaN semiconductor device 1 is manufactured using various manufacturing equipment, including a resist coating apparatus, exposure apparatus, etching apparatus, ion implantation apparatus, heat treatment apparatus, film deposition apparatus, and CMP (Chemical Mechanical Polishing) apparatus. In Figure 3A, the manufacturing apparatus sequentially epitaxially grows a Si-doped GaN layer 12 and an Mg-doped GaN layer 13 on a GaN single crystal substrate 11 (see Figure 2). Si is doped into the GaN layer 12 during the epitaxial growth process. Mg is doped into the GaN layer 13 during the epitaxial growth process.

[0027] Next, the manufacturing apparatus ion-implants n-type impurities into the source formation region (hereinafter referred to as the source formation region) 23' and the drain formation region (hereinafter referred to as the drain formation region) 24' in the GaN layer 13. For example, the manufacturing apparatus forms a mask (not shown) on the GaN layer 13. The mask is composed of an SiO2 film, an Al2O3 film, or a photoresist. The mask has an opening above the source formation region and the drain formation region, and covers the other regions. The manufacturing apparatus ion-implants Si into the GaN layer 13 on which the mask has been formed. After ion implantation, the manufacturing apparatus removes the mask from the GaN layer 13.

[0028] Next, the manufacturing apparatus performs heat treatment to activate the source formation region 23' and drain formation region 24', i.e., the Si ion-implanted layer, in which n-type impurities (e.g., Si) are ion-implanted. For example, a 300 nm AlN protective film (not shown) is formed on the GaN layer 13, and heat treatment is performed at 1100°C / 5 min in an RTA processing apparatus under an N2, 1 atm atmosphere. This heat treatment activates the Si, and the source formation region 23' and drain formation region 24' become n+ type source region 23 and drain region 24. Furthermore, this heat treatment can recover to some extent defects in the source region 23 and drain region 24 caused by Si ion implantation. Furthermore, if the high-temperature heat treatment after SiO2 film formation, as described later, is performed at 1100°C or higher, the heat treatment step for activating the Si ion implantation layer may be omitted here and instead performed in conjunction with the high-temperature heat treatment after SiO2 film formation, as described later.

[0029] Next, as shown in Figure 3B, the manufacturing apparatus forms an SiO2 film as a gate insulating film 21' on the GaN layer 13. This SiO2 film is formed by a microwave plasma CVD method using a gas mixture of monosilane (SiH4), oxygen (O2), and argon (Ar). The components of the gas used to form this SiO2 film are not limited to those described above. In addition to monosilane, disilane (Si2H6) may be used as the Si raw material in the gas. In addition to oxygen gas, water or oxygen radicals may be used as the oxygen raw material in the gas. Furthermore, the method for forming this SiO2 film may be, for example, remote plasma CVD or RF plasma CVD.

[0030] Furthermore, it is preferable that the substrate temperature (i.e., the temperature of the GaN substrate 10) when forming the SiO2 film as the gate insulating film 21' be kept below 350°C, for example. This sufficiently suppresses Ga diffusion from the GaN substrate 10 into the SiO2 film, preventing Ga from being incorporated into the SiO2 film.

[0031] Next, the manufacturing apparatus performs a high-temperature heat treatment on the gate insulating film 21' and the GaN substrate 10 at a processing temperature of 800°C to 1200°C. This high-temperature heat treatment uses nitrogen at a pressure higher than the decomposition pressure of the GaN constituting the GaN substrate 10. moleculeThe process is carried out in an atmosphere containing (N2) gas. For example, this high-temperature heat treatment may be carried out in an atmosphere containing only N2, or in an atmosphere containing N2 and another inert gas (for example, Ar). If the high-temperature heat treatment is carried out in an atmosphere containing only N2, the pressure of N2 is set to a pressure higher than the decomposition pressure of GaN. If the high-temperature heat treatment is carried out in an atmosphere of a mixed gas containing N2 and another inert gas (for example, Ar), the partial pressure of N2 in the mixed gas is set to a pressure higher than the decomposition pressure of GaN. Note that the "other inert gas" mentioned above is not limited to Ar, but may also be neon (Ne), etc. Also, the "other inert gas" mentioned above may be a gas mixture of multiple types of inert gases (for example, a gas mixture of Ar and Ne).

[0032] Figure 4 is a graph showing the equilibrium vapor pressure curve of GaN. This graph was created based on the literature "Journal of Crystal Growth 350 (2012) 21-26, Fig. 2". In Figure 4, the horizontal axis represents the heat treatment temperature, and the vertical axis represents the N2 pressure (partial pressure) in the heat treatment atmosphere. As shown in Figure 4, when the heat treatment temperature exceeds approximately 800°C, the N2 pressure (partial pressure) exceeds 1 atmosphere, and nitrogen is released from the GaN surface. atom (N) Omissions occur.

[0033] In the embodiments of the present invention, high-temperature heat treatment after SiO2 film formation is performed using a nitrogen atmosphere pressure higher than this pressure, thereby reducing nitrogen from the GaN surface. atom (N) Suppression of leakage. A high-pressure nitrogen atmosphere is used so that the N2 pressure (partial pressure) is maintained above the equilibrium vapor pressure curve of GaN from the start to the end of the high-temperature heat treatment (i.e., the region where GaN does not decompose). If the high-temperature heat treatment temperature is between 900°C and 1000°C, the N2 pressure (partial pressure) is set to between 10 atmospheres and 50 atmospheres so that the N2 pressure (partial pressure) is above the equilibrium vapor pressure curve of GaN. If the high-temperature heat treatment temperature is between 1000°C and 1200°C, the N2 pressure (partial pressure) is set to between 50 atmospheres and 1000 atmospheres.

[0034] For example, if the high-temperature heat treatment temperature is 900°C, set the N2 pressure (partial pressure) to 10 atmospheres or higher. If the high-temperature heat treatment temperature is 1000°C, set the N2 pressure (partial pressure) to 50 atmospheres or higher. If the high-temperature heat treatment temperature is 1200°C, set the N2 pressure (partial pressure) to approximately 1000 atmospheres. This makes it possible to maintain the pressure (partial pressure) of N2 in the region above the equilibrium vapor pressure curve of GaN during high-temperature heat treatment. This suppresses the breaking of Ga-N bonds on the surface of the GaN layer 13 during high-temperature heat treatment, and prevents nitrogen from being released from the surface of the GaN layer 13. atom (N) Leakage can be suppressed. The diffusion of Ga from the GaN layer 13 into the SiO2 film can be suppressed, and the incorporation of Ga into the SiO2 film can be suppressed.

[0035] Furthermore, since the decomposition of GaN is suppressed at the SiO2 film-GaN layer 13 interface, the reaction between Ga, which constitutes GaN, and O, which constitutes SiO2, is also suppressed. As a result, the formation of a gallium oxide layer at the SiO2 film-GaN layer 13 interface can be suppressed. At the SiO2 film-GaN layer 13 interface, the thickness of the gallium oxide layer can be limited to the equivalent of one atomic layer, for example, between 1 Å and 5 Å. Furthermore, as mentioned above, if this high-temperature heat treatment is performed at 1100°C or higher, the heat treatment process for activating the Si ion implantation layer may be carried out in conjunction with this high-temperature heat treatment process.

[0036] Furthermore, as shown in Figure 5 below, an example of a high-temperature heat treatment sequence is provided. In each embodiment of the present invention, an additional heat treatment step of 900°C or lower may be performed after the high-temperature heat treatment sequence. This allows for additional modification annealing of the oxide film, additional interface formation treatment, or dehydrogenation treatment in cases where hydrogen (H) may be incorporated into the Mg-doped layer during high-pressure annealing.

[0037] Next, the manufacturing apparatus partially etches the gate insulating film 21'. The manufacturing apparatus leaves the gate insulating film 21' in the region that will become the gate of the lateral MOSFET 20 and its surroundings, and removes the gate insulating film 21' from the other regions. As a result, as shown in Figure 3C, the gate insulating film 21 is formed from the gate insulating film 21', and openings h1 and h2 are formed.

[0038] Next, as shown in Figure 3D, the manufacturing apparatus forms a metal film on top of the GaN layer 13 and patterns the formed metal film to form the gate electrode 22. The metal film constituting the gate electrode 22 is formed by vapor deposition or sputtering. The patterning of the metal film is performed by wet etching, dry etching, or lift-off method.

[0039] Next, the manufacturing apparatus forms an interlayer insulating film (not shown) by plasma CVD or the like. Next, the manufacturing apparatus partially etches the interlayer insulating film to form contact holes that open above the source region 23 and above the drain region 24, respectively. Next, the manufacturing apparatus forms a source electrode 25 and a drain electrode 26 on the source region 23 and the drain region 24 that are exposed from below the contact holes, respectively. The metal films constituting the source electrode 25 and the drain electrode 26 are formed by evaporation or sputtering, etc. The patterning of the metal films is performed by wet etching, dry etching, or lift-off method. After these steps, the GaN semiconductor device 1 shown in Figures 1 and 2 is completed.

[0040] (An example of a high-temperature heat treatment sequence) Figure 5 is a graph showing an example of a high-temperature heat treatment sequence according to Embodiment 1. In Figure 5, the upper graph shows the sequence of pressure changes in the chamber, and the lower graph shows the sequence of temperature changes. In both the upper and lower graphs of Figure 5, P1 on the horizontal axis represents the period of the heating process from 650°C to 1000°C, P2 represents the period of maintaining 1000°C, and P3 represents the period of the cooling process from 1000°C to 650°C.

[0041] In one example sequence shown in Figure 5, nitrogen is introduced into the chamber at the start of the process so that the pressure is 100 atmospheres at 1000°C according to Boyle's Law (PV=nRT). molecule (N2) is added, the chamber is sealed, and initial pressure is applied. After sealing the chamber and applying initial pressure, the inside of the chamber is heated (period P1). As the temperature inside the chamber rises, the N2 pressure inside the chamber rises according to Boyle's Law. As long as the inside of the chamber is sealed, the N2 pressure inside the chamber is in the region above the equilibrium vapor pressure curve shown in Figure 4 (i.e., the region where GaN does not decompose). During periods P1 and P2, the N2 pressure inside the chamber is maintained at a pressure higher than the decomposition pressure of GaN. Therefore, during periods P1 and P2, nitrogen from GaN is released. atom (N) This can suppress omissions.

[0042] Furthermore, during period P2, nitrogen is transferred from a high-pressure nitrogen atmosphere into the SiO2 film used as a gate insulating film. atom (N) diffuses into the SiO2 film, and nitrogen enters the film. atom (N) is dissolved in the SiO2 film. molecule (N2) The solid solution concentration is close to the solid solution limit determined by the temperature and pressure during period P2 (for example, 1 × 10⁻¹⁰ 17 cm -3 The above 1.5 × 10 19 cm -3 The following results. Therefore, it is possible to prevent N from detaching from the GaN surface and solid-solving into the SiO2 film, thereby suppressing the decomposition of GaN.

[0043] Furthermore, during the cooling process (period P3) after the 1000°C heat treatment, the chamber is kept sealed until the temperature inside the chamber drops below 650°C. Even during period P3, the N2 pressure inside the chamber is maintained at a pressure higher than the GaN decomposition pressure. This ensures that nitrogen is not released from the GaN during period P3. atom (N) leakage can be suppressed. The N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 is set to a high value (for example, 1 × 10⁻⁶). 17 cm -3 The above 1.5 × 10 19 cm -3It can be maintained as follows: At temperatures below 650°C, nitrogen is released from GaN. atom (N) Almost no omission occurs, and nitrogen in the SiO2 film atom Because the diffusion coefficient of (N) is also small, Ga diffusion from GaN to the SiO2 film is suppressed even when the chamber is opened to the atmosphere. In other words, the effect of suppressing Ga diffusion by inhibiting GaN decomposition continues.

[0044] In this example, the chamber pressure is controlled based on Boyle's Law (PV=nRT) during periods P1 to P3 by sealing the chamber and applying an initial pressure. However, embodiments of the present invention are not limited to this. In embodiments of the present invention, high-temperature heat treatment may be performed using a device that can increase or decrease the pressure inside the chamber during periods P1 to P3. Even in such cases, the pressure inside the chamber is maintained in a region above the equilibrium vapor pressure curve shown in Figure 4 (i.e., a region where GaN is not decomposed) from the start of the heating process until the end of the cooling process. This prevents nitrogen from being released from the GaN. atom (N) leakage can be suppressed. The N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 is set to a high value (for example, 1 × 10⁻⁶). 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies.

[0045] (Effects of Embodiment 1) As described above, the method for manufacturing a GaN semiconductor device 1 according to Embodiment 1 of the present invention comprises the steps of: forming an SiO2 film as a gate insulating film 21 on the surface 10a of a GaN substrate 10 (for example, the surface of a GaN layer 13); performing a high-temperature heat treatment on the SiO2 film and the GaN substrate 10 at a processing temperature of 800°C or more and 1200°C or less; and forming a gate electrode 22 on the SiO2 film that has undergone the high-temperature heat treatment. The high-temperature heat treatment is performed using nitrogen at a pressure higher than the decomposition pressure of the GaN layer 13. molecule The procedure is carried out in an atmosphere containing (N2) gas.

[0046] According to this, it is possible to suppress the breaking of Ga-N bonds on the surface of the GaN layer 13 during high-temperature heat treatment, and nitrogen from the surface of the GaN layer 13 atom (N) leakage can be suppressed. Ga diffusion from the GaN layer 13 into the SiO2 film used as the gate insulating film 21 can be suppressed, and the incorporation of Ga into the SiO2 film used as the gate insulating film 21 can be suppressed. As a result, a gate insulating film 21 with excellent breakdown strength and suppressed Ga incorporation can be formed. Furthermore, the above high-temperature heat treatment results in a high N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 (for example, 1 × 10⁻⁶). 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies. (Evaluation results) Table 1 shows the evaluation results performed by the inventors. In Table 1, "e" is an exponential notation indicating a power of 10. For example, 1e17 is 1 × 10⁻¹⁷. 17 This means that 1e18 is 1 × 10 18 It means...

[0047] [Table 1]

[0048] (1) Comparative Example 1 In Table 1, the processing condition "No heat treatment" represents the data for the case where high-temperature heat treatment is not performed after forming the SiO2 film used as the gate insulating film (Comparative Example 1). In Comparative Example 1, the N2 solid solution concentration in the SiO2 film is 1e17cm³. -3 It is less than 1 e17 cm³, and the Ga concentration in the SiO2 film is also 1 e17 cm³. -3 It was less than [value missing]. In Comparative Example 1, where no heat treatment was performed, no Ga diffusion from GaN to the SiO2 film occurred.

[0049] (2) Comparative Example 2 In Table 1, the processing condition "1 atmosphere, 900°C" represents data (Comparative Example 2) obtained when heat treatment at 1 atmosphere, 900°C was performed after forming the SiO2 film used as the gate insulating film. Since 1 atmosphere, 900°C corresponds to the region below the equilibrium vapor pressure curve shown in Figure 4, GaN decomposes into Ga and N2, and Ga diffusion occurs from the GaN layer to the SiO2 film. In Comparative Example 2, the Ga concentration in the SiO2 film is 1e18cm³. -3 It was a higher value than that. The mobility of the MOS transistor using the SiO2 film as the gate insulating film in Comparative Example 2 (hereinafter referred to as the MOS transistor of Comparative Example 2) was reduced compared to the mobility of the MOS transistor using the SiO2 film as the gate insulating film in Comparative Example 1 (hereinafter referred to as the MOS transistor of Comparative Example 1). Furthermore, the threshold voltage and gate leakage of the MOS transistor of Comparative Example 2 were also reduced compared to the threshold voltage and gate leakage of the MOS transistor of Comparative Example 1.

[0050] (3) Example 1 In Table 1, the processing condition "10 atmospheres, 900°C" represents data (Example 1) obtained when heat treatment at 10 atmospheres, 900°C was performed after forming the SiO2 film used as the gate insulating film. Since 10 atmospheres, 900°C corresponds to the region above the equilibrium vapor pressure curve shown in Figure 4, GaN hardly decomposes, and Ga diffusion from the GaN layer to the SiO2 film hardly occurs. In Example 1, the N2 solid solution concentration in the SiO2 film is 1.4e17cm². -3 Therefore, the Ga concentration in the SiO2 film is 1e17cm³. -3 It was less than [amount missing]. The mobility and threshold values ​​of the MOS transistor using the SiO2 film of Example 1 as the gate insulating film (hereinafter referred to as the MOS transistor of Example 1) were comparable to those of the MOS transistor of Comparative Example 1. The gate leakage of the MOS transistor of Example 1 was reduced compared to that of the MOS transistor of Comparative Example 1.

[0051] (4) Example 2 In Table 1, the processing condition "100 atmospheres, 1000°C" represents the data (Example 2) obtained when heat treatment at 100 atmospheres and 1000°C was performed after forming the SiO2 film used as the gate insulating film. Since 100 atmospheres and 1000°C corresponds to the region above the equilibrium vapor pressure curve shown in Figure 4, GaN hardly decomposes, and Ga diffusion from the GaN layer to the SiO2 film hardly occurs. In Example 2, the N2 solid solution concentration in the SiO2 film is 1.3e17cm². -3 Therefore, the Ga concentration in the SiO2 film is 1e17cm³. -3 It was less than [amount missing].

[0052] The mobility and threshold values ​​of the MOS transistor using the SiO2 film of Example 2 as the gate insulating film (hereinafter referred to as the MOS transistor of Example 2) were comparable to those of the MOS transistor of Comparative Example 1. The gate leakage of the MOS transistor of Example 2 was further reduced compared to that of the MOS transistor of Comparative Example 1. (Regarding the N2 solid solubility limit in SiO2 films)

[0053] Equations (1) and (2) below are disclosed in the paper "K. Kajihara et al., Appl. Phys. Lett. 91, 071904 (2007)". This paper evaluates the solid solubility limit when N2 is initially present in amorphous SiO2. Equation (1) is the formula for calculating the solid solubility concentration of N2 in an SiO2 film. Equation (2) is the formula for calculating the solid solubility S, one of the parameters of equation (1). In equation (1), C N2 ∫ represents the N2 solid solution concentration in the SiO2 film, and Pressure represents the N2 pressure. In equation (2), k represents the Boltzmann constant, and T represents the temperature (absolute temperature (K)).

[0054]

number

[0055] From equations (1) and (2), when high-temperature heat treatment is performed under the processing conditions of "processing temperature of 900°C and N2 pressure of 10 atmospheres or higher", the N2 solid solution concentration in the SiO2 film is approximately 1.4 × 10⁻⁶. 17 cm -3 In summary, by maintaining the SiO2 film in a high N2 solid solution state during high-temperature heat treatment, a pseudo-high N2 application state is created at the SiO2-GaN interface, suppressing the decomposition of GaN.

[0056] From equations (1) and (2), when high-temperature heat treatment is performed under the processing conditions of "processing temperature of 1000°C and N2 pressure of approximately 50 atmospheres", the N2 solid solution concentration in the SiO2 film is approximately 6.6 × 10⁻¹⁰ 17 cm -3 That concludes the explanation. When high-temperature heat treatment is performed under the processing conditions of "processing temperature of 1200°C and N2 pressure of approximately 1000 atmospheres," the N2 solid solution concentration in the SiO2 film is approximately 1.2 × 10⁻¹⁰. 19 cm -3 This concludes the explanation. As a result, at high processing temperatures and N2 pressures, the N2 solid solution concentration in the SiO2 film becomes too high. For this reason, it is preferable to set the upper limits of the processing conditions for the high-temperature heat treatment of the present invention to "processing temperature of 1200°C and N2 pressure of 1000 atmospheres". The amount of N2 in the SiO2 film can be measured by SIMS analysis or Raman spectroscopy.

[0057] <Embodiment 2> Embodiment 1 described above illustrates the application of the present invention to a lateral MOSFET. However, the application of the present invention is not limited to lateral MOSFETs. For example, the present invention may be applied to a vertical MOSFET, or to a power device comprising a vertical MOSFET.

[0058] (Example configuration) Figure 6 is a plan view showing an example configuration of a GaN semiconductor device 1A (an example of the "nitride semiconductor device" of the present invention) according to Embodiment 2 of the present invention. Figure 7 is a cross-sectional view showing an example configuration of a GaN semiconductor device 1A according to Embodiment 2. Figure 7 shows a cross-section obtained by cutting the plan view of Figure 6 along the line X2-X'2. As shown in Figures 6 and 7, the GaN semiconductor device 1A comprises a GaN substrate 10A and a plurality of vertical MOSFETs 20A provided on the GaN substrate 10. In the GaN semiconductor device 1A, the vertical MOSFETs 20A are repeatedly provided in one direction (for example, in the X-axis direction). Each vertical MOSFET 20A is a repeating unit structure, and these unit structures are arranged in a line in one direction (for example, in the X-axis direction). For example, in the GaN semiconductor device 1A, elongated vertical MOSFETs 20A in the Y-axis direction are arranged in a line in the X-axis direction, and are arranged in a stripe pattern in a plan view.

[0059] The GaN substrate 10A comprises, for example, an n+ type GaN single crystal substrate 11 and an n type GaN layer 12 provided on the GaN single crystal substrate 11. The configuration of the GaN single crystal substrate 11 is as described in Embodiment 1. The GaN layer 12 is a layer epitaxially grown on the surface of the GaN single crystal substrate 11 and contains Si or O as an n-type impurity. Si or O is doped during the epitaxial growth process of the GaN layer 12. In Embodiment 2 and Embodiment 3 described later, the GaN layer 12 contains, for example, Si in a quantity of 1 × 10⁻¹⁶ as an n-type impurity. 16 cm -3 The above 1 x 10 17 cm -3 It is contained in the following concentrations. The thickness of the GaN layer 12 is, for example, 5 μm to 20 μm.

[0060] Furthermore, a p-type well region 14 (an example of the "gallium nitride layer" of the present invention) is provided on the surface side of the GaN layer 12 (i.e., the surface 10Aa of the GaN substrate 10A). The well region 14 is a p-type impurity layer formed by ion implantation of Mg (magnesium) as a p-type impurity into the surface of the GaN layer 12 and heat treatment. The concentration of p-type impurities (e.g., Mg) in the well region 14 is higher than the concentration of n-type impurities (e.g., Si) contained in the GaN layer 12, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm -3 The following applies:

[0061] As shown in Figure 7, the vertical MOSFET 20A has a planar structure. For example, the vertical MOSFET 20A has a gate electrode 22 provided on a flat gate insulating film 21. The vertical MOSFET 20A has a structure in which a p-type well region 14 and an n+-type source region 23 are arranged in a double configuration on the surface side of the n-type GaN layer 12. Because of this structure, the vertical MOSFET 20A may also be called a vertical MOSFET with a DMOS structure.

[0062] The source electrode 25 of the vertical MOSFET 20A is located on the front surface 10Aa side of the GaN substrate 10A and is in contact with the source region 23 and the well region 14, respectively. The drain electrode 26 of the vertical MOSFET 20A is located on the back surface 10Ab side of the GaN substrate 10A and is in contact with the GaN single crystal substrate 11. The gate insulating film 21 of the vertical MOSFET 20A has the same configuration as the gate insulating film 21 of the horizontal MOSFET 20 described in Embodiment 1 (see Figure 2). For example, the gate insulating film 21 is an SiO2 film with a thickness of 100 nm. Alternatively, the gate insulating film 21 may be a laminated film including an SiO2 film provided on the surface 10Aa of the GaN substrate 10A and another insulating film provided on the SiO2 film. Examples of the other insulating film include one or more of the following: an Al2O3 film, a SiON film, an AlSiO film, and an AlON film.

[0063] (Manufacturing method) The gate insulating film 21 of the vertical MOSFET 20A is formed in the same manner as the gate insulating film 21 of the horizontal MOSFET 20 described in Embodiment 1 (see Figure 2). For example, the manufacturing apparatus forms an SiO2 film on the surface 10Aa of the GaN substrate 10A using a plasma CVD method. Next, the manufacturing apparatus applies a high-temperature heat treatment to this SiO2 film as illustrated in the sequence shown in Figure 5. Subsequently, the manufacturing apparatus partially etches the SiO2 film that has undergone the high-temperature heat treatment. The manufacturing apparatus leaves the SiO2 film in the region that will become the gate of the vertical MOSFET 20A and its surroundings, and removes the SiO2 film from the other regions. In this way, the manufacturing apparatus forms a high-temperature heat-treated SiO2 film as the gate insulating film 21.

[0064] After the gate insulating film 21 is formed, the manufacturing apparatus forms the gate electrode 22 on the gate insulating film 21. Next, the manufacturing apparatus forms the source electrode 25 on the front surface 10Aa side of the GaN substrate 10A and the drain electrode 26 on the back surface 10Ab side of the GaN substrate 10A. Through these steps, the GaN semiconductor device 1A shown in Figures 6 and 7 is completed.

[0065] In Embodiment 2, in the above high-temperature heat treatment, nitrogen is introduced into the SiO2 film from a high-pressure nitrogen atmosphere. atom (N) diffuses into the SiO2 film, and nitrogen enters the film. atom (N) is dissolved in solid solution. For this reason, in the vertical MOSFET 20A, the N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 is close to the solid solution limit (for example, 1 × 10⁻⁶). 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies:

[0066] (Effects of Embodiment 2) As described above, the method for manufacturing a GaN semiconductor device 1A according to Embodiment 2 of the present invention comprises the same steps as the method for manufacturing a GaN semiconductor device 1 according to Embodiment 1. This makes it possible to suppress the breaking of Ga-N bonds on the surface 10Aa of the GaN substrate 10A (for example, the surface of the GaN layer 12) during high-temperature heat treatment, and nitrogen from the surface of the GaN layer 12 atom (N) leakage can be suppressed. Ga diffusion from the GaN layer 12 into the SiO2 film used as the gate insulating film 21 can be suppressed, and Ga incorporation into the SiO2 film used as the gate insulating film 21 can be suppressed. As a result, a gate insulating film 21 with excellent breakdown strength and suppressed Ga incorporation can be formed. Furthermore, the above high-temperature heat treatment results in a high N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 (for example, 1 × 10⁻⁶). 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies.

[0067] (modified version) In the vertical MOSFET 20A with a planar structure shown in Figure 7, a JFET region (not shown) may be provided in the n-type GaN layer 12. The JFET region is an n-type impurity layer. The JFET region is part of the drift region and functions as a current path between the n+-type GaN single crystal substrate 11 and the channel formed in the p-type well region 14. The JFET region has a higher concentration of n-type impurities than other drift regions (e.g., the n-type GaN layer 12). By providing the JFET region, the on-resistance of the vertical MOSFET 20A can be reduced.

[0068] <Embodiment 3> The present invention may be applied to a vertical MOSFET having a trench gate structure, or to a power device comprising a vertical MOSFET having a trench gate structure.

[0069] (Example configuration) Figure 8 is a plan view showing an example configuration of a GaN semiconductor device 1B according to Embodiment 3 of the present invention (an example of a "nitride semiconductor device" of the present invention). Figure 9 is a cross-sectional view showing an example configuration of a GaN semiconductor device 1B according to Embodiment 3. Figure 9 shows a cross-section obtained by cutting the plan view of Figure 8 along the line X3-X'3. As shown in Figures 8 and 9, the GaN semiconductor device 1B comprises a GaN substrate 10 and a plurality of vertical MOSFETs 20B provided on the GaN substrate 10. In the GaN semiconductor device 1B, the vertical MOSFETs 20B are repeatedly provided in one direction (for example, in the X-axis direction). Each vertical MOSFET 20B is a repeating unit structure, and these unit structures are arranged in a line in one direction (for example, in the X-axis direction). For example, in the GaN semiconductor device 1B, elongated vertical MOSFETs 20B in the Y-axis direction are arranged in a line in the X-axis direction, forming a stripe pattern in plan view.

[0070] As shown in Figure 9, the vertical MOSFET 20B has a trench gate structure. For example, a trench H is formed in the GaN substrate 10, opening on the surface side of the p-type GaN layer 13 and with the n-type GaN layer 12 as its bottom surface. The gate insulating film 21 is formed to cover the bottom and sides of the trench H. The n+ type source region 23 is a GaN layer 13 and is provided in the regions located on both sides of the trench H. The source electrode 25 is provided on the surface 10a side of the GaN substrate 10 and is in contact with the n+ type source region 23 and the p type GaN layer 13. The drain electrode 26 is provided on the back surface 10b side of the GaN substrate 10 and is in contact with the GaN single crystal substrate 11.

[0071] The gate insulating film 21 of the vertical MOSFET 20B has the same configuration as the gate insulating film 21 of the horizontal MOSFET 20 described in Embodiment 1 (see Figure 2). For example, the gate insulating film 21 is an SiO2 film provided to cover the bottom and sides of the trench H, and its thickness is 100 nm. Alternatively, the gate insulating film 21 may be a laminated film including an SiO2 film provided to cover the bottom and sides of the trench H and another insulating film provided on the SiO2 film. Examples of other insulating films include one or more of the following: an Al2O3 film, a SiON film, an AlSiO film, and an AlON film.

[0072] (Manufacturing method) The gate insulating film 21 of the vertical MOSFET 20B is formed in the same manner as the gate insulating film 21 of the horizontal MOSFET 20 described in Embodiment 1 (see Figure 2). For example, the manufacturing apparatus forms an SiO2 film on the surface 10a of the GaN substrate 10 in which the trench H is formed using plasma CVD. Next, the manufacturing apparatus applies a high-temperature heat treatment to this SiO2 film as illustrated in the sequence shown in Figure 5. Subsequently, the manufacturing apparatus partially etches the SiO2 film that has undergone the high-temperature heat treatment. The manufacturing apparatus leaves the SiO2 film on the bottom surface, sides and surrounding areas of the trench H, and removes the SiO2 film from the other areas. In this way, the manufacturing apparatus forms a high-temperature heat-treated SiO2 film as the gate insulating film 21.

[0073] After the gate insulating film 21 is formed, the manufacturing apparatus forms the gate electrode 22 on the gate insulating film 21. Next, the manufacturing apparatus forms the source electrode 25 on the surface 10a side of the GaN substrate 10 and the drain electrode 26 on the back surface 10b side of the GaN substrate 10. Through these steps, the GaN semiconductor device 1B shown in Figures 8 and 9 is completed.

[0074] In Embodiment 3, in the above high-temperature heat treatment, nitrogen is introduced into the SiO2 film from a high-pressure nitrogen atmosphere. atom (N) diffuses into the SiO2 film, and nitrogen enters the film. atom (N) is dissolved in solid solution. For this reason, in the vertical MOSFET 20B, the N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 is close to the solid solution limit (for example, 1 × 10⁻¹⁰). 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies:

[0075] (Effects of Embodiment 3) The method for manufacturing the GaN semiconductor device 1B according to Embodiment 3 comprises the same steps as the method for manufacturing the GaN semiconductor device 1 according to Embodiment 1. According to this, it is possible to suppress the breaking of Ga-N bonds on the surface 10a of the GaN substrate 10 (for example, the surface of the GaN layer 13) during high-temperature heat treatment, and nitrogen from the surface of the GaN layer 13 atom (N) leakage can be suppressed. Ga diffusion from the GaN layer 13 into the SiO2 film used as the gate insulating film 21 can be suppressed, and the incorporation of Ga into the SiO2 film used as the gate insulating film 21 can be suppressed. As a result, a gate insulating film 21 with excellent breakdown strength and suppressed Ga incorporation can be formed. Furthermore, the above high-temperature heat treatment results in a high N2 solid solution concentration in the SiO2 film used as the gate insulating film 21 (for example, 1 × 10⁻⁶). 17 cm -3 The above 1.5 × 10 19 cm -3 The following applies.

[0076] (modified version) Figure 10 is a cross-sectional view showing a modified example 1 of the vertical MOSFET 20B according to Embodiment 3. As shown in Figure 10, the vertical MOSFET 20B may have a structure in which the p-type region is deeply formed in areas other than the trench H. For example, the p-type GaN layer 13, which is the p-type region, may not be at the bottom of the trench H, but may be formed shallowly from the surface of the GaN substrate 10 in the area surrounding the trench H, and deeply from the surface of the GaN substrate 10 in areas other than the area surrounding the trench H. With such a structure, it is possible to mitigate the electric field at the bottom of the trench H.

[0077] Figure 11 is a cross-sectional view showing a modified example 2 of the vertical MOSFET 20B according to Embodiment 3. As shown in Figure 11, the vertical MOSFET 20B may have a structure in which a p-type region is located at the bottom of the trench H. For example, the p-type GaN layer 13, which is the p-type region, may be located at the bottom of the trench H. In this modified example 2 as well, the p-type GaN layer 13 may be formed shallowly from the surface of the GaN substrate 10 in the peripheral region of the trench H, and deeply from the surface of the GaN substrate 10 in regions other than the peripheral region of the trench H. With such a structure, it is possible to further mitigate the electric field at the bottom of the trench H.

[0078] Figure 12 is a cross-sectional view showing a modified example 2 of the vertical MOSFET 20B according to Embodiment 3. As shown in Figure 12, the vertical MOSFET 20B may have an n-type JFET region 121 in the peripheral region of the trench H, where the n-type impurity concentration is higher than that of the GaN layer 11. For example, the n-type JFET region 121 may be located in the peripheral region of the trench H, directly beneath a p-type GaN layer 13 formed shallowly from the surface of the GaN substrate 10. With such a structure, the on-resistance of the vertical MOSFET 20B can be reduced while mitigating the electric field at the bottom of the trench H.

[0079] <Other Embodiments> As described above, the present invention has been described by embodiments and modifications, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure. Of course, the present invention includes various embodiments and the like that are not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the embodiments and modifications described above. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist. The technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable from the above description. [Explanation of Symbols]

[0080] 1, 1A, 1B GaN semiconductor device 10, 10A GaN substrate 10a, 10Aa surface 10Ab, 10b back side 11 GaN single crystal substrate 12, 13 GaN layer 14-well area 20 Horizontal MOSFETs 20A, 20B Vertical MOSFETs 21 Gate insulating film 22 Grid cells 23 Source Area 23' Source formation region 24 Drain region 24' Drain formation region 25 Source electrodes 26 Drain electrode H Trench P1, P2, P3 period

Claims

1. A step of forming a silicon oxide film as a gate insulating film on a gallium nitride layer, A step of performing high-temperature heat treatment on the silicon oxide film and the gallium nitride layer at a treatment temperature of 800°C or more and 1200°C or less, The process includes forming an electrode on the silicon oxide film that has undergone the high-temperature heat treatment, The aforementioned high-temperature heat treatment is The process is carried out in an atmosphere containing nitrogen gas at a pressure higher than the decomposition pressure of the gallium nitride layer. In the aforementioned high-temperature heat treatment, Nitrogen molecules (N) that are solid-dissolved in the silicon oxide film ２ ) Concentration is 1 × 10 １７ cm －３ The above 1.5 x 10 １９ cm －３ A method for manufacturing a nitride semiconductor device, comprising setting the processing temperature and the pressure of the nitrogen gas as follows.

2. In the process of performing the high-temperature heat treatment, The processing temperature is 900°C or higher and 1000°C or lower. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the pressure of the nitrogen gas is 10 atmospheres or more and 50 atmospheres or less.

3. In the process of performing the high-temperature heat treatment, The processing temperature is 1000°C or higher and 1200°C or lower. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the pressure of the nitrogen gas is 50 atmospheres or more and 1000 atmospheres or less.

4. The process of performing the aforementioned high-temperature heat treatment is: The process includes raising the temperature of the silicon oxide film and the gallium nitride layer from 650°C to the processing temperature. The aforementioned heating process is A method for manufacturing a nitride semiconductor device according to any one of claims 1 to 3, wherein the method is carried out in the atmosphere containing nitrogen gas at a pressure higher than the decomposition pressure.

5. The process of performing the aforementioned high-temperature heat treatment is: The process includes a cooling process for reducing the temperature of the silicon oxide film and the gallium nitride layer from the processing temperature to 650°C. The aforementioned cooling process is A method for manufacturing a nitride semiconductor device according to any one of claims 1 to 4, wherein the method is carried out in the atmosphere containing nitrogen gas at a pressure higher than the decomposition pressure.

6. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 5, wherein the gallium nitride layer is a Mg-doped p-type GaN layer.

7. The Mg concentration in the p-type GaN layer is 1×10 １６ cm －３ or more and 1×10 １８ cm －３ or less. A method for manufacturing a nitride semiconductor device according to claim 6.

8. Gallium nitride layer, A gate insulating film provided on the gallium nitride layer, The gate insulating film comprises an electrode provided on the gate insulating film, The gate insulating film includes a silicon oxide film. Nitrogen molecules (N) that are solid-dissolved in the silicon oxide film ２ ) Concentration is 1 × 10 １７ cm －３ The above 1.5 x 10 １９ cm －３ The following is a nitride semiconductor device.

9. The nitride semiconductor device according to claim 8, wherein the thickness of the gallium oxide layer between the gallium nitride layer and the silicon oxide film is 1 Å or more and 5 Å or less.

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