Multilayer electronic components and their manufacturing methods

Abstract

To provide a laminated electronic component and a manufacturing method thereof that improve defects such as side margin gaps, occurrence of short circuits, and deterioration of moisture resistance reliability.SOLUTION: A method includes providing a ceramic green sheet 211 having a plurality of internal electrode patterns 221 and 222 spaced apart from each other, laminating ceramic green sheets to form a ceramic green sheet laminate, obtaining a laminate body 210 by cutting the ceramic green sheet laminate such that the ends of the internal electrode patterns have side surfaces exposed in the width direction, an adhesive layer adhering step of adhering an adhesive layer AD attached to a base film BF to the exposed side surface of the internal electrode pattern of the laminate, and an adhesive layer peeling step of removing foreign matter on the side surface by peeling the adhesive layer.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a multilayer electronic component and a method for manufacturing the same.

Background Art

[0002] A multilayer ceramic capacitor (MLCC), which is one type of multilayer electronic component, is a chip-type capacitor that is mounted on printed circuit boards of various electronic products such as video devices like liquid crystal display (LCD) devices and plasma display panel (PDP) panels, computers, smartphones, and mobile phones, and serves to charge or discharge electricity.

[0003] Such a multilayer ceramic capacitor can be used as a component of various electronic devices due to its advantages of being small in size while ensuring high capacitance and being easy to mount. With the miniaturization and high-power output of various electronic devices such as computers and mobile devices, the requirements for miniaturization and high capacitance of multilayer ceramic capacitors are increasing.

[0004] Also, recently, the industry's interest in automotive electrical components has increased, and multilayer ceramic capacitors are also required to have high reliability and high-strength characteristics for use in automobiles or infotainment systems.

[0005] In order to miniaturize and increase the capacitance of multilayer ceramic capacitors, it is required to maximize the effective electrode area (by increasing the effective volume fraction necessary for realizing capacitance).

[0006] As described above, in order to realize small and high-capacitance multilayer ceramic capacitors, when manufacturing multilayer ceramic capacitors, the internal electrodes are exposed in the width direction of the main body, thereby maximizing the area of ​​the internal electrodes in the width direction by a margin-less design. Furthermore, after fabricating such a chip, a side margin portion is attached separately to the exposed electrode surface in the width direction of the chip before firing to complete the process.

[0007] While attaching the side margin separately can improve the capacitance per unit volume of the capacitor, it may lead to problems such as gaps forming in the side margin, short circuits, and reduced moisture resistance. [Overview of the project] [Problems that the invention aims to solve]

[0008] One of the several objectives of the present invention is to provide a stacked electronic component and a method for manufacturing the same that improves defects such as gaps forming in the side margin, the occurrence of short circuits, and reduced moisture resistance.

[0009] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0010] A method for manufacturing a stacked electronic component according to one embodiment of the present invention includes the steps of: providing a first ceramic green sheet on which a plurality of first internal electrode patterns are formed at predetermined intervals and a second ceramic green sheet on which a plurality of second internal electrode patterns are formed at predetermined intervals; stacking the first ceramic green sheet and the second ceramic green sheet so that the first internal electrode patterns and the second internal electrode patterns intersect to form a ceramic green sheet stack; cutting the ceramic green sheet stack so that the ends of the first internal electrode patterns and the second internal electrode patterns are exposed in the width direction to obtain a stacked body; attaching a ceramic green sheet for side margins to the side surfaces of the stacked body on which the ends of the first internal electrode patterns and the second internal electrode patterns are exposed; firing the stacked body to which the ceramic green sheet for side margins is attached; heat treating the stacked body in a reducing atmosphere after firing; and forming external electrodes on the stacked body that has been heat treated in a reducing atmosphere, wherein the ceramic green sheet for side margins contains a metal oxide.

[0011] A stacked electronic component according to one embodiment of the present invention includes a body comprising a plurality of dielectric layers, a first and second surface facing each other in a first direction, a third and fourth surface connected to the first and second surfaces and facing each other in a second direction, a fifth and sixth surface connected from the first to the fourth surface and facing each other in a third direction, a side margin portion disposed on the first and second surfaces, external electrodes disposed on the third and fourth surfaces, and a plurality of internal electrodes disposed inside the body, connected to the external electrodes on the third or fourth surface and connected to the side margin portion on the first and second surfaces, wherein when the number of voids in the internal electrodes located within 3 μm from the side margin portion in the direction inward of the body is Np and the number of internal electrodes is Ne, Np / Ne is 0.15 or less. [Effects of the Invention]

[0012] One of the several advantages of this invention is that it suppresses the occurrence of short circuits by removing foreign matter from the cut surface using an adhesive layer.

[0013] Furthermore, one of the several effects of the present invention is that it suppresses defects such as gaps forming in the side margin area, thereby improving the reduction in moisture resistance reliability.

[0014] However, the diverse and beneficial advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0015] [Figure 1] This is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. [Figure 2] This is a perspective view of the multilayer electronic component shown in Figure 1, excluding the external electrodes. [Figure 3] Figure 1 is a perspective view of a stacked electronic component, excluding the external electrodes and side margins. [Figure 4] This is a cross-sectional view along the line I-I' in Figure 1. [Figure 5] This is a cross-sectional view along the line II-II' in Figure 1. [Figure 6] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 7] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 8] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 9] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 10] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 11] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 12] This is a schematic diagram illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention. [Figure 13] It is a drawing schematically showing a method for manufacturing a multilayer electronic component according to an embodiment of the present invention. [Figure 14] It is a drawing schematically showing a method for manufacturing a multilayer electronic component according to an embodiment of the present invention. [Figure 15] It is a drawing schematically showing a method for manufacturing a multilayer electronic component according to an embodiment of the present invention. [Figure 16] It is a drawing schematically showing a method for manufacturing a multilayer electronic component according to an embodiment of the present invention. [Figure 17] It is a drawing schematically showing a method for manufacturing a multilayer electronic component according to an embodiment of the present invention. [Figure 18] It is a drawing schematically showing a method for manufacturing a multilayer electronic component according to an embodiment of the present invention. [Figure 19] An image obtained by scanning with a scanning electron microscope (SEM) so that 20 internal electrodes can be seen at the boundary between the side margin portion and the main body in the central portion in the thickness direction after cutting the inventive example from the center in the length direction in the thickness and width directions. [Figure 20] An image obtained by scanning with a scanning electron microscope (SEM) so that 20 internal electrodes can be seen at the boundary between the side margin portion and the main body in the central portion in the thickness direction after cutting the comparative example from the center in the length direction in the thickness and width directions.

MODE FOR CARRYING OUT THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to ordinary technicians. Therefore, the shape and size of elements in the drawings may be enlarged or reduced (or emphasized or simplified) for a clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0017] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the explanation have been omitted, and thicknesses have been enlarged to clearly represent multiple layers and regions. For the sake of convenience of explanation, the present invention is not necessarily limited to what is shown in the drawings. In addition, components with the same function within the scope of the same idea will be described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, this does not mean that other components are excluded, but rather that other components may be further included, unless otherwise stated.

[0018] In drawings, the W direction can be defined as the first direction or width direction, the L direction as the second direction or length direction, and the T direction as the third direction or thickness direction.

[0019] [Manufacturing method for multilayer electronic components] Figures 6 to 18 are schematic diagrams illustrating a method for manufacturing a stacked electronic component according to one embodiment of the present invention.

[0020] A method for manufacturing a stacked electronic component, which is one embodiment of the present invention, will be described in detail below with reference to Figures 6 to 18.

[0021] A method for manufacturing a stacked electronic component according to yet another embodiment of the present invention includes the steps of: providing a first ceramic green sheet on which a plurality of first internal electrode patterns are formed at predetermined intervals and a second ceramic green sheet on which a plurality of second internal electrode patterns are formed at predetermined intervals; forming a ceramic green sheet stack by stacking the first ceramic green sheet and the second ceramic green sheet so that the first internal electrode patterns and the second internal electrode patterns intersect; obtaining a stacked body by cutting the ceramic green sheet stack so that the ends of the first internal electrode patterns and the second internal electrode patterns are exposed on the sides in the width direction; adhering an adhesive layer to the sides of the stacked body on which the ends of the first internal electrode patterns and the second internal electrode patterns are exposed; and peeling off the adhesive layer to remove foreign matter from the sides.

[0022] As shown in Figure 6, a plurality of first internal electrode patterns 221 are formed on the ceramic green sheet 211 at predetermined intervals. The plurality of first internal electrode patterns 221 may be in the shape of stripes or may be formed parallel to each other.

[0023] The ceramic green sheet 211 described above may be formed from a ceramic paste containing ceramic powder, an organic solvent, and an organic binder.

[0024] The ceramic powder described above is not limited to this, but can be a material with a high dielectric constant, such as a barium titanate (BaTiO3) based material, a lead-composite perovskite based material, or a strontium titanate (SrTiO3) based material, and preferably a barium titanate (BaTiO3) powder can be used. When the ceramic green sheet 211 is fired, it becomes a dielectric layer 111 that constitutes the main body 110.

[0025] The first internal electrode pattern 221 may be formed from an internal electrode paste containing a conductive metal. The conductive metal may be, but is not limited to, one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0026] The method for forming the first internal electrode pattern 221 on the ceramic green sheet 211 is not particularly limited, but it can be formed by a printing method such as screen printing or gravure printing.

[0027] Furthermore, multiple second internal electrode patterns 222 can be formed on another ceramic green sheet 211 at predetermined intervals. These multiple second internal electrode patterns 221 may be in the shape of stripes or may be formed parallel to each other.

[0028] Hereinafter, a ceramic green sheet on which the first internal electrode pattern 221 is formed may be called the first ceramic green sheet 221a, and a ceramic green sheet on which the second internal electrode pattern 222 is formed may be called the second ceramic green sheet 221b.

[0029] Next, as shown in Figure 7, the first and second ceramic green sheets 221a and 221b can be alternately stacked so that the first internal electrode pattern 221 and the second internal electrode pattern 222 are intersected.

[0030] Subsequently, the first internal electrode pattern 221 can become the first internal electrode 121, and the second internal electrode pattern 222 can become the second internal electrode 122.

[0031] In this case, the thickness td' of the first and second ceramic green sheets may be 0.6 μm or less. This makes it possible to realize an ultra-small, high-capacitance stacked electronic component having a thin film with a dielectric layer td thickness of 0.4 μm or less.

[0032] Furthermore, the thickness te' of the first and second internal electrode patterns may be 0.5 μm or less. This makes it possible to realize an ultra-small, high-capacitance stacked electronic component having a thin film with an internal electrode te thickness of 0.4 μm or less.

[0033] Figure 8 is a cross-sectional view showing a ceramic green sheet laminate 220 in which first and second ceramic green sheets are laminated according to one embodiment of the present invention, and Figure 9 is a perspective view showing the ceramic green sheet laminate 220 in which first and second ceramic green sheets are laminated.

[0034] Referring to Figures 8 and 9, the first ceramic green sheet 211a, on which multiple parallel first internal electrode patterns 221 are printed, and the second ceramic green sheet 211b, on which multiple parallel second internal electrode patterns 222 are printed, are stacked alternately on each other.

[0035] More specifically, the layers may be stacked such that the spacing between the central part of the striped first internal electrode pattern 221 printed on the first ceramic green sheet 211a and the striped second internal electrode pattern 222 printed on the second ceramic green sheet 211b overlaps.

[0036] Next, as shown in Figure 9, the ceramic green sheet laminate 220 may be cut across a plurality of striped first internal electrode patterns 221 and striped second internal electrode patterns 222. That is, the ceramic green sheet laminate 210 can become a laminate body 210 cut along mutually orthogonal C1-C1 and C2-C2 cutting lines.

[0037] More specifically, the striped first internal electrode pattern 221 and the striped second internal electrode pattern 222 may be cut in the longitudinal direction to divide them into a plurality of internal electrodes having a certain width. In this case, the laminated ceramic green sheet is also cut together with the internal electrode pattern. This allows the dielectric layer to be formed to have the same width as the internal electrode.

[0038] Furthermore, the laminate can be cut along the C2-C2 cutting line to match individual body sizes. That is, before forming the first and second side margin sections, the rod-shaped laminate can be cut along the C2-C2 cutting line to match individual body sizes to form multiple laminated bodies 210.

[0039] In other words, the rod-shaped laminate can be cut such that a predetermined distance formed between the center of the stacked first internal electrode and the second internal electrode is cut by the same cutting line. As a result, one end of the first internal electrode and the second internal electrode can be alternately exposed on the cut surface.

[0040] The method for cutting the ceramic green sheet laminate 220 is not particularly limited. For example, it can be cut using a blade in a guillotine manner, or a dicing method can be used in which a dicing blade is rotated to cut the material.

[0041] Referring to Figure 10, the laminated body 210 includes first and second surfaces 1 and 2 facing in the first direction, third and fourth surfaces 3 and 4 facing in the second direction, and fifth and sixth surfaces 5 and 6 facing in the third direction, with the first internal electrode pattern 221 exposed on the first, second and third surfaces and the second internal electrode pattern 222 exposed on the first, second and fourth surfaces. The sides on which the ends 222 of the first internal electrode pattern 221 and the second internal electrode pattern are exposed in the width direction may be the first and second surfaces 1 and 2.

[0042] When performing the adhesive layer adhesion step and the adhesive layer peeling step on the first and second surfaces of the laminated body 210, the adhesive layer adhesion step and the adhesive layer peeling step can be performed on one of the first and second surfaces first, and then on the remaining surface.

[0043] Subsequently, an adhesive layer AD is bonded to the exposed side surfaces of the first internal electrode pattern 221 and the second internal electrode pattern 222 of the laminated body 210, and foreign matter on the side surfaces can be removed by peeling off the adhesive layer AD.

[0044] When cutting the ceramic green sheet laminate 220, adhesive material used to fix the ceramic green sheet laminate 220 may adhere to the blade or dicing blade, and this adhesive material may transfer to the laminate body 210, becoming adhesive residue 30. This adhesive residue 30 may cause defects such as gaps in the side margins, potentially reducing moisture resistance reliability.

[0045] Furthermore, referring to Figure 12, which is an enlarged view of the S1 region in Figure 11, when the ceramic green sheet laminate 220 is cut, the metal particles 21 of the internal electrode patterns 221 and 222 may be pushed out by the blade or dicing blade and exist as foreign matter on the surface of the ceramic green sheet 211 on the side of the laminate body 210. At this time, some of the metal particles 21 may oxidize upon exposure to the surface and exist as oxide metal particles 21'. The metal particles 21 and oxide metal particles 21' present on the surface of the ceramic green sheet 211 may become passages that electrically connect the first internal electrode and the second internal electrode after firing, potentially causing a short circuit. On the other hand, the laminate body 210 shown in Figures 11 to 18 is a cross-section cut along the line III-III' in Figure 10 so that both the first and second internal electrode patterns are visible.

[0046] According to one embodiment of the present invention, when an adhesive layer AD is bonded to the side surface of the laminated body 210 where the ends of the first internal electrode pattern 221 and the second internal electrode pattern 222 are exposed, and foreign matter on the side surface is removed by peeling off the adhesive layer AD, short circuits caused by metal particles 21 and metal oxide particles 21' arranged on the surface of the ceramic green sheet 211 on the side surface of the laminated body 210 can be suppressed, and defects such as gaps in the side margin portion due to adhesive residue 30 and defects in moisture resistance reliability can be suppressed.

[0047] Furthermore, by removing foreign matter using the adhesive layer AD, the physical and chemical deformation of the laminated body 210 can be minimized compared to foreign matter removal methods such as polishing, cutting, etching, and laser polishing, thereby increasing productivity and efficiently removing foreign matter.

[0048] As shown in Figures 11 and 13, after preparing the base film BF to which the adhesive layer AD is attached, pressure can be applied so that the adhesive layer AD adheres to the exposed sides of the first internal electrode pattern 221 and the second internal electrode pattern 222 of the laminate body 210.

[0049] Next, as shown in Figure 15, when the adhesive layer AD is peeled off, foreign substances such as adhesive residue 30, conductive metal 21, and oxidized conductive metal 21' can be removed from the adhesive layer AD.

[0050] Figure 16 is an enlarged view of region S2 in Figure 15. Referring to Figure 16, which shows an enlarged view of the side surface of the laminated body 210 from which the foreign matter has been removed, it can be confirmed that some of the metal particles 21 are exposed on the surface, thereby removing the oxidized metal oxide particles 21'.

[0051] Furthermore, it can be confirmed that the surface roughness increased due to the removal of the metal particles 21 and the oxidized conductive metal 21', and that a portion of the ceramic green sheet and internal electrode pattern was removed.

[0052] In this case, the average centerline roughness of the sides 1 and 2 of the laminated body 210 after peeling off the adhesive layer AD may be 1.5 times or more greater than the average centerline roughness of the sides 1 and 2 of the laminated body 210 before peeling off the adhesive layer AD. This increases the contact area between the side margin and the side surface, and improves the adhesive strength with the side margin.

[0053] In this case, the removed portion of the region may have a depth d in the direction perpendicular to the side surface of the laminated body 210 that is greater than 0 nm and less than or equal to 250 nm. If the depth d exceeds 250 nm, the capacitance may decrease, which may result in a defect in appearance.

[0054] The type of adhesive layer AD does not need to be particularly limited and may be natural, synthetic rubber, silicone, urethane, acrylic, or a mixture of silicone, acrylic, urethane, etc. Examples of natural materials include latex, starch, cellulose, and protein, while examples of synthetic rubber materials include IR (Isoprene Rubber), NBR (Nitrile Butadiene Rubber), SBR (Styrene Butadiene Rubber), CR (Chloroprene Rubber), and Silicon Rubber.

[0055] However, according to one embodiment of the present invention, as shown in Figure 14, the adhesive layer AD contains a substance that hardens when irradiated with ultraviolet light, and the process may further include the step of irradiating the adhesive layer AD with ultraviolet light (UV) before peeling it off after it has been adhered.

[0056] If the adhesive layer AD contains a substance that hardens when irradiated with ultraviolet light, when pressure is applied to the adhesive layer AD so that it adheres to the exposed sides of the ends of the first internal electrode pattern 221 and the second internal electrode pattern 222 of the laminated body 210, the foreign matter becomes partially embedded within the adhesive layer AD. Subsequently, when ultraviolet light (UV) is irradiated, the adhesive layer hardens and its adhesive strength decreases, allowing the foreign matter to be easily removed without causing significant damage to the surface of the laminated body 210.

[0057] On the other hand, there is no particular need to limit the ratio of the thickness of the base film BF to the thickness of the adhesive layer AD. Experiments have confirmed that even when the thickness of the base film BF is very thin, and the ratio of the thickness of the base film to the thickness of the adhesive layer is 2.8%, foreign matter can be stably removed.

[0058] Therefore, the side of the adhesive layer opposite to the side attached to the laminated body is bonded to the base film, and the ratio of the thickness of the base film to the thickness of the adhesive layer may be 2.8% or more.

[0059] In this case, the type of base film does not need to be particularly limited and may be metallic, polymer, paper, cotton, rubber, etc. Examples of metallic films include Cu foil and Al foil, while examples of film films include PET (Polyethylene terephthalate), PI (Polyimid), PU (Polyurethane), PO (Polyolefin), PP (Polypropylene), PE (Polyethylene), nylon, cellophane, PEN (Polyethylene Naphtalate), Teflon® (Polytetrafluoroethylene), PVC (Polyvinyl chloride), PVDC (Polyvinylidene chloride), and PS (Polystyrene).

[0060] In one embodiment, the adhesive layer bonding step can be performed at a temperature of 85°C or lower. At temperatures exceeding 85°C, the adhesive layer may stick to the laminate body 210, and the amount of adhesive residue may increase, which may lead to an increase in defects such as gaps in the side margins and defects in moisture resistance reliability.

[0061] Subsequently, a first side margin portion and a second side margin portion can be formed on the first and second surfaces of the laminated body 210.

[0062] As shown in Figure 17, the ceramic green sheet 212 for the side margin can be attached to the side surface of the laminated body 210 where the ends of the first internal electrode pattern and the second internal electrode pattern are exposed.

[0063] A ceramic green sheet 212 for the side margin portion can be attached to the first surface of the laminated body 210 to form a first side margin portion 112, and then a ceramic green sheet 212 for the side margin portion can be attached to the second surface of the laminated body 220 to form a second side margin portion 113.

[0064] Specifically, the method for forming the first side margin portion 112 involves placing a ceramic green sheet 212 for the side margin portion on top of a rubber perforated elastic material 300.

[0065] Next, the laminated body 210 is rotated 90 degrees so that its first side faces the ceramic green sheet 212 for the side margin, and then the laminated body 210 is pressed and adhered to the ceramic green sheet 212 for the side margin.

[0066] When the laminated body 210 is pressed and adhered to the ceramic green sheet 212 for the side margin, and the ceramic green sheet 212 for the side margin is transferred to the laminated body 210, the rubber perforated elastic material 300 ensures that the ceramic green sheet 212 for the side margin extends to the corners of the side surface of the laminated body 210, and the remaining portion may be cut off.

[0067] Figure 18 shows that the ceramic green sheet 212 for the side margin is formed up to the corner of the side surface of the laminated body 210.

[0068] Subsequently, the laminated body 210 can be rotated 180 degrees, and the above-described process can be repeated to form the second side margin portion 113 on the second side surface of the laminated body 210.

[0069] Next, the laminated body 210 to which the ceramic green sheet for the side margin is attached can be sintered. After sintering, the ceramic green sheet 211 becomes the dielectric layer 111, and the first and second internal electrode patterns 221 and 222 become the first and second internal electrodes 121 and 122, respectively. Therefore, after sintering, the laminated body 210 can become a body 110 including the dielectric layer 111 and the first and second internal electrodes 121 and 122.

[0070] In this invention, since the adhesive layer removes the oxide metal particles 21' from sides 1 and 2, the weakly alkaline components of the ceramic green sheet 212 for the side margin come into contact with the unoxidized metal particles of the internal electrode patterns 221 and 222, thereby suppressing the shrinkage of the internal electrodes during firing. As a result, after firing, the number of voids within 3 μm in the direction from sides 1 and 2 towards the interior of the laminated body can be reduced, improving moisture resistance reliability.

[0071] In one embodiment, after firing, when the number of voids within 3 μm from the sides 1 and 2 of the laminated body 210 in the direction toward the interior of the laminated body 210 is Np, and the number of internal electrodes is Ne, the Np / Ne ratio can be ensured to be 0.15 or less. More preferably, the Np / Ne ratio may be 0.10 or less, and even more preferably 0.05 or less.

[0072] Subsequently, external electrodes 131 and 132 can be formed on the third surface of the main body 110 where the first internal electrode 121 is exposed, and on the fourth surface of the main body 110 where the second internal electrode 122 is exposed.

[0073] First, a conductive paste for external electrodes can be applied to the laminated body 210 so as to cover a portion of the side margin portion 212.

[0074] Subsequently, the applied conductive paste for the external electrode can be fired to form the external electrode.

[0075] Subsequently, the step of forming a plating layer on the external electrode can be carried out.

[0076] The method for forming the plating layer is not particularly limited, and electrolytic plating, electroless plating, etc., can be used. Furthermore, the plating layer can be formed using materials such as Ni, Sn, and Pd. In addition, the plating layer can be formed in such a way that two or more layers are formed.

[0077] To give a more specific example of the plating layer, the plating layer may be a Ni plating layer, a Sn plating layer, or a Pd plating layer, and may be formed in a manner in which a Ni plating layer and a Sn plating layer are formed sequentially, or in a manner in which a Ni plating layer and a Pd plating layer are formed sequentially, or in a manner in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are formed sequentially. Furthermore, the plating layer may include multiple Ni plating layers and / or multiple Sn plating layers.

[0078] [Multilayer electronic components] Figure 1 shows a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. Figure 2 is a perspective view of the stacked electronic component shown in Figure 1, excluding the external electrodes. Figure 3 is a perspective view of the stacked electronic component shown in Figure 1, excluding the external electrodes and side margins. Figure 4 is a cross-sectional view along the line I-I' in Figure 1. Figure 5 is a cross-sectional view along the line II-II' in Figure 1. Figure 6 is an enlarged view of the S region in Figure 5.

[0079] In the following, a stacked electronic component 100 according to one embodiment of the present invention will be described with reference to Figures 1 to 6.

[0080] A stacked electronic component 100 according to one embodiment of the present invention includes a plurality of dielectric layers 111, a main body 110 including a first surface 1 and a second surface 2 facing each other in a first direction (W direction), a third surface 3 and a fourth surface 4 connected to the first and second surfaces and facing each other in a second direction (L direction), and a fifth surface 5 and a sixth surface 6 connected to the first to fourth surfaces and facing each other in a third direction (T direction), side margin portions 112 and 113 arranged on the first surface 1 and the second surface 2, and arranged on the third surface 3 and the fourth surface 4 The device includes external electrodes 131 and 132, and a plurality of internal electrodes 121 and 122 arranged inside the main body 110, connected to the external electrodes 131 and 132 on the third surface 3 or the fourth surface 4, and connected to the side margin portions 112 and 113 on the first and second surfaces 1 and 2. When the number of voids in the internal electrodes located within 3 μm from the side margin portion in the direction inward of the main body is Np, and the number of internal electrodes is Ne, then Np / Ne is 0.15 or less.

[0081] The main body 110 has dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0082] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 may be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 may not be a perfectly straight hexahedral shape, but may have a substantially hexahedral shape.

[0083] The main body 110 may have first and second surfaces 1 and 2 facing each other in the first direction (W direction), third and fourth surfaces 3 and 4 connected to the first and second surfaces 1 and 2 and facing each other in the second direction (L direction), and fifth and sixth surfaces 5 and 6 connected to the first and second surfaces 1 and 2 and connected to the third and fourth surfaces 3 and 4 and facing each other in the third direction (Z direction).

[0084] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0085] According to one embodiment of the present invention, the raw materials for forming the dielectric layer 111 are not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate-based materials, lead-composite perovskite-based materials, or strontium titanate-based materials can be used. The barium titanate-based material may include BaTiO3-based ceramic powder, and examples of the ceramic powder include BaTiO3, (Ba1-xCax)TiO3 in which Ca (calcium), Zr (zirconium), etc. are partially dissolved in BaTiO3, Ba(Ti1-yCay)O3, (Ba1-xCax)(Ti1-yZry)O3, or Ba(Ti1-yZry)O3.

[0086] Furthermore, various ceramic additives, organic solvents, binders, dispersants, etc., can be added depending on the purpose of the present invention.

[0087] Multiple internal electrodes 121 and 122, arranged inside the main body 110, have one end exposed on the third surface 3 or the fourth surface 4 of the main body.

[0088] The internal electrodes 121 and 122 described above can be a pair consisting of a first internal electrode 121 and a second internal electrode 122 having opposite polarities.

[0089] One end of the first internal electrode 121 may be exposed to the third surface 3, and one end of the second internal electrode 122 may be exposed to the fourth surface 4. The other end of the first internal electrode 121 may be positioned away from the fourth surface 4, and the other end of the second internal electrode 122 may be positioned away from the third surface 3.

[0090] External electrodes 131 and 132 may be placed on the third surface 3 and the fourth surface 4 of the main body and connected to the internal electrodes 121 and 122.

[0091] Referring to Figure 3, a first internal electrode 121 is formed on the dielectric layer 111. The first internal electrode 121 is not formed along the entire length of the dielectric layer. That is, one end of the first internal electrode 121 is formed up to the third surface 3 and exposed to the third surface 3, and the other end of the first internal electrode 121 may be formed at a predetermined distance from the fourth surface 4 of the main body 110.

[0092] The end of the first internal electrode exposed on the third surface 3 of the main body 110 is connected to the first external electrode 131. Unlike the first internal electrode, one end of the second internal electrode 122 is exposed to the fourth surface 4 and connected to the second external electrode 132, while the other end of the second internal electrode 122 is formed at a predetermined distance from the third surface 3. The above-mentioned internal electrodes may be stacked in more than 400 layers for mounting high-capacitance multilayer electronic components, but are not necessarily limited to this.

[0093] When Np is the number of voids in the internal electrodes located within 3 μm from the side margin portions 112 and 113 in the direction inward of the main body 110, and Ne is the number of internal electrodes, then Np / Ne may be 0.15 or less. More preferably, Np / Ne may be 0.10 or less, and even more preferably 0.05 or less.

[0094] If the number of voids at the ends of internal electrodes adjacent to the side margin increases, they may act as pathways for moisture penetration, potentially reducing moisture resistance reliability. However, by setting Np / Ne to 0.15 or less according to one embodiment of the present invention, moisture resistance reliability can be improved.

[0095] There is no particular limit to the method for controlling the number of voids at the ends of the internal electrodes adjacent to the side margins. However, as described above, by removing the oxide metal particles 21' from the first and second surfaces 1 and 2 of the main body with an adhesive layer before placing the side margins, the weakly alkaline components of the ceramic green sheet 212 for the side margins come into contact with the unoxidized metal particles of the internal electrode patterns 221 and 222, thereby suppressing the shrinkage of the internal electrodes during firing. This makes it possible to suppress the number of voids at the ends of the internal electrodes adjacent to the side margins.

[0096] There are no particular limitations on how to control Np / Ne to 0.15 or less.

[0097] In this case, Np and Ne may be measured from 20 internal electrodes located in the central part of the third direction in a cross-section obtained by cutting the main body from the central part of the second direction in the first and third directions.

[0098] The materials used to form the internal electrodes 121 and 122 are not particularly limited, and any material with excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 can be formed by printing a conductive paste for internal electrodes containing one or more of the following on a ceramic green sheet: nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0099] The present invention is not limited to the printing method of the conductive paste for the internal electrodes described above, and can be screen printing or gravure printing.

[0100] The main body 110 may include a capacitance forming section A that includes a first internal electrode 121 and a second internal electrode 122 arranged facing each other with a dielectric layer 111 in between, and protective layers 114 and 115 formed on both end surfaces (end surfaces) of the capacitance forming section A in the third direction (T direction).

[0101] The capacitance forming section A described above is a part that contributes to the capacitance formation of the capacitor, and can be formed by repeatedly stacking a plurality of first and second internal electrodes 121 and 122 in a third direction (T direction) with a dielectric layer 111 in between.

[0102] The protective layers 114 and 115 can be formed by stacking a single dielectric layer or two or more dielectric layers in the third direction (T direction) on both end surfaces (end surfaces) of the capacitance forming portion in the third direction (T direction), and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress. The protective layers 114 and 115 do not contain internal electrodes and may contain the same material as the dielectric layer 111.

[0103] In one embodiment, the average thickness of the dielectric layer 111 may be 0.4 μm or less. Since the thickness of the dielectric layer corresponds to the spacing of the internal electrodes, a thinner dielectric layer can improve the capacitance of the multilayer electronic component.

[0104] In one embodiment, the average thickness of the internal electrodes 121 and 122 may be 0.4 μm or less. In this embodiment, the multilayer electronic component can improve the step in the capacitor body at the ends of the internal electrodes. Therefore, even if the thickness of the dielectric layer and internal electrodes is reduced as described above to create a multilayer thin film, no major problems occur in the reliability of the multilayer electronic component, and reliability can be ensured while increasing the capacitance of the multilayer electronic component. Furthermore, as described above, when the average thickness of the first and second internal electrodes is reduced, the shrinkage rate after firing decreases, so the diameter of voids at the ends and margins of the capacitor body can be further reduced. Therefore, the reliability of the multilayer electronic component can be further improved.

[0105] The average thickness of the dielectric layer and internal electrode layer can be measured by scanning an image of the longitudinal cross-section of the laminate body with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, in the scanned image, the thickness of one dielectric layer and internal electrode layer can be measured at 30 equally spaced points along its length, and the average value can be calculated. These 30 equally spaced points can be specified in the capacitance formation section A. Furthermore, by extending this average value measurement to 10 dielectric layers and internal electrodes, the average thickness of the dielectric layer and internal electrode layer can be further generalized.

[0106] Side margins 112 and 113 are provided on the first surface 1 and second surface 2 of the main body. The side margins 112 and 113 may include a first side margin 112 provided on the first surface 1 and a second side margin 113 provided on the second surface 2.

[0107] Each side of the multiple internal electrodes 121 and 122 is exposed to the first surface 1 and the second surface 2, which are the widthwise surfaces of the main body 110, and the first side margin portion 112 and the second side margin portion 113 can be arranged on the exposed side portions. The side margins 112 and 113 essentially serve to prevent damage to the internal electrodes 121 and 122 due to physical or chemical stress.

[0108] The size of the first and second side margin portions 112 and 113 in the first direction does not need to be particularly limited. For example, the size of the first and second side margin portions 112 in the first direction may be 2 μm or more and 10 μm or less, respectively. In this case, the size of the first and second side margin portions 112 in the first direction can mean the thickness tc1 of the first or second side margin region that is in contact with the end of the internal electrode located in the central part of the plurality of internal electrodes 121 and 122.

[0109] If the size of the first and second side margin portions 112 and 113 in the first direction is less than 2 μm, it may become difficult to prevent short circuits of the internal electrodes 121 and 122 exposed on the sides. This is because, if it exceeds 10 μm, the overlapping area of ​​the internal electrodes 121 and 122 decreases relatively, and the effect of securing high capacitance by introducing the side margin portions may become weak.

[0110] Referring to Figure 5, the ratio of the thickness tc1 of the first or second side margin region in contact with the end of the central internal electrode among the multiple internal electrodes 121, 122 to the thickness tc2 of the first or second side margin region in contact with the end of the outermost internal electrode may be 1.0 or less. In this case, the thicknesses of the first and second side margin regions can represent the size of the first and second side margins in the first direction.

[0111] There is no particular lower limit to the ratio of the thickness tc2 of the first or second side margin region in contact with the end of the outermost internal electrode to the thickness tc1 of the first or second side margin region in contact with the end of the internal electrode located in the central part, but it is preferably 0.9 or more.

[0112] According to one embodiment of the present invention, unlike in the conventional invention, the first or second side margin portions 112 and 113 are formed by attaching a ceramic green sheet for the side margin portion to the side surface of the main body 110, so that the thickness of the first or second side margin portion is constant at different positions.

[0113] In other words, conventionally, the side margin portion was formed by coating or printing a ceramic slurry, resulting in significant variations in the thickness of the side margin portion depending on its location.

[0114] Specifically, in conventional designs, the thickness of the first or second side margin region that contacts the end of the internal electrode located in the center of the main body was formed to be thicker than the thickness of other regions.

[0115] For example, in conventional designs, the ratio of the thickness of the first or second side margin region in contact with the end of the inner electrode located at the outermost edge to the thickness of the first or second side margin region in contact with the end of the inner electrode located at the central part is less than 0.9, and there is considerable variation in this ratio.

[0116] Thus, in conventional designs where the thickness of the side margin varies significantly depending on its location, the side margin occupies a large portion of a stacked electronic component of the same size. As a result, it is difficult to secure a large size for the capacitance-forming portion, making it challenging to achieve high capacitance.

[0117] In contrast, in one embodiment of the present invention, the ratio of the thickness tc2 of the first or second side margin region that contacts the end of the outermost internal electrode to the thickness tc1 of the first or second side margin region that contacts the end of the central internal electrode among the plurality of internal electrodes 121, 122 is 0.9 or more and 1.0 or less. Therefore, the length of the first and second side margin regions 112, 113 in the first direction can be made thinner, and the size of the capacitance forming portion can be made larger.

[0118] In one embodiment of the present invention, unlike conventional methods, the ceramic green sheet is formed by adhering it to the side surface of the main body, so that the thickness of the first or second side margin portion is constant at different positions. This makes it possible to realize high-capacity stacked electronic components.

[0119] On the other hand, referring to Figure 5, the ratio of the thickness tc3 of the first or second side margin region that contacts the corner of the main body 110 to the thickness tc1 of the first or second side margin region that contacts the end of the internal electrode located in the central part of the multiple internal electrodes 121, 122 may be 1.0 or less.

[0120] Preferably, the lower limit of the ratio of the thickness tc3 of the first or second side margin region that contacts the corner of the main body 110 to the thickness tc1 of the first or second side margin region that contacts the end of the internal electrode located in the central part is 0.9 or more.

[0121] Due to the above characteristics, there is less variation in the thickness of the side margin region, and a larger size can be secured for the capacitance formation area. This makes it possible to realize high-capacitance multilayer electronic components.

[0122] The above tc1, tc2, and tc3 may be measured at cross-sections obtained by cutting the main body from the central part in the second direction in the first and third directions.

[0123] The external electrodes 131 and 132 are positioned on the third surface 3 and fourth surface 4 of the main body 110. As shown in the embodiment in Figure 4, the first and second external electrodes 131 and 132 are positioned on the third and fourth surfaces 3 and 4 of the main body 110, respectively, and are connected to the first and second internal electrodes 121 and 122, respectively.

[0124] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed depending on the form of the internal electrodes 121 and 122 or other purposes.

[0125] Also, referring to Figure 1, the external electrodes 131 and 132 may be arranged in a manner that covers a portion of the side margins 112 and 113.

[0126] On the other hand, the external electrodes 131 and 132 may be formed using any material that has electrical conductivity, such as metal, and the specific material may be determined by considering electrical properties, structural stability, etc., and may also have a multilayer structure.

[0127] As an example of the multilayer structure of the external electrodes 131 and 132, as shown in Figure 4, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, conductive resin layers 131b and 132b placed on the electrode layers 131a and 132a, and plating layers 131c and 132c placed on the conductive resin layers 131b and 132b.

[0128] However, the external electrode may have a two-layer structure including electrode layers 131a and 132a and a plating layer disposed on the electrode layers 131a and 132a.

[0129] The electrode layers 131a and 132a may be fired electrodes containing conductive metal and glass. Alternatively, the electrode layers 131a and 132a may be formed by transferring a sheet containing conductive metal onto the main body. Furthermore, the first and second electrode layers 131a and 132a may be formed using methods such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), or sputtering.

[0130] The conductive metal used in the electrode layers 131a and 132a is not particularly limited as long as it is a material that can be electrically connected to the internal electrodes for capacitance formation. For example, it may include one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0131] The conductive resin layers 131b and 132b may be resin-based electrodes containing a conductive metal and a resin. The conductive metal used in the conductive resin layers 131b and 132b is not particularly limited as long as it is a material that can be electrically connected to the internal electrodes for capacitance formation. For example, it may include one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0132] To give a more specific example for the plating layers 131c and 132c, the plating layer may be a Ni plating layer, an Sn plating layer, or a Pd plating layer, and may be formed in a manner in which a Ni plating layer and an Sn plating layer are formed sequentially, or in a manner in which a Ni plating layer and a Pd plating layer are formed sequentially, or in a manner in which an Sn plating layer, a Ni plating layer, and an Sn plating layer are formed sequentially. Furthermore, the plating layer may include multiple Ni plating layers and / or multiple Sn plating layers.

[0133] (Experimental Example 1) After cutting the ceramic green sheet laminate to form the laminated body as shown in Figure 10, the inventive example performed a foreign matter removal step in which UV tape was adhered and pressed to sides 1 and 2, the UV tape was cured by irradiating it with UV light, and then the UV tape was peeled off. On the other hand, the comparative example did not perform a separate foreign matter removal step.

[0134] Subsequently, the centerline average roughness Ra of sides 1 and 2 of the inventive example and comparative example was measured in the thickness direction and length direction. The average centerline roughness in the thickness direction was measured for 12 lines spaced evenly in the length direction, and the average of these values ​​is shown in Table 1 below. Similarly, the average centerline roughness in the length direction was measured for 12 lines spaced evenly in the thickness direction, and the average of these values ​​is shown in Table 1 below.

[0135] The arithmetic mean roughness Ra is calculated by extracting a reference length l in the direction of the mean line of the roughness curve, then taking the X-axis in the direction of the mean line of this extracted portion and the Y-axis in the direction of the vertical scaling, representing the roughness curve as y=f(x), and expressing the value obtained by the following equation 1 in micrometers.

[0136] [Formula 1] TIFF0007859739000001.tif39153

[0137] The arithmetic mean roughness Ra was measured by scanning the LT surface of the chip in both the length and thickness directions using a Keyence VK-X1000 (Nanosurface 3D optical profiler) device.

[0138] [Table 1]

[0139] The average centerline roughness in the thickness direction for the comparative example was measured to be 0.431, while the average centerline roughness in the thickness direction for the example of the invention was measured to be 0.717, confirming that the centerline roughness in the thickness direction improved by more than 1.5 times.

[0140] Furthermore, the average value of the average centerline roughness in the longitudinal direction for the comparative example was measured to be 0.324, while the average value of the average centerline roughness in the longitudinal direction for the inventive example was measured to be 0.602, confirming that the average centerline roughness in the longitudinal direction improved by more than 1.5 times.

[0141] Subsequently, after forming side margins on the first and second surfaces, the adhesive strength of the side margins was measured. For 100 samples each of the comparative example and the inventive example, the adhesive strength of the side margins was measured using a Dage 4000plus instrument, by pulling the side margins laterally and determining the maximum strength at which the side margins peeled off.

[0142] When the average adhesive strength of the side margin portion of the comparative example was set to 100, the average adhesive strength of the side margin portion of the inventive example was approximately 112, confirming a 12% improvement in adhesive strength.

[0143] After the firing process, the void at the tip of the internal electrode in the width direction was observed.

[0144] First, the WT side surface of the sample chips of the inventive example and comparative example was polished using a polishing machine so that the surface defined by the width direction (W direction) and the thickness direction (T direction) (WT surface) was exposed. At this time, polishing was carried out to a depth of about half the length direction (L direction) of the sample chip, exposing the polished surface, the WT surface (WT polished cross section). The region in which the internal electrodes are stacked was divided into three equal parts in the T direction, and divided into three regions: the upper region, the middle region, and the lower region. Then, as shown in Figures 19 and 20, in the middle region, the number of voids contained in the internal electrodes located within 3 μm from the side margin in the direction inward of the main body was measured as Np.

[0145] Figure 19 is an image of the inventive example, and Figure 20 is an image of the comparative example. Comparing Figure 19 and Figure 20, when Np is the number of voids contained in the internal electrode located within 3 μm from the side margin in the direction toward the inside of the main body, and Ne is the number of internal electrodes, the Np / Ne ratio for the inventive example is 0.15, and the Np / Ne ratio for the comparative example is 0.35. It can be confirmed that the number of voids at the tip of the internal electrode in the inventive example is significantly reduced compared to the comparative example.

[0146] Furthermore, 100 samples each of the comparative example and the inventive example were prepared and their short-circuit failure rates were compared. When the short-circuit failure rate of the comparative example was set to 100, the short-circuit failure rate of the inventive example was measured at 41.10, confirming a significant reduction in the short-circuit failure rate.

[0147] (Experimental Example 2) After removing foreign matter from the adhesive tape according to the specifications and process conditions in Table 2 below, the adhesive residue, defects in the side margins, and moisture resistance reliability were measured and recorded in Table 3 below.

[0148] After clearly separating the adhesive residue from other parts using an image analysis program, the area of ​​the adhesive residue was quantitatively measured.

[0149] For side margin defects, 1200 sample tips per test number were molded and polished in the WT direction. Then, the presence of gaps in the side margins was checked using an optical microscope three times each at 1 / 10, 1 / 3, and 1 / 2 of the T direction. Samples with gaps in the side margins were judged to be defective, and the number of such samples is recorded in Table 3 below.

[0150] The humidity resistance reliability was evaluated on 120 sample chips per test number. Each sample chip was subjected to a 5V / μm electric field for 20 hours in an atmosphere of 120°C and 95% relative humidity. Sample chips whose insulation resistance decreased to 1 / 10 or less compared to before the electric field was applied were judged to be defective, and the number of defective sample chips is listed in Table 3 below.

[0151] [Table 2]

[0152] [Table 3]

[0153] In test number 15, where the temperature during adhesive layer bonding was 100°C, the amount of adhesive residue increased compared to test number 16, where no foreign matter removal process was performed, and the number of defects resulting in gaps in the side margins also increased.

[0154] In all tests from 1 to 14, with the exception of test number 15, the defect rate in the side margin area was significantly reduced compared to test number 16, and the moisture resistance reliability was also improved.

[0155] In particular, in the case of test number 4, the base film was made very thin for the experiment, and it was experimentally confirmed that foreign matter can be stably removed even when the ratio of the thickness of the base film to the thickness of the adhesive layer is 2.8%.

[0156] As described above, embodiments of the present invention have been explained in detail, but the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the accompanying claims. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention. [Explanation of Symbols]

[0157] 100: Stacked Electronic Components 110: Main unit 111: Dielectric layer 112, 113: Side margin section 121, 122: Internal electrode 131, 132: External electrode

Claims

1. The steps include providing a first ceramic green sheet on which a plurality of first internal electrode patterns are formed at predetermined intervals and a second ceramic green sheet on which a plurality of second internal electrode patterns are formed at predetermined intervals, The steps include forming a ceramic green sheet laminate by stacking the first ceramic green sheet and the second ceramic green sheet so that the first internal electrode pattern and the second internal electrode pattern intersect, The steps include: cutting the ceramic green sheet laminate to obtain a laminate body by having sides exposed in the width direction at the ends of the first internal electrode pattern and the second internal electrode pattern; The adhesive layer bonding step involves bonding an adhesive layer to the side surface of the laminated body where the ends of the first internal electrode pattern and the second internal electrode pattern are exposed. The process includes a step of removing the adhesive layer to remove foreign matter from the side surface, A method for manufacturing a laminated electronic component, wherein the average centerline roughness of the side surface after the adhesive layer peeling step is 1.5 times or more than the average centerline roughness of the side surface before the adhesive layer peeling step.

2. The method for manufacturing a stacked electronic component according to claim 1, wherein in the adhesive layer peeling step, a portion of the ceramic green sheet and internal electrode pattern on the side surface is removed, and the portion of the region is greater than 0 nm and less than or equal to 250 nm in the direction perpendicular to the side surface.

3. The adhesive layer contains a substance that hardens when exposed to ultraviolet light. A method for manufacturing a laminated electronic component according to claim 1 or 2, further comprising a step of irradiating the adhesive layer with ultraviolet light between the adhesive layer bonding step and the adhesive layer peeling step.

4. The side of the adhesive layer opposite to the side that adheres to the ceramic green sheet laminate is bonded to the base film. A method for manufacturing a laminated electronic component according to any one of claims 1 to 3, wherein the ratio of the thickness of the base film to the thickness of the adhesive layer is 2.8% or more.

5. The method for manufacturing a stacked electronic component according to any one of claims 1 to 4, wherein the adhesive layer bonding step is performed at 85°C or below.

6. A method for manufacturing a laminated electronic component according to any one of claims 1 to 5, wherein the laminated body includes first and second surfaces facing in a first direction, third and fourth surfaces facing in a second direction, and fifth and sixth surfaces facing in a third direction, the first internal electrode pattern is exposed on the first, second and third surfaces, the second internal electrode pattern is exposed on the first, second and fourth surfaces, and the sides on which the ends of the first internal electrode pattern and the second internal electrode pattern are exposed in the width direction are the first and second surfaces.

7. A method for manufacturing a laminated electronic component according to any one of claims 1 to 6, further comprising the step of attaching a ceramic green sheet for side margins to the side surface of the laminated body from which the adhesive layer has been removed to form a side margin.

8. The method for manufacturing a laminated electronic component according to claim 7, further comprising the step of firing the laminated body to which the ceramic green sheet for the side margin portion is attached.

9. The method for manufacturing a laminated electronic component according to claim 8, wherein, after the firing step, when Np is the number of voids within 3 μm in the direction from the side to the interior of the laminated body and Ne is the number of internal electrodes, Np / Ne is 0.15 or less.

10. The method for manufacturing a stacked electronic component according to claim 8 or 9, further comprising the step of applying a conductive paste for external electrodes to the stacked body so as to cover a portion of the side margin portion.

11. The method for manufacturing a laminated electronic component according to claim 10, further comprising the step of firing the laminated body to which the conductive paste for the external electrodes has been applied to form the external electrodes.

12. The method for manufacturing a stacked electronic component according to claim 11, further comprising the step of forming a plating layer on the external electrode.

13. The method for manufacturing a stacked electronic component according to claim 12, wherein the step of forming the plating layer is carried out so that two or more plating layers are formed.

14. A method for manufacturing a laminated electronic component according to any one of claims 1 to 13, wherein the average centerline roughness of the side surface after the adhesive layer peeling step is 1.5 times or more than the average centerline roughness of the side surface before the adhesive layer peeling step.

15. A method for manufacturing a stacked electronic component according to any one of claims 1 to 14, wherein in the adhesive layer peeling step, a portion of the ceramic green sheet and internal electrode pattern on the side surface is removed, and the portion of the region is greater than 0 nm and less than or equal to 250 nm in the direction perpendicular to the side surface.

16. The side of the adhesive layer opposite to the side that adheres to the laminated body is bonded to the base film. A method for manufacturing a laminated electronic component according to any one of claims 1 to 15, wherein the ratio of the thickness of the base film to the thickness of the adhesive layer is 2.8% or more.

17. The method for manufacturing a laminated electronic component according to any one of claims 1 to 16, wherein the adhesive layer bonding step is performed at 85°C or below.

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