I / O circuit, semiconductor device, cell library, and method for designing circuit of semiconductor device

Abstract

An I / O circuit 10 is formed by combining a plurality of types of standard cells 140 to 160 included in a cell library 100. For example, the standard cell 160 includes: a first element formation region 161 in which to-be-protected elements P61 and N61 having gates in electrical communication with an external terminal T61 are formed; a second element formation region 162 which is disposed closest to the external terminal T61 and in which first protection elements D61 and D62 are formed; and a third element formation region 163 which is disposed between the first element formation region 161 and the second element formation region 162, and in which transistors P62 and N62 are formed. Each of the transistors P62 and N62 has a drain connected to the gates of the to-be-protected elements P61 and N61, and has a source, a gate, and a backgate each connected to a power supply terminal or a ground terminal, to function as a second protection element.

Description

I / O circuit, semiconductor device, cell library, and semiconductor device circuit design method

[0001] The invention disclosed in this specification relates to an I / O (input / output) circuit, a semiconductor device, a cell library, and a circuit design method for a semiconductor device.

[0002] 2. Description of the Related Art Conventionally, a method for designing a circuit of a semiconductor device by arbitrarily combining a plurality of types of standard cells contained in a cell library has been known.

[0003] As prior art related to the above, Patent Documents 1 and 2 can be cited.

[0004] JP 2010-28126 A JP 2010-192932 A

[0005] However, it has been difficult for conventional I / O circuits to simultaneously improve ESD (electro static discharge) resistance and reduce the area.

[0006] In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in this specification has an object to provide an I / O circuit that achieves both improved ESD resistance and a smaller area.

[0007] For example, the I / O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and at least one of the multiple types of standard cells includes: a first element formation region configured to form a protected element having a gate conductive to an external terminal; a second element formation region arranged in the immediate vicinity of the external terminal and configured to form a first protection element for protecting the protected element from electrostatic breakdown; and a third element formation region arranged between the first element formation region and the second element formation region and configured to form a first transistor and a second transistor, and at least one of the first transistor and the second transistor functions as a second protection element for protecting the protected element from electrostatic breakdown by having its drain connected to the gate of the protected element and its source, gate, and back gate all connected to constant potential terminals.

[0008] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0009] According to the invention disclosed in this specification, it is possible to provide an I / O circuit that achieves both improved ESD resistance and a smaller area.

[0010] FIG. 1 is a diagram showing an example of the configuration of a semiconductor device. FIG. 2 is a diagram showing a first comparative example of an I / O circuit. FIG. 3 is a diagram showing a second comparative example of an I / O circuit. FIG. 4 is a diagram showing a third comparative example of an I / O circuit. FIG. 5 is a diagram showing a new embodiment of an I / O circuit.

[0011] 1 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 1 of this example is an LSI that integrates CMOS (complementary MOS) circuits (logic / analog mixed circuits) that are driven mainly at 5 V or less. An I / O circuit 10 that performs ESD protection and signal input / output functions is arranged at the outermost periphery of the semiconductor device 1.

[0012] In addition to the I / O circuit 10, various internal circuits are integrated in the semiconductor device 1. Referring to this figure, the various internal circuits integrated in the semiconductor device 1 include a logic circuit LOGIC, an analog circuit ANALOG, an interface circuit I / F, a non-volatile memory NVM, a volatile memory SRAM, a digital-to-analog converter DAC, an analog-to-digital converter ADC, and a regulator LDO.

[0013] The I / O circuit 10 may be arranged along the four sides of the semiconductor device 1 so as to surround the internal circuitry in a plan view of the semiconductor device 1 .

[0014] An example of the semiconductor device 1 is an in-vehicle integrated communication IC (integrated circuit) that receives commands via an in-vehicle network and controls controllers (such as ECUs (electronic control units)) mounted on various terminal devices (such as LED (light emitting diode) lamps, motors, or switches). In this case, the interface circuit I / F may be compliant with any in-vehicle network (such as LIN (local interconnect network), CXPI (clock extension peripheral interface), or CAN (controller area network)).

[0015] <I / O Circuit (First Comparative Example)> First, before describing a novel embodiment of the I / O circuit 10, a brief description will be given of the electrostatic protection function required for the I / O circuit 10 (the necessity for a secondary clamp). ESD models include the MM (machine model) and the CDM (charged device model). The MM standardizes the phenomenon in which a charged metal releases charge to an IC. On the other hand, the CDM standardizes the phenomenon in which a charged IC releases charge to another conductor. The MM pulse and the CDM pulse have a damped oscillatory waveform with a short period compared to other ESD pulses.

[0016] 2 is a diagram showing a first comparative example of the I / O circuit 10. The I / O circuit 10 of this comparative example includes electrostatic protection diodes D1 and D2 and a current limiting resistor R1 as means for protecting protected elements (in this figure, a P-channel transistor P1 (e.g., a PMOSFET) and an N-channel transistor N1 (e.g., an NMOSFET)) having gates that are electrically connected to the external terminal T1 from electrostatic breakdown.

[0017] The external terminal T1 is a terminal other than a power supply terminal and a ground terminal, and may be, for example, a signal input terminal, a signal output terminal, or a signal input / output terminal.

[0018] In the I / O circuit 10 of this comparative example, for example, when an ESD pulse (CDM pulse) is applied to the external terminal T1, the potential difference (phase shift) between the gate and backgate of the transistor N1 may become large even if the electrostatic protection diodes D1 and D2 are provided, which may result in an overvoltage being applied to the gate oxide film of the transistor N1, which may destroy the transistor N1 or cause a shift in the characteristics of the transistor N1.

[0019] Although not shown, the same problem may occur in the transistor P1. That is, when an ESD pulse (MM pulse or CDM pulse) is applied to the external terminal T1, the transistor P1 may be destroyed or its characteristics may shift.

[0020] <I / O Circuit (Second Comparative Example)> Fig. 3 is a diagram showing a second comparative example of the I / O circuit 10. The I / O circuit 10 of this comparative example is based on the first comparative example (Fig. 2) described above, and further includes an electrostatic protection diode D3.

[0021] The I / O circuit 10 of this comparative example includes electrostatic protection diode D3 arranged immediately adjacent to the gate of transistor N1, in addition to electrostatic protection diodes D1 and D2 arranged immediately adjacent to external terminal T1, so that the transistor N1 is not destroyed or its characteristics shifted even when an ESD pulse (MM pulse or CDM pulse) is applied to the external terminal T1.

[0022] The electrostatic protection diode D3 serves to protect the area between the gate and back gate of the transistor N1 from electrostatic breakdown by passing a current therethrough to suppress a rise in the gate potential of the transistor N1 when an ESD pulse (MM pulse or CDM pulse) is applied to the external terminal T1. Such an electrostatic protection diode D3 is called a secondary clamp.

[0023] Although not shown, a secondary clamp may be provided between the gate and back gate of the transistor P1.

[0024] However, in order to provide a secondary clamp in the I / O circuit 10, an electrostatic protection diode D3 (or a diode-connected MOSFET) must be provided separately in addition to the electrostatic protection diodes D1 and D2, which leads to an increase in the area of ​​the I / O circuit 10.

[0025] <I / O Circuit (Third Comparative Example)> Figure 4 is a diagram showing a third comparative example of the I / O circuit 10 (i.e., a general configuration example for comparison with the embodiments described later). This figure is basically a circuit diagram of the I / O circuit 10. However, if one focuses on the small dashed line frame, it can also be understood as a depiction of a schematic circuit layout of the I / O circuit 10 in a plan view.

[0026] The I / O circuit 10 of this comparative example is formed by arbitrarily combining multiple types of standard cells contained in the I / O cell library 100. The I / O cell library 100 is read from a circuit design program executed by a computer, and can be understood as a type of database for circuit design.

[0027] Each of the multiple types of standard cells has an interface function with the outside of the device (ESD protection function and signal input / output function), and the shapes and layouts of the multiple types of standard cells are standardized so that even if one standard cell is replaced with another standard cell, there is no need to make any modifications to the standard cells arranged around it.

[0028] A circuit design method for the semiconductor device 1 (particularly the I / O circuit 10) using the I / O cell library 100 will now be briefly described. First, a step is performed in which multiple types of standard cells included in the I / O cell library 100 are selected, arranged, and combined arbitrarily. Next, a step is performed in which power lines, signal lines, etc. are laid so as to connect the arbitrarily combined multiple types of standard cells to other circuit blocks. Finally, a step is performed in which it is verified whether the designed circuit satisfies desired conditions (such as electrical characteristics).

[0029] By using such an I / O cell library 100 to design the circuit of the semiconductor device 1 (particularly the I / O circuit 10), it becomes unnecessary to design ESD resistance, latch-up resistance, electrical characteristics, etc. for each terminal, which reduces the burden on the circuit designer and reduces design errors.

[0030] Referring to this figure, the I / O circuit 10 of this comparative example is formed by combining three types of I / O cells 110, 120, and 130 as the above-mentioned multiple types of standard cells.

[0031] I / O cells 110, 120, and 130 have many common parts. Therefore, in the description common to all I / O cells 110, 120, and 130, the prefix "*" (where *=1, 2, or 3) is used in the reference numerals of the components to minimize redundant description.

[0032] The I / O cell 1*0 includes a first element forming region 1*1, a second element forming region 1*2, a third element forming region 1*3, and a fourth element forming region 1*4.

[0033] In the first element formation region 1*1, a P-channel transistor P*1 (e.g., a PMOSFET) and an N-channel transistor N*1 (e.g., an NMOSFET) are formed as protected elements having gates that are conductive to an external terminal T*1.

[0034] The source and back gate of transistor P*1 are both connected to the power supply terminal. The source and back gate of transistor N*1 are both connected to the ground terminal. The drains of transistors P*1 and N*1 are both connected to the output terminal. The gates of transistors P*1 and N*1 are both connected to external terminal T*1 via current limiting resistor R*1. Transistors P*1 and N*1 connected in this manner form a CMOS inverter (a so-called I / O buffer).

[0035] The second element forming region 1*2 is disposed in close proximity to the external terminal T*1. In the second element forming region 1*2, electrostatic protection diodes D*1 and D*2 are formed as first protection elements for protecting the transistors P*1 and N*1 from electrostatic breakdown.

[0036] The anode of the electrostatic protection diode D*1 is connected to the external terminal T*1. The cathode of the electrostatic protection diode D*1 is connected to the power supply terminal. In this way, the electrostatic protection diode D*1 serves as a first upper protection element and is connected between the gates of the transistors P*1 and N*1 and the power supply terminal.

[0037] The cathode of the electrostatic protection diode D*2 is connected to the external terminal T*1. The anode of the electrostatic protection diode D*2 is connected to the ground terminal. In this way, the electrostatic protection diode D*2 serves as a first lower protection element and is connected between the gates of the transistors P*1 and N*1 and the ground terminal.

[0038] The third element formation region 1*3 is disposed between the first element formation region 1*1 and the second element formation region 1*2 (or, in the context of this drawing, between the first element formation region 1*1 and the fourth element formation region 1*4). A P-channel transistor P*2 (e.g., a PMOSFET) and an N-channel transistor N*2 (e.g., an NMOSFET) are formed in the third element formation region 1*3. Note that the connection relationship between the transistors P*2 and N*2 differs for each of the I / O cells 110, 120, and 130, and will be described separately below.

[0039] The fourth element forming region 1*4 is disposed between the first element forming region 1*1 and the second element forming region 1*2 (in accordance with the figure, between the third element forming region 1*3 and the second element forming region 1*2). In the fourth element forming region 1*4, a current limiting resistor R*1 is formed, which is connected between the gates of the transistors P*1 and N*1 and the external terminal T*1.

[0040] The I / O cells 110, 120, and 130 are each formed in the same rectangular shape in a plan view of the I / O circuit 10, and are arranged in the illustrated order from the top of the page.

[0041] Looking more closely, the first element formation regions 111, 121, and 131 are each formed in the same rectangular shape in a plan view of the I / O circuit 10, and are arranged in the illustrated order from the top of the page. The same is true for the second element formation region 1*2, the third element formation region 1*3, and the fourth element formation region 1*4.

[0042] Next, differences between the I / O cells 110, 120, and 130 (connections between the transistors P*2 and N*2) will be described.

[0043] First, the description will focus on the third element formation region 113 of the I / O cell 110. The source, drain, gate, and back gate of the transistor P12 are all connected to the power supply terminal. That is, the transistor P12 is a dummy transistor that has no function and is isolated from the gates of the transistors P11 and N11.

[0044] Meanwhile, the drain of transistor N12 is connected to the gates of transistors P11 and N11. The source and back gate of transistor N12 are both connected to the ground terminal. The gate of transistor N12 is connected to a bias potential terminal (e.g., an intermediate potential between the power supply potential and the ground potential). Transistor N12 connected in this manner functions as a pull-down element (=pull-down resistor) for pulling down the gates of transistors P11 and N11 to the ground potential when external terminal T11 is in an open state (high impedance state).

[0045] In addition, a body diode is provided between the drain and source of the transistor N12, with the drain of the transistor N12 as the cathode and the back gate of the transistor N12 as the anode. Therefore, the transistor N12 also functions as a secondary clamp (corresponding to a second lower protection element) that protects the area between the gate and back gate of the transistor N11 from electrostatic breakdown.

[0046] Next, the description will focus on the third element formation region 123 of the I / O cell 120. The source, drain, gate, and back gate of the transistor N22 are all connected to the ground terminal. That is, the transistor N22 is a dummy transistor that has no function and is isolated from the gates of the transistors P21 and N21.

[0047] Meanwhile, the drain of transistor P22 is connected to the gates of transistors P21 and N21. The source and back gate of transistor P22 are both connected to the power supply terminal. The gate of transistor P22 is connected to a bias potential terminal (e.g., an intermediate potential between the power supply potential and ground potential). Transistor P22 connected in this manner functions as a pull-up element (=pull-up resistor) for pulling up the gates of transistors P21 and N21 to the power supply potential when external terminal T21 is in an open state (high impedance state).

[0048] In addition, a body diode is provided between the drain and source of the transistor P22, with the drain of the transistor P22 as the anode and the back gate of the transistor P22 as the cathode, so that the transistor P22 also functions as a secondary clamp (= second upper protection element) that protects the area between the gate and back gate of the transistor P21 from electrostatic breakdown.

[0049] Next, the description will focus on the third element formation region 133 of the I / O cell 130. The source, drain, gate, and back gate of transistor P32 are all connected to the power supply terminal. The source, drain, gate, and back gate of transistor N32 are all connected to the ground terminal. In other words, transistors P32 and N32 are dummy transistors that have no function and are isolated from the gates of transistors P31 and N31, respectively.

[0050] To summarize the above, in the I / O circuit 10 of this comparative example, a pull-down function by transistor N12 is added to I / O cell 110. Also, a pull-up function by transistor P22 is added to I / O cell 120. On the other hand, in I / O cell 130, both transistors P32 and N32 are dummyed, so that both the pull-up and pull-down functions are disabled.

[0051] In this way, by arbitrarily combining the multiple types of standard cells (I / O cells 110, 120, and 130 in this figure) included in the I / O cell library 100, it is possible to design a wide variety of I / O circuits 10 according to the specifications of each of the external terminals T11, T21, and T31.

[0052] However, the I / O cell 130, which has neither a pull-up function nor a pull-down function, does not have any secondary clamp. Therefore, when an ESD pulse (CDM pulse) is applied to the external terminal T31, there is a risk that the transistors P31 and N31 will be destroyed or their characteristics will shift, as in the first comparative example ( FIG. 2 ).

[0053] Furthermore, the I / O cells 110 and 120 also have only one of the upper and lower secondary clamps, which makes it difficult to say that they provide a sufficient ESD countermeasure (MM countermeasure or CDM countermeasure).

[0054] In the following, a new embodiment will be proposed that can achieve both improved ESD resistance and a smaller area by effectively utilizing the third element forming region 1*3.

[0055] <I / O Circuit (Embodiment)> Fig. 5 is a diagram showing a new embodiment of the I / O circuit 10. The I / O circuit 10 of this embodiment is formed by combining three types of I / O cells 140, 150, and 160 included in the I / O cell library 100, as in the previously described third comparative example (Fig. 4).

[0056] I / O cells 140, 150, and 160 have many common parts. Therefore, in the description common to all I / O cells 140, 150, and 160, a prefix "#" (where #=4, 5, or 6) is used in the reference numerals of the components to minimize redundant description.

[0057] I / O cell 1#0 includes a first element forming region 1#1, a second element forming region 1#2, a third element forming region 1#3, and a fourth element forming region 1#4.

[0058] In the first element formation region 1#1, a P-channel transistor P#1 (e.g., a PMOSFET) and an N-channel transistor N#1 (e.g., an NMOSFET) are formed as protected elements having gates that are conductive to the external terminal T#1.

[0059] The source and back gate of transistor P#1 are both connected to the power supply terminal. The source and back gate of transistor N#1 are both connected to the ground terminal. The drains of transistors P#1 and N#1 are both connected to the output terminal. The gates of transistors P#1 and N#1 are both connected to external terminal T#1 via current limiting resistor R#1. Transistors P#1 and N#1 connected in this manner form a CMOS inverter (a so-called I / O buffer).

[0060] The second element forming region 1#2 is disposed in close proximity to the external terminal T#1. In the second element forming region 1#2, electrostatic protection diodes D#1 and D#2 are formed as first protection elements for protecting the transistors P#1 and N#1 from electrostatic breakdown.

[0061] The anode of the electrostatic protection diode D#1 is connected to the external terminal T#1. The cathode of the electrostatic protection diode D#1 is connected to the power supply terminal. In this way, the electrostatic protection diode D#1 serves as a first upper protection element and is connected between the gates of the transistors P#1 and N#1 and the power supply terminal.

[0062] The cathode of the electrostatic protection diode D#2 is connected to the external terminal T#1, and the anode of the electrostatic protection diode D#2 is connected to the ground terminal. In this way, the electrostatic protection diode D#2 serves as a first lower-side protection element and is connected between the gates of the transistors P#1 and N#1 and the ground terminal.

[0063] The third element formation region 1#3 is disposed between the first element formation region 1#1 and the second element formation region 1#2 (or, in the context of this figure, between the first element formation region 1#1 and the fourth element formation region 1#4). A P-channel transistor P#2 (e.g., a PMOSFET) and an N-channel transistor N#2 (e.g., an NMOSFET) are formed in the third element formation region 1#3. The connection relationship between the transistors P#2 and N#2 differs for each of the I / O cells 140, 150, and 160, and will be described separately below.

[0064] The fourth element formation region 1#4 is disposed between the first element formation region 1#1 and the second element formation region 1#2 (or, in the present drawing, between the third element formation region 1#3 and the second element formation region 1#2). In the fourth element formation region 1#4, a current limiting resistor R#1 is formed, which is connected between the gates of the transistors P#1 and N#1 and the external terminal T#1.

[0065] The I / O cells 140, 150, and 160 are each formed in the same rectangular shape in a plan view of the I / O circuit 10, and are arranged in the illustrated order from the top of the page.

[0066] Looking more closely, the first element formation regions 141, 151, and 161 are each formed in the same rectangular shape in a plan view of the I / O circuit 10, and are arranged in the order shown from the top of the page. The same is true for the second element formation region 1#2, the third element formation region 1#3, and the fourth element formation region 1#4.

[0067] Next, differences between the I / O cells 140, 150, and 160 (connections between the transistors P#2 and N#2) will be described.

[0068] First, the description will focus on the third element formation region 143 of the I / O cell 140. The source, gate, and back gate of transistor P42 are all connected to the power supply terminal. The drain of transistor P42 is connected to the gates of transistors P41 and N41. A body diode is provided between the drain and source of transistor P42, with the drain of transistor P42 as the anode and the back gate of transistor P42 as the cathode. Therefore, transistor P42 functions as a secondary clamp (corresponding to a second upper protection element) that protects the gate and back gate of transistor P41 from electrostatic discharge damage.

[0069] Meanwhile, the drain of transistor N42 is connected to the gates of transistors P41 and N41. The source and back gate of transistor N42 are both connected to the ground terminal. The gate of transistor N42 is connected to a bias potential terminal (e.g., an intermediate potential between the power supply potential and the ground potential). Transistor N42 connected in this manner functions as a pull-down element (=pull-down resistor) for pulling down the gates of transistors P41 and N41 to the ground potential when external terminal T41 is in an open state (high impedance state).

[0070] In addition, a body diode is provided between the drain and source of transistor N42, with the drain of transistor N42 as the cathode and the back gate of transistor N42 as the anode. Therefore, transistor N42 also functions as a secondary clamp (= second lower protection element) that protects the area between the gate and back gate of transistor N41 from electrostatic breakdown.

[0071] Next, the description will focus on the third element formation region 153 of the I / O cell 150. The drain of transistor P52 is connected to the gates of transistors P51 and N51. The source and back gate of transistor P52 are both connected to the power supply terminal. The gate of transistor P52 is connected to a bias potential terminal (e.g., an intermediate potential between the power supply potential and the ground potential). Transistor P52 connected in this manner functions as a pull-up element (= pull-up resistor) for pulling up the gates of transistors P51 and N51 to the power supply potential when external terminal T51 is in an open state (high impedance state).

[0072] In addition, a body diode is provided between the drain and source of the transistor P52, with the drain of the transistor P52 as the anode and the back gate of the transistor P52 as the cathode. Therefore, the transistor P52 also functions as a secondary clamp (= second upper protection element) that protects the area between the gate and back gate of the transistor P51 from electrostatic breakdown.

[0073] Meanwhile, the source, gate, and back gate of transistor N52 are all connected to the ground terminal. The drain of transistor N52 is connected to the gates of transistors P51 and N51. A body diode is provided between the drain and source of transistor N52, with the drain of transistor N52 as the cathode and the back gate of transistor N52 as the anode. Therefore, transistor N52 functions as a secondary clamp (corresponding to a second lower protection element) that protects the area between the gate and back gate of transistor N51 from electrostatic discharge.

[0074] Finally, the following description focuses on the third element formation region 163 of the I / O cell 160. The source, gate, and back gate of transistor P62 are all connected to the power supply terminal. The drain of transistor P62 is connected to the gates of transistors P61 and N61. A body diode is provided between the drain and source of transistor P62, with the drain of transistor P62 as the anode and the back gate of transistor P62 as the cathode. Therefore, transistor P62 functions as a secondary clamp (corresponding to a second upper protection element) that protects the area between the gate and back gate of transistor P61 from electrostatic discharge.

[0075] Meanwhile, the source, gate, and back gate of transistor N62 are all connected to the ground terminal. The drain of transistor N62 is connected to the gates of transistors P61 and N61. A body diode is provided between the drain and source of transistor N62, with the drain of transistor N62 as the cathode and the back gate of transistor N62 as the anode. Therefore, transistor N62 functions as a secondary clamp (corresponding to a second lower protection element) that protects the area between the gate and back gate of transistor N61 from electrostatic discharge.

[0076] To summarize the above, in the I / O circuit 10 of this embodiment, an upper secondary clamp function by transistor P42 and a pull-down function and lower secondary clamp function by transistor N42 are added to the I / O cell 140. Also, a pull-up function and upper secondary clamp function by transistor P52 and a lower secondary clamp function by transistor N52 are added to the I / O cell 150. Meanwhile, an upper secondary clamp function by transistor P62 and a lower secondary clamp function by transistor N62 are added to the I / O cell 160.

[0077] In this manner, in the I / O circuit 10 of this embodiment, the transistors P#2 and N#2 formed in the third element formation region 1#3 of the I / O cell 1#0 that are not used as pull-up or pull-down elements are effectively utilized as secondary clamps rather than being dummy elements. This makes it possible to provide stronger ESD protection (MM protection or CDM protection) without increasing the area of ​​the I / O cell 1#0, thereby achieving both improved ESD resistance and a smaller area.

[0078] <Summary> The various embodiments described above will be summarized below.

[0079] For example, the I / O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and at least one of the multiple types of standard cells includes: a first element formation region configured to form a protected element having a gate conductive to an external terminal; a second element formation region arranged in the immediate vicinity of the external terminal to form a first protection element for protecting the protected element from electrostatic breakdown; and a third element formation region arranged between the first element formation region and the second element formation region to form a first transistor and a second transistor, and at least one of the first transistor and the second transistor has a configuration (first configuration) in which its drain is connected to the gate of the protected element and its source, gate, and back gate are all connected to constant potential terminals, thereby functioning as a second protection element for protecting the protected element from electrostatic breakdown.

[0080] In addition, in the I / O circuit of the first configuration described above, the first protection element may be configured (second configuration) to include a first upper protection element configured to be connected between the gate of the protected element and the power supply terminal, and a first lower protection element configured to be connected between the gate of the protected element and the ground terminal.

[0081] Furthermore, in the I / O circuit having the first or second configuration, the first transistor may have a drain connected to the gate of the protected element and a source, gate, and back gate all connected to a power supply terminal, thereby functioning as a second upper protection element, and the second transistor may have a drain connected to the gate of the protected element, a source, and back gate all connected to a ground terminal, and a gate connected to a bias potential terminal, thereby functioning as a pull-down element and a second lower protection element (third configuration).

[0082] Furthermore, in the I / O circuit having the first or second configuration, the first transistor may have a drain connected to the gate of the protected element, a source and a back gate all connected to a power supply terminal, and a gate connected to a bias potential terminal, thereby functioning as a pull-up element and a second upper protection element, and the second transistor may have a drain connected to the gate of the protected element, and a source, a gate, and a back gate all connected to a ground terminal, thereby functioning as a second lower protection element (fourth configuration).

[0083] Furthermore, in the I / O circuit having the first or second configuration, the first transistor may have a drain connected to the gate of the protected element and a source, gate, and back gate all connected to a power supply terminal, thereby functioning as a second upper protection element, and the second transistor may have a drain connected to the gate of the protected element and a source, gate, and back gate all connected to a ground terminal, thereby functioning as a second lower protection element (fifth configuration).

[0084] Furthermore, in an I / O circuit having any of the first to fifth configurations, the protected element may be configured (sixth configuration) to include a P-channel transistor configured so that its source and back gate are both connected to a power supply terminal, its drain is connected to an output terminal, and its gate is connected to the external terminal, and an N-channel transistor configured so that its drain is connected to the output terminal, its source and back gate are both connected to a ground terminal, and its gate is connected to the external terminal.

[0085] Furthermore, the I / O circuit having any of the first to sixth configurations may be configured (seventh configuration) to further include a fourth element formation region arranged between the first element formation region and the second element formation region and configured to form a current limiting resistor connected between the gate of the protected element and the external terminal.

[0086] Furthermore, for example, the semiconductor device disclosed in this specification has a configuration (eighth configuration) including an I / O circuit having any one of the first to seventh configurations.

[0087] Furthermore, for example, the cell library disclosed in this specification includes a plurality of types of standard cells that can be read out from a circuit design program executed by a computer and arbitrarily combined to form an I / O circuit of a semiconductor device, and at least one of the plurality of types of standard cells includes: a first element formation region configured to form a protected element having a gate conductive to an external terminal; a second element formation region configured to be located immediately adjacent to the external terminal and to form a first protection element for protecting the protected element from electrostatic discharge; and a third element formation region configured to be located between the first element formation region and the second element formation region and to form a first transistor and a second transistor, and at least one of the first transistor and the second transistor has a drain connected to the gate of the protected element and a source, a gate, and a back gate all connected to constant potential terminals, thereby functioning as a second protection element for protecting the protected element from electrostatic discharge (ninth configuration).

[0088] Furthermore, for example, the circuit design method for a semiconductor device disclosed in this specification uses the above-mentioned ninth cell library, and is configured (tenth configuration) to include the steps of selecting, arranging, and arbitrarily combining the multiple types of standard cells included in the cell library, and laying power lines and signal lines to connect the arbitrarily combined multiple types of standard cells to other circuit blocks.

[0089] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0090] 1 Semiconductor device 10 I / O circuit 100 Cell library 110, 120, 130, 140, 150, 160 I / O cell (standard cell) 111, 121, 131, 141, 151, 161 First element forming region 112, 122, 132, 142, 152, 162 Second element forming region 113, 123, 133, 143, 153, 163 Third element forming region 114, 124, 134, 144, 154, 164 Fourth element forming region ADC Analog / digital converter ANALOG Analog circuit D1, D2, D3, D11, D12, D21, D22, D31, D32, D41, D42, D51, D52, D61, D62 Electrostatic protection diode DAC Digital / analog converter I / F Interface circuit LDO Regulator LOGIC Logic circuit N1, N11, N12, N21, N22, N31, N32, N41, N42, N51, N52, N61, N62 Transistor (NMOSFET) NVM Non-volatile memory P1, P11, P12, P21, P22, P31, P32, P41, P42, P51, P52, P61, P62 Transistor (PMOSFET) R1, R11, R21, R31, R41, R51, R61 Current limiting resistor SRAM Volatile memory T1, T11, T21, T31, T41, T51, T61 External terminal

Claims

1. An I / O circuit formed by arbitrarily combining a plurality of types of standard cells included in a cell library, At least one of the plurality of types of standard cells is a first element formation region configured to form a protected element having a gate electrically connected to an external terminal; a second element forming region configured to form a first protection element for protecting the protected element from electrostatic breakdown, the second element forming region being disposed immediately adjacent to the external terminal; a third element forming region disposed between the first element forming region and the second element forming region and configured to form a first transistor and a second transistor; Including, an I / O circuit, wherein at least one of the first transistor and the second transistor functions as a second protection element for protecting the protected element from electrostatic damage by having a drain connected to a gate of the protected element and a source, a gate, and a back gate all connected to a constant potential terminal.

2. 2. The I / O circuit of claim 1, wherein the first protection element includes a first upper protection element configured to be connected between a gate of the protected element and a power supply terminal, and a first lower protection element configured to be connected between a gate of the protected element and a ground terminal.

3. the first transistor has a drain connected to the gate of the protected element and a source, a gate and a back gate all connected to a power supply terminal, thereby functioning as a second upper protection element; 2. The I / O circuit according to claim 1, wherein the second transistor functions as a pull-down element and a second lower protection element by having a drain connected to the gate of the protected element, a source and a backgate both connected to a ground terminal, and a gate connected to a bias potential terminal.

4. the first transistor has a drain connected to the gate of the protected element, a source and a back gate both connected to a power supply terminal, and a gate connected to a bias potential terminal, thereby functioning as a pull-up element and a second upper protection element; 2 . The I / O circuit according to claim 1 , wherein the second transistor functions as a second lower protection element by having a drain connected to the gate of the protected element and a source, a gate and a back gate all connected to a ground terminal.

5. the first transistor has a drain connected to the gate of the protected element and a source, a gate and a back gate all connected to a power supply terminal, thereby functioning as a second upper protection element; 2 . The I / O circuit according to claim 1 , wherein the second transistor functions as a second lower protection element by having a drain connected to the gate of the protected element and a source, a gate and a back gate all connected to a ground terminal.

6. 2. The I / O circuit according to claim 1, wherein the protected element includes a P-channel transistor configured such that a source and a backgate are both connected to a power supply terminal, a drain is connected to an output terminal, and a gate is connected to the external terminal, and an N-channel transistor configured such that a drain is connected to the output terminal, a source and a backgate are both connected to a ground terminal, and a gate is connected to the external terminal.

7. 2. The I / O circuit according to claim 1, further comprising a fourth element formation region arranged between the first element formation region and the second element formation region and configured to form a current limiting resistor connected between a gate of the protected element and the external terminal.

8. A semiconductor device comprising the I / O circuit according to any one of claims 1 to 7.

9. A cell library including a plurality of types of standard cells that can be read out from a circuit design program executed by a computer and arbitrarily combined to form an I / O circuit of a semiconductor device, At least one of the plurality of types of standard cells is a first element formation region configured to form a protected element having a gate electrically connected to an external terminal; a second element forming region configured to form a first protection element for protecting the protected element from electrostatic breakdown, the second element forming region being disposed immediately adjacent to the external terminal; a third element forming region disposed between the first element forming region and the second element forming region and configured to form a first transistor and a second transistor; Including, at least one of the first transistor and the second transistor has a drain connected to a gate of the protected element and a source, a gate, and a back gate all connected to a constant potential terminal, thereby functioning as a second protection element for protecting the protected element from electrostatic destruction.

10. A circuit design method for a semiconductor device using the cell library of claim 9, comprising the steps of: selecting and arranging the plurality of types of standard cells included in the cell library in an arbitrary combination; laying power lines and signal lines so as to connect the plurality of types of standard cells arbitrarily combined with other circuit blocks; A circuit design method for a semiconductor device comprising: