Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device is provided with a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein: the silicon carbide substrate has a drift region having a first conductivity type; the silicon carbide substrate further has an electric field relaxation region provided between the first main surface and the second main surface and having a second conductivity type different from the first conductivity type; the drift region has a first region located between the electric field relaxation region and the first main surface, a second region that is adjacent to the first region within a plane parallel to the first main surface, a third region that is located between the second region and the second main surface, is connected to the second region, and is adjacent to the electric field relaxation region within a plane parallel to the first main surface, and a fourth region that is located between the electric field relaxation region, the third region, and the second main surface, and is connected to the third region; a first maximum value of the effective concentration of the first conductivity-type impurity in the first region is higher than a second maximum value of the effective concentration of the first conductivity-type impurity in the second region; a third maximum value of the effective concentration of the first conductivity-type impurity in the third region is equal to or less than the second maximum value; and a fourth maximum value of the effective concentration of the first conductivity-type impurity in the fourth region is equal to or less than the third maximum value.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2022-085313 filed on May 25, 2022, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] A silicon carbide semiconductor device is disclosed in which a current diffusion region is provided in contact with the lower surface of a gate trench, and an electric field relaxation region in contact with the lower surface of the current diffusion region is provided wider than the current diffusion region.

[0004] International Publication No. 2014 / 115253 Japanese Patent Application Laid-Open No. 2017-50516

[0005] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be spaced from the drift region and having the first conductivity type, the first main surface having a gate trench defined by a side surface extending through the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the silicon carbide substrate further having an electric field relaxation region having the second conductivity type provided between the gate trench and the second main surface, the drift region being in contact with the electric field relaxation region and the first main surface having a gate trench formed therein, a first region located between the first major surface and the second major surface, a second region adjacent to the first region in a plane parallel to the first major surface, a third region located between the second region and the second major surface, connected to the second region, and adjacent to the electric field relaxation region in a plane parallel to the first major surface, and a fourth region located between the electric field relaxation region, the third region, and the second major surface and connected to the third region, wherein a first maximum value of the effective concentration of the first conductivity type impurity in the first region is higher than a second maximum value of the effective concentration of the first conductivity type impurity in the second region, a third maximum value of the effective concentration of the first conductivity type impurity in the third region is equal to or less than the second maximum value, and a fourth maximum value of the effective concentration of the first conductivity type impurity in the fourth region is equal to or less than the third maximum value.

[0006] FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a diagram showing an example of the distribution of effective impurity concentrations. FIG. 3 is a cross-sectional view (part 1) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view (part 2) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (part 3) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view (part 4) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view (part 5) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view (part 6) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view (part 7) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view (part 8) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view (part 9) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view showing a silicon carbide semiconductor device according to a second embodiment. Fig. 13 is a cross-sectional view showing a method for manufacturing a silicon carbide semiconductor device according to the second embodiment. Fig. 14 is a cross-sectional view showing a silicon carbide semiconductor device according to a third embodiment. Fig. 15 is a cross-sectional view (part 1) showing a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig. 16 is a cross-sectional view (part 2) showing a method for manufacturing a silicon carbide semiconductor device according to the third embodiment.

[0007] [Problem to be Solved by the Present Disclosure] Conventional silicon carbide semiconductor devices are unable to simultaneously reduce on-resistance and improve breakdown voltage.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can achieve both reduced on-resistance and improved breakdown voltage.

[0009] [Effects of the Present Disclosure] According to the present disclosure, it is possible to achieve both a reduction in on-resistance and an improvement in breakdown voltage.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are denoted by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually expressed by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of a silicon carbide semiconductor device or the like. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; and a source region provided on the body region to be separated from the drift region and having the first conductivity type, the first main surface including a gate trench defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface continuous with the side surface; the silicon carbide substrate further including an electric field relaxation region provided between the gate trench and the second main surface and having the second conductivity type, the drift region having a first conductivity type and a second conductivity type different from the first conductivity type. a first region located between the electric field relaxation region and the first main surface, a second region adjacent to the first region in a plane parallel to the first main surface, a third region located between the second region and the second main surface, connected to the second region, and adjacent to the electric field relaxation region in a plane parallel to the first main surface, and a fourth region located between the electric field relaxation region, the third region, and the second main surface and connected to the third region, wherein a first maximum value of the effective concentration of the impurity of the first conductivity type in the first region is higher than a second maximum value of the effective concentration of the impurity of the first conductivity type in the second region, a third maximum value of the effective concentration of the impurity of the first conductivity type in the third region is equal to or less than the second maximum value, and a fourth maximum value of the effective concentration of the impurity of the first conductivity type in the fourth region is equal to or less than the third maximum value.

[0013] The first maximum value of the effective concentration of the first conductivity type impurity in the first region is higher than the second maximum value of the effective concentration of the first conductivity type impurity in the second region. Therefore, while reducing the on-resistance, excessive electric field concentration below the body region is suppressed, thereby achieving a high breakdown voltage. Furthermore, since the third maximum value of the effective concentration of the first conductivity type impurity in the third region is equal to or less than the second maximum value, and the fourth maximum value of the effective concentration of the first conductivity type impurity in the fourth region is equal to or less than the third maximum value, an increase in electrical resistance in the second and third regions can be suppressed. In this way, both a reduction in on-resistance and an improvement in breakdown voltage can be achieved.

[0014] [2] In [1], the third maximum value may be higher than the fourth maximum value and lower than the second maximum value. In this case, an excessive increase in electrical resistance in the second region and the third region can be easily suppressed.

[0015] [3] In [1] or [2], the electric field buffer region may have a first surface in contact with the first region and a second surface opposite to the first surface, and the effective concentration of the second conductivity type impurity in the electric field buffer region may gradually decrease from a first imaginary plane that is 0.3 μm away from the first surface toward the second surface, toward the second surface. In this case, electric field concentration in the gate insulating film at the bottom of the gate trench is easily alleviated.

[0016] [4] In any one of [1] to [3], the first maximum value may be 50% or more of a fifth maximum value of the effective concentration of the second conductivity type impurity in the electric field buffer region. In this case, the on-resistance is easily reduced.

[0017] [5] In any one of [1] to [4], the second maximum value may be 20% or more of a fifth maximum value of the effective concentration of the second conductivity type impurity in the electric field buffer region. In this case, during avalanche breakdown, the electric field in the body region above the second region is likely to be higher than the electric field in the electric field buffer region. The locations where electric field concentration occurs are dispersed, resulting in a higher breakdown voltage.

[0018] [6] In any one of [1] to [5], the electric field buffer region may have a thickness of 1 μm or more, the electric field buffer region having a first surface in contact with the first region, the third region having a third surface in contact with the second region and flush with the first surface, and a fifth region between the third surface and a second imaginary plane 1 μm away from the third surface toward the second major surface, wherein the effective concentration of the first conductivity type impurity in the fifth region at a position a first distance away from the third surface toward the second major surface may be 10% or more of the effective concentration of the second conductivity type impurity in the electric field buffer region at a position a first distance away from the first surface toward the second major surface. In this case, depletion in the electric field buffer region is likely to be promoted, and electric field concentration is likely to occur in the body region above the second region. This makes it easier to obtain a higher breakdown voltage.

[0019] [7] In any one of [1] to [6], the bottom surface of the gate trench may be formed by the first region. In this case, on-resistance is easily reduced.

[0020] [8] In any one of [1] to [7], the width of the first region may be wider than the width of the electric field buffer region, which makes it easier to reduce on-resistance.

[0021] [9] In any one of [1] to [8], the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0022] First Embodiment A first embodiment will be described. The first embodiment relates to a so-called vertical MOS field effect transistor (FET) using silicon carbide, and this MOS FET is an example of a silicon carbide semiconductor device. Fig. 1 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment.

[0023] As shown in FIG. 1 , the silicon carbide semiconductor device 100 according to the first embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

[0024] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0025] The first main surface 1 is a {0001} plane or a {0001} plane tilted at an off angle of 8 degrees or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a (000-1) plane tilted at an off angle of 8 degrees or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 degree or more, or 2 degrees or more. The off angle may be 6 degrees or less, or 4 degrees or less.

[0026] The silicon carbide epitaxial layer 40 mainly includes a drift region 11 , a body region 12 , a source region 13 , a contact region 18 , and an electric field reduction region 16 .

[0027] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. The drift region 11 has a first region 11A, a second region 11B, a third region 11C, and a fourth region 11D.

[0028] The fourth region 11D is provided on the silicon carbide single crystal substrate 50. The lower surface of the fourth region 11D and the upper surface of the silicon carbide single crystal substrate 50 are in contact with each other. The effective concentration of n-type impurities in the fourth region 11D is, for example, 1.0×10 １５ cm －３ Above 5.0 x 10 １６ cm －３ The following is the result.

[0029] The electric field relaxation region 16 contains p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). The electric field relaxation region 16 is provided on a part of the fourth region 11D. The lower surface of the electric field relaxation region 16 and the upper surface of the fourth region 11D are in contact with each other. The effective concentration of the p-type impurity in the electric field relaxation region 16 is, for example, 1.0×10 １６ cm －３ Above 5.0 x 10 １８ cm －３The lower surface of electric field relaxation region 16 may be separated from the upper surface of fourth region 11D, with part of third region 11C between them. Furthermore, the lower surfaces of electric field relaxation region 16 and third region 11C may not be flush with each other, and the lower surface of electric field relaxation region 16 may be closer to second main surface 2 than the lower surface of third region 11C. In other words, electric field relaxation region 16 may be formed deeper than third region 11C.

[0030] The third region 11C is provided on a part of the fourth region 11D. The lower surface of the third region 11C and the upper surface of the fourth region 11D are in contact with each other. The third region 11C is adjacent to the electric field relaxation region 16. The side surface of the third region 11C and the side surface of the electric field relaxation region 16 are in contact with each other. The effective concentration of n-type impurities in the third region 11C is, for example, 5.0×10 １５ cm －３ Above 2.0 x 10 １８ cm －３ The following is the result.

[0031] The first region 11A is provided on the electric field relaxation region 16. The lower surface of the first region 11A and the upper surface of the electric field relaxation region 16 are in contact with each other. The effective concentration of n-type impurities in the first region 11A is, for example, 1.0×10 １６ cm －３ Above 2.0 x 10 １８ cm －３ The following is the result.

[0032] The second region 11B is provided on the third region 11C. The lower surface of the second region 11B and the upper surface of the third region 11C are in contact with each other. The second region 11B is adjacent to the first region 11A. The side surface of the second region 11B and the side surface of the first region 11A are in contact with each other. The effective concentration of n-type impurities in the second region 11B is, for example, 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ The first region 11A and the second region 11B are sometimes called current spreading regions.

[0033] For example, the interface between third region 11C and second region 11B is flush with the interface between electric field relaxation region 16 and first region 11A. The interface between third region 11C and second region 11B may be closer to first main surface 1 or second main surface 2 than the interface between electric field relaxation region 16 and first region 11A. The interface between first region 11A and second region 11B may be flush with the interface between electric field relaxation region 16 and third region 11C, or may be located above third region 11C. In other words, the width of first region 11A may be equal to or wider than the width of electric field relaxation region 16.

[0034] Thus, first region 11A is located between electric field relaxation region 16 and first main surface 1. Second region 11B is adjacent to first region 11A in a plane parallel to first main surface 1. Third region 11C is located between second region 11B and second main surface 2, is connected to second region 11B, and is adjacent to electric field relaxation region 16 in a plane parallel to first main surface 1. Fourth region 11D is located between electric field relaxation region 16 and third region 11C and second main surface 2, and is connected to third region 11C.

[0035] The body region 12 contains p-type impurities such as aluminum and has p-type conductivity. The body region 12 is provided on the drift region 11. The body region 12 is provided on the first region 11A and the second region 11B. The effective concentration of the p-type impurities in the body region 12 is, for example, 1.0×10 １７ cm －３ Above 5.0 x 10 １８ cm －３ The following is the result.

[0036] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurity in the source region 13 is, for example, 5.0×10 １８ cm －３ Above 2.0 x 10 ２０ cm －３ The following is the result.

[0037] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact region 18 constitutes the first main surface 1. The effective concentration of the p-type impurity in the contact region 18 is, for example, 1.0×10 １８ cm －３ Above 5.0 x 10 ２０ cm －３ The electric field relaxation region 16 is electrically connected to the contact region 18. The contact region 18 may be formed at a position that appears in a cross section different from the cross section shown in FIG.

[0038] A gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided in the first major surface 1. The gate trench 5 extends, for example, along the Y axis. The side surface 3 penetrates the source region 13, the body region 12, and a portion of the first region 11A, and reaches the first region 11A. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the first region 11A. For example, the bottom surface 4 is parallel to the first major surface 1 and the second major surface 2. An angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0039] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the first region 11A at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the first region 11A at the side surface 3. The gate insulating film 81 may also contact the source region 13 at the first main surface 1.

[0040] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

[0041] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0042] A barrier metal film 84 is provided to cover the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0043] A contact hole 90 is formed in the interlayer insulating film 83 and the gate insulating film 81. Through the contact hole 90, the source region 13 is exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0044] The source electrode 60 is in contact with the first major surface 1. The source electrode 60 includes a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first major surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum. A potential is applied from the source electrode 60 to the body region 12 and the electric field relaxation region 16 via the contact region 18.

[0045] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 forms an ohmic junction with the silicon carbide single crystal substrate 50.

[0046] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and fourth region 11D. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in fourth region 11D.

[0047] The effective concentration of p-type impurities in a p-type region is a value obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities in that region. The effective concentration of n-type impurities in an n-type region is a value obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities in that region. The effective concentrations of p-type impurities and n-type impurities can be measured, for example, by a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. The position of the boundary surface between the p-type region and the n-type region (i.e., the pn junction interface) can be identified, for example, by the SCM method or the SIMS method.

[0048] Next, the relationship between the effective concentrations of the regions in the first embodiment will be described. Fig. 2 is a diagram showing an example of the distribution of the effective impurity concentration. Fig. 2 shows the distribution of the absolute values ​​of the effective impurity concentration along the two-dot chain line L in Fig. 1. The horizontal axis of Fig. 2 represents the depth relative to the first main surface 1, and the vertical axis represents the absolute value of the effective impurity concentration.

[0049] In this embodiment, the first maximum value of the effective concentration of n-type impurities in the first region 11A is higher than the second maximum value of the effective concentration of n-type impurities in the second region 11B. The third maximum value of the effective concentration of n-type impurities in the third region 11C is equal to or less than the second maximum value. The fourth maximum value of the effective concentration of n-type impurities in the fourth region 11D is equal to or less than the third maximum value.

[0050] 2 , the maximum value of the effective concentration of n-type impurities in the source region 13 may be higher than the maximum value of the effective concentration of p-type impurities in the body region 12. The maximum value of the effective concentration of p-type impurities in the body region 12 may be higher than a first maximum value of the effective concentration of n-type impurities in the first region 11A. The first maximum value of the effective concentration of n-type impurities in the first region 11A may be higher than a fifth maximum value of the effective concentration of p-type impurities in the electric field buffer region 16.

[0051] Next, a method for manufacturing silicon carbide semiconductor device 100 according to the first embodiment will be described. Figures 3 to 11 are cross-sectional views illustrating the method for manufacturing silicon carbide semiconductor device 100 according to the first embodiment.

[0052] First, as shown in FIG. 3 , a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 includes a fourth region 11D and an n-type region 111C where a third region 11C and the like will be formed later. For example, the silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of an n-type impurity such as nitrogen. In this manner, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained.

[0053] 4, a resist mask 30 is formed on silicon carbide epitaxial layer 40. Resist mask 30 has an opening 31 formed therein that exposes a region of n-type region 111C where electric field relaxation region 16 is to be formed.

[0054] 5, p-type impurity 21 is ion-implanted through opening 31 to form p-type region 116 in n-type region 111C. p-type region 116 is a region that will become electric field buffer region 16, but is formed to a region shallower than electric field buffer region 16. The ion implantation of p-type impurity 21 is performed, for example, by channeling implantation. That is, ion implantation is performed perpendicular to the {0001} plane.

[0055] Next, as shown in FIG. 6 , n-type impurity 22 is ion-implanted through opening 31 to form n-type region 111A in n-type region 111C. n-type region 111A is a region that will become first region 11A, but is formed to a region shallower than first region 11A. For example, n-type region 111A constitutes first main surface 1. Furthermore, n-type region 111A is formed to overlap a portion of p-type region 116. As n-type region 111A is formed, electric field relaxation region 16 is formed from p-type region 116. In the ion-implantation of n-type impurity 22, ions are implanted perpendicular to first main surface 1 along the Z-axis.

[0056] 7 , the resist mask 30 is removed, and p-type impurities 23 are ion-implanted into the entire first main surface 1, thereby forming p-type regions 112 in the n-type regions 111C and 111A. The p-type regions 112 are regions that will become the body regions 12, but are formed to extend to regions shallower than the body regions 12. For example, the p-type regions 112 constitute the first main surface 1. The ion implantation of the p-type impurities 23 is performed perpendicular to the first main surface 1 along the Z axis.

[0057] 8, ions of n-type impurities 24 are implanted into the entire first main surface 1, thereby forming an n-type region 113 in the p-type region 112, a first region 11A in the n-type region 111A, and a second region 11B in the n-type region 111C. As the second region 11B is formed, a third region 11C is formed from the n-type region 111C. The ion implantation of the n-type impurities 24 is performed perpendicular to the first main surface 1 along the Z axis.

[0058] 9 , a p-type impurity is ion-implanted into a portion of the first main surface 1 using a resist mask (not shown), thereby forming a contact region 18 in the n-type region 113. As the contact region 18 is formed, a source region 13 is formed in the n-type region 113. The p-type impurity ion implantation is performed perpendicular to the first main surface 1 along the Z axis.

[0059] 10, a gate trench 5 having a side surface 3 and a bottom surface 4 is formed. The gate trench 5 can be formed by, for example, reactive ion etching (RIE) and thermal etching using a mask.

[0060] 11, a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 are formed. Next, a contact hole 90 is formed in the gate insulating film 81 and the interlayer insulating film 83, and a barrier metal film 84 is formed. Next, a source electrode 60 including a contact electrode 61 and a source wiring 62 is formed. Also, a drain electrode 70 is formed.

[0061] In this manner, silicon carbide semiconductor device 100 according to the first embodiment can be manufactured.

[0062] In silicon carbide semiconductor device 100 according to the first embodiment, the first maximum value of the effective concentration of n-type impurities in first region 11A is higher than the second maximum value of the effective concentration of n-type impurities in second region 11B. This reduces the on-resistance while suppressing excessive electric field concentration below body region 12, thereby achieving a high breakdown voltage. Furthermore, because the second maximum value is smaller than the first maximum value, the capacitance between source electrode 60 and drain electrode 70 can be kept low, thereby reducing switching loss.

[0063] Furthermore, the third maximum value of the effective concentration of the n-type impurity in the third region 11C is equal to or less than the second maximum value, which can suppress an increase in electrical resistance in the second region 11B. Preferably, the third maximum value is higher than the fourth maximum value.

[0064] Furthermore, the fourth maximum value of the effective concentration of n-type impurities in the fourth region 11D is equal to or less than the third maximum value. This makes it possible to suppress an increase in electrical resistance in the third region 11C. For example, even when the electric field buffer regions 16 and the third regions 11C are alternately arranged and multiple cells are arranged, the electrical resistance in the third region 11C between adjacent electric field buffer regions 16 can be suppressed low. Preferably, the third maximum value is lower than the second maximum value.

[0065] 2 , the effective concentration of the p-type impurity in the electric field relaxation region 16 gradually decreases from a first imaginary plane 51, which is 0.3 μm away from the first surface 41 toward the second surface 42, to the second surface 42. In this case, electric field concentration on the gate insulating film 81 at the bottom of the gate trench 5 is easily alleviated.

[0066] The first maximum value is preferably 50% or more of the fifth maximum value of the effective concentration of the p-type impurity in the electric field buffer region 16. In this case, the on-resistance is easily reduced. The first maximum value is more preferably 60% or more, and even more preferably 70% or more of the fifth maximum value. Note that, in order to suppress punch-through in the portion of the body region 12 that functions as a channel, the first maximum value is preferably lower than the maximum value of the effective concentration of the p-type impurity in the body region 12.

[0067] The second maximum value is preferably 20% or more of the fifth maximum value of the effective concentration of p-type impurities in the electric field buffer region 16. In this case, during avalanche breakdown, the electric field in the body region 12 above the second region 11B is likely to be higher than the electric field in the electric field buffer region 16. The locations where electric field concentration occurs are dispersed, resulting in a higher breakdown voltage. The second maximum value is more preferably 30% or more, and even more preferably 40% or more of the fifth maximum value.

[0068] The third region 11C has a third surface 43 flush with the first surface 41. The third surface 43 is in contact with the second region 11B. The third region 11C further includes a fifth region 11E. The fifth region 11E is a region between the third surface 43 and a second imaginary plane 52 1 μm away from the third surface 43 toward the second main surface 2. The electric field buffer region 16 has a thickness of 1 μm or more. The effective concentration of n-type impurities in the fifth region 11E at a position a first distance away from the third surface 43 toward the second main surface 2 is preferably 10% or more, more preferably 20% or more, and even more preferably 30% or more of the effective concentration of p-type impurities in the electric field buffer region 16 at a position a first distance away from the first surface 41 toward the second main surface 2. When this relationship holds, depletion in the electric field buffer region 16 is likely to be promoted. Furthermore, electric field concentration is likely to occur in the body region 12 above the second region 11B. Therefore, a higher breakdown voltage can be obtained. The thickness of the electric field buffer region 16 is preferably 1 μm or more, more preferably 1.5 μm or more, and even more preferably 2 μm or more.

[0069] In this embodiment, the on-resistance is easily reduced by forming the bottom surface 4 of the gate trench 5 with the first region 11A. Furthermore, when the width of the first region 11A is wider than the width of the electric field buffer region 16, the on-resistance is more easily reduced.

[0070] Second Embodiment A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of electric field relaxation region 16. Fig. 12 is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment.

[0071] As shown in FIG. 12 , in the silicon carbide semiconductor device 200 according to the second embodiment, the electric field relaxation region 16 has a sixth region 16X and a seventh region 16Y. The sixth region 16X is provided on a part of the fourth region 11D. The lower surface of the sixth region 16X and the upper surface of the fourth region 11D are in contact with each other. The seventh region 16Y is provided on the sixth region 16X. The lower surface of the seventh region 16Y and the upper surface of the sixth region 16X are in contact with each other. Furthermore, the upper surface of the seventh region 16Y and the lower surface of the first region 11A are in contact with each other. The effective concentration of p-type impurities in the seventh region 16Y is higher than the effective concentration of p-type impurities in the sixth region 16X. The effective concentration of p-type impurities in the sixth region 16X is, for example, 1.0×10 １６ cm －３ Above 4.0 x 10 １８ cm －３ The effective concentration of the p-type impurity in the seventh region 16Y is, for example, 1.0×10 １７ cm －３ Above 5.0 x 10 １８ cm －３ The following is the result.

[0072] The other configurations are the same as those of the first embodiment.

[0073] Next, a method for manufacturing silicon carbide semiconductor device 200 according to the second embodiment will be described. Figure 13 is a cross-sectional view illustrating the method for manufacturing silicon carbide semiconductor device 200 according to the second embodiment.

[0074] First, following the first embodiment, processing up to ion implantation of n-type impurities 22 is performed (see FIG. 6 ). In this embodiment, the electric field buffer region 16 is not formed when the n-type region 111A is formed. Next, as shown in FIG. 13 , p-type impurities 25 are ion implanted through the opening 31 to form a seventh region 16Y in the p-type region 116. As the seventh region 16Y is formed, a sixth region 16X is formed from the p-type region 116. As a result, the electric field buffer region 16 including the sixth region 16X and the seventh region 16Y is formed. In the ion implantation of the p-type impurities 25, ions are implanted perpendicular to the first main surface 1 along the Z axis.

[0075] Thereafter, similar to the first embodiment, the processes subsequent to the removal of resist mask 30 are carried out. In this manner, silicon carbide semiconductor device 200 in accordance with the second embodiment can be manufactured.

[0076] The second embodiment also provides the same effects as the first embodiment.

[0077] Third Embodiment A third embodiment will be described. The third embodiment differs from the second embodiment mainly in the configuration of a third region 11C. Fig. 14 is a cross-sectional view showing a silicon carbide semiconductor device in accordance with the third embodiment.

[0078] As shown in FIG. 14 , in the silicon carbide semiconductor device 300 according to the third embodiment, the third region 11C has an eighth region 11X and a ninth region 11Y. The eighth region 11X is provided on a part of the fourth region 11D. The lower surface of the eighth region 11X and the upper surface of the fourth region 11D are in contact with each other. The ninth region 11Y is provided on the eighth region 11X. The lower surface of the 9th region 11Y and the upper surface of the eighth region 11X are in contact with each other. Furthermore, the upper surface of the 9th region 11Y and the lower surface of the second region 11B are in contact with each other. The effective concentration of n-type impurities in the ninth region 11Y is higher than the effective concentration of p-type impurities in the eighth region 11X. The effective concentration of n-type impurities in the eighth region 11X is, for example, 5.0×10 １５ cm －３ Above 5.0 x 10 １７ cm －３ The effective concentration of the n-type impurity in the ninth region 11Y is, for example, 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0079] The other configurations are the same as those of the second embodiment.

[0080] The interface between the eighth region 11X and the ninth region 11Y may coincide with the second imaginary plane 52 (see FIG. 1 ), may be closer to the first main surface 1 than the second imaginary plane 52, or may be closer to the second main surface 2 than the second imaginary plane 52. As described above, the second imaginary plane 52 is a plane that is 1 μm away from the third surface 43 that contacts the second region 11B toward the second main surface 2.

[0081] Next, a method for manufacturing the silicon carbide semiconductor device 300 according to the third embodiment will be described. Figures 15 and 16 are cross-sectional views showing the method for manufacturing the silicon carbide semiconductor device according to the third embodiment.

[0082] First, as shown in FIG. 15 , following the second embodiment, processing up to removal of the resist mask 30 is performed. Next, as shown in FIG. 16 , an n-type region 111Y is formed in the n-type region 111C by ion implantation of n-type impurities 26 into the entire first main surface 1. The n-type region 111Y is a region that will become the ninth region 11Y, but is formed to a region shallower than the ninth region 11Y. For example, the n-type region 111Y constitutes the first main surface 1. As the n-type region 111Y is formed, the eighth region 11X is formed from the n-type region 111C. The ion implantation of the n-type impurities 26 is performed, for example, by channeling implantation. That is, the ion implantation is performed perpendicular to the {0001} plane.

[0083] Thereafter, similar to the first embodiment, processes subsequent to the formation of p-type region 112 are performed. Second region 11B is formed by ion implantation of n-type impurities 24 into the entire first main surface 1 (see FIG. 8 ). As second region 11B is formed, n-type regions 111X to ninth region 11Y are formed (see FIG. 14 ). As a result, third region 11C including eighth region 11X and ninth region 11Y is formed. In this manner, silicon carbide semiconductor device 300 according to the third embodiment can be manufactured.

[0084] The third embodiment also provides the same effects as the first and second embodiments.

[0085] As a mask used for ion implantation, a hard mask such as polysilicon or silicon oxide may be used instead of a resist mask.

[0086] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0087] REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 11A First region 11B Second region 11C Third region 11D Fourth region 11E Fifth region 11X Eighth region 11Y Ninth region 12 Body region 13 Source region 16 Electric field relaxation region 16X Sixth region 16Y Seventh region 21, 23, 25 P-type impurity 22, 24, 26 N-type impurity 30 Resist mask 31 Opening 40 Silicon carbide epitaxial layer 41 First surface 42 Second surface 43 Third surface 50 Silicon carbide single crystal substrate 51 First imaginary surface 52 Second imaginary surface 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 90 Contact hole 100, 200, 300 Silicon carbide semiconductor device 111A, 111C, 111X, 111Y N-type region 112, 116 P-type region 113 N-type region

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; having a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface; the silicon carbide substrate further includes an electric field relaxation region having the second conductivity type, the electric field relaxation region being provided between the gate trench and the second main surface; The drift region is a first region located between the electric field buffer region and the first main surface; A second region adjacent to the first region in a plane parallel to the first main surface; a third region located between the second region and the second main surface, connected to the second region, and adjacent to the electric field relaxation region in a plane parallel to the first main surface; a fourth region located between the electric field buffer region and the second main surface and connected to the third region; having a first maximum value of an effective concentration of the first conductivity type impurity in the first region is higher than a second maximum value of an effective concentration of the first conductivity type impurity in the second region; a third maximum value of the effective concentration of the first conductivity type impurity in the third region is equal to or less than the second maximum value; a fourth maximum value of the effective concentration of the impurity of the first conductivity type in the fourth region is not greater than the third maximum value.

2. The silicon carbide semiconductor device according to claim 1 , wherein said third maximum value is higher than said fourth maximum value and lower than said second maximum value.

3. The electric field relaxation region is a first surface in contact with the first region; a second surface opposite the first surface; having 3. The silicon carbide semiconductor device according to claim 1, wherein an effective concentration of the second conductivity type impurity in the electric field relaxation region gradually decreases from a first imaginary plane that is 0.3 μm away from the first surface toward the second surface, toward the second surface.

4. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said first maximum value is equal to or greater than 50% of a fifth maximum value of an effective concentration of said second conductivity type impurity in said electric field relaxation region.

5. 3 . The silicon carbide semiconductor device according to claim 1 , wherein said second maximum value is equal to or greater than 20% of a fifth maximum value of an effective concentration of said impurity of the second conductivity type in said electric field relaxation region.

6. The thickness of the electric field relaxation region is 1 μm or more, the electric field buffer region has a first surface in contact with the first region, The third region is a third surface in contact with the second region and flush with the first surface; a fifth region between the third surface and a second imaginary surface that is 1 μm away from the third surface toward the second main surface; having 3. The silicon carbide semiconductor device according to claim 1, wherein an effective concentration of the first conductivity type impurity in the fifth region at a position a first distance away from the third surface toward the second main surface is 10% or more of an effective concentration of the second conductivity type impurity in the electric field relaxation region at a position the first distance away from the first surface toward the second main surface.

7. The silicon carbide semiconductor device according to claim 1 , wherein said bottom surface of said gate trench is formed by said first region.

8. The silicon carbide semiconductor device according to claim 1 , wherein a width of said first region is wider than a width of said electric field relaxation region.

9. 3. The silicon carbide semiconductor device according to claim 1, wherein said side surface of said gate trench includes a {0-33-8} plane.