Electronic component

Abstract

An electronic component (101) comprises: a substrate (1); an insulator layer (2); an inductor formed in the insulator layer; planar conductors (3, 4) extending along the substrate (1); and planar conductor connection conductors (7A, 7B, 7C, 8) that conduct to the planar conductors (3, 4). The inductor comprises: surface direction conductors (5A, 5B); and a plurality of inductor via conductors (6) that connect the surface direction conductors (5A, 5B) to each other. The direction of current flowing to inductor via conductors (6) adjacent to the planar conductor connection conductors (7A, 7B, 7C, 8), among the plurality of inductor via conductors (6) that constitute a portion of a helical coil having a winding axis (WA) along the surface of the substrate (1), is mutually opposite to the direction of current flowing to the planar conductor connection conductors (7A, 7B, 7C, 8).

Description

Electronic Components

[0001] The present invention relates to an electronic component including a helical coil inductor and a planar conductor.

[0002] A coil component in which a helical coil is formed on a substrate is used as an inductor.

[0003] Patent Document 1 discloses a coil component. The coil component of Patent Document 1 is fabricated by cutting a core substrate, on the front and back surfaces of which are formed a plurality of strip-shaped conductors and insulating layers covering the strip-shaped conductors, into chips. Specifically, this coil component has a plurality of side conductors made of strip-shaped conductors and insulating layers covering the side conductors on both the left and right sides of a rectangular parallelepiped insulator made of the core substrate. Furthermore, a rectangular helical coil is formed by having bridge conductors connecting the side conductors on the top and bottom surfaces of the insulator.

[0004] Patent Document 2 discloses a wiring board. The wiring board of Patent Document 2 includes a first insulating layer formed without a core material, a first conductor layer and a second conductor layer disposed opposite each other via the first insulating layer, and a plurality of via conductors penetrating the first insulating layer to connect the first conductor layer and the second conductor layer. The first conductor layer and the second conductor layer are adjacent to each other via the first insulating layer. A magnetic body having a predetermined shape is embedded in the first insulating layer so as not to contact the first conductor layer, the second conductor layer, or the plurality of via conductors. A coil is formed around the magnetic body by wiring patterns and the plurality of via conductors included in each of the first conductor layer and the second conductor layer. The coil extends in a direction intersecting the stacking direction of the wiring board.

[0005] JP 2004-103756 A JP 2021-197454 A

[0006] When constructing an inductor on a conductive substrate such as a doped silicon substrate, it is effective to arrange the magnetic flux opening direction of the helical coil parallel to the substrate to prevent degradation of the Q value. In other words, the magnetic flux generated by the coil does not penetrate the substrate, reducing losses due to eddy currents. However, when this inductor is made into a component and placed on a circuit board together with elements such as conductors and other electronic components, the following issues arise when combining the inductor with a capacitor to form an LC composite component such as an LC filter or impedance matching circuit.

[0007] When making a helical coil like the coil components described in Patent Documents 1 and 2, the helical coil is formed along a plane parallel to the surface of the substrate. However, if another electronic component is formed close to the opening of the helical coil, eddy currents are generated in the conductors of the electronic component due to the magnetic field of the helical coil, degrading the electrical characteristics of the composite component.

[0008] Furthermore, when a capacitor is combined with the above-mentioned inductor to form an LC composite component such as an LC filter or an impedance matching circuit, the following problems arise.

[0009] When making a helical coil, as in the coil components described in Patent Documents 1 and 2, either the upper or lower surface of the surfaces parallel to the surface of the substrate becomes the starting or ending point. However, if internal wiring that is conductive to terminals or other elements is formed near the opening of the helical coil, eddy currents due to the magnetic field will be generated in this internal wiring, degrading the electrical characteristics of the composite component.

[0010] Therefore, an object of the present invention is to provide an electronic component having a helical coil in which the opening direction of the magnetic flux of the helical coil is arranged parallel to the substrate, which allows for miniaturization of electronic equipment in which the electronic component having the helical coil and other elements are mounted, even when mounted together with other conductors, electronic components, etc.

[0011] Another object of the present invention is to provide a small electronic component that includes an inductor having a predetermined inductance as well as internal wiring.

[0012] An electronic component as an example of the present disclosure comprises: a substrate; an insulator layer formed along a surface of the substrate; an inductor formed in the insulator layer; one or more planar conductors formed on the substrate or the insulator layer and extending along the substrate; and one or more planar conductor connecting conductors that are conductive to the planar conductors; wherein the inductor includes a plurality of planar conductors that extend in a plurality of layers along the surface of the substrate, respectively, and a plurality of inductor via conductors that connect the planar conductors that extend in different layers among the plurality of layers, and is an inductor formed by a helical coil having a winding axis that is along the surface of the substrate; and wherein the direction of current flowing in an inductor via conductor adjacent to the planar conductor connecting conductor among the plurality of inductor via conductors is opposite to the direction of current flowing in the planar conductor connecting conductor.

[0013] According to the present invention, in an electronic component having a helical coil in which the opening direction of the magnetic flux of the helical coil is arranged parallel to the substrate, when the electronic component is mounted together with other elements such as other conductors or electronic components, it is possible to obtain an electronic component that allows for miniaturization of an electronic device in which the electronic component having the helical coil and other elements are mounted, and it is also possible to obtain a small electronic component that has internal wiring together with an inductor having a predetermined inductance.

[0014] FIG. 1 is a diagram showing the structure of an electronic component 101 according to a first embodiment. FIG. 2 is an equivalent circuit diagram of the electronic component 101. FIG. 3A is a plan view showing the positional relationship between the electronic component 101 and another adjacent member 201. FIG. 3B is a plan view showing the positional relationship between an electronic component 301 as a comparative example and another adjacent member 201 such as another electronic component. FIG. 4A is a plan view of an electronic component 111. FIG. 4B is a plan view of an electronic component 311 as a comparative example, which includes another member 21 together with a helical coil within the electronic component. FIG. 5 is a diagram showing the structure of an electronic component 102 according to a second embodiment. FIG. 6 is a cross-sectional view showing a state in which a sheet conductor 3 is formed. FIG. 7 is a cross-sectional view showing a state in which a dielectric layer 11 is formed. FIG. 8 is a cross-sectional view showing a state in which a sheet conductor 4 is formed. FIG. 9 is a cross-sectional view showing a state in which an insulator layer 2 is formed. FIG. 10 is a cross-sectional view showing a state in which a planar conductor 5B and a sheet-conductor-connecting conductor 7B are formed. FIG. 11 is a cross-sectional view showing the state in which the inductor via conductor 6 and the planar conductor connecting conductor 7C have been formed. FIG. 12 is a cross-sectional view showing the state in which the planar conductor 5A and terminal electrodes 9A and 9B have been formed. FIG. 13 is a cross-sectional view showing the state in which the terminal electrodes 10A and 10B have been formed. FIG. 14 is a diagram showing the structure of an electronic component 103 according to a third embodiment. FIG. 15 is a cross-sectional view showing the state in which the board conduction electrode 12, the dielectric layer 11, the planar conductor 4, etc. have been formed. FIG. 16 is a cross-sectional view showing the state in which the planar conductor 5B and the planar conductor connecting conductor 7B have been formed. FIG. 17 is a cross-sectional view showing the state in which the inductor via conductor 6 and the planar conductor connecting conductor 7C have been formed. FIG. 18 is a cross-sectional view showing the state in which the planar conductor 5A and the terminal electrodes 9A and 9B have been formed. FIG. 19 is a cross-sectional view showing the state in which the terminal electrodes 10A and 10B have been formed. FIG. 20 is a diagram showing the structure of an electronic component 104 according to a fourth embodiment.

[0015] Hereinafter, several specific examples will be given with reference to the drawings to illustrate multiple embodiments for carrying out the present invention. The same reference numerals are used for the same parts in each drawing. For ease of explanation and understanding of the main points, the embodiments are shown divided into multiple embodiments for convenience of explanation, but partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0016] First Embodiment Fig. 1 is a diagram showing the structure of an electronic component 101 according to a first embodiment. The <Plan View> in Fig. 1 is a plan view of the electronic component 101. The <X1 Cross Section> in Fig. 1 is a cross section taken along the X1-X1 line in the plan view of the electronic component 101, and the <X2 Cross Section> in Fig. 1 is a cross section taken along the X2-X2 line in the plan view of the electronic component 101. Furthermore, the <Y1 Cross Section> in Fig. 1 is a cross section taken along the Y1-Y1 line in the plan view of the electronic component 101, and the <Y2 Cross Section> in Fig. 1 is a cross section taken along the Y2-Y2 line in the plan view of the electronic component 101.

[0017] The electronic component 101 includes a substrate 1, an insulator layer 2 formed along the surface of the substrate 1, and an inductor formed in the insulator layer 2. The electronic component 101 also includes planar conductor connecting conductors 7A, 7B, and 7C formed on the substrate 1 and electrically connected to a planar conductor 3 extending along the substrate 1, and a planar conductor connecting conductor 8 electrically connected to a planar conductor 4 extending along the substrate 1.

[0018] The inductor includes a plurality of planar conductors 5A, 5B extending in a plurality of layers (two layers in this example) along the surface of the substrate 1, and a plurality of inductor via conductors 6 connecting the planar conductors 5A, 5B extending in different layers among the plurality of layers. The inductor is an inductor formed by a helical coil having a winding axis WA along the surface of the substrate 1.

[0019] The planar conductor connecting conductors 7A, 7B, 7C, and 8 are located at the ends of the helical coil in the winding axis direction (coil openings of the helical coil).

[0020] The sheet conductors 3 and 4 are capacitor electrodes. That is, the sheet conductors 3 and 4 and the dielectric layer 11 sandwiched between these sheet conductors 3 and 4 form a capacitor.

[0021] In this way, the sheet conductors 3 and 4 are formed closer to the substrate 1 than the multiple planar conductors 5A and 5B. With this structure, the inductor, which is a helical coil composed of the multiple planar conductors 5A and 5B and the multiple inductor via conductors 6, is located closer to the terminal electrodes 9A and 9B. This minimizes the path from the circuit to the inductor, keeping the inductor's Q value high. Furthermore, the capacitor electrodes can be arranged overlapping the coil formation area, thereby saving space.

[0022] Of the multiple inductor via conductors 6, the direction of current flowing through the inductor via conductors 6 adjacent to the planar conductor connection conductors 7A, 7B, and 7C is opposite to that of current flowing through the planar conductor connection conductors 7A, 7B, and 7C. Also, the direction of current flowing through the inductor via conductor 6 adjacent to the planar conductor connection conductor 8 is opposite to that of current flowing through the planar conductor connection conductor 8. This will be explained later with reference to Figures 3(A) and 3(B), etc.

[0023] The substrate 1 is, for example, a silicon substrate, and a thin-film planar conductor 3 made of polysilicon, Al, or the like is formed on the surface of the substrate 1. A dielectric layer 11 made of SiO2, SiN, or the like is formed in a predetermined region on the upper surface of the planar conductor 3. A thin-film planar conductor 4 made of polysilicon, Al, or the like is formed on the surface of this dielectric layer 11.

[0024] A planar conductor 5A and terminal electrodes 9A and 9B are formed on the surface of the insulator layer 2. The planar conductor 3 is electrically connected to the terminal electrode 9B through planar conductor connecting conductors 7A, 7B, and 7C. The planar conductor 4 is electrically connected to the planar conductor 5B through a planar conductor connecting conductor 8.

[0025] As described above, the planar conductor connecting conductor is composed of three parts: planar conductor connecting conductors 7A, 7B, and 7C. One of these parts, planar conductor connecting conductor 7B, is formed on the same layer as planar conductor 5B. Planar conductor connecting conductor 7B is formed during the process of forming planar conductor 5B. Therefore, there is no need for a process of forming a special conductor pattern to reverse the direction of current flowing through inductor via conductors 6 adjacent to planar conductors 5A and 5B and the direction of current flowing through planar conductor connecting conductor 7C.

[0026] As shown in Fig. 2, this electronic component 101 functions as an LC composite component consisting of a series circuit of an inductor and a capacitor. In this electronic component 101, the planar conductors 5A and 5B and the inductor via conductor 6 form a helical coil inductor L1. The planar conductors 3 and 4 and the dielectric layer 11 sandwiched between these planar conductors 3 and 4 form a capacitor C. The planar conductor connecting conductors 7A, 7B, 7C, 8, etc. form an inductor L2.

[0027] When the sheet conductors 3 and 4 shown in FIG. 1 are resistors, the electronic component 101 functions as an LCR composite component made up of a series circuit of an inductor, a capacitor, and a resistive element.

[0028] Such an electronic component in which an inductor and a capacitor are connected in series can be used as a frequency filter or an impedance matching circuit.

[0029] First, a comparative example of the electronic component 101 according to the present embodiment will be described. Fig. 3B is a plan view showing the positional relationship between the comparative electronic component 301 and an adjacent member 201 such as another electronic component. In this comparative electronic component 301, when a current flows in from the terminal electrode 9A, the magnetic flux around the upper inductor via conductor 6 has the same direction (right-handed) as shown in Fig. 3B, and the magnetic flux around the lower inductor via conductor 6 has the same direction (left-handed). Therefore, the overall magnetic flux φ (thick dashed line) generated inside and outside the helical coil is greatly expanded.

[0030] 3A is a plan view showing the positional relationship between the electronic component 101 according to this embodiment and another adjacent member 201. The dashed concentric circles in the figure indicate magnetic flux generated in the inductor via conductor 6 and the planar conductor connecting conductor 7C, etc. The overall magnetic flux φ generated inside and outside the helical coil is shown by a thick line.

[0031] In the electronic component 101, among the multiple inductor via conductors 6, the direction of current flowing through the inductor via conductor adjacent to the planar conductor connecting conductors 7A, 7B, and 7C (the rightmost inductor via conductor 6 among the upper three inductor via conductors 6 in the orientation shown in FIG. 3A) is opposite to the direction of current flowing through the planar conductor connecting conductors 7A, 7B, and 7C. This suppresses the spread of magnetic flux φ compared to the example shown in FIG. 3B. Therefore, even if a member 201 is adjacent to the electronic component 101, there is little mutual influence between them.

[0032] In the electronic component 101 of this embodiment, the direction of the current flowing through the inductor via conductor adjacent to the planar conductor connection conductor 8 (the rightmost inductor via conductor 6 of the two lower inductor via conductors 6 in the orientation shown in FIG. 3A ) is opposite to the direction of the current flowing through the planar conductor connection conductor 8. This effectively suppresses the spread of the magnetic flux φ.

[0033] In the electronic component 301 as a comparative example, the magnetic flux φ spreads widely, but in the electronic component 101 of this embodiment, the spread of the magnetic flux φ is suppressed, so the distance d1 between the electronic component 101 and the member 201 can be made smaller than the distance d2 shown in Figure 3 (B).

[0034] 4B is a plan view of an electronic component 311 as a comparative example, which includes the helical coil and another member 21. The structure of the helical coil in this electronic component 311 is as shown in FIG.

[0035] 4A is a plan view of electronic component 111 according to this embodiment. This electronic component 311 includes the helical coil and the other member 21. The structure of the helical coil in electronic component 111 is as shown in FIG.

[0036] In the electronic component 311 as a comparative example, the magnetic flux φ spreads widely, but in the electronic component 111 of this embodiment, the spread of the magnetic flux φ is suppressed, so that the distance d1 between the helical coil and the member 21 can be made smaller than the distance d2 in the comparative example, and a small electronic component 111 can be constructed.

[0037] In the first embodiment, the inductor via conductors 6 are arranged in two rows, and the sheet conductor connecting conductors 7A, 7B, and 7C are positioned next to the end of one of the two rows of inductor via conductors 6, and the sheet conductor connecting conductor 8 is positioned next to the end of the other row. However, the number of inductor via conductors 6 is not limited to two. Furthermore, even if the sheet conductor connecting conductors 8 are not positioned next to the end of all rows, the effect of suppressing the spread of magnetic flux φ can be achieved.

[0038] In the examples shown in Figures 3(A) and 4(A), the spacing between the ends of the inductor via conductors 6 and the planar conductor connecting conductors 7A, 7B, 7C, or 8 is equal to the spacing between the multiple inductor via conductors 6, but this spacing does not necessarily have to be equal. However, if the spacing is too close, the magnetic fields generated by the helical coils will be weakened, reducing the inductance of the inductor generated by the helical coil. Conversely, if the spacing is too large, the effect of suppressing the spread of magnetic flux generated by the helical coil will be reduced. Therefore, it is best for the spacing to be approximately equal.

[0039] In the example shown in FIG. 1, the sheet conductors 3 and 4 are formed on the substrate 1, but the sheet conductors 3 and 4 may also be formed on an intermediate layer of the insulating layer 2.

[0040] The high-frequency magnetic field generated by the helical coil may generate eddy currents in the sheet conductors 3 and 4. However, as shown in Figures 3A, 3B, 4A, and 4B, the spread of the magnetic flux φ is suppressed, so the loss due to the eddy currents (deterioration of the Q value of the inductor) is suppressed.

[0041] Furthermore, in the electronic component shown in the first embodiment, the planar conductor 3 is formed not only in the capacitor formation area but also over almost the entire surface of the substrate 1. Therefore, the electronic component provides electromagnetic shielding for the components and circuits below the substrate 1.

[0042] Second Embodiment In a second embodiment, an electronic component having a terminal electrode configuration different from that of the example shown in the first embodiment will be described.

[0043] Fig. 5 is a diagram showing the structure of an electronic component 102 according to the second embodiment. The <Plan View> in Fig. 5 is a plan view of the electronic component 102. The <X1 Cross Section> in Fig. 5 is a cross section taken along the X1-X1 line in the plan view of the electronic component 102, and the <X2 Cross Section> in Fig. 5 is a cross section taken along the X2-X2 line in the plan view of the electronic component 102.

[0044] The electronic component 102 includes a substrate 1, an insulator layer 2 formed along the surface of the substrate 1, an inductor formed in the insulator layer 2, sheet conductors 3 and 4 formed on the substrate 1 and extending along the substrate 1, sheet conductor connecting conductors 7A, 7B, and 7C that are electrically connected to the sheet conductor 3, and a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4.

[0045] Terminal electrodes 10A and 10B are formed on the surface of the insulator layer 2. The terminal electrodes 10A and 10B are electrically connected to the terminal electrodes 9A and 9B. In the electronic component 101 shown in the first embodiment, as shown in FIG. 1, the planar conductors 5A and 5B are exposed together with the terminal electrodes 9A and 9B, but in the electronic component 102 shown in the data of the second embodiment, only the terminal electrodes 10A and 10B are exposed. The other configurations are the same as those shown in the first embodiment.

[0046] Next, an example of a manufacturing method for the electronic component 102 will be described. Fig. 6 is a cross-sectional view of the state after the planar conductor 3 has been formed. The substrate 1 is a silicon intrinsic semiconductor substrate or a silicon-impurity semiconductor substrate, and in this process, the substrate is formed by semiconductor processes such as evaporating an Al film or Cu film on the surface of the substrate 1 and lifting it off, or depositing the Al film or Cu film by sputtering or CVD, followed by lithography and etching.

[0047] 7 is a cross-sectional view of the state after forming the dielectric layer 11. In this process, the dielectric layer 11, such as an SiO2 film or SiN film, is formed on the surface of the planar conductor 3 by a semiconductor process such as sputtering or CVD, and then lithography is performed and a pattern of the dielectric layer 11 is formed by etching.

[0048] 8 is a cross-sectional view of the formed sheet conductor 4. In this process, similar to the method for forming the sheet conductor 3, the pattern of the sheet conductor 4 is formed by semiconductor processes such as evaporating an Al or Cu film and lifting it off, or depositing an Al or Cu film by sputtering or CVD, and then performing lithography and etching.

[0049] 9 is a cross-sectional view of the insulating layer 2 after it has been formed. In this process, a resin (organic) film or an inorganic film such as an SiO2 film or an SiN film is formed by a method such as spin coating, CVD, or sputtering, and then openings AP are formed in predetermined locations by lithography and etching.

[0050] 10 is a cross-sectional view showing the state in which the planar conductors 5B and the conductors for connecting planar conductors 7B have been formed. In this process, the conductors for connecting planar conductors 7A and 8 are formed in the opening AP shown in FIG. 9, and the planar conductors 5B and the conductors for connecting planar conductors 7B are formed on the surface of the insulator layer 2. For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0051] 11 is a cross-sectional view of the inductor via conductor 6 and the planar conductor connecting conductor 7C after they have been formed. In this process, the pattern of the planar conductor 4 is formed by semiconductor processes such as vapor deposition of an Al or Cu film, lift-off, deposition of the Al or Cu film by sputtering or CVD, lithography, and etching.

[0052] 12 is a cross-sectional view showing the state in which the planar conductors 5A and the terminal electrodes 9A and 9B have been formed. In this process, the planar conductors 5A and the terminal electrodes 9A and 9B are formed on the surface of the insulator layer 2. For example, they can be formed by forming a Cu film, lithography, and plating, or by sputtering Cu, lithography, and etching, or by lithography, vapor deposition, and lift-off of a Cu film.

[0053] Figure 13 is a cross-sectional view of the terminal electrodes 10A, 10B after they have been formed. In this process, the terminal electrodes 10A, 10B are electrodes for mounting, and are formed by plating the surfaces of the terminal electrodes 9A, 9B with Ni or Au. A protective film is then formed, and windows are opened in the areas corresponding to the terminal electrodes 10A, 10B to expose them. The insulator layer 2 may be composed of multiple types of layers. If all of the layers are made of the same material, the boundaries between them may not be visible after completion, as shown in Figure 13.

[0054] In this second embodiment, even if the terminal electrodes 9B, 10B are large, the high-frequency magnetic field generated by the helical coil effectively avoids the terminal electrodes 9B, 10B. This reduces loss due to eddy currents and prevents a decrease in the Q value of the inductor due to the helical coil. This also applies to the following embodiments.

[0055] Third Embodiment In a third embodiment, an electronic component having a sheet conductor configuration different from the examples shown in the first and second embodiments will be illustrated.

[0056] Fig. 14 is a diagram showing the structure of an electronic component 103 according to the third embodiment. The <Plan View> in Fig. 14 is a plan view of the electronic component 103. The <X1 Cross Section> in Fig. 14 is a cross section taken along the X1-X1 line in the plan view of the electronic component 103, and the <X2 Cross Section> in Fig. 14 is a cross section taken along the X2-X2 line in the plan view of the electronic component 103.

[0057] The electronic component 103 comprises a substrate 1, an insulator layer 2 formed along the surface of the substrate 1, an inductor formed in the insulator layer 2, a sheet conductor 4 formed on the substrate 1 and extending along the substrate 1, sheet conductor connecting conductors 7A, 7B, and 7C that are electrically connected to the sheet conductor 4, and a sheet conductor connecting conductor 8 that is electrically connected to the sheet conductor 4.

[0058] As shown in the X2 cross section, a dielectric layer 11 is formed on the surface of the substrate 1. A sheet conductor 4 is formed on the surface of this dielectric layer 11. Furthermore, as shown in the X1 cross section, a substrate conduction electrode 12 is formed at a predetermined position on the surface of the substrate 1. The substrate 1 is a semiconductor substrate with high conductivity, or a semiconductor substrate on which a layer with high conductivity is formed on the surface on which the above-mentioned layers are formed. The other configurations are as shown in the second embodiment.

[0059] Next, a method for manufacturing the electronic component 103 will be illustrated. FIG. 15 is a cross-sectional view showing the state in which the substrate conductive electrodes 12, the dielectric layer 11, the planar conductor 4, and the like have been formed. The substrate 1 is a silicon-doped semiconductor substrate. In this process, as shown in the X1 cross-sectional view, an Al or Cu film is vapor-deposited on the surface of the substrate 1, followed by lift-off, and then another Al or Cu film is deposited by sputtering or CVD, followed by lithography and etching, using a semiconductor process. Also, as shown in the X2 cross-sectional view, a dielectric layer 11 such as a SiO2 film or SiN film is formed on the surface of the substrate 1 by a semiconductor process such as sputtering or CVD, followed by lithography and etching to form a pattern in the dielectric layer 11.

[0060] Fig. 16 is a cross-sectional view of the planar conductor 5B and the planar conductor connecting conductor 7B after formation. Fig. 17 is a cross-sectional view of the inductor via conductor 6 and the planar conductor connecting conductor 7C after formation. Fig. 18 is a cross-sectional view of the planar conductor 5A and the terminal electrodes 9A and 9B after formation. Fig. 19 is a cross-sectional view of the terminal electrodes 10A and 10B after formation.

[0061] The steps shown in FIGS. 16 to 19 are the same as the steps shown in FIGS. 10 to 13 in the second embodiment.

[0062] In this way, the present invention can also be applied to cases where the substrate is used as part of a planar conductor for a capacitor.

[0063] Fourth Embodiment In a fourth embodiment, an electronic component in which a sheet conductor and a semiconductor substrate constitute a semiconductor element will be described as an example.

[0064] Fig. 20 is a diagram showing the structure of an electronic component 104 according to the fourth embodiment. The <Plan View> in Fig. 20 is a plan view of the electronic component 104. The <X1 Cross Section> in Fig. 20 is a cross section taken along the X1-X1 line in the plan view of the electronic component 104, and the <X2 Cross Section> in Fig. 20 is a cross section taken along the X2-X2 line in the plan view of the electronic component 104.

[0065] The substrate 1 is a P-type silicon semiconductor substrate, and an N-well 13 is formed in a predetermined location of the substrate 1, and a P+ region 14 is formed in a predetermined region within the N-well.

[0066] The substrate conductive electrode 12 is formed on the surface of the N well 13 region. The substrate conductive electrode 15 is formed on the surface of the P+ region. With this structure, a diode is formed by the N well 13, the substrate conductive electrode 12 that is electrically connected to the N well 13, the P+ region 14, and the substrate conductive electrode 15 that is electrically connected to the P+ region.

[0067] With the above configuration, the electronic component 104 functions as an electronic component in which a diode is connected in series to an inductor formed by a helical coil, and can be used as, for example, an ESD protection element.

[0068] In the example shown in FIG. 20, a diode is formed on the substrate 1, but a transistor may also be formed in the same manner.

[0069] Finally, the present invention is not limited to the above-described embodiments. Those skilled in the art can make appropriate modifications and variations. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications and variations from the embodiments within the scope of the claims and their equivalents.

[0070] The configuration of the electronic component of the present invention is listed below.

[0071] <1> An electronic component comprising: a substrate; an insulator layer formed along a surface of the substrate; an inductor formed in the insulator layer; a sheet conductor formed on the substrate or the insulator layer and extending along the substrate; and a sheet-conductor connecting conductor conducting to the sheet conductor, wherein the inductor includes a plurality of planar conductors extending in a plurality of layers along the surface of the substrate, and a plurality of inductor via conductors connecting the planar conductors extending in different layers among the plurality of layers, and is an inductor formed by a helical coil having a winding axis along the surface of the substrate, wherein the direction of a current flowing in an inductor via conductor adjacent to the sheet-conductor connecting conductor among the plurality of inductor via conductors is opposite to the direction of a current flowing in the sheet-conductor connecting conductor.

[0072] <2> The electronic component according to <1>, wherein the planar conductor connecting conductor is located at an end of the helical coil in the direction of the winding axis (a coil opening of a helical coil inductor).

[0073] <3> The electronic component according to <1> or <2>, wherein the planar conductor is formed at a position closer to the substrate than the plurality of planar conductors.

[0074] <4> The electronic component according to <3>, wherein the planar conductor connecting conductor is composed of three or more parts, one of which is formed in the same layer as the planar conductor.

[0075] <5> The electronic component according to any one of <1> to <4>, wherein the substrate is a low-resistance semiconductor substrate, and the planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate.

[0076] <6> The electronic component according to any one of <1> to <5>, wherein the sheet conductor is a resistor film.

[0077] <7> The electronic component according to any one of <1> to <6>, wherein the substrate is a semiconductor substrate, and the planar conductor forms a semiconductor element together with the semiconductor substrate.

[0078] <8> The electronic component according to any one of <1> to <7>, wherein the inductor via conductors are arranged in two rows, and the planar conductor connecting conductors are positioned next to ends of the two rows of inductor via conductors.

[0079] <9> The electronic component according to <8>, wherein the end of the inductor via conductor and the planar conductor connecting conductor are arranged at equal intervals.

[0080] AP...opening C...capacitor d...spacing L1...helical coil inductor L2...inductor WA...winding axis 1...substrate 2...insulating layer 3, 4...plane conductor 5A, 5B...plane-direction conductor 6...inductor via conductor 7A, 7B, 7C, 8...conductor for connecting plane conductor 9A, 9B...terminal electrode 10A, 10B...terminal electrode 11...dielectric layer 12...substrate conductive electrode 13...N well 14...P+ region 15...substrate conductive electrode 21...member 101-104...electronic component 111...electronic component 201...member 301...electronic component as comparative example 311...electronic component

Claims

1. a substrate, an insulator layer formed along a surface of the substrate, an inductor formed in the insulator layer, one or more planar conductors formed on the substrate or the insulator layer and extending along the substrate, and one or more planar conductor connecting conductors electrically connected to the planar conductors; the inductor includes a plurality of planar conductors extending in a plurality of layers along a surface of the substrate, and a plurality of inductor via conductors connecting the planar conductors extending in different layers among the plurality of layers, and is an inductor formed by a helical coil having a winding axis along the surface of the substrate; one of the plurality of inductor via conductors runs adjacent to the planar conductor in a direction parallel to the winding axis, and a direction of a current flowing through the adjacent inductor via conductor running in parallel is opposite to a direction of a current flowing through the planar conductor; Electronic components.

2. the planar conductor connecting conductor is located at an end of the helical coil in the direction of the winding axis, The electronic component according to claim 1 .

3. the planar conductor is formed at a position closer to the substrate than the plurality of planar conductors; The electronic component according to claim 1 or 2.

4. 4. The electronic component according to claim 3, wherein the planar conductor connecting conductor is composed of three or more portions, one of which is formed in the same layer as the planar conductor.

5. the substrate is a low resistance semiconductor substrate, the planar conductor is a capacitor electrode that constitutes a capacitor together with the semiconductor substrate; The electronic component according to claim 1 or 2.

6. The sheet conductor is a resistor film. The electronic component according to claim 1 or 2.

7. the substrate is a semiconductor substrate; The planar conductor constitutes a semiconductor element together with the semiconductor substrate. The electronic component according to claim 1 or 2.

8. the inductor via conductors are arranged in two rows, and the planar conductor connecting conductors are positioned next to ends of the two rows of inductor via conductors. The electronic component according to claim 1 or 2.

9. the ends of the inductor via conductors and the planar conductor connecting conductors are disposed at equal intervals. The electronic component according to claim 8.