Gate driving device of semiconductor element for electric power, and electric power conversion device

Abstract

This gate driving device comprises: gate driving voltage output units that are provided in correspondence to each of a plurality of power semiconductor elements connected in series, and that output gate driving voltages; gate lines provided in correspondence to each of the gate driving voltage output units and are connected to control terminals of the power semiconductor elements corresponding to the gate driving voltage output units; a magnetic coupling unit that magnetically couples the gate lines to each other; a first wiring path through which a current flows from the gate driving voltage output units toward the gate lines corresponding to the gate driving voltage output units; a second wiring path through which a current flows from the gate lines connected to the first wiring path toward the gate driving voltage output units corresponding to the gate lines; and a third wiring path that attenuates an excitation current generated by the magnetic coupling unit.

Description

Gate driver for power semiconductor device and power converter

[0001] The present disclosure relates to a gate driver for a power semiconductor device and a power conversion device.

[0002] 2. Description of the Related Art Various gate drive devices have been proposed for turning on and off semiconductor switching elements, which are power semiconductor elements connected in series.

[0003] For example, in a semiconductor switch circuit comprising a plurality of voltage-driven semiconductor elements connected in series to form arms, and a gate drive circuit that supplies gate signals to the gate terminals of each of the plurality of voltage-driven semiconductor elements in each arm, there is known a control device for series-connected voltage-driven semiconductor elements, characterized in that gate lines connecting the gate drive circuit to the gate terminals of each voltage-driven semiconductor element in each arm are magnetically coupled to each other (see, for example, Patent Document 1).

[0004] For example, in a semiconductor switch circuit comprising a plurality of voltage-driven semiconductor elements connected in series and a gate drive circuit that supplies gate signals to the gate terminals of the voltage-driven semiconductor elements to turn these voltage-driven semiconductor elements on and off, a control device for series-connected voltage-driven semiconductor elements is known, which is characterized in that a winding that magnetically couples the gate lines connecting the gate drive circuit to the gate terminals of the voltage-driven semiconductor elements and a reset winding are provided, and excitation energy stored based on this magnetic coupling is reset via the reset winding (see, for example, Patent Document 2).

[0005] Patent No. 4396036 Patent No. 4396059

[0006] For example, in the invention described in Patent Document 1 (Japanese Patent No. 4396036), the gate lines of a voltage-driven semiconductor element are magnetically coupled, and if the current values ​​flowing through the gate lines differ when the voltage-driven semiconductor element is turned on or off, the impedance of the gate lines is instantly changed in accordance with the difference, thereby matching the gate currents and suppressing variations in switching timing. However, in the invention described in Patent Document 1 (Japanese Patent No. 4396036), when each of the series-connected power semiconductor elements is turned on or off, depending on the conditions, oscillations of different phases appear in the gate-source voltages (gate voltages) of each power semiconductor element at a certain period. If the next switching operation of the power semiconductor element is performed before the oscillations have decayed, the difference in gate voltages at the start of switching will cause an imbalance in the voltage distribution (drain-source voltage imbalance) for each of the series-connected power semiconductor elements to increase.

[0007] Therefore, in a gate drive device for a plurality of power semiconductor elements connected in series and in a power conversion device equipped with the same, there is a need for a technology that can suppress the oscillation of the current flowing through the gate terminals of each power semiconductor element, even if there is variation in the transmission time of the gate signal or the characteristics of the power semiconductor elements, and thereby suppress imbalances in voltage distribution during switching operations for each power semiconductor element.

[0008] According to one aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series includes: a gate drive voltage output section provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; a gate line provided corresponding to each of the gate drive voltage output sections and connected to a control terminal of the power semiconductor element corresponding to the gate drive voltage output section; a magnetic coupling section magnetically coupling each of the gate lines to each other; a first wiring path which is a path for current flowing from the gate drive voltage output section to the gate line corresponding to the gate drive voltage output section; a second wiring path which is a path for current flowing from the gate line connected to the first wiring path to the gate drive voltage output section corresponding to the gate line; and a third wiring path which attenuates excitation current generated in the magnetic coupling section.

[0009] Here, the first wiring path may include a first diode having an anode connected to the wiring leading to the positive terminal of the gate drive voltage output unit and a cathode connected to the wiring leading to the magnetic coupling unit, and the second wiring path may include a second diode having a cathode connected to the wiring leading to the negative terminal of the gate drive voltage output unit and an anode connected to the wiring leading to the magnetic coupling unit.

[0010] The third wiring path may also include a first resistor connected in parallel to the first diode and a second resistor connected in parallel to the second diode.

[0011] In addition, the third wiring path may include a series circuit consisting of a third resistor and a first switch that opens and closes the wiring connected to the third resistor, and the series circuit may be connected to one of the two gate lines magnetically coupled by the magnetic coupling portion so as to be in parallel with the magnetic coupling portion.

[0012] In addition, the first switch may be configured to be turned on during a first fixed period of time during which a current flows through the first wiring path and to be turned off during periods other than the first fixed period, and to be turned on during a second fixed period of time during which a current flows through the second wiring path and to be turned off during periods other than the second fixed period.

[0013] The first wiring path may include a positive-side switch that applies or cuts off the positive side potential of the gate drive voltage output unit to the control terminal of the power semiconductor element corresponding to the first wiring path, and a positive-side gate resistor connected in series to the positive-side switch, and the second wiring path may include a negative-side switch that applies or cuts off a potential of 0 volts or less, which is the negative side potential of the gate drive voltage output unit, to the control terminal of the power semiconductor element corresponding to the second wiring path, and a negative-side gate resistor connected in series to the negative-side switch.

[0014] Furthermore, each of the gate drive voltage output units may have a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, and the third wiring path may include a second switch that opens and closes the wiring between the control terminal of the power semiconductor element and the connection point between the positive switch and the positive side of the positive potential output unit, and a third switch that opens and closes the wiring between the control terminal of the power semiconductor element and the connection point between the negative switch and the negative side of the negative potential output unit.

[0015] In addition, the second switch may be configured to perform an ON operation while the positive side switch is in an ON operation, and then perform an OFF operation before the negative side switch starts to turn on, and the third switch may be configured to perform an ON operation while the negative side switch is in an ON operation, and then perform an OFF operation before the positive side switch starts to turn on.

[0016] The current output terminal of the power semiconductor element may be a source terminal, an emitter terminal, or a cathode terminal.

[0017] Furthermore, according to one aspect of the present disclosure, a gate drive device for a plurality of power semiconductor elements connected in series includes: a gate drive voltage output section provided corresponding to each of the power semiconductor elements and outputting a gate drive voltage; a gate line provided corresponding to each of the gate drive voltage output sections and connected to a control terminal of the power semiconductor element corresponding to the gate drive voltage output section; a magnetic coupling section magnetically coupling each of the gate lines to each other; a fourth wiring path which is a path for current flowing from the gate drive voltage output section to the gate line corresponding to the gate drive voltage output section; a fifth wiring path which is a path for current flowing from the control terminal of the power semiconductor element to which the gate line is connected to the gate drive voltage output section corresponding to the gate line; and a sixth wiring path which attenuates excitation current generated in the magnetic coupling section.

[0018] Here, the fourth wiring path may include a fourth diode having an anode connected to the wiring leading to the positive terminal of the gate drive voltage output section and a cathode connected to the wiring leading to the magnetic coupling section, and the sixth wiring path may include a fourth resistor connected in parallel to the fourth diode.

[0019] The control terminal of the power semiconductor element may be a gate terminal or a base terminal.

[0020] According to one aspect of the present disclosure, the power conversion device includes the gate drive device, a power conversion circuit unit having an arm on which a plurality of power semiconductor elements connected in series are provided and performing power conversion operations in response to the on / off operations of the power semiconductor elements, and a power conversion control unit that controls the power conversion operation of the power conversion circuit unit.

[0021] According to one aspect of the present disclosure, in a gate drive device for a plurality of power semiconductor elements connected in series and a power conversion device including the same, even if there is variation in the transmission time of the gate signal or the characteristics of the power semiconductor elements, it is possible to suppress oscillations in the current flowing through the control terminals of each of the power semiconductor elements, thereby suppressing imbalances in voltage distribution during switching operations for each of the power semiconductor elements.

[0022] 1 is a circuit diagram showing a gate driver according to a first embodiment of the present disclosure; FIG. 2 is a diagram illustrating a magnetic coupling unit in the gate driver according to the first to fourth embodiments of the present disclosure; and FIG. 3 is a diagram illustrating a power semiconductor element Q in the gate driver according to the first embodiment of the present disclosure. A 1 is a circuit diagram (part 1) illustrating a current flow during an ON operation of the power semiconductor element Q in the gate driver according to the first embodiment of the present disclosure. A 5 is a circuit diagram (part 2) illustrating the flow of current during an on-operation of a power semiconductor element Q. FIG. 6 is a diagram illustrating a power conversion device including a gate driver according to an embodiment of the present disclosure. FIG. 7 is a circuit diagram illustrating an arm provided in the power conversion device shown in FIG. 5. FIG. 8 is a circuit diagram illustrating a gate driver according to the invention described in Patent Document 1 (Japanese Patent No. 4396036). FIG. 9 is a diagram illustrating an example of the waveform of the gate-source voltage of each power semiconductor element Q when transitioning from an off state to an on state in the case where there is a transmission delay in the gate signal in the invention described in Patent Document 1 (Japanese Patent No. 4396036). A and Q BWhen the power semiconductor element Q transitions from the on state to the off state, A and Q B 1 is a diagram illustrating an example of a drain-source voltage and a current flowing from the drain to the source of a power semiconductor element Q when an imbalance in voltage sharing occurs in the invention described in Patent Document 1 (Japanese Patent No. 4396036). A and Q B When the power semiconductor element Q transitions from the OFF state to the ON state, A and Q B 1 is a diagram illustrating an example of a drain-source voltage and a drain current flowing from the drain to the source. It is an equivalent circuit diagram showing a current flow when a power semiconductor element transitions from an off state to an on state in the case where there is a transmission delay in the gate signal in the invention described in Patent Document 1 (Japanese Patent No. 4396036). It is an equivalent circuit diagram showing a current flow when a power semiconductor element transitions from an off state to an on state in the case where there is no transmission delay in the gate signal in the invention described in Patent Document 1 (Japanese Patent No. 4396036). It is a diagram illustrating a simulated waveform of the gate-source voltage in the invention described in Patent Document 1 (Japanese Patent No. 4396036). It is a diagram illustrating a simulated waveform of the gate-source voltage in the gate drive device according to the first embodiment of the present disclosure. It is a circuit diagram showing a gate drive device according to the second embodiment of the present disclosure. It is a circuit diagram showing a gate drive device according to the third embodiment of the present disclosure. It is a diagram illustrating a simulated waveform of the gate-source voltage in the gate drive device according to the third embodiment of the present disclosure. It is a diagram explaining the operation of a first switch, a positive-side switch, and a negative-side switch in the gate drive device according to the third embodiment of the present disclosure. 10 is a circuit diagram showing a gate driver according to a fourth embodiment of the present disclosure, and is a diagram illustrating the operation of each switch in the gate driver according to the fourth embodiment of the present disclosure.

[0023] A gate driver for a power semiconductor device and a power conversion device will be described below with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals. The drawings are not limited to the illustrated embodiment. The illustrated embodiment is merely an example, and the present invention is not limited to these embodiments. Here, "on" of a switch means that the circuit in which the switch is provided is closed; that is, when the switch is turned on, the circuit in which the switch is provided is connected and closed. Furthermore, "off" of a switch means that the circuit in which the switch is provided is opened; that is, when the switch is turned off, the circuit in which the switch is provided is interrupted and opened.

[0024] A gate driver according to each embodiment of the present disclosure drives on and off a plurality of power semiconductor elements connected in series. Examples of power semiconductor elements include MOSFETs, IGBTs, thyristors, GTOs, and transistors. MOSFETs have gate, drain, and source terminals as their terminals. IGBTs have gate, collector, and emitter terminals as their terminals. Transistors have base, collector, and emitter terminals as their terminals. Thyristors and GTOs have gate, anode, and cathode terminals as their terminals. The "current inflow terminals" of power semiconductor elements correspond to the "drain terminals" of MOSFETs, the "collector terminals" of IGBTs and transistors, and the "anode terminals" of thyristors and GTOs, respectively. The "current outflow terminals" of power semiconductor elements correspond to the "source terminals" of MOSFETs, the "emitter terminals" of IGBTs and transistors, and the "cathode terminals" of thyristors and GTOs, respectively. The "control terminal" of a power semiconductor element corresponds to the "gate terminal" of a MOSFET, IGBT, thyristor, and GTO, and the "base terminal" of a transistor.

[0025] The following description will be given of a case where the power semiconductor element is configured as a MOSFET as an example, but the embodiments of the present disclosure are also applicable to IGBTs, thyristors, GTOs, or transistors. Furthermore, when the power semiconductor element is configured as an IGBT, the "drain" as a current inflow terminal is replaced with the "collector," and the "source" as a current outflow terminal is replaced with the "emitter," and the embodiments of the present disclosure are applicable. Furthermore, when the power semiconductor element is configured as a transistor, the "gate" as a control terminal is replaced with the "base," the "drain" as a current inflow terminal is replaced with the "collector," and the "source" as a current outflow terminal is replaced with the "emitter," and the embodiments of the present disclosure are applicable. Furthermore, when the power semiconductor element is configured as a thyristor or GTO, the "drain" as a current inflow terminal is replaced with the "anode," and the "source" as a current outflow terminal is replaced with the "cathode," and the embodiments of the present disclosure are applicable.

[0026] First Embodiment

[0027] FIG. 1 is a circuit diagram showing a gate driver according to a first embodiment of the present disclosure.

[0028] The gate driver 1 according to the first embodiment and the second to fourth embodiments of the present disclosure drives a plurality of power semiconductor elements connected in series to turn on and off. Here, as an example, two power semiconductor elements Q A and Q B However, the following description is also applicable to the case where three or more power semiconductor elements connected in series are turned on and off.

[0029] Power semiconductor element Q A The feedback diode D A are connected in antiparallel. Similarly, the power semiconductor element Q B The feedback diode D B are connected in inverse parallel.

[0030] The gate driver 1 according to the first embodiment of the present disclosure includes gate drive voltage output units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, first wiring paths 14-A and 14-B, second wiring paths 15-A and 15-B, and third wiring paths 16-A1, 16-A2, 16-B1, and 16-B2.

[0031] The gate drive voltage output unit 11-A is connected to the power semiconductor device Q A The gate drive voltage output section 11-B is provided corresponding to the power semiconductor element Q and outputs a positive gate drive voltage (for example, 17 V) corresponding to an ON signal of the gate signal, and 0 V or a negative gate drive voltage (for example, −11 V) corresponding to an OFF signal of the gate signal. B and outputs a positive gate drive voltage (for example, 17 V) corresponding to an ON signal of the gate signal, and 0 V or a negative gate drive voltage (for example, −11 V) corresponding to an OFF signal of the gate signal. The gate drive voltage output units 11-A and 11-B insulate or convert the voltage level of the ON signal or OFF signal inputted, and output the ON signal or OFF signal to the power semiconductor element Q A , Q B For simplicity of explanation, hereinafter, unless otherwise specified, an OFF signal of the gate signal will be explained as corresponding to a gate drive voltage of 0 V, but the OFF signal of the gate signal may also be a negative gate drive voltage.

[0032] The gate drive voltage output section 11-A is a positive potential output section VF that outputs a positive potential of the gate drive voltage. A and a negative potential output unit VR that outputs a negative potential of the gate drive voltage. A and the positive switch SH A and the negative switch SL A The negative voltage output unit VR A is the positive potential output section VF A In the gate drive voltage output section 11-A, the positive side switch SH A performs an ON operation, and the negative side switch SL AWhen the positive switch SH is turned off, a positive gate drive voltage (for example, 17 V) corresponding to the ON signal of the gate signal is output from the positive terminal of the gate drive voltage output unit 11-A. A performs an off operation, and the negative side switch SL A When the gate driving voltage output section 11-A performs an ON operation, 0V or a negative gate driving voltage (for example, -11V) corresponding to the OFF signal of the gate signal is output from the negative terminal of the gate driving voltage output section 11-A.

[0033] Similarly, the gate drive voltage output section 11-B outputs a positive potential of the gate drive voltage to a positive potential output section VF B and a negative potential output unit VR that outputs a negative potential of the gate drive voltage. B and the positive switch SH B and the negative switch SL B The negative voltage output unit VR B is the positive potential output section VF B In the gate drive voltage output section 11-B, the positive side switch SH B performs an ON operation, and the negative side switch SL B When the positive switch SH is turned off, a positive gate drive voltage (for example, 17 V) corresponding to the ON signal of the gate signal is output from the positive terminal of the gate drive voltage output unit 11-B. B performs an off operation, and the negative side switch SL B When the gate drive voltage output section 11-B performs an ON operation, 0V or a negative gate drive voltage (for example, -11V) corresponding to the OFF signal of the gate signal is output from the negative terminal of the gate drive voltage output section 11-B.

[0034] Positive switch SH in gate drive voltage output unit 11-A A and the positive switch SH in the gate drive voltage output unit 11-B B The positive side switches SH perform ON and OFF operations synchronously. A and SH B Similarly, the ON / OFF timings of the SL in the gate drive voltage output section 11-A are the same. Aand the negative switch SL in the gate drive voltage output unit 11-B B The negative side switches SL perform on and off operations synchronously. A and SL B The on / off timing is the same between the positive terminal of the gate drive voltage output unit 11-A and the negative terminal of the gate drive voltage output unit 11-B. Therefore, when a positive gate drive voltage is output from the positive terminal of the gate drive voltage output unit 11-A, a positive gate drive voltage is output from the positive terminal of the gate drive voltage output unit 11-B. Also, when a gate drive voltage of 0 V is output from the negative terminal of the gate drive voltage output unit 11-A, a gate drive voltage of 0 V is output from the negative terminal of the gate drive voltage output unit 11-B.

[0035] The gate lines 12-A and 12-B are provided corresponding to the gate drive voltage output units 11-A and 11-B, respectively, and are connected to the power semiconductor elements Q A and Q B is connected to the gate terminal of the

[0036] The gate line 12-A supplies the gate drive voltage output from the gate drive voltage output unit 11-A to the corresponding power semiconductor element Q A The power semiconductor element Q is supplied with a voltage from the gate terminal, which is the control terminal of the power semiconductor element Q. A When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q A is turned on, and the power semiconductor element Q A When a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q A is turned off.

[0037] The gate line 12-B transmits the gate drive voltage output from the gate drive voltage output unit 11-B to the corresponding power semiconductor element Q B The power semiconductor element Q is supplied with a voltage from the gate terminal, which is the control terminal of the power semiconductor element Q. B When a positive gate drive voltage is applied to the gate terminal of the power semiconductor element Q B is turned on, and the power semiconductor element Q B When a gate drive voltage of 0 V is applied to the gate terminal of the power semiconductor element Q B is turned off.

[0038] The magnetic coupling unit 13 magnetically couples the gate line 12-A and the gate line 12-B. FIG. 2 is a diagram illustrating a magnetic coupling unit in a gate driver according to the first to fourth embodiments of the present disclosure. FIG. 2 is also applicable to the second to fourth embodiments described below. The magnetic coupling unit 13 has a magnetic body 30. The gate lines 12-A and 12-B are wound around the magnetic body 30. For example, as shown in FIG. 2, when a gate current Ig1 flows, a magnetic flux Φ1 is generated in the magnetic body 30 and crosses the gate line 12-B. Similarly, when a gate current Ig2 flows, a magnetic flux Φ2 is generated in the magnetic body 30 and crosses the gate line 12-A. This magnetically couples the gate line 12-A and the gate line 12-B. The number of turns N1 of the gate line 12-A to the magnetic body 30 is the same as the number of turns N2 of the gate line 12-B to the magnetic body 30, and when the gate currents Ig1 and Ig2 are equal, |Φ1| = |Φ2| holds, and when the gate currents Ig1 and Ig2 have opposite polarities, Φ1 and Φ2 have opposite polarities.

[0039] For example, a power semiconductor element Q A and power semiconductor element Q B The timing of the power semiconductor element Q A is the power semiconductor element Q B If the gate line 12-A is turned off before the gate line 12-B, the magnetic flux Φ1 and the magnetic flux Φ2 will not be equal when the gate current Ig1 starts flowing before the gate current Ig2, and a magnetic flux of |Φ1-Φ2| will be generated in the magnetic body 30, resulting in magnetic coupling. At this time, an inductance L1 is generated in the gate line 12-A and an inductance L2 is generated in the gate line 12-B, and these inductances L1 and L2 are proportional to |Φ1-Φ2|. The greater the imbalance between the gate currents Ig1 and Ig2, the larger the inductances L1 and L2. Furthermore, as the inductances L1 and L2 increase, the impedance of the gate lines 12-A and 12-B increases, making it more difficult for the gate currents Ig1 and Ig2 to flow. This changes the impedance of the gate lines 12-A and 12-B depending on the imbalance between the gate currents Ig1 and Ig2, allowing the gate currents Ig1 and Ig2 to match.

[0040] In this way, the magnetic coupling portion 13 has a power semiconductor element Q A and power semiconductor element Q B The gate current Ig1 and the gate current Ig2 are operated so as to match each other even if the timing of the turn-off operations of the two transistors is not synchronized.

[0041] The positive terminal of the gate drive voltage output unit 11-A is connected to a positive gate resistor R gAon is connected to the negative terminal, and the negative gate resistor R gAoff Similarly, a positive gate resistor R is connected to the positive terminal of the gate drive voltage output unit 11-B. gBon is connected to the negative terminal, and the negative gate resistor R gBoff is connected.

[0042] Power semiconductor element Q A The first wiring path 14-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A, and the first wiring path 14-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A. gAon The first wiring path 14-A is provided between the gate line 12-A and the positive side gate resistor R gAon and a cathode connected to the gate line 12-A, which is the wiring connected to the magnetic coupling portion 13. Aon Equipped with.

[0043] Power semiconductor element Q B The first wiring path 14-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B, and the first wiring path 14-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B. gBon The first wiring path 14-B is provided between the gate line 12-B and the positive side gate resistor R gBon and a cathode connected to the gate line 12-B, which is the wiring connected to the magnetic coupling portion 13. Bon Equipped with.

[0044] Power semiconductor element Q AThe second wiring path 15-A corresponding to the negative side gate resistance R gAoff The second wiring path 15-A is provided between the gate line 12-A and the negative side gate resistor R gAoff and an anode connected to the gate line 12-A, which is the wiring connected to the magnetic coupling portion 13. Aoff Equipped with.

[0045] Power semiconductor element Q B The second wiring path 15-B corresponding to the negative side gate resistance R gBoff The second wiring path 15-B is provided between the gate line 12-B and the negative side gate resistor R gBoff and an anode connected to the gate line 12-B, which is the wiring connected to the magnetic coupling portion 13. Boff Equipped with.

[0046] Power semiconductor element Q A The third wiring paths 16-A1 and 16-A2 corresponding to the first diode D Aon A first resistor R Aon The third wiring path 16-A2 includes a second diode D Aoff A second resistor R Aoff Equipped with.

[0047] Power semiconductor element Q B The third wiring paths 16-B1 and 16-B2 corresponding to the first diode D Bon A first resistor RBon The third wiring path 16-B2 includes a second diode D Boff A second resistor R Boff Equipped with.

[0048] Next, the operation of the gate driver 1 according to the first embodiment of the present disclosure will be described with reference to FIGS. 3 and 4. FIG.

[0049] 3 and 4 show the power semiconductor element Q in the gate driver according to the first embodiment of the present disclosure. A 3 and 4 are circuit diagrams illustrating the flow of current during the ON operation of the power semiconductor element Q. A When viewed from the gate terminal side, the input capacitance is Cgs A and the power semiconductor element Q B When viewed from the gate terminal side, the input capacitance is Cgs B Let's say.

[0050] Power semiconductor element Q A The ON operation of the positive side switch SH of the gate drive voltage output unit 11-A is A is turned on and the negative switch SL A When this is turned off, a positive gate drive voltage (for example, 17 V) is output from the positive terminal of the gate drive voltage output unit 11-A, and the power semiconductor element Q A This is realized by applying a voltage to the gate terminal of the positive side potential output section VF of the gate drive voltage output section 11-A. A The positive potential of the gate drive voltage output from the power semiconductor element Q B Power semiconductor device Q A When a voltage is applied to the power semiconductor device Q A The gate-source voltage of the transistor VF starts to rise from a negative potential to a positive potential. At this time, as shown by the bold arrow in FIG. A , positive switch SH A , positive gate resistance R gAon , the first diode D on the first wiring path 14-A Aon , the magnetic coupling portion 13, and the power semiconductor element Q A Input capacitance Cgs A The current flows through the positive gate resistor R gAonis the power semiconductor element Q A In order to make the switching speed of the power semiconductor element Q as fast as possible, the resonance condition is met and the current oscillates. A Input capacitance Cgs A The voltage of the positive side potential output part VF A When the gate drive voltage output from the power semiconductor element Q A to the positive potential output section VF A The current flows backward toward the power semiconductor element Q. A Input capacitance Cgs A , the magnetic coupling portion 13, the first resistor R on the third wiring path 16-A1 Aon , positive gate resistance R gAon , positive switch SH A , and the positive potential output section VF A The first resistor R Aon Since the value of is large enough to attenuate the current, the current is attenuated and the power semiconductor element Q A The oscillation of the gate-source voltage is suppressed.

[0051] Power semiconductor element Q A During the off operation of the power semiconductor element Q A The current flow direction is opposite to that of the power semiconductor element Q when it is turned on. A The turning-off operation of the positive side switch SH of the gate drive voltage output unit 11-A is A is turned off and the negative switch SL A When this is turned on, a negative gate drive voltage (for example, 0 V or less) is output from the negative terminal of the gate drive voltage output unit 11-A, and the power semiconductor element Q A This is realized by applying the negative voltage output section VR of the gate drive voltage output section 11-A to the gate terminal of the A The negative potential of the gate drive voltage output from the power semiconductor element Q B Power semiconductor device Q A When a voltage is applied to the power semiconductor device Q AThe gate-source voltage of the power semiconductor device Q starts to decrease from a positive potential to a negative potential. A Input capacitance Cgs A , the magnetic coupling portion 13, the second diode D on the second wiring path 15-A, Aoff , negative gate resistance R gAoff , negative switch SL A , and the negative potential output unit VR A The negative gate resistor R gAoff is the power semiconductor element Q B In order to make the switching speed of the power semiconductor element Q as fast as possible, the resonance condition is met and the current oscillates. A Input capacitance Cgs A The voltage of the negative side potential output part VR A When the gate drive voltage becomes equal to or lower than the negative potential output from the negative potential output section VR A From power semiconductor element Q A The current flows backward toward the negative side potential output section VR A , negative switch SL A , negative gate resistance R gAoff , the second resistor R on the third wiring path 16-A2 Aoff , the magnetic coupling portion 13, and the power semiconductor element Q A Input capacitance Cgs A The second resistor R Aoff Since the value of is large enough to attenuate the current, the current is attenuated and the power semiconductor element Q A The oscillation of the gate-source voltage is suppressed.

[0052] The above is the power semiconductor element Q in the gate drive device. A The current flow during the on-state and off-state of the power semiconductor element Q B The same explanation applies to the current flow during ON and OFF operations.

[0053] By using the gate drive device 1 described above, it is possible to drive the power semiconductor elements on and off in a power conversion device configured by connecting a plurality of arms in series, each arm having a plurality of power semiconductor elements connected in series.

[0054] 5 is a diagram showing a power conversion device including a gate driver according to an embodiment of the present disclosure. Also, FIG. 6 is a circuit diagram showing an arm provided in the power conversion device shown in FIG. 5. Here, as an example, two power semiconductor elements Q connected in series are used. A and Q B An example of the configuration of the arm 50 will be described.

[0055] The power conversion device 100 according to one embodiment of the present disclosure includes the above-described gate drive device 1, a power conversion circuit unit 2 having an arm 50 provided with a plurality of power semiconductor elements connected in series and performing power conversion operations in response to the on / off operations of the power semiconductor elements, and a power conversion control unit 3 controlling the power conversion operation of the power conversion circuit unit 2.

[0056] As shown in FIG. 6, the arm 50 is made up of, for example, two power semiconductor elements Q A and Q B Power semiconductor element Q A The terminal P1 is drawn out from the drain terminal of the power semiconductor element Q B A terminal P2 is drawn out from the source terminal of the arm 50. In the power conversion circuit unit 2, the terminal P2 of one arm 50 is connected to the terminal P1 of another arm 50, and the connection point is connected to one terminal of the load. In the example shown in Figure 5, two arms 50 are connected in series to form one leg 60, and the two legs 60 form the power conversion circuit unit 2.

[0057] A DC power supply 200 is connected to a leg 60 formed of arms 50 connected in series. A load 300 is connected between a terminal T1 between the arms 50 connected in series in one leg 60 and a terminal T2 between the arms 50 connected in series in the other leg 60.

[0058] The gate driver 1 is provided corresponding to each arm 50.A and power semiconductor element Q B are turned on and off by the corresponding gate drive devices 1. That is, the gate drive voltage output units 11-A and 11-B generate the gate drive voltages as described above, and then each positive switch SH A and SH B and each negative switch SL A and SL B By turning on and off the power semiconductor element Q A and Q B The voltage applied to the gate terminal of the transistor is controlled.

[0059] The power conversion control unit 3 controls the positive side switches SH in the gate drive devices 1. A and SH B and each negative switch SL A and SL B That is, the power conversion control unit 3 controls the on and off operations of each positive side switch SH in each gate driver 1. A and SH B and each negative switch SL A and SL B By controlling the on and off operations of the power semiconductor element Q A and Q B This controls the voltage applied to the gate terminal of the power semiconductor element Q A and Q B The positive side switches SH in each gate driver 1 are turned on and off. As a result, the power conversion circuit unit 2 performs a power conversion operation of converting DC power supplied from the DC power supply 200 into desired power and supplying it to the load 300. The power conversion control unit 3 controls the positive side switches SH in each gate driver 1 so that there is no deviation between the detected value i of the current flowing from the positive side terminal T1 to the load 300 and the current command which is the control target value. A and SH B and each negative switch SL A and SL B A gate signal is generated to control the on and off operations of the transistors.

[0060] The power conversion device 100 includes an arithmetic processing unit (processor). The arithmetic processing unit includes a power conversion control unit 3. The power conversion control unit 3 included in the arithmetic processing unit is a functional module implemented, for example, by a computer program executed on the processor. For example, if the power conversion control unit 3 is implemented in the form of a computer program, the relevant function can be realized by operating the arithmetic processing unit in accordance with the computer program. The computer program for executing the processing of the power conversion control unit 3 may be provided in a form recorded on a computer-readable recording medium such as a semiconductor memory, a magnetic recording medium, or an optical recording medium. Alternatively, the power conversion control unit 3 may be realized as a semiconductor integrated circuit into which a computer program for realizing the relevant function is written.

[0061] Next, the power semiconductor element Q in the invention described in Patent Document 1 (Japanese Patent No. 4396036) A and Q B The imbalance in voltage distribution (imbalance in drain-source voltage) for each of these will be described below.

[0062] FIG. 7 is a circuit diagram showing a gate driving device according to the invention described in Patent Document 1 (Japanese Patent No. 4396036).

[0063] The gate driver 1001 according to the invention described in Patent Document 1 (Japanese Patent No. 4396036) is a power semiconductor device Q A and Q B and a gate drive voltage output section 111-A that outputs a gate drive voltage and a gate drive voltage output section 111-B that outputs a gate drive voltage to a corresponding power semiconductor device Q. A and Q B and a magnetic coupling portion 131 that magnetically couples the gate lines that are supplied to the gate terminals of the power semiconductor element Q. A The feedback diode D A are connected in antiparallel. Similarly, the power semiconductor element Q B The feedback diode D BThe gate drive voltage output section 111-A is connected in anti-parallel to a positive potential output section VF A and a negative potential output unit VR that outputs a negative potential of the gate drive voltage. A and the positive switch SH A and the negative switch SL A The negative voltage output unit VR A is the positive potential output section VF A The gate drive voltage output section 111-B is connected in series to a positive potential output section VF B and a negative potential output unit VR that outputs a negative potential of the gate drive voltage. B and the positive switch SH B and the negative switch SL B The positive terminal of the gate drive voltage output unit 111-A is connected to a positive gate resistor R gAon is connected to the negative terminal, and the negative gate resistor R gAoff The positive terminal of the gate drive voltage output unit 111-B is connected to a positive gate resistor R gBon is connected to the negative terminal, and the negative gate resistor R gBoff is connected.

[0064] 8 is a diagram illustrating the waveform of the gate-source voltage of each power semiconductor element when it transitions from an OFF state to an ON state in the case where there is a transmission delay in the gate signal in the invention described in Patent Document 1 (Japanese Patent No. 4396036). A The on / off signal of the gate signal for the power semiconductor element Q B The gate signal is output 250 ns earlier than the on / off signal for the gate signal.

[0065] As shown in FIG. 8, the power semiconductor element Q A and Q B In the on state, the gate-source voltage V gsA and V gsB If the device transitions to the OFF state while this oscillation continues, an imbalance in the voltage applied to the device occurs during the OFF operation, depending on the duration of the ON state.

[0066] For example, at the off timing t2, the power semiconductor element Q A The gate-source voltage V gsA and power semiconductor element Q B The gate-source voltage V gsb The same as above. Power semiconductor element Q A The gate signal for the power semiconductor element Q B The gate signal for the power semiconductor device Q is output 250 ns earlier than the off signal for the power semiconductor device Q. A Applied voltage (drain-source voltage) V dsA is the power semiconductor element Q B Applied voltage (drain-source voltage) V dsB will be slightly larger than

[0067] For example, at the off timing t1, the power semiconductor element Q A The gate-source voltage V gsA is the power semiconductor element Q B The gate-source voltage V gsb Larger. Power semiconductor element Q A The gate-source voltage V gsA is the power semiconductor element Q B The gate-source voltage V gsb from a state in which the power semiconductor element Q A Since the power semiconductor element Q A The start of the off operation of the power semiconductor device Q B Therefore, the start of the power semiconductor device Q B Applied voltage (drain-source voltage) V dsB is the power semiconductor element Q A Applied voltage (drain-source voltage) V dsA becomes larger than

[0068] For example, at the off timing t3, the power semiconductor element Q B The gate-source voltage V gsb is the power semiconductor element Q A The gate-source voltage V gsALarger. Power semiconductor element Q B The gate-source voltage V gsb is the power semiconductor element Q A The gate-source voltage V gsA from a state in which the power semiconductor element Q B Since the power semiconductor element Q B The start of the off operation of the power semiconductor device Q A Therefore, the start of the power semiconductor device Q A Applied voltage (drain-source voltage) V dsA is the power semiconductor element Q B Applied voltage (drain-source voltage) V dsB Moreover, the power semiconductor element Q A The gate signal for the power semiconductor element Q B Since the gate signal for the power semiconductor element Q is output 250 ns earlier than the OFF signal for the power semiconductor element Q A Applied voltage (drain-source voltage) V dsA and power semiconductor element Q B Applied voltage (drain-source voltage) V dsB The difference becomes even greater.

[0069] The above has explained the waveform of the gate-source voltage of each power semiconductor element when it transitions from an OFF state to an ON state, but the same explanation applies when it transitions from an ON state to an OFF state.

[0070] Power semiconductor element Q A and Q B If there is a transmission delay in the gate signal or a difference in the gate-source voltage, the power semiconductor element Q A and Q B An imbalance in voltage distribution (drain-source voltage imbalance) occurs during switching operations for each of these.

[0071] FIG. 9 shows the power semiconductor element Q when an imbalance in voltage sharing occurs in the invention described in Patent Document 1 (Japanese Patent No. 4396036). A and Q BWhen the power semiconductor element Q transitions from the on state to the off state, A and Q B 1 is a diagram illustrating an example of the drain-source voltage and the drain current flowing from the drain to the source of the power semiconductor element Q. A and Q B When the power semiconductor element Q1 transitions from the on state to the off state, the drain current begins to decrease from a certain value. A and Q B Drain-source voltage V dsA and V dsB Power semiconductor element Q A and Q B If there is any difference in the switching operation of the power semiconductor element Q A and Q B The voltage distribution after the power-off operation becomes unbalanced.

[0072] FIG. 10 shows the power semiconductor element Q when an imbalance in voltage sharing occurs in the invention described in Patent Document 1 (Japanese Patent No. 4396036). A and Q B When the power semiconductor element Q transitions from the OFF state to the ON state, A and Q B 1 is a diagram illustrating an example of the drain-source voltage and the drain current flowing from the drain to the source of the power semiconductor element Q. A and Q B When the power semiconductor element Q1 transitions from the off state to the on state, the drain current begins to increase from zero. A The drain-source voltage V dsA The power semiconductor element Q B The drain-source voltage V dsB increases. Power semiconductor element Q A and Q B If the on state of the power semiconductor element Q continues, A and Q B Drain-source voltage V dsA and V dsB is near zero, but around the time of switching from the OFF state to the ON state, the power semiconductor element Q Aand Q B This causes an imbalance in voltage sharing.

[0073] Next, the reason why oscillation occurs in the gate-source voltage of each power semiconductor element will be described with reference to FIGS.

[0074] Fig. 11 is an equivalent circuit diagram showing the flow of current when a power semiconductor element transitions from an off state to an on state in the case where there is a transmission delay in the gate signal in the invention described in Patent Document 1 (Japanese Patent No. 4396036). Fig. 12 is an equivalent circuit diagram showing the flow of current when a power semiconductor element transitions from an off state to an on state in the case where there is no transmission delay in the gate signal in the invention described in Patent Document 1 (Japanese Patent No. 4396036). In Figs. 11 and 12, A When viewed from the gate terminal side, the input capacitance is Cgs A and the power semiconductor element Q B When viewed from the gate terminal side, the input capacitance is Cgs B The excitation inductance of the magnetic coupling portion 131 is set as L m , power semiconductor element Q A The leakage inductance corresponding to rA and the power semiconductor element Q B The leakage inductance corresponding to rB Power semiconductor element Q A The current flowing through the gate terminal of i gA and the power semiconductor element Q B The current flowing through the gate terminal of i gB Let's say.

[0075] As an example, a power semiconductor element Q A When the gate signal for the power semiconductor element Q B The following describes the occurrence of vibration when a gate signal for a power semiconductor device Q is output earlier than an ON signal. A The positive switch SH corresponding to A is turned on and the positive potential output section VF A The positive potential of the gate drive voltage output from the power semiconductor element Q Aand the power semiconductor element Q B The negative switch SL corresponding to B maintains the ON state, and the negative side potential output section VR B The negative potential of the gate drive voltage output from the power semiconductor element Q B is output to.

[0076] In the state shown in FIG. 11, the excitation inductance L m A potential difference occurs between both ends of the magnetizing inductance L, and an exciting current i1 flows. m An exciting current flows through the power semiconductor element Q. A The current i flowing through the gate terminal of gA = i1 + i2, and the power semiconductor element Q B The current i flowing through the gate terminal of gB = i2.

[0077] Excitation inductance L m is designed to be relatively large in order to match the gate currents and suppress variations in switching timing. gA1 , R gA2 , R gB1 and R gB2 is a power semiconductor element Q A and Q B Therefore, it is difficult to avoid the resonance condition of the LCR series circuit, and the power semiconductor element Q A and Q B The current flowing through the gate terminal of oscillates, and the gate-source voltage V gsA and V gsB will vibrate.

[0078] In the state shown in FIG. 12, the positive side potential output section VF in the gate drive voltage output section 111-A A and the positive potential output from the positive side potential output section VF in the gate drive voltage output section 111-B. B The positive potential output from the power semiconductor element Q A The input capacitance of Cgs A and power semiconductor element Q B Input capacitance Cgs BThe amount of charge stored in each of the power semiconductor elements Q A The leakage inductance corresponding to rA and power semiconductor element Q B The leakage inductance corresponding to rB The electromotive voltages at the gate resistor R gA1 and gate resistance R gB1 If the electromotive forces of the two are the same, then the excitation inductance L m Since there is no potential difference between both ends of the gA -i gB " becomes zero, that is, the magnetizing inductance L m No excitation current flows through the excitation inductance L m Since no excitation current flows through the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB does not vibrate.

[0079] However, the positive potential output section VF A and positive potential output section VF B Each positive potential output from the input capacitance Cgs A and input capacitance Cgs B The charge amount stored in each of the rA and leakage inductance L rB Each electromotive voltage, gate resistance R gA1 and gate resistance R gB1 If there is any difference among the four parameters of each electromotive voltage, i gA -i gB is no longer zero, and the excitation inductance L m An exciting current flows through the power semiconductor element Q. A and Q B The current flowing through the gate terminal of oscillates, and the gate-source voltage V gsA and V gsB will vibrate.

[0080] In this way, the positive potential output section VF A and positive potential output section VF B Each positive potential output from the input capacitance CgsA and input capacitance Cgs B The charge amount stored in each of the rA and leakage inductance L rB Each electromotive voltage, gate resistance R gA1 and gate resistance R gB1 If any one of the four parameters of each electromotive voltage is different, or if there is a transmission difference in the gate signal, an excitation current will flow. This excitation current will cause oscillation of the current flowing through each gate terminal of the power semiconductor element, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB The excitation current is oscillated by the excitation inductance L m , gate resistance R gA1 , R gA2 , R gB1 and R gB2 , input capacitance C gsA and C gsB The excitation inductance L m is designed to be relatively large in order to match the gate currents and suppress variations in switching timing. gA1 , R gA2 , R gB1 and R gB2 is a power semiconductor element Q A and Q B Therefore, it is difficult to avoid the resonance condition of the LCR series circuit, and the power semiconductor element Q A and Q B The current flowing through the gate terminal oscillates, and the gate-source voltage V gsA and V gsB will vibrate.

[0081] In contrast, the gate driver 1 according to the first embodiment of the present disclosure can suppress the oscillation of the current flowing through the gate terminals of the power semiconductor elements, thereby suppressing the imbalance in voltage distribution during switching operations for each of the power semiconductor elements.

[0082] Here, the waveforms of the gate-source voltage when there is magnetic coupling of the gate lines in Patent Document 1 (Japanese Patent No. 4396036) and in the first embodiment of the present disclosure will be compared and examined using simulations shown in FIGS. 13 and 14.

[0083] Fig. 13 is a diagram showing a simulated waveform of the gate-source voltage in the invention described in Patent Document 1 (Japanese Patent No. 4396036), and Fig. 14 is a diagram showing a simulated waveform of the gate-source voltage in the gate driver according to the first embodiment of the present disclosure.

[0084] In the simulation, the power semiconductor element Q A The gate signal for the power semiconductor element Q B The gate signal for the power semiconductor element Q is output 250 ns earlier than the ON signal for the power semiconductor element Q. A and Q B The simulation was performed assuming that a load current of 325 A flows when a voltage of 1.8 kV is applied to a SiC-MOSFET with a breakdown voltage of 3.3 kV / 750 A. The load is an inductive load. In addition, in the simulation, the positive gate resistance R gAon and R gBon is set to 4.1Ω, and the negative gate resistance R gAoff and R gBoff is set to 6.1Ω, and the first resistor R Aon and R Bon is set to 36 Ω, and the second resistor R Aoff and R Boff is set to 34Ω, and the positive potential output section VF A and VF B The positive potential of the gate drive voltage output from the negative potential output unit VR is set to 17V. A and V.R. B The negative potential of the gate drive voltage output from is set to −11V.

[0085] As shown in FIG. 13, according to the invention described in Patent Document 1 (Japanese Patent No. 4396036), a power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsBAfter rising from -11V to 17V, the power semiconductor element Q A The gate-source voltage V gsA and power semiconductor element Q B The gate-source voltage V gsB The vibrations are out of phase with each other by 180 degrees.

[0086] As shown in FIG. 14, in the gate driver according to the first embodiment of the present disclosure, the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB After rising from -11V to 17V, the oscillation attenuates and after 25μs, the power semiconductor element Q A The gate-source voltage V gsA and power semiconductor element Q B The gate-source voltage V gsB In this way, according to the gate driver according to the first embodiment of the present disclosure, it is possible to suppress the oscillation of the gate-source voltage, and no difference occurs in the gate-source voltage at the start of switching, and the power semiconductor element Q A and Q B However, the imbalance in voltage distribution during the switching operation of the power semiconductor element Q A The gate-source voltage V gsA and power semiconductor element Q B The gate-source voltage V gsB It takes about 25 μs for the gate-source voltage V gsB In order to avoid switching during vibration, it is necessary to ensure a minimum on or off period of about 25 μs.

[0087] Second Embodiment

[0088] FIG. 15 is a circuit diagram showing a gate driver according to a second embodiment of the present disclosure.

[0089] The second embodiment of the present disclosure is a diode similar to the second diode D Aoff and D Boff and a second resistor R Aoff and RBoff is an abbreviation of

[0090] The gate driver 1 according to the second embodiment of the present disclosure includes gate drive voltage output units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, fourth wiring paths 21-A and 21-B, fifth wiring paths 22-A and 22-B, and sixth wiring paths 23-A and 23-B.

[0091] The gate drive voltage output units 11-A and 11-B, the gate lines 12-A and 12-B, and the magnetic coupling unit 13 are as described in the first embodiment.

[0092] The positive terminal of the gate drive voltage output unit 11-A is connected to a positive gate resistor R gAon is connected to the negative terminal, and the negative gate resistor R gAoff Similarly, a positive gate resistor R is connected to the positive terminal of the gate drive voltage output unit 11-B. gBon is connected to the negative terminal, and the negative gate resistor R gBoff is connected.

[0093] Power semiconductor element Q A The fourth wiring path 21-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A, and the fourth wiring path 21-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A. gAon and the gate line 12-A. The fourth wiring path 21-A is provided between the positive gate resistor R gAon and a cathode connected to the gate line 12-A, which is a wiring connected to the magnetic coupling portion 13. Aon Equipped with.

[0094] Power semiconductor element Q B The fourth wiring path 21-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B, and the fourth wiring path 21-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B. gBonThe fourth wiring path 21-B is provided between the gate line 12-B and the positive side gate resistor R gBon and a cathode connected to the gate line 12-B, which is a wiring connected to the magnetic coupling portion 13. Bon Equipped with.

[0095] Power semiconductor element Q A The fifth wiring path 22-A corresponding to the gate line 12-A is connected to the power semiconductor element Q A From the gate terminal of the power semiconductor element Q A is a path of current flowing toward the gate drive voltage output unit 11-A corresponding to the negative side gate resistance R gAoff and power semiconductor element Q A It is provided between.

[0096] Power semiconductor element Q B The fifth wiring path 22-B corresponding to the gate line 12-B is connected to the power semiconductor element Q B From the gate terminal of the power semiconductor element Q B is a path of current flowing toward the gate drive voltage output section 11-B corresponding to the negative side gate resistance R gBoff and power semiconductor element Q B It is provided between.

[0097] Power semiconductor element Q A The sixth wiring path 23-A corresponding to the fourth diode D Aon A fourth resistor R Aon Equipped with.

[0098] Power semiconductor element Q B The sixth wiring path 23-B corresponding to the fourth diode D Bon A fourth resistor R Bon Equipped with.

[0099] The ON operation of the gate driver 1 according to the second embodiment of the present disclosure is similar to the ON operation of the gate driver 1 according to the first embodiment described with reference to FIGS.

[0100] On the other hand, the off operation of the gate driver 1 according to the second embodiment of the present disclosure is performed by switching on the power semiconductor element Q without going through the magnetic coupling portion 13. A and Q B The second embodiment differs from the first embodiment in that a gate-source voltage is applied to the power semiconductor element Q. A The turning-off operation of the positive side switch SH of the gate drive voltage output unit 11-A is A is turned off and the negative switch SL A When this is turned on, a negative gate drive voltage (for example, 0 V or less) is output from the negative terminal of the gate drive voltage output unit 11-A, and the power semiconductor element Q A This is realized by applying the negative voltage output section VR of the gate drive voltage output section 11-A to the gate terminal of the A The negative potential of the gate drive voltage output from the power semiconductor element Q B Power semiconductor device Q A When a voltage is applied to the power semiconductor device Q A The gate-source voltage of the power semiconductor device Q starts to decrease from a positive potential to a negative potential. A Input capacitance Cgs A , negative gate resistance R gAoff , negative switch SL A , and the negative potential output unit VR A The negative gate resistor R gAoff is the negative switch SL in the gate drive voltage output unit 11-A A The value is set to a small value in order to make the switching speed as fast as possible. Since no current flows through the magnetic coupling portion 13, the current does not oscillate.

[0101] In the second embodiment of the present disclosure, the gate-source voltage does not oscillate during the OFF operation. Also, during the ON operation, as in the invention described in Patent Document 1 (Japanese Patent No. 4396036), the gate signal transmission time and the power semiconductor element Q A and Q BIf there is variation in the characteristics of the power semiconductor element Q A and Q B The voltage distribution between the elements will not be equal, and an excessive voltage will be applied to one of the elements. However, as can be seen from the waveforms of the drain-source voltage and drain current when a voltage imbalance occurs, shown in FIG. 10, the imbalance in the applied voltage when transitioning from the off state to the on state is a short-term phenomenon. Therefore, in the second embodiment of the present disclosure, the imbalance in the applied voltage when transitioning from the off state to the on state is permitted, and the voltage imbalance that occurs in the off state is suppressed by suppressing the oscillation of the gate-source voltage due to the excitation current of the magnetic coupling unit 13 that occurs when transitioning from the on state to the off state. Therefore, in the second embodiment of the present disclosure, the gate-source voltage V gsA and V gsB There is no need to ensure a minimum off period to avoid switching under oscillatory conditions.

[0102] Third Embodiment

[0103] FIG. 16 is a circuit diagram showing a gate driver according to a third embodiment of the present disclosure.

[0104] The gate drive device 1 according to the third embodiment of the present disclosure includes gate drive voltage output units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, first wiring paths 14-A and 14-B, second wiring paths 15-A and 15-B, and a third wiring path 16.

[0105] The gate drive voltage output units 11-A and 11-B, the gate lines 12-A and 12-B, and the magnetic coupling unit 13 are as described in the first embodiment.

[0106] The positive terminal of the gate drive voltage output unit 11-A is connected to a positive gate resistor R gAon is connected to the negative terminal, and the negative gate resistor R gAoff Similarly, a positive gate resistor R is connected to the positive terminal of the gate drive voltage output unit 11-B. gBon is connected to the negative terminal, and the negative gate resistor R gBoff is connected.

[0107] Power semiconductor element QA The first wiring path 14-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A, and the first wiring path 14-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A. gAon and the gate line 12-A.

[0108] Power semiconductor element Q B The first wiring path 14-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B, and the first wiring path 14-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B. gBon and the gate line 12-B.

[0109] Power semiconductor element Q A The second wiring path 15-A corresponding to the negative side gate resistance R gAoff and the gate line 12-A.

[0110] Power semiconductor element Q B The second wiring path 15-B corresponding to the negative side gate resistance R gBoff and the gate line 12-B.

[0111] The third wiring path 16 attenuates the excitation current generated in the magnetic coupling unit 13. The third wiring path 16 is provided in parallel with the magnetic coupling unit 13 for one of the two gate lines 12-A and 12-B magnetically coupled by the magnetic coupling unit 13. In the example shown in FIG. 16, the third wiring path 16 is provided in parallel with the magnetic coupling unit 13 for the gate line 12-A. The third wiring path 16 is connected to a third resistor R S and a third resistor R Sand a first switch SS that opens and closes the wiring connected to the gate line 12-A. Therefore, the series circuit is connected to the gate line 12-A so as to be in parallel with the magnetic coupling portion 13.

[0112] Next, the operation of the gate driver 1 according to the third embodiment of the present disclosure will be described.

[0113] Power semiconductor element Q A The ON operation of the positive side switch SH of the gate drive voltage output unit 11-A is A is turned on and the negative switch SL A When this is turned off, a positive gate drive voltage (for example, 17 V) is output from the positive terminal of the gate drive voltage output unit 11-A, and the power semiconductor element Q A When the first switch SS is in the OFF state, the positive potential output section VF of the gate drive voltage output section 11-A is applied to the gate terminal of the A The positive potential of the gate drive voltage output from the power semiconductor element Q B Power semiconductor device Q A When a voltage is applied to the power semiconductor device Q A The gate-source voltage of the positive side potential output section VF starts to rise from a negative potential to a positive potential. A , positive switch SH A , positive gate resistance R gAon , the magnetic coupling portion 13, and the power semiconductor element Q A Input capacitance Cgs A The current flows through the positive gate resistor R gAon is the positive switch SH in the gate drive voltage output unit 11-A A In order to make the switching speed of the power semiconductor element Q as fast as possible, the value is set to a small value, which may satisfy the resonance condition and cause the current to oscillate. A Input capacitance Cgs A The voltage of the positive side potential output part VF A When the first switch SS is turned on after the gate drive voltage output from the third resistor R rises to near the positive side potential, the excitation current that causes the current flowing through the magnetic coupling portion 13 to oscillate is STherefore, the current flows through the power semiconductor element Q A The oscillation of the gate-source voltage is suppressed.

[0114] Here, the effects of the third embodiment of the present disclosure will be described using a simulation.

[0115] FIG. 17 is a diagram showing a simulated waveform of the gate-source voltage in the gate driver according to the third embodiment of the present disclosure.

[0116] In the simulation, the power semiconductor element Q A When the gate signal for the power semiconductor element Q B The gate signal for the power semiconductor element Q is output 250 ns earlier than the ON signal for the power semiconductor element Q. A and Q B The simulation was performed assuming that a load current of 325 A flows when a voltage of 1.8 kV is applied to a SiC-MOSFET with a breakdown voltage of 3.3 kV / 750 A. The load is an inductive load. In addition, in the simulation, the positive gate resistance R gAon and R gBon is set to 4.1Ω, and the negative gate resistance R gAoff and R gBoff is set to 6.1Ω, and the positive potential output section VF A and VF B The positive potential of the gate drive voltage output from the negative potential output unit VR is set to 17V. A and V.R. A The negative potential of the gate drive voltage output from the first switch SS is set to −11 V. The first switch SS is connected to the gate-source voltage V gsA and V gsB is the positive potential output section VF A and positive potential output section VF B The first switch SS is turned on 8 μs after the rising edge of the on signal output from the gate-source voltage V gsA and V gsB is the negative voltage output section VR A and negative potential output section VR BThe ON operation is performed 8 μs after the falling edge of the OFF signal output from the MOSFET 11 and reaching the vicinity of each negative potential, and the OFF operation is performed 18 μs after that.

[0117] As shown in FIG. 17, a power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB After rising, when the first switch SS is turned on, the gate-source voltage V gsA and V gsB After the first switch SS is turned on, the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB As can be seen, according to the third embodiment of the present disclosure, the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB Since the oscillation of the power semiconductor element Q can be suppressed, no difference occurs in the gate voltage at the start of switching. A and Q B In the first embodiment of the present disclosure, as described with reference to FIG. 14, it is possible to avoid an increase in the imbalance in voltage sharing (imbalance in drain-source voltage) between the power semiconductor element Q A The gate-source voltage V gsA and power semiconductor element Q B The gate-source voltage V gsB In contrast, in the third embodiment of the present disclosure, it takes about 25 μs for the gate-source voltage V to become equal to the gate-source voltage V. In contrast, in the third embodiment of the present disclosure, it is possible to significantly shorten this time to about 12 μs from the start of the on or off operation. This time can be further shortened by advancing the timing at which the first switch SS is turned on. Therefore, in the third embodiment of the present disclosure, it is possible to further shorten the gate-source voltage V gsA and V gsB The minimum on or off period can be set short to avoid switching during oscillations.

[0118] FIG. 18 is a diagram illustrating the operations of the first switch, the positive-side switch, and the negative-side switch in the gate driver according to the third embodiment of the present disclosure.

[0119] In the third embodiment of the present disclosure, the first switch SS is turned on during a first fixed period of the period during which current flows through the first wiring paths 14-A and 14-B and is turned off during periods other than the first fixed period, and is turned on during a second fixed period of the period during which current flows through the second wiring paths 15-A and 15-B and is turned off during periods other than the second fixed period.

[0120] A signal for controlling the on / off of the first switch SS is igs and the positive switch SH A The signal to control the on / off of igH and the negative switch SL A The signal to control the on / off of igL The signals for controlling these switches are generated by the power conversion control unit 3 included in the processor provided in the power conversion device 100 shown in FIG. 6. In the example shown in FIG. 18, the signal S igs , signal S igH , signal S igL When the voltage is high, the switch is turned on, and when the voltage is low, the switch is turned off.

[0121] Power semiconductor element Q A and Q B During the ON operation of the signal S igH By setting the voltage to High, the positive switch S HA and S HB When the power supply is turned on, a current flows through the first wiring paths 14-A and 14-B, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB rises towards a positive voltage. When the voltage rises sufficiently, the signal S igS By setting the voltage to High, the first switch SS is turned on for a short time, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsBThe vibration of the power semiconductor element Q is rapidly damped. A and Q B The power semiconductor device Q completes the turning-off operation. A and Q B The gate-source voltage V gsA and V gsB After the vibration of the signal S igS By setting the voltage to low, the first switch SS is turned off, and the power semiconductor element Q A and Q B The ON operation of the switch is continued.

[0122] Power semiconductor element Q A and Q B In the off operation of the signal S igH By setting the voltage to low, the positive switch SH A and SH B is turned off, and then the signal S igL By setting the voltage to High, the negative switch SL A and SL B is turned on, current flows through the second wiring paths 15-A and 15-B, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB When the voltage drops sufficiently, the signal S igS By setting the voltage to High, the first switch SS is turned on for a short time, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB The vibration of the power semiconductor element Q is rapidly damped. A and Q B The power semiconductor device Q A and Q B The gate-source voltage V gsA and V gsB After the vibration of the signal S igS By setting the voltage to low, the first switch SS is turned off, and the power semiconductor element Q A and Q B The off operation continues.

[0123] According to the third embodiment of the present disclosure, in a gate drive device for a plurality of power semiconductor elements connected in series and a power conversion device including the same, even if there is variation in the transmission time of the gate signal or the characteristics of the power semiconductor elements, it is possible to suppress oscillations in the current flowing through the gate terminals of each of the power semiconductor elements, thereby suppressing imbalances in voltage distribution during switching operations for each of the power semiconductor elements.

[0124] <Fourth embodiment>

[0125] FIG. 19 is a circuit diagram showing a gate driver according to a fourth embodiment of the present disclosure.

[0126] The fourth embodiment of the present disclosure is a modification of the third embodiment. The third embodiment of the present disclosure is a modification of the third embodiment. igS Signal lines are required to transmit the signals. The increase in signal lines leads to complication of the circuit and processing from the viewpoint of controlling the power conversion device 100 configured using the gate driver 1. The fourth embodiment of the present disclosure realizes a circuit configuration that reduces the routing of signal lines for each switch.

[0127] The gate driver 1 according to the fourth embodiment of the present disclosure includes gate drive voltage output units 11-A and 11-B, gate lines 12-A and 12-B, a magnetic coupling unit 13, first wiring paths 14-A and 14-B, second wiring paths 15-A and 15-B, and third wiring paths 16-A1 and 16-A2.

[0128] The gate drive voltage output units 11-A and 11-B, the gate lines 12-A and 12-B, and the magnetic coupling unit 13 are as described in the first embodiment.

[0129] The positive terminal of the gate drive voltage output unit 11-A is connected to a positive gate resistor R gAon is connected to the negative terminal, and the negative gate resistor R gAoff Similarly, a positive gate resistor R is connected to the positive terminal of the gate drive voltage output unit 11-B. gBon is connected to the negative terminal, and the negative gate resistor R gBoff is connected.

[0130] Power semiconductor element QA The first wiring path 14-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A, and the first wiring path 14-A corresponding to the gate drive voltage output section 11-A is a path of current flowing from the gate drive voltage output section 11-A to the gate line 12-A corresponding to the gate drive voltage output section 11-A. gAon and the gate line 12-A. Therefore, on the first wiring path 14-A, the power semiconductor element Q A The positive potential output section VF of the gate drive voltage output section 11-A is connected to the gate terminal of A A positive switch SH that applies or cuts off the positive side potential of A and the positive switch SH A The positive gate resistor R gAon and will be established.

[0131] Power semiconductor element Q B The first wiring path 14-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B, and the first wiring path 14-B corresponding to the gate drive voltage output section 11-B is a path of current flowing from the gate drive voltage output section 11-B to the gate line 12-B corresponding to the gate drive voltage output section 11-B. gBon and the gate line 12-B. Therefore, on the first wiring path 14-B, the power semiconductor element Q B The positive potential output section VF of the gate drive voltage output section 11-B is connected to the gate terminal of B A positive switch SH that applies or cuts off the positive side potential of B and the positive switch SH B The positive gate resistor R gBon and will be established.

[0132] Power semiconductor element Q A The second wiring path 15-A corresponding to the negative side gate resistance R gAoff and the gate line 12-A. Therefore, the second wiring path 15-A is provided with a power semiconductor element Q corresponding to the second wiring path 15-A. A The negative potential output section VR of the gate drive voltage output section 11-A is connected to the gate terminal of AA negative switch SL that applies or cuts off a potential of 0 volts or less on the negative side of A and the negative switch SL A The negative gate resistor R gAoff and will be established.

[0133] Power semiconductor element Q B The second wiring path 15-B corresponding to the negative side gate resistance R gBoff and the gate line 12-B. Therefore, the second wiring path 15-B is provided with a power semiconductor element Q corresponding to the second wiring path 15-B. B The negative potential output section VR of the gate drive voltage output section 11-B is connected to the source terminal of the B A negative switch SL that applies or cuts off a potential of 0 volts or less on the negative side of B and the negative switch SL B The negative gate resistor R gBoff and will be established.

[0134] Power semiconductor element Q A The third wiring paths 16-A1 and 16-A2 corresponding to the above attenuate the excitation current generated in the magnetic coupling portion 13.

[0135] The third wiring path 16-A1 is connected to the power semiconductor element Q A The gate terminal of the positive switch SH A and the positive potential output section VF of the gate drive voltage output section 11-A. A A second switch S that opens and closes the wiring between the connection point with the positive electrode of pH The second switch S pH is a p-type MOSFET, which turns on when a negative voltage is applied to the gate terminal with respect to the source terminal.

[0136] The third wiring path 16-A2 is connected to the power semiconductor element Q A and the gate terminal of the negative switch SL A and the negative potential output section VR of the gate drive voltage output section 11-A. Aand a third switch S for opening and closing the wiring between the connection point with the negative electrode of nL The third switch S nL is an n-type MOSFET, which turns on when a positive voltage is applied to the gate terminal with respect to the source terminal.

[0137] Power semiconductor element Q A and Q B During the ON operation of the magnetic coupling part 13, the excitation current generated in the magnetic coupling part 13 flows through the positive gate resistance R gAon , positive switch SH A , and a second switch S pH The current flows through the power semiconductor element Q and is attenuated. A and Q B During the OFF operation, the excitation current generated in the magnetic coupling unit 13 flows through the magnetic coupling unit 13 and the third switch S nL , negative switch SL A , and the negative gate resistance R gAoff , and is attenuated by flowing through the path.

[0138] Second switch S pH The gate terminal of the first comparator C is connected to its source terminal via a resistor r9. omH The second switch S pH The source terminal of the positive potential output part VF A A second switch S pH The drain terminal of the power semiconductor element Q A The first comparator C is connected to the gate terminal of the omH is, for example, an open collector comparator.

[0139] First Comparator C omH The inverting input terminal (- terminal) of the power semiconductor element Q A The gate terminal and the negative potential output part VR A The voltage obtained by dividing the potential difference between the negative terminal of the first comparator C and the negative terminal of the second comparator C by resistors r5 and r6 is input. omH The non-inverting input terminal (+ terminal) of the positive side potential output section VF A and the positive side potential of the power semiconductor element Q AThe voltage obtained by dividing the potential difference between the source terminal of the first comparator C and the source terminal of the second comparator C by resistors r1 and r2 is input. omH The non-inverting input terminal (+ terminal) of the fourth switch S pCH The drain terminals of the fourth switch S pCH The source terminal of the positive potential output part VF A The positive side of the

[0140] A fifth switch S consisting of an n-type MOSFET nCH The gate terminal of igL As already explained, the signal S igL is the negative switch SL of the gate drive voltage output unit 11-A A The fifth switch S nCH The drain terminal of the fourth switch S pCH The gate terminals of the fourth switch S pCH The source terminal of 11 The gate terminal is connected via the signal S igL A fifth switch S controlled by nCH The fourth switch S pCH is controlled.

[0141] Third switch S nL The gate terminal of 10 via the power semiconductor element Q A and the source terminal of the second comparator C omL The third switch S nL The source terminal of the negative voltage output section VR A A third switch S nL The drain terminal of the power semiconductor element Q A The second comparator C is connected to the gate terminal of the omL is, for example, an open collector comparator.

[0142] Second Comparator C omL The inverting input terminal (- terminal) of the positive side potential output section VF A and the positive electrode side of the power semiconductor element QA The voltage obtained by dividing the potential difference between the gate terminal of the second comparator C and the gate terminal of the second comparator C by resistors r7 and r8 is input. omL The non-inverting input terminal (+ terminal) of the power semiconductor element Q A and the source terminal of the negative potential output section VR A The voltage obtained by dividing the potential difference between the negative terminal of the second comparator C and the negative terminal of the second comparator C by resistors r3 and r4 is input. omL The non-inverting input terminal (+ terminal) of the sixth switch S nCL The drain terminals of the sixth switch S nCL The source terminal of the negative voltage output section VR A The negative side of the

[0143] Sixth switch S nCL The gate terminal of igH As already explained, the signal S igH is the positive switch SH of the gate drive voltage output unit 11-A A This is a signal that controls the on / off of the

[0144] FIG. 20 is a diagram illustrating the operation of each switch in the gate driver according to the fourth embodiment of the present disclosure.

[0145] In the fourth embodiment of the present disclosure, the second switch S pH is the positive switch SH A performs an ON operation during the ON operation, and then the negative side switch S LA The third switch S nL is the negative switch S LA is turned on during the on-state, and then the positive side switch SH A The OFF operation is performed before the ON operation of the

[0146] In FIG. 20, the second switch S pH The signal to control the on / off of pH V of gs , the third switch S nL The signal to control the on / off of nL V of gs Positive switch SH AThe signal to control the on / off of igH and the negative switch SL A The signal to control the on / off of igL Signal S igH and S igL is generated by the power conversion control unit 3 included in the processor provided in the power conversion device 100 shown in FIG.

[0147] Power semiconductor element Q A and Q B During the ON operation of the signal S igH is set to a high voltage and the signal S igL By setting the voltage to low, the positive switch SH A and SH B is turned on and the negative switch SL A and SL B is turned off, and current flows through the first wiring paths 14-A and 14-B, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB When the potential at the connection point a between the resistors r5 and r6 becomes greater than the potential at the connection point x between the resistors r1 and r2, the first comparator C omH Output and power semiconductor element Q A The source terminals of the second switch S pH A negative voltage is applied between the gate and source terminals of the second switch S. pH is turned on, and the excitation current generated in the magnetic coupling portion 13 flows through the magnetic coupling portion 13 and the positive gate resistance R gAon , positive switch SH A , and a second switch S pH The current flows through the path and is attenuated.

[0148] Then, the signal S igH is set to a low voltage and the signal S igL By setting the voltage to High, the fifth switch S nCH is turned on and the fourth switch S pCH is turned on, the potential at the connection point a between the resistors r5 and r6 becomes smaller than the potential at the connection point x between the resistors r1 and r2, and the second switch SpH This fourth switch S pCH By the operation of the negative switch SL A and a second switch S pH This can prevent short circuits caused by the two power supplies being turned on at the same time.

[0149] Power semiconductor element Q A and Q B During the off operation of the signal S igH is set to a low voltage and the signal S igL By setting to High voltage, the positive switch SH A and SH B is turned off and the negative switch SL A and SL B is turned on, and current flows through the second wiring paths 15-A and 15-B, and the power semiconductor element Q A and Q B The gate-source voltage V gsA and V gsB When the potential at the connection point b between the resistors r7 and r8 becomes smaller than the potential at the connection point y between the resistors r3 and r4, the shorted second comparator C omL output and negative voltage output section VR A The connection with the negative terminal of the third switch S nL A positive voltage is applied between the gate and source terminals of the third switch S nL is turned on, and the excitation current generated in the magnetic coupling unit 13 flows through the magnetic coupling unit 13 and the third switch S nL , negative switch SL A , and the negative gate resistance R gAoff , flows through the path and is attenuated.

[0150] Then, the signal S igL is set to a low voltage and the signal S igH By setting the voltage to High, the fifth switch S nCH is turned on, the potential at the connection point b between the resistors r7 and r8 becomes greater than the potential at the connection point y between the resistors r3 and r4, and the second comparator C omL output and negative voltage output section VR A The negative side of the third switch S nLThis sixth switch S nCL By this operation, the positive switch SH A and a third switch S nL This can prevent short circuits caused by the two power supplies being turned on at the same time.

[0151] The first comparator C omH and a second comparator C omL The circuit section connected to the internal output terminal of each is an open collector circuit. When a voltage greater than that of the non-inverting input terminal (+ terminal) is input to the inverting input terminal (- terminal), the output terminal is connected to the negative side of the comparator power supply terminal, and when a voltage smaller than that of the non-inverting input terminal (+ terminal) is input to the inverting input terminal (- terminal), the output terminal is released from the connection to the negative side of the comparator power supply terminal.

[0152] According to the fourth embodiment of the present disclosure, in a gate driver for a plurality of power semiconductor devices connected in series and a power conversion device including the same, even if there are variations in the transmission time of gate signals or the characteristics of the power semiconductor devices, it is possible to suppress oscillations in the current flowing through the gate terminals of each of the power semiconductor devices and to suppress imbalances in voltage distribution during switching operations for each of the power semiconductor devices. In addition, it is possible to reduce the routing of signal lines for each switch.

[0153] Although the present disclosure has been described in detail above, the present disclosure is not limited to the individual embodiments described above. Various additions, substitutions, modifications, partial deletions, etc. are possible in these embodiments without departing from the gist of the present disclosure or the gist of the present disclosure derived from the content of the claims and their equivalents. For example, in the above-described embodiments, the order of each operation and the order of each process are shown as examples and are not limited to these. The same applies when numerical values ​​or mathematical expressions are used in the description of the above-described embodiments.

[0154] 1 Gate driving device 11-A, 11-B Gate driving voltage output unit 12-A, 12-B Gate line 13 Magnetic coupling unit 14-A, 14-B First wiring path 15-A, 15-B Second wiring path 16, 16-A1, 16-A2, 16-B1, 16-B2 Third wiring path 21-A, 21-B Fourth wiring path 22-A, 22-B Fifth wiring path 23-A, 23-B Sixth wiring path 30 Magnetic body 50 Arm 60 Leg 100 Power conversion device 200 DC power supply 300 Load Cgs A , Cgs B Input capacitance of power semiconductor device C omH First Comparator C omL Second Comparator D A , D B Feedback diode D Aon , D Bon First diode, fourth diode D Aoff , D Boff Second diode Q A , Q B Power semiconductor device R Aon , R Bon First resistor R Aoff , R Boff Second resistor R gAon , R gBon Positive gate resistance R gAoff , R gBoff Negative gate resistance R S Third resistor r1, r2, r3, r4, r5, r6, r7, r8, r9, r 10 , r 11 Resistance SH A , S.H. B Positive switch SL A , S.L. B Negative switch S nL Third switch S nCH Fifth switch S pCH Fourth switch S nCL 6th switch S PHSecond switch SS First switch T1, T2 terminal VF A , V.F. B Positive voltage output section VR A , V.R. B Positive potential output section

Claims

1. A gate driver for a plurality of power semiconductor devices connected in series, comprising: a gate drive voltage output section provided corresponding to each of the power semiconductor devices and configured to output a gate drive voltage; a gate line provided corresponding to each of the gate drive voltage output units and connected to a control terminal of the power semiconductor element corresponding to the gate drive voltage output unit; a magnetic coupling portion that magnetically couples each of the gate lines to each other; a first wiring path which is a path of a current flowing from the gate drive voltage output unit to the gate line corresponding to the gate drive voltage output unit; a second wiring path which is a path of a current flowing from the gate line connected to the first wiring path to the gate drive voltage output unit corresponding to the gate line; a third wiring path for attenuating an excitation current generated in the magnetic coupling portion; Equipped with the first wiring path includes a first diode having an anode connected to a wiring connected to a positive terminal of the gate drive voltage output unit and a cathode connected to a wiring connected to the magnetic coupling unit; The second wiring path includes a second diode having a cathode connected to a wiring connected to a negative terminal of the gate drive voltage output section and an anode connected to a wiring connected to the magnetic coupling section.

2. 2. The gate driver according to claim 1, wherein the third wiring path comprises a first resistor connected in parallel to the first diode and a second resistor connected in parallel to the second diode.

3. A gate drive device for a plurality of power semiconductor devices connected in series, comprising: a gate drive voltage output section provided corresponding to each of the power semiconductor devices and configured to output a gate drive voltage; a gate line provided corresponding to each of the gate drive voltage output units and connected to a control terminal of the power semiconductor element corresponding to the gate drive voltage output unit; a magnetic coupling portion that magnetically couples each of the gate lines to each other; a first wiring path which is a path of a current flowing from the gate drive voltage output unit to the gate line corresponding to the gate drive voltage output unit; a second wiring path which is a path of a current flowing from the gate line connected to the first wiring path to the gate drive voltage output unit corresponding to the gate line; a third wiring path for attenuating an excitation current generated in the magnetic coupling portion; Equipped with the third wiring path includes a series circuit including a third resistor and a first switch that opens and closes a wiring connected to the third resistor; A gate driver, wherein the series circuit is connected to one of the two gate lines magnetically coupled by the magnetic coupling portion so as to be in parallel with the magnetic coupling portion.

4. 4. The gate drive device according to claim 3, wherein the first switch is turned on during a first fixed period of a period during which a current flows through the first wiring path and is turned off except for the first fixed period, and is turned on during a second fixed period of a period during which a current flows through the second wiring path and is turned off except for the second fixed period.

5. A gate drive device for a plurality of power semiconductor devices connected in series, comprising: a gate drive voltage output section provided corresponding to each of the power semiconductor devices and configured to output a gate drive voltage; a gate line provided corresponding to each of the gate drive voltage output units and connected to a control terminal of the power semiconductor element corresponding to the gate drive voltage output unit; a magnetic coupling portion that magnetically couples each of the gate lines to each other; a first wiring path which is a path of a current flowing from the gate drive voltage output unit to the gate line corresponding to the gate drive voltage output unit; a second wiring path which is a path of a current flowing from the gate line connected to the first wiring path to the gate drive voltage output unit corresponding to the gate line; a third wiring path for attenuating an excitation current generated in the magnetic coupling portion; Equipped with the first wiring path includes a positive-side switch that applies or cuts off a positive-side potential of the gate drive voltage output unit to a control terminal of the power semiconductor device corresponding to the first wiring path, and a positive-side gate resistor that is connected in series to the positive-side switch; the second wiring path includes a negative-side switch that applies or cuts off a potential of 0 volts or less, which is a negative potential of the gate drive voltage output unit, to a control terminal of the power semiconductor element corresponding to the second wiring path, and a negative-side gate resistor that is connected in series to the negative-side switch; Each of the gate drive voltage output units includes a positive potential output unit that outputs a positive potential of the gate drive voltage, and a negative potential output unit that is connected in series to the positive potential output unit and outputs a negative potential of the gate drive voltage, The third wiring path is a second switch that opens and closes a wiring between a control terminal of the power semiconductor device and a connection point between the positive side switch and a positive electrode side of the positive side potential output unit; a third switch that opens and closes a wiring between a control terminal of the power semiconductor element and a connection point between the negative switch and a negative electrode side of the negative potential output unit.

6. the second switch performs an ON operation while the positive-side switch is performing an ON operation, and then performs an OFF operation before the negative-side switch starts to perform an ON operation; 6. The gate driver according to claim 5, wherein the third switch performs an ON operation while the negative-side switch is performing an ON operation, and thereafter performs an OFF operation before the positive-side switch starts to perform an ON operation.

7. 6. The gate driver according to claim 5, wherein the current-outflow terminal of the power semiconductor element is a source terminal, an emitter terminal, or a cathode terminal.

8. A gate driver for a plurality of power semiconductor devices connected in series, comprising: a gate drive voltage output section provided corresponding to each of the power semiconductor devices and configured to output a gate drive voltage; a gate line provided corresponding to each of the gate drive voltage output units and connected to a control terminal of the power semiconductor element corresponding to the gate drive voltage output unit; a magnetic coupling portion that magnetically couples each of the gate lines to each other; a fourth wiring path which is a path of a current flowing from the gate drive voltage output unit to the gate line corresponding to the gate drive voltage output unit; a fifth wiring path which is a path of a current flowing from a control terminal of the power semiconductor element to which the gate line is connected toward the gate drive voltage output section corresponding to the power semiconductor element; a sixth wiring path for attenuating an excitation current generated in the magnetic coupling portion; A gate drive device comprising:

9. the fourth wiring path includes a fourth diode having an anode connected to a wiring connected to a positive terminal of the gate drive voltage output unit and a cathode connected to a wiring connected to the magnetic coupling unit; 9. The gate driver of claim 8, wherein the sixth wiring path comprises a fourth resistor connected in parallel with the fourth diode.

10. 10. The gate driver according to claim 1, wherein the control terminal of the power semiconductor element is a gate terminal or a base terminal.

11. A gate drive device according to any one of claims 1 to 9; a power conversion circuit section having an arm on which a plurality of the power semiconductor elements connected in series are provided, the power conversion circuit section performing a power conversion operation in response to an on / off operation of the power semiconductor elements; a power conversion control unit that controls a power conversion operation of the power conversion circuit unit; A power conversion device comprising:

12. A power conversion device as described in claim 11, wherein the control terminal of the power semiconductor element is a gate terminal or a base terminal.