Semiconductor device

Abstract

This semiconductor device comprises an n-type semiconductor layer, a plurality of trenches, an insulating layer, a third electrode, and a p-type well region. The plurality of trenches extend in a first direction orthogonal to the thickness direction of the semiconductor layer, and are separated in a second direction orthogonal to the first direction. The insulating layer is provided so as to cover the trenches. The third electrode is formed within the insulating layer and is in contact with the first electrode. The p-type well region is formed in the surface of the semiconductor layer. The well region extends in a direction intersecting the first direction and is one of a plurality of well regions separated from each other in the first direction. The surface of the semiconductor layer forms ohmic contact with the first electrode on the well surface of the well region. The surface of the semiconductor layer forms Schottky contact with the first electrode on exposed surfaces positioned between the plurality of well surfaces.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor device is known that includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, an anode electrode formed on the semiconductor layer, and a cathode electrode formed on the semiconductor substrate on the side opposite to the semiconductor layer (see, for example, Patent Document 1).

[0003] JP 2012-124329 A

[0004] Meanwhile, there is a demand for a technology for adjusting the characteristics of reducing the forward voltage drop and the characteristics of suppressing the leakage current in semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first conductivity type semiconductor substrate having a substrate surface and a substrate back surface opposite to the substrate surface, a first conductivity type semiconductor layer formed on the substrate surface and having a surface, a first electrode formed on the surface of the semiconductor layer, a second electrode formed on the substrate back surface, a plurality of trenches extending from the surface of the semiconductor layer in a thickness direction of the semiconductor layer and in a first direction orthogonal to the thickness direction of the semiconductor layer, and spaced apart in a second direction orthogonal to the thickness direction of the semiconductor layer and the first direction, an insulating layer provided so as to cover bottom walls and side walls of each of the trenches, and a third electrode formed in the insulating layer and in contact with the first electrode. and a well region of a second conductivity type formed in a portion of the surface of the semiconductor layer, the well region extending in a direction intersecting the first direction and being one of a plurality of well regions spaced apart in the first direction, the well region having a well surface forming a portion of the surface of the semiconductor layer and a well end contacting the insulating layer of the trench, the well surface being one of a plurality of well surfaces, the surface of the semiconductor layer forming an ohmic contact with the first electrode at the well surface, and the surface of the semiconductor layer forming a Schottky contact with the first electrode at an exposed surface located between the plurality of well surfaces.

[0006] According to the semiconductor device of the present disclosure, the characteristics of reducing the forward voltage drop and the characteristics of suppressing the leakage current can be easily adjusted.

[0007] FIG. 1 is a schematic plan view of a semiconductor device of one embodiment. FIG. 2 is a schematic plan view of a semiconductor layer of the semiconductor device of FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 2. FIG. 4 is a schematic cross-sectional view enlarging the periphery of the trench in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 2. FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. 2. FIG. 7 is a schematic cross-sectional perspective view showing the surface of the semiconductor layer and the shape of the trench in the semiconductor device of FIG. 1. FIG. 8 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device. FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 8. FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 9. FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 10. FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 11. FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 12. FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 13. FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 14. Fig. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to Fig. 15. Fig. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to Fig. 16. Fig. 18 is a schematic plan view of a semiconductor layer showing the arrangement of well regions in a modified example.

[0008] Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] (Schematic Configuration of Semiconductor Device) The schematic configuration of a semiconductor device 10 of this embodiment will be described with reference to Figures 1 to 4. Figure 1 shows a schematic planar structure of the semiconductor device 10. Figure 2 shows a schematic planar structure of a semiconductor chip 11 (described later) of the semiconductor device 10 of Figure 1. Figure 3 shows a schematic cross-sectional structure taken along line F3-F3 in Figure 2. Figure 4 is an enlarged cross-sectional view of the range indicated by arrow F4 in Figure 3.

[0011] In order to facilitate understanding, a surface protection layer 70 (described later) is indicated by cross-hatched lines in Fig. 1. In order to facilitate understanding, a surface insulating layer 60, an anode electrode 42, and the surface protection layer 70 (described later) are omitted from Fig. 2, and an isolation trench 24 and a trench 25 (described later) are indicated by cross-hatched lines. In Fig. 3 and Fig. 4, for the sake of convenience, some of the hatched lines in the semiconductor device 10 are omitted.

[0012] Furthermore, the term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 1. For convenience, in the semiconductor device 10 shown in Fig. 3, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless explicitly stated otherwise, "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0013] The semiconductor device 10 is a semiconductor rectifier. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor chip 11. The semiconductor chip 11 is formed of a material containing, for example, silicon (Si). Note that the material constituting the semiconductor chip 11 is not limited to Si and is arbitrary. In this embodiment, the semiconductor chip 11 is formed in a flat plate shape. The semiconductor chip 11 includes a chip front surface 11s and a chip back surface 11r (see FIG. 3). Furthermore, the semiconductor chip 11 includes first to fourth chip side surfaces 12A to 12D that connect the chip front surface 11s and the chip back surface 11r.

[0014] The shape of the semiconductor chip 11 in a plan view, in other words, the shape of the chip surface 11s and the chip back surface 11r in a plan view, is rectangular. The first chip side surface 12A and the second chip side surface 12B extend along the X-axis direction, and the third chip side surface 12C and the fourth chip side surface 12D extend along the Y-axis direction. The first chip side surface 12A and the second chip side surface 12B are arranged to face the Y-axis direction, and the third chip side surface 12C and the fourth chip side surface 12D are arranged to face the X-axis direction.

[0015] 3, the semiconductor device 10 includes a semiconductor substrate 21 formed on the semiconductor chip 11 near the chip back surface 11r. The semiconductor substrate 21 has a substrate front surface 21s and a substrate back surface 21r opposite the substrate front surface 21s. The substrate front surface 21s faces the same side as the chip front surface 11s, and the substrate back surface 21r faces the same side as the chip back surface 11r.

[0016] The semiconductor substrate 21 has an electrical resistivity of, for example, 0.5 mΩ·cm or more and 3 mΩ·cm or less. １８ cm －３ 1x10 or more ２１ cm －３ The semiconductor substrate 21 has an n-type impurity concentration of 0.1 to 1.0 μm. The semiconductor substrate 21 has a thickness of 5 μm or more and 300 μm or less. For example, the thickness of the semiconductor substrate 21 is 50 μm or more and 300 μm or less. In this embodiment, the semiconductor substrate 21 is formed of an n-type semiconductor substrate. For example, a Si substrate is used as the semiconductor substrate 21. Note that the constituent material of the semiconductor substrate 21 is not limited to Si and may be any material. For example, the constituent material of the semiconductor substrate 21 may be silicon carbide (SiC).

[0017] The semiconductor device 10 includes a cathode electrode 41 formed on the substrate back surface 21r of the semiconductor substrate 21. The cathode electrode 41 is formed over the entire substrate back surface 21r. The cathode electrode 41 is electrically connected to the semiconductor substrate 21. The cathode electrode 41 forms ohmic contact with the semiconductor substrate 21 (substrate back surface 21r). The cathode electrode 41 forms the chip back surface 11r. Here, in this embodiment, the cathode electrode 41 corresponds to the "second electrode."

[0018] The cathode electrode 41 has a laminated structure of a plurality of metal films. In one example, the cathode electrode 41 has a structure in which a first metal film, a second metal film, and a third metal film are laminated in this order from the rear surface 21r of the substrate.

[0019] The first metal film is formed, for example, from a material containing titanium (Ti). The first metal film has a thickness of, for example, 500 Å or more and 2000 Å or less. The second metal film is formed, for example, from a material containing nickel (Ni). The second metal film is thicker than the first metal film. The second metal film has a thickness of, for example, 2000 Å or more and 6000 Å or less. The third metal film is formed, for example, from a material containing gold (Au). The third metal film is thinner than the second metal film. The third metal film is thinner than the first metal film. The third metal film has a thickness of, for example, 100 Å or more and 1000 Å or less. Examples of combinations of the first metal film, second metal film, and third metal film (first metal film / second metal film / third metal film) include Ti / Ni / Au and Ti / Ni / silver (Ag). The cathode electrode 41 may have a fourth metal film interposed between the second metal film and the third metal film. The fourth metal film is formed of a material containing, for example, palladium (Pd). Alternatively, the cathode electrode 41 may have the first metal film and the second metal film, and the third metal film may be omitted. In this case, an example of the combination of the first metal film and the second metal film (first metal film / second metal film) is Ti / Ni. Note that the materials forming each of the metal films of the cathode electrode 41 are not limited to the above materials.

[0020] The semiconductor device 10 includes an n-type buffer layer 22 formed on a semiconductor substrate 21, and an n-type drift layer 23 formed on the buffer layer 22. The drift layer 23 is formed on the semiconductor substrate 21 via the buffer layer 22. Therefore, it can also be said that the drift layer 23 is formed on the semiconductor substrate 21. Here, in this embodiment, the drift layer 23 corresponds to the "semiconductor layer," and the n-type corresponds to the "first conductivity type."

[0021] The buffer layer 22 is in contact with the substrate surface 21s of the semiconductor substrate 21. The buffer layer 22 is formed over the entire substrate surface 21s. The buffer layer 22 has a concentration gradient in which the n-type impurity concentration decreases upward from the semiconductor substrate 21. The buffer layer 22 has a thickness of 1 μm or more and 10 μm or less. In this embodiment, the buffer layer 22 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0022] The drift layer 23 is in contact with the buffer layer 22. The drift layer 23 has a surface 23s facing the same side as the chip surface 11s. In this embodiment, the surface 23s of the drift layer 23 forms the chip surface 11s. The drift layer 23 is formed over the entire buffer layer 22 in a plan view. The drift layer 23 has an n-type impurity concentration lower than that of the semiconductor substrate 21. The n-type impurity concentration of the drift layer 23 is, for example, 1×10 １５ cm －３ 1x10 or more １６ cm －３ The drift layer 23 has an electrical resistivity of, for example, 1.0 Ω·cm or more and 4.0 Ω·cm or less. The drift layer 23 has a thickness of 6 μm or more and 20 μm or less. In this embodiment, the drift layer 23 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0023] As shown in FIGS. 1 and 2 , the semiconductor device 10 includes an isolation trench 24 extending in the Z-axis direction from the surface 23s of the drift layer 23. The isolation trench 24 is located inward from the first to fourth chip side surfaces 12A to 12D in a plan view. The isolation trench 24 is formed in a ring shape in a plan view. In this embodiment, the shape of the isolation trench 24 in a plan view is a substantially rectangular frame shape. The isolation trench 24 partitions an active region 51, which is an area inside the isolation trench 24, and a peripheral region 52, which is an area outside the isolation trench 24 in a plan view. The shape of the isolation trench 24 in a plan view can be changed as desired.

[0024] The active region 51 is a region where a diode is formed. The active region 51 is formed in a rectangular shape in a plan view. The peripheral region 52 is a region where no diode is formed. In the peripheral region 52, for example, a termination structure for improving breakdown voltage is formed. The peripheral region 52 is formed in a ring shape surrounding the active region 51 in a plan view.

[0025] 3 , the isolation trench 24 includes a pair of sidewalls 24a and a bottom wall 24b connecting the pair of sidewalls 24a. The isolation trench 24 is provided in the drift layer 23. That is, the bottom wall 24b of the isolation trench 24 is located above the buffer layer 22. In this embodiment, the bottom wall 24b is formed in a curved shape that is convex toward the buffer layer 22. The shape of the bottom wall 24b can be changed as desired.

[0026] The depth of the isolation trench 24 may be, for example, 1 μm or more and 5 μm or less. The depth of the isolation trench 24 may be, for example, 1.5 μm or more and 3 μm or less. The isolation trench 24 is formed at a distance of 1 μm or more (preferably 3 μm or more) from the bottom of the drift layer 23 (buffer layer 22). The width of the isolation trench 24 may be, for example, 0.5 μm or more and 3 μm or less. The width of the isolation trench 24 may be, for example, 0.8 μm or more and 1.5 μm or less. Here, the width of the isolation trench 24 is the size in a direction perpendicular to the direction in which the isolation trench 24 extends in a plan view.

[0027] The semiconductor device 10 includes an isolation insulating film 31 and an isolation electrode 32 provided in the isolation trench 24. The isolation insulating film 31 is formed along a pair of side walls 24a and a bottom wall 24b of the isolation trench 24. The isolation insulating film 31 is made of, for example, silicon oxide (SiO ２ ) is formed. The isolation insulating film 31 has a thickness of, for example, 0.05 μm or more and 0.5 μm or less. The thickness of the isolation insulating film 31 may be 0.1 μm or more and 0.4 μm or less. The isolation insulating film 31 defines a recess space in the isolation trench 24.

[0028] The isolation electrode 32 is formed to fill the recess space in the isolation trench 24. That is, the isolation electrode 32 is embedded in the isolation trench 24 with the isolation insulating film 31 sandwiched therebetween. The isolation electrode 32 includes, for example, conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon.

[0029] As shown in FIGS. 1 to 3 , a plurality of trenches 25 (five in this embodiment) are formed in the active region 51. That is, the semiconductor device 10 includes the trenches 25. Each trench 25 extends from the surface 23s of the drift layer 23 in the Z-axis direction and in the Y-axis direction. In this embodiment, each trench 25 has a linear shape extending in the Y-axis direction in a plan view. The trenches 25 are formed spaced apart from one another in the X-axis direction. In other words, the trenches 25 are formed in a striped pattern in a plan view. Each trench 25 communicates with the isolation trench 24 in the Y-axis direction. Here, in this embodiment, the Y-axis direction corresponds to the "first direction," and the X-axis direction corresponds to the "second direction." Note that the trenches 25 and the isolation trench 24 may be spaced apart from one another. That is, the trenches 25 and the isolation trench 24 do not necessarily need to communicate with one another.

[0030] 3 and 4 , the trench 25 includes a pair of sidewalls 25a and a bottom wall 25b connecting the pair of sidewalls 25a. The trench 25 is provided in the drift layer 23. That is, the bottom wall 25b of the trench 25 is located above the buffer layer 22. In this embodiment, the bottom wall 25b is formed in a curved shape that is convex toward the buffer layer 22. The shape of the bottom wall 25b can be changed as desired.

[0031] In this embodiment, the depth dimension HT of the trench 25 is shallower than the depth of the isolation trench 24. In other words, the depth of the isolation trench 24 is deeper than the depth dimension HT of the trench 25. Note that the depth dimension HT of the trench 25 may be equal to the depth of the isolation trench 24.

[0032] In one example, the depth dimension HT of trench 25 may be, for example, 1 μm or more and 5 μm or less. The depth dimension HT of trench 25 may be, for example, 0.8 μm or more and 2 μm or less. Trench 25 is formed at a distance of 1 μm or more (preferably 3 μm or more) from the bottom of drift layer 23 (buffer layer 22).

[0033] The width L1 of the trench 25 is smaller than the width of the isolation trench 24. In other words, the width of the isolation trench 24 is larger than the width L1 of the trench 25. In one example, the width L1 of the trench 25 may be, for example, 0.1 μm or more and 2 μm or less. The width L1 of the trench 25 may be, for example, 0.4 μm or more and 1.2 μm or less. Here, the width L1 of the trench 25 is the size in a direction perpendicular to the direction in which the trench 25 extends in a planar view. In this embodiment, since the trench 25 extends in the Y-axis direction in a planar view, the width of the trench 25 is the size in the X-axis direction of the trench 25 in a planar view (the second direction length).

[0034] The distance D1 between two trenches 25 adjacent in the X-axis direction may be, for example, 1 μm or more and 5 μm or less. The distance D1 between two trenches 25 adjacent in the X-axis direction may be 2 μm or more and 4 μm or less. Furthermore, as shown in FIG. 3 , the distance between the trenches 25 located at both ends in the X-axis direction and the isolation trench 24 adjacent to the trench 25 in the X-axis direction is approximately equal to the distance D1 between the two trenches 25 adjacent in the X-axis direction.

[0035] The semiconductor device 10 includes an insulating layer 33 and a buried electrode 34 provided in each trench 25. In this embodiment, the buried electrode 34 corresponds to a "third electrode." As shown in FIG. 4 , the insulating layer 33 is formed along a pair of sidewalls 25 a and a bottom wall 25 b of the trench 25. Specifically, the insulating layer 33 has two first portions 33 a formed along the sidewalls 25 a of the trench 25 and a second portion 33 b formed along the bottom wall 25 b of the trench 25. The first portions 33 a are in contact with the drift layer 23 and a well edge 80 e of a well region 80 (described later). The second portion 33 b is located between the two first portions 33 a and is in contact with the drift layer 23.

[0036] The insulating layer 33 is connected to the isolation insulating film 31 at the portion of the trench 25 that communicates with the isolation trench 24. The insulating layer 33 is made of, for example, SiO ２ The insulating layer 33 has a thickness of, for example, 0.05 μm or more and 0.5 μm or less. The thickness of the insulating layer 33 may be 0.1 μm or more and 0.4 μm or less. The thickness of the isolation insulating film 31 is, for example, equal to or greater than the thickness of the insulating layer 33. The insulating layer 33 defines a recess space within the trench 25.

[0037] The buried electrode 34 is formed to fill the recess space in the trench 25. That is, the buried electrode 34 is buried in the trench 25 with the insulating layer 33 sandwiched therebetween. The buried electrode 34 is connected to the isolation electrode 32 at the portion of the trench 25 that communicates with the isolation trench 24. The buried electrode 34 includes, for example, conductive polysilicon. Note that the conductive polysilicon may be n-type polysilicon or p-type polysilicon.

[0038] 1 to 3, the semiconductor device 10 includes a p-type peripheral well region 26 formed in the surface layer portion of the drift layer 23 along the isolation trench 24 in the peripheral region 52. Here, in this embodiment, the p-type corresponds to the "second conductivity type."

[0039] The peripheral well region 26 is formed on the surface 23s of the drift layer 23. As shown in FIG. 2, the peripheral well region 26 is formed in a ring shape in a plan view. The peripheral well region 26 is an example of a termination structure, and is formed in an electrically floating state. In other words, the peripheral well region 26 is formed electrically isolated from the isolation electrode 32 and the buried electrode 34. The peripheral well region 26 has a size of 1×10 １７ cm －３ 1x10 or more １９ cm －３ 3, the p-type impurity concentration of the peripheral well region 26 has a concentration gradient that gradually decreases from the surface 23s of the drift layer 23 toward the bottom (buffer layer 22) of the drift layer 23.

[0040] 2, the peripheral well region 26 is provided so as to be adjacent to the isolation trench 24 in a plan view. The peripheral well region 26 contacts the sidewall 24a of the isolation trench 24.

[0041] As shown in FIG. 3 , in this embodiment, the thickness of the peripheral well region 26 is thicker than the depth of the isolation trench 24. The thickness of the peripheral well region 26 is thicker than the depth of the trench 25. The bottom of the peripheral well region 26 is formed with a gap between the bottom of the drift layer 23 (the buffer layer 22). In one example, the thickness of the peripheral well region 26 may be 1 μm or more and 5 μm or less. The thickness of the peripheral well region 26 can be changed as desired. In one example, the peripheral well region 26 may be thinner than the depth of the isolation trench 24. Furthermore, the peripheral well region 26 may be formed so as to cover a portion of the bottom wall 24 b of the isolation trench 24.

[0042] The width of the peripheral well region 26 is greater than the width of the isolation trench 24. The width of the peripheral well region 26 is greater than the width L1 of the trench 25. The width of the peripheral well region 26 is greater than the thickness of the peripheral well region 26. In one example, the width of the peripheral well region 26 may be 2 μm or more and 20 μm or less. In another example, the width of the peripheral well region 26 may be 5 μm or more and 15 μm or less. Here, the width of the peripheral well region 26 can be defined by the size in a direction perpendicular to the direction in which the peripheral well region 26 extends in a plan view.

[0043] 1 and 3, the semiconductor device 10 includes a surface insulating layer 60 that covers the surface 23s of the drift layer 23 in the peripheral region 52. The surface insulating layer 60 is formed in a ring shape corresponding to the shape of the peripheral region 52 in a plan view. That is, as shown in FIG. 3, the surface insulating layer 60 has a through hole 60A that exposes the active region 51. The inner peripheral edge of the surface insulating layer 60 is formed at a position that overlaps with a part of the isolation electrode 32 in a plan view. That is, the surface insulating layer 60 covers a part of the upper surface of the isolation electrode 32. The surface insulating layer 60 covers the entire peripheral well region 26. This insulates the peripheral well region 26 from the outside.

[0044] The surface insulating layer 60 has a laminated structure including a first insulating film 61 and a second insulating film 62. The first insulating film 61 is in contact with the surface 23s of the drift layer 23. The first insulating film 61 is made of, for example, SiO ２ In one example, the first insulating film 61 is formed of a field oxide film containing an oxide of the drift layer 23.

[0045] The second insulating film 62 is formed on the first insulating film 61. The second insulating film 62 includes a silicon oxide film having properties different from those of the first insulating film 61. In one example, the second insulating film 62 may include at least one of a PSG (Phosphorus Silicate Glass) film and a USG (Undoped Silicate Glass) film. PSG is a silicon oxide film containing P, and the USG film is a silicon oxide film without doping. Alternatively, the second insulating film 62 may have a stacked structure of a PSG film and a USG film.

[0046] The first insulating film 61 has a thickness of 1000 Å or more and 5000 Å or less. The thickness of the first insulating film 61 may be 1500 Å or more and 3500 Å or less. The second insulating film 62 has a thickness of 1000 Å or more and 6000 Å or less. The thickness of the second insulating film 62 may be 2500 Å or more and 4500 Å or less.

[0047] The semiconductor device 10 includes an anode electrode 42 formed on the surface 23s of the drift layer 23. The anode electrode 42 corresponds to a "first electrode." The anode electrode 42 is formed across both the active region 51 and the peripheral region 52. More specifically, the anode electrode 42 is formed across the entire active region 51. Meanwhile, as shown in FIG. 1 , the anode electrode 42 is formed in the peripheral region 52, more inward than the first to fourth chip side surfaces 12A to 12D, in a plan view. In other words, the anode electrode 42 is formed on the inner periphery of the peripheral region 52. The anode electrode 42 has a rectangular shape in a plan view.

[0048] 3, the anode electrode 42 is in contact with both the separated electrode 32 and the buried electrode 34. More specifically, the anode electrode 42 forms ohmic contact with both the separated electrode 32 and the buried electrode 34. As a result, the anode electrode 42 is electrically connected to both the separated electrode 32 and the buried electrode 34.

[0049] In the peripheral region 52, the anode electrode 42 is formed on the surface insulating layer 60. Therefore, in the peripheral region 52, the anode electrode 42 is insulated from the drift layer 23 and the peripheral well region 26. In this embodiment, the peripheral edge of the anode electrode 42 is located outward from the peripheral well region 26.

[0050] As shown in FIG. 4 , the anode electrode 42 has a layered structure including, for example, a first electrode film 42A, a second electrode film 42B, and a third electrode film 42C. The first electrode film 42A is in contact with the surface 23s of the drift layer 23. The second electrode film 42B is formed on the first electrode film 42A, and the third electrode film 42C is formed on the second electrode film 42B. The second electrode film 42B is thicker than the first electrode film 42A. The third electrode film 42C is thicker than the first electrode film 42A and the second electrode film 42B. The first electrode film 42A may have a thickness of, for example, 50 Å or more and 1000 Å or less. The first electrode film 42A may have a thickness of, for example, 250 Å or more and 500 Å or less. The second electrode film 42B may have a thickness of, for example, 500 Å or more and 5000 Å or less. The second electrode film 42B may have a thickness of, for example, 1500 Å or more and 4500 Å or less. The thickness of the third electrode film 42C may be 0.5 μm or more and 10 μm or less, or 2.5 μm or more and 7.5 μm or less.

[0051] The electrode material of the first electrode film 42A may include at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au). The first electrode film 42A may be formed of a single film or a stacked structure of multiple films. The multiple films may be formed of different electrode materials. In one example, the first electrode film 42A may include, for example, Mo.

[0052] The second electrode film 42B is a metal barrier film and is formed, for example, of a Ti-based metal film. The electrode material of the second electrode film 42B may contain at least one of Ti and titanium nitride (TiN). The second electrode film 42B may be formed of a single film formed of Ti or TiN. The second electrode film 42B may be formed of a stacked structure of Ti films or TiN films. In this embodiment, the second electrode film 42B is formed of a material containing TiN.

[0053] The third electrode film 42C constitutes an electrode pad and is formed, for example, from a material containing at least one of Cu and Al. The electrode material of the third electrode film 42C may contain at least one of Cu, Al, an aluminum-copper alloy (AlCu), an aluminum-silicon alloy (AlSi), and an aluminum-silicon-copper alloy (AlSiCu). In this embodiment, the third electrode film 42C is formed from a material containing Al.

[0054] The semiconductor device 10 includes a surface protection layer 70 formed on the surface insulating layer 60 so as to cover the anode electrode 42. As shown in FIG. 1, the outer peripheral edge of the surface protection layer 70 is formed at a position spaced apart from the first to fourth chip side surfaces 12A to 12D. As shown in FIG. 3, the surface protection layer 70 is formed continuously from the top surface to the side surface of the anode electrode 42. The surface protection layer 70 is formed outward beyond the anode electrode 42. The surface protection layer 70 has an opening 71 that exposes the center of the anode electrode 42. The portion of the anode electrode 42 exposed through the opening 71 forms an electrode pad to which a connecting member such as a wire is bonded.

[0055] The surface protective layer 70 has a single-layer structure formed of an inorganic insulating film. The surface protective layer 70 is formed of an insulator different from the surface insulating layer 60. The surface protective layer 70 may contain at least one of SiN and silicon oxynitride (SiON), for example. The thickness of the surface protective layer 70 may be, for example, 0.2 μm or more and 1.5 μm or less. The thickness of the surface protective layer 70 may be, for example, 0.6 μm or more and 1.2 μm or less. The surface protective layer 70 may also be formed of an organic insulating film such as polyimide.

[0056] 2, the semiconductor device 10 includes a p-type well region 80 formed in a surface portion of the drift layer 23 in the active region 51. Here, in this embodiment, the p-type corresponds to the "second conductivity type."

[0057] The well region 80 will be described in detail below with reference to FIGS. 1 to 7. FIG. 5 shows a schematic cross-sectional structure taken along line F5-F5 in FIG. 2. FIG. 6 shows a schematic cross-sectional structure taken along line F6-F6 in FIG. 2. FIG. 7 is a perspective cross-sectional view of the area indicated by arrow F6 in FIG. 2. In FIGS. 1 to 7, the well region 80 is indicated by dot hatching for ease of understanding. In FIGS. 4 to 7, some hatching lines of the semiconductor device 10 are omitted for convenience. In FIG. 7, the lower part of the drift layer 23 and the upper part of the anode electrode 42 are omitted for ease of understanding.

[0058] As shown in FIGS. 2 and 3 , the well region 80 is formed in the surface 23s of the drift layer 23 located in the active region 51. The well region 80 is formed in a region between two trenches 25 adjacent to each other in the X-axis direction in the drift layer 23 (hereinafter referred to as an inter-trench region 27). The well region 80 may also be formed in a region between an isolation trench 24 and a trench 25 adjacent to each other in the X-axis direction in the drift layer 23 (hereinafter referred to as a trench side region 28). In the example shown in FIGS. 2 and 3 , the well region 80 is provided in both the inter-trench region 27 and the trench side region 28. The well region 80 provided in the trench side region 28 may be omitted. The well region 80 may also be provided in only one of the two trench side regions 28.

[0059] 2, in this embodiment, a plurality of well regions 80 are formed, extending in the X-axis direction and spaced apart in the Y-axis direction, in the inter-trench region 27 and the trench side region 28. In one example, a plurality of well regions 80 are formed, spaced apart at equal intervals in the Y-axis direction.

[0060] The well regions 80 formed in each of the inter-trench region 27 and the trench side region 28 are arranged so as to be aligned in a direction (X-axis direction) perpendicular to the Y-axis direction across the trench 25. Therefore, the well regions 80 extend in the X-axis direction across the trench 25. In other words, the multiple well regions 80 spaced apart in the Y-axis direction are arranged in stripes that extend in the X-axis direction across the trench 25 and are spaced apart in the Y-axis direction.

[0061] The well region 80 is formed across the entire inter-trench region 27 in the X-axis direction. Alternatively, the well region 80 may be formed across the entire inter-trench region 27 and trench side region 28 in the X-axis direction. The direction in which the well regions 80 are arranged across the trenches 25 is not limited to a direction perpendicular to the Y-axis direction (X-axis direction). For example, the direction in which the well regions 80 are arranged across the trenches 25 may be a direction intersecting the X-axis and Y-axis directions.

[0062] 4 , the well region 80 has a well surface 80s exposed on the surface 23s of the drift layer 23. The well surface 80s constitutes a part of the surface 23s of the drift layer 23. The well surface 80s contacts the anode electrode 42 in the active region 51. More specifically, the well surface 80s forms ohmic contact with the anode electrode 42 in the active region 51.

[0063] The well region 80 has well ends 80e located at both ends in the X-axis direction, which is the direction in which the well region 80 extends. Each well end 80e of the well region 80 located in the inter-trench region 27 is in contact with the insulating layer 33 of the trench 25. Therefore, the well region 80 located in the inter-trench region 27 is in contact with each of the two trenches 25 that sandwich the well region 80 in the X-axis direction. The well end 80e of the well region 80 located in the trench side region 28 is in contact with the isolation insulating film 31 of the isolation trench 24 and the insulating layer 33 of the trench 25. Therefore, the well region 80 located in the trench side region 28 is in contact with each of the isolation trench 24 and the trench 25 that sandwich the well region 80 in the X-axis direction.

[0064] 6 and 7 , the well region 80 is formed in a semicircular shape when viewed from the X-axis direction, for example. More specifically, the well region 80 is formed so that its width (dimension in the Y-axis direction) is greatest at the well surface 80s and gradually decreases with increasing distance from the well surface 80s. For example, the maximum width of the well region 80, i.e., the width dimension W1 of the well surface 80s, is equal to twice the maximum thickness dimension HW of the well region 80. Details of the width dimension W1 and the thickness dimension HW will be described later.

[0065] 2 and 7 , the surface 23s of the drift layer 23 located in the inter-trench region 27 and the trench side region 28 has an exposed surface 90s located between the well surfaces 80s of two adjacent well regions 80. The exposed surface 90s is in contact with the anode electrode 42 in the active region 51. More specifically, the exposed surface 90s forms a Schottky contact with the anode electrode 42 in the active region 51. Note that in this embodiment, portions 91s of the surface 23s of the drift layer 23 located between the isolation trench 24 and the well surfaces 80s of the well regions 80 located at both ends in the Y-axis direction are not included in the exposed surface 90s.

[0066] The surface 23s of the drift layer 23 located in the inter-trench region 27 and the trench lateral region 28 includes a portion formed by the well surface 80s and a portion formed by the exposed surface 90s. As shown in Figures 6 and 7 , the surface 23s of the drift layer 23 located in the inter-trench region 27 and the trench lateral region 28 forms ohmic contact with the anode electrode 42 at the well surface 80s and also forms a Schottky contact with the anode electrode 42 at the exposed surface 90s. In other words, the anode electrode 42 forms ohmic contact with the well surface 80s in the active region 51 and also forms a Schottky contact with the exposed surface 90s.

[0067] As shown in FIG. 7 , the width dimension W1 (first-direction length W1) of the well surface 80s in the Y-axis direction may be, for example, 0.1 μm or more and 10 mm or less. The width dimension W1 may also be within the range described below. As shown in FIG. 2 , the sum of the width dimensions in the Y-axis direction of each of the well surfaces 80s and exposed surfaces 90s arranged in the Y-axis direction (the sum of the first-direction lengths) is defined as the total width dimension Wt. In this case, the width dimension W1 may be, for example, 0.00001 Wt or more and 0.99999 Wt or less. The total width dimension Wt may be, for example, 0.1 mm or more and 10 mm or less. The width dimension W1 of the well surfaces 80s may be the same for all well surfaces 80s, or may be different for one or more well surfaces 80s.

[0068] An example of the width dimension W1 of the well surface 80s is shorter than the distance D1 between two trenches 25 adjacent in the X-axis direction. An example of the width dimension W1 of the well surface 80s is longer than the distance D1 between two trenches 25 adjacent in the X-axis direction. An example of the width dimension W1 of the well surface 80s is the same as the distance D1 between two trenches 25 adjacent in the X-axis direction. An example of the width dimension W1 of the well surface 80s is longer than the width L1 of the trench 25. An example of the width dimension W1 of the well surface 80s is shorter than the width L1 of the trench 25. An example of the width dimension W1 of the well surface 80s is the same as the width L1 of the trench 25.

[0069] The thickness dimension HW of the well region 80 in the Z-axis direction may be, for example, 0.01 μm or more and 5 μm or less. An example of the thickness dimension HW of the well region 80 is thinner than the depth dimension HT of the trench 25. For example, the thickness dimension HW of the well region 80 is ½ or less of the depth dimension HT. The thickness dimension HW may also be ⅓ or less of the depth dimension HT. The thickness dimension HW of the well region 80 may be the same in all well regions 80, or may be different in one or more well regions 80. Note that the thickness dimension HW of the well region 80 here refers to the maximum thickness dimension of the well region 80.

[0070] At the surface 23s of the drift layer 23, the width dimension W2 of the exposed surface 90s in the Y-axis direction may be, for example, not less than 0.1 μm and not more than 10 mm. Furthermore, the width dimension W2 may be, for example, not less than 0.00001 Wt and not more than 0.99999 Wt (see FIG. 2 ). The width dimension W2 can also be referred to as the distance between two adjacent well regions 80 in the Y-axis direction. The width dimension W2 of the exposed surfaces 90s may be the same for all exposed surfaces 90s, or may be different for one or more exposed surfaces 90s. Note that when multiple well regions 80 are formed at equal intervals in the Y-axis direction, the width dimension W2 of all exposed surfaces 90s is the same.

[0071] Here, the sum of the areas of the well surfaces 80s located in each inter-trench region 27 and each trench lateral region 28 is defined as total area S1, and the sum of the areas of the exposed surfaces 90s located in each inter-trench region 27 and each trench lateral region 28 is defined as total area S2. The total area S1 is the sum of the areas of the well surfaces 80s within the range surrounded by the dashed line shown in FIG. 2. The total area S2 is the sum of the areas of the exposed surfaces 90s within the range surrounded by the dashed line shown in FIG. 2. The area ratio (S1 / S2) of the total area S1 of the well surfaces 80s to the total area S2 of the exposed surfaces 90s is, for example, a value that satisfies 0<S1 / S2≦100. The area ratio (S1 / S2) is, for example, 0.00001 or greater or 0.0001 or greater.

[0072] In one example, the total area S1 of the well surfaces 80s is larger than the total area S2 of the exposed surfaces 90s. In this case, the area ratio (S1 / S2) of the total area S1 of the well surfaces 80s to the total area S2 of the exposed surfaces 90s is, for example, a value that satisfies 1 < S1 / S2 ≦ 100. In another example, the total area S1 of the well surfaces 80s is smaller than the total area S2 of the exposed surfaces 90s. In this case, the area ratio (S1 / S2) of the total area S1 of the well surfaces 80s to the total area S2 of the exposed surfaces 90s is, for example, a value that satisfies 0 < S1 / S2 < 1. In another example, the total area S1 of the well surfaces 80s is the same as the total area S2 of the exposed surfaces 90s (area ratio S1 / S2 = 1).

[0073] The total area S1 of the well surface 80s and the total area S2 of the exposed surface 90s can be adjusted, for example, by changing the width dimension W1 of the well surface 80s and the width dimension W2 of the exposed surface 90s. The width dimension W1 of the well surface 80s and the width dimension W2 of the exposed surface 90s can be changed arbitrarily. The width dimension W1 of the well surface 80s may be longer than the width dimension W2 of the exposed surface 90s. The width dimension W1 of the well surface 80s may be shorter than the width dimension W2 of the exposed surface 90s. The width dimension W1 of the well surface 80s may be the same as the width dimension W2 of the exposed surface 90s.

[0074] Furthermore, the width dimension W1 of one or more of the multiple well surfaces 80s may be different. The width dimension W2 of one or more of the multiple exposed surfaces 90s may be different. As an example, as shown in Figure 18, the width dimension W1 of the well surfaces 80s may be different. Figure 18 shows a case where well surfaces 80s1 with a relatively long width dimension W1 and well surfaces 80s2 with a relatively short width dimension W1 are alternately arranged in the Y-axis direction, and the width dimension W2 of the multiple exposed surfaces 90s is constant.

[0075] The p-type impurity concentration of the well region 80 is, for example, 1×10 １６ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the drift layer 23 is lower than the p-type impurity concentration of the well region 80.

[0076] 8 to 17, an example of a method for manufacturing the semiconductor device 10 will be described. 8 to 17 are cross-sectional views showing enlarged views of a portion of the active region 51 and the peripheral region 52 for explaining the method for manufacturing the semiconductor device 10.

[0077] 8, a semiconductor wafer 821 is prepared as the base of the semiconductor substrate 21. The semiconductor wafer 821 includes a wafer front surface 821s and a wafer back surface 821r opposite to the wafer front surface 821s. An example of the semiconductor wafer 821 is a Si wafer. Here, in this embodiment, the semiconductor wafer 821 corresponds to a "semiconductor substrate" in a semiconductor device manufacturing method, the wafer front surface 821s corresponds to a "substrate front surface," and the wafer back surface 821r corresponds to a "substrate back surface."

[0078] Next, by epitaxial growth, Si is crystal-grown from the wafer surface 821s of the semiconductor wafer 821. As a result, a buffer layer 822 having a predetermined n-type impurity concentration and a drift layer 823 having a predetermined n-type impurity concentration are formed in this order. Here, in this embodiment, the drift layer 823 corresponds to the "semiconductor layer" in the method of manufacturing a semiconductor device.

[0079] Next, a mask 900 is formed on the surface 823s of the drift layer 823. The mask 900 is made of SiO ２ The mask 900 may be formed by at least one of a chemical vapor deposition (CVD) method and a thermal oxidation method. In this embodiment, the mask 900 is formed by a thermal oxidation method.

[0080] Next, a first resist mask 910 having a predetermined pattern is formed on the mask 900. The first resist mask 910 has a plurality of openings 911 corresponding to regions of the surface 823s of the drift layer 823 where the isolation trench 24 and the plurality of trenches 25 (both see FIG. 3 ) are to be formed.

[0081] Subsequently, openings 901 are formed in the portions of the mask 900 exposed by the openings 911 by an etching method using the first resist mask 910. The openings 901, 911 expose regions of the surface 823s of the drift layer 823 where the isolation trench 24 and the trenches 25 are to be formed. After the openings 901 are formed in the mask 900, the first resist mask 910 is removed.

[0082] 9 , an etching method using a mask 900 is used to remove regions of the surface 823s of the drift layer 823 where the isolation trench 24 and the plurality of trenches 25 are to be formed. This forms the isolation trench 24 and the plurality of trenches 25. The isolation trench 24 extends from the surface 823s of the drift layer 823 in the Z-axis direction and is formed in the shape of a rectangular frame in plan view. Each trench 25 extends from the surface 823s of the drift layer 823 in the Z-axis direction and also in the Y-axis direction. Each trench 25 communicates with the isolation trench 24. The plurality of trenches 25 are spaced apart from one another in the X-axis direction.

[0083] The isolation trench 24 also defines the active region 51 and the peripheral region 52. The etching method may be at least one of wet etching and dry etching. In this embodiment, dry etching is used. The dry etching method may be, for example, reactive ion etching (RIE). After the isolation trench 24 and the plurality of trenches 25 are formed, the mask 900 is removed.

[0084] 10, a first base insulating film 850 is formed on the surface 823s of the drift layer 823, the inner walls of the isolation trenches 24, and the inner walls of the trenches 25 by at least one of CVD and thermal oxidation. In this embodiment, the first base insulating film 850 is formed by thermal oxidation. The first base insulating film 850 is a field oxide film. The first base insulating film 850 is made of SiO ２ The first base insulating film 850 is formed of a film. The first base insulating film 850 serves as a base for the isolation insulating film 31, the insulating layer 33 in the trench 25, and the first insulating film 61 (all see FIG. 3 ). The first base insulating film 850 grows while absorbing n-type impurities in the vicinity of the drift layer 823. Therefore, the first base insulating film 850 contains the n-type impurities of the drift layer 823. Here, in this embodiment, the first base insulating film 850 corresponds to an "insulating layer" in the method for manufacturing a semiconductor device.

[0085] 11 , a first base electrode film 830 is formed on the first base insulating film 850 by a CVD method. The first base electrode film 830 serves as the base of the isolation electrode 32 and the buried electrode 34 (see FIG. 3 for both). The first base electrode film 830 fills both the first recess space formed by the first base insulating film 850 in the isolation trench 24 and the second recess space formed by the first base insulating film 850 in the trench 25, and is formed over the entire surface 823s of the drift layer 823. The first base electrode film 830 is formed of, for example, a conductive polysilicon film.

[0086] 12, the first base electrode film 830 is removed by etching except for the portions filled in the first recess space and the second recess space. This results in the formation of the isolated electrode 32 and the buried electrode 34. As the etching method, for example, at least one of wet etching and dry etching is used. Here, in this embodiment, the buried electrode 34 corresponds to the "third electrode" in the method for manufacturing a semiconductor device.

[0087] 13, a second resist mask 920 having a predetermined pattern is formed on the first base insulating film 850. The second resist mask 920 has an opening 921 that exposes a region in the surface 823s of the drift layer 823 where the peripheral well region 26 is to be formed.

[0088] Next, p-type impurities are implanted into the surface 823s of the drift layer 823 by ion implantation via the second resist mask 920. The p-type impurities are implanted into the surface portion of the drift layer 823 via the first base insulating film 850. Then, by drive-in processing, the p-type impurities implanted into the surface portion of the drift layer 823 are diffused in the width direction (X-axis direction) and depth direction (Z-axis direction) of the drift layer 823. Through the above steps, the peripheral well region 26 is formed. Then, after the peripheral well region 26 is formed, the second resist mask 920 is removed.

[0089] 14, a second base insulating film 860 is formed on the first base insulating film 850, on the isolation electrode 32, and on the buried electrode 34 by CVD. The second base insulating film 860 serves as the base of the second insulating film 62. The second base insulating film 860 is made of an insulating material different from that of the first base insulating film 850. More specifically, the second base insulating film 860 is made of SiO 2 , which has properties different from those of the first base insulating film 850. ２ The second base insulating film 860 includes, for example, at least one of a PSG film and a USG film.

[0090] 15 , a third resist mask 930 having a predetermined pattern is formed on the second base insulating film 860. The third resist mask 930 has openings 931 that expose regions of the second base insulating film 860 where the through holes 60A of the surface insulating layer 60 will be formed. Then, the portions of the second base insulating film 860 exposed by the openings 931 are removed by etching via the third resist mask 930. As the etching method, at least one of wet etching and dry etching is used. In this embodiment, dry etching (e.g., RIE) is used. As a result, the through holes 861 are formed in the second base insulating film 860.

[0091] Next, the portions of the first base insulating film 850 exposed by the openings 931 and the through-holes 861 are removed by etching via the third resist mask 930. At least one of wet etching and dry etching is used as the etching method. In this embodiment, dry etching (e.g., RIE) is used. As a result, the first base insulating film 850 is separated into the isolation insulating film 31, the insulating layer 33, and the first insulating film 61. The second base insulating film 860 becomes the second insulating film 62. As a result, a surface insulating layer 60 having a stacked structure of the first insulating film 61 and the second insulating film 62 is formed on the surface 823s of the drift layer 823. After patterning the first base insulating film 850 and the second base insulating film 860, the third resist mask 930 is removed.

[0092] 16 , a fourth resist mask 940 having a predetermined pattern is formed on the surface insulating layer 60. The fourth resist mask 940 has openings 941 that expose parts of the inter-trench region 27 and the trench lateral region 28 of the surface 823s of the drift layer 823. The openings 941 in the fourth resist mask 940 are formed for each inter-trench region 27 and each trench lateral region 28. The fourth resist mask 940 exposes the parts of the inter-trench region 27 and the trench lateral region 28 that will become the well surface 80s through the openings 941, and covers the entire parts that will not become the well surface 80s.

[0093] Next, p-type impurities are implanted into the surface 823s of the drift layer 823 by ion implantation via the fourth resist mask 940. That is, the p-type impurities are implanted into the inter-trench region 27 and the trench side region 28 through the openings 941. The p-type impurities are implanted into the surface portion of the drift layer 823. Then, by drive-in processing, the p-type impurities implanted into the surface portion of the drift layer 823 are diffused in the width direction (X-axis direction) and depth direction (Z-axis direction) of the drift layer 823. Through the above steps, the well region 80 is formed, and an exposed surface 90s (not shown) is formed between well regions 80 adjacent in the Y direction. After the well region 80 is formed, the fourth resist mask 940 is removed.

[0094] In this embodiment, the number of times p-type impurities are implanted by ion implantation through the fourth resist mask 940 is, for example, one. The number of times p-type impurities are implanted by ion implantation through the fourth resist mask 940 may be, for example, multiple times. The more times p-type impurities are implanted, the larger the thickness HW of the well region 80 becomes. Note that the ratio of the width of the opening 941 to the widths of the inter-trench region 27 and the trench side region 28 and the number of implantations can be changed as desired depending on the shape of the well region 80.

[0095] 17 , a second base electrode film 840 is formed by CVD on the well surface 80s of the well region 80, on the exposed surface 90s (not shown), on the isolation electrode 32, on the buried electrode 34, and on the surface insulating layer 60. The second base electrode film 840 forms ohmic contact with each of the well surface 80s of the well region 80, the isolation electrode 32, and the buried electrode 34. As a result, the second base electrode film 840 is electrically connected to the isolation electrode 32 and the buried electrode 34. On the other hand, the second base electrode film 840 is insulated from the peripheral well region 26. Here, in this embodiment, the second base electrode film 840 corresponds to the "first electrode" in the method for manufacturing a semiconductor device.

[0096] The second base electrode film 840 has a laminated structure of a first electrode film (not shown), a second electrode film (not shown), and a third electrode film (not shown). The first electrode film is formed so as to contact the well surface 80s of the well region 80, the exposed surface 90s (not shown), the isolation electrode 32, the buried electrode 34, and the surface insulating layer 60. In this embodiment, the first electrode film is formed of a material containing, for example, Ti. The second electrode film is formed on the first electrode film. In this embodiment, the second electrode film is formed of a material containing, for example, TiN. The third electrode film is formed on the second electrode film. In this embodiment, the third electrode film is formed of a material containing, for example, Al.

[0097] Each of the first electrode film, the second electrode film, and the third electrode film may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method, for example. In this embodiment, each of the first electrode film, the second electrode film, and the third electrode film is formed by a sputtering method.

[0098] Subsequently, although not shown, a sixth resist mask is formed on the second base electrode film 840. The sixth resist mask does not cover the outer peripheral portion of the second base electrode film 840. Subsequently, the outer peripheral portion of the second base electrode film 840 is removed by etching via the sixth resist mask. This forms the anode electrode 42.

[0099] Although not shown, the manufacturing method of the semiconductor device 10 further includes forming a surface protection layer 70, forming a cathode electrode 41, and singulating. The surface protection layer 70 is formed after the second base electrode film 840 is formed. For example, the surface protection layer 70 is formed on the surface insulating layer 60 and the second base electrode film 840 by a CVD method.

[0100] The cathode electrode 41 is formed by sputtering on the wafer back surface 821r of the semiconductor wafer 821. The cathode electrode 41 forms ohmic contact with the wafer back surface 821r of the semiconductor wafer 821.

[0101] The individualization is performed after the surface protection layer 70 is formed. For example, a dicing blade is used to cut the surface protection layer 70, the drift layer 823, the buffer layer 822, and the cathode electrode 41 along cutting lines CL shown by dashed lines in FIG. 17. Through the above steps, the semiconductor device 10 is manufactured.

[0102] (Function) The function of this embodiment will be described. In the semiconductor device 10, the p-type well region 80 is partially provided on the surface 23s of the n-type drift layer 23 located in the inter-trench region 27. Therefore, the surface 23s of the drift layer 23 has a well surface 80s formed by the p-type well region 80 and an exposed surface 90s formed by the n-type drift layer 23. The surface 23s of the drift layer 23 forms ohmic contact with the anode electrode 42 at the well surface 80s, and also forms a Schottky contact with the anode electrode 42 at the exposed surface 90s.

[0103] In this embodiment, the well regions 80 extend in the Y-axis direction intersecting the extension direction (X-axis direction) of the trenches 25, and are formed in plurality at intervals in the extension direction (X-axis direction) of the trenches 25. As a result, as shown in FIG. 2 , both a first region R1 that forms ohmic contact with the anode electrode 42 and a second region R2 that forms Schottky contact with the anode electrode 42 are formed as regions adjacent to a common trench 25. Furthermore, the first regions R1 and the second regions R2 are formed alternately in the extension direction of the trenches 25.

[0104] 3 , in the first region R1, a well region 80 is formed over the entire surface 23 s of the drift layer 23 in the inter-trench region 27 and the trench side region 28. The entire surface 23 s of the drift layer 23 in the first region R1 is constituted by a well surface 80 s, and forms ohmic contact with the anode electrode 42. In the first region R1, the well surface 80 s that forms ohmic contact with the anode electrode 42 is adjacent to the sidewall 25 a of the trench 25.

[0105] 5 , in the second region R2, the entire surface 23s of the drift layer 23 between adjacent trenches 25 is formed by the n-type drift layer 23. The entire surface 23s of the drift layer 23 in the second region R2 is composed of an exposed surface 90s, and forms a Schottky contact with the anode electrode 42. In the second region R2, the exposed surface 90s forming the Schottky contact with the anode electrode 42 is adjacent to the sidewall 25a of the trench 25.

[0106] As described above, in this embodiment, both the first region R1, which forms ohmic contact with the anode electrode 42, and the second region R2, which forms Schottky contact with the anode electrode 42, are adjacent to the common sidewall 25a of the trench 25. In this case, the first region R1, which forms ohmic contact with the anode electrode 42, exhibits a characteristic of suppressing leakage current. Furthermore, the second region R2, which forms Schottky contact with the anode electrode 42, exhibits a characteristic of reducing forward voltage drop VF. In particular, the configuration in which the second region R2 is provided adjacent to the sidewall 25a of the trench 25 enhances the characteristic of reducing forward voltage drop VF.

[0107] In this embodiment, the characteristics of reducing the forward voltage drop VF and suppressing the leakage current can be easily adjusted by adjusting the total area S1 of the well surfaces 80s of the well region 80. To strengthen the characteristics of reducing the forward voltage drop VF, the well region 80 is formed so that the total area S1 of the well surfaces 80s is reduced. Reducing the total area S1 of the well surfaces 80s relatively increases the total area S2 of the exposed surfaces 90s. As the exposed surface 90s increases, the second region R2 that forms Schottky contact with the anode electrode 42 increases, and the first region R1 that forms ohmic contact with the anode electrode 42 decreases. As a result, the characteristics of reducing the forward voltage drop VF are strengthened, and the characteristics of suppressing the leakage current are weakened.

[0108] On the other hand, to strengthen the leakage current suppression characteristic, the well region 80 is formed so that the total area S1 of the well surface 80s is increased. As the total area S1 of the well surface 80s increases, the first region R1 that forms ohmic contact with the anode electrode 42 becomes larger, and the second region R2 that forms Schottky contact with the anode electrode 42 becomes smaller. As a result, the leakage current suppression characteristic is strengthened, and the characteristic of reducing the forward voltage drop VF is weakened.

[0109] According to this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a semiconductor substrate 21 of a first conductivity type having a substrate front surface 21 s and a substrate back surface 21 r, a drift layer 23 of the first conductivity type formed on the substrate front surface 21 s, an anode electrode 42 formed on the front surface 23 s of the drift layer 23, a cathode electrode 41 formed on the substrate back surface 21 r, a plurality of trenches 25 extending in a first direction orthogonal to the thickness direction of the drift layer 23 and formed at intervals in a second direction orthogonal to the thickness direction of the drift layer 23 and the first direction, an insulating layer 33 provided to cover bottom walls 25 b and sidewalls 25 a of the trenches 25, a buried electrode 34 formed in the insulating layer 33 and in contact with the anode electrode 42, and a well region 80 of a second conductivity type formed in a part of the front surface 23 s of the drift layer 23. The well regions 80 extend in a direction intersecting the first direction and are formed at intervals in the first direction. The well region 80 has a well surface 80s forming a part of the surface 23s of the drift layer 23, and a well edge 80e in contact with the insulating layer 33 of the trench 25. The surface 23s of the drift layer 23 forms an ohmic contact with the anode electrode 42 at the well surface 80s, and forms a Schottky contact with the anode electrode 42 at an exposed surface 90s located between the multiple well surfaces 80s.

[0110] According to this configuration, by forming the well regions 80 so that the total area S1 of the well surfaces 80s is small, the characteristic of reducing the forward voltage drop VF can be strengthened. Also, by forming the well regions 80 so that the total area S1 of the well surfaces 80s is large, the characteristic of suppressing the leakage current can be strengthened. Therefore, by adjusting the total area S1 of the well surfaces 80s of the well regions 80, the characteristic of reducing the forward voltage drop VF and the characteristic of suppressing the leakage current can be easily adjusted.

[0111] (2) The well region 80 extends across the trench 25 in a direction intersecting the first direction. With this configuration, a first region R1 that forms ohmic contact with the anode electrode 42 and a second region R2 that forms Schottky contact with the anode electrode 42 can be formed adjacent to both sides of the trench 25 in the X direction. This makes it possible to more significantly achieve the effect of (1) above.

[0112] (3) The well region 80 extends in the second direction, i.e., in a direction perpendicular to the trench 25. This configuration can prevent both a well surface 80s that forms ohmic contact with the anode electrode 42 and an exposed surface 90s that forms Schottky contact with the anode electrode 42 from being formed in one inter-trench region 27 in a cross section perpendicular to the trench 25 as shown in Fig. 3. In this case, the leakage current suppression characteristic is more pronounced in the first region R1 that forms ohmic contact with the anode electrode 42.

[0113] (4) The multiple well regions 80 are formed at equal intervals in the first direction. In this case, the total area S1 of the well surfaces 80s can be easily adjusted by changing the length W1 of the well surfaces 80s in the first direction.

[0114] [Modifications] The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0115] A structure may be adopted in which the conductivity types of the semiconductor substrate 21, buffer layer 22, drift layer 23, peripheral well region 26, and well region 80 are inverted. That is, a p-type region may be an n-type region, and an n-type region may be a p-type region.

[0116] (Examples of Modifications Related to Well Regions) The shape and arrangement of the well regions 80 can be changed as desired. For example, the arrangement of the well regions 80 is not limited to being aligned in a specific direction across the trenches 25. As an example, in two inter-trench regions 27 adjacent to each other in the X-axis direction, the well surfaces 80s and the exposed surfaces 90s may be arranged alternately.

[0117] In one well region 80, the width dimension W1 of the well surface 80s may be constant within the range of the inter-trench region 27, or may vary partially or entirely. In one well region 80, the thickness dimension HW of the well region 80 may be constant within the range of the inter-trench region 27, or may vary partially or entirely.

[0118] The cross-sectional shape of the well region 80 as viewed from the X-axis direction (cross-sectional shape perpendicular to the X-axis direction (second direction)) is not limited to a semicircular shape. For example, the well region 80 may have a cross-sectional shape defined as the inner region of an arc, both ends of which are located on the well surface 80s.

[0119] One well region 80 has two well ends 80e located at both ends. At least one of these two well ends 80e needs to be in contact with the insulating layer 33 of the trench 25. A configuration in which one well end 80e is in contact with the insulating layer 33 of the trench 25 and the other well end 80e is not in contact with the insulating layer 33 of the trench 25 may also be used.

[0120] (Modifications Related to Trench) The plurality of trenches 25 may be formed in a lattice shape so that they extend in the Y-axis direction in plan view and two adjacent trenches 25 in the X-axis direction are connected to each other. Each trench 25 may have a portion extending in the Y-axis direction.

[0121] The isolation trench 24 may have any shape in plan view as long as it is formed in a ring shape surrounding the plurality of trenches 25. In one example, the isolation trench 24 may have a curved shape in plan view at a portion that connects two trenches 25 adjacent to each other in the X-axis direction.

[0122] As used in this disclosure, the term "on" includes the meanings "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0123] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0124] The statement "at least one of A and B" in this disclosure should be understood to mean "A only, or B only, or both A and B." [Note] The technical ideas that can be understood from the above-described embodiment and each modified example are described below. Note that, for the purpose of aiding understanding without intending to be limiting, the corresponding symbols in the embodiment are shown in parentheses for the configurations described in the notes. The symbols are shown as examples to aid understanding, and the components described with each symbol should not be limited to the components indicated by the symbol.

[0125] [Supplementary Note 1] A semiconductor substrate (21) of a first conductivity type (n) having a substrate surface (21s) and a substrate back surface (21r) opposite to the substrate surface (21s); A semiconductor layer (23) of a first conductivity type (n) formed on the substrate surface (21s) and having a surface (23s); A first electrode (42) formed on the surface (23s) of the semiconductor layer (23); A second electrode (41) formed on the substrate back surface (21r); A plurality of trenches (25) extending from the surface (23s) of the semiconductor layer (23) in a thickness direction of the semiconductor layer (23) and in a first direction perpendicular to the thickness direction of the semiconductor layer (23), and formed to be spaced apart in a second direction perpendicular to the thickness direction of the semiconductor layer (23) and the first direction; An insulating layer (33) provided so as to cover a bottom wall (25b) and a side wall (25a) of each of the trenches (25); the well region (80) includes a third electrode (34) formed in the insulating layer (33) and in contact with the first electrode (42); and a well region (80) of a second conductivity type (p) formed in a part of the surface (23s) of the semiconductor layer (23), the well region (80) extending in a direction intersecting the first direction and being one of a plurality of well regions (80) spaced apart in the first direction, the well region (80) having a well surface (80s) forming a part of the surface (23s) of the semiconductor layer (23) and a well end (80e) in contact with the insulating layer (33) of the trench (25), the well surface (80s) being one of the plurality of well surfaces (80s); The surface (23s) of the semiconductor layer (23) forms an ohmic contact with the first electrode (42) at the well surface (80s), and the surface (23s) of the semiconductor layer (23) forms a Schottky contact with the first electrode (42) at an exposed surface (90s) located between the multiple well surfaces (80s).

[0126] [Supplementary Note 2] The semiconductor device (10) according to Supplementary Note 1, wherein the well region (80) extends across the trench (25) in a direction intersecting the first direction.

[0127] [Supplementary Note 3] The semiconductor device (10) according to Supplementary Note 1 or Supplementary Note 2, wherein the well region (80) extends in the second direction.

[0128] [Supplementary Note 4] The semiconductor device (10) according to any one of Supplementary Notes 1 to 3, wherein the plurality of well regions (80) are formed at equal intervals in the first direction.

[0129] [Appendix 5] The semiconductor device (10) according to any one of Appendices 1 to 4, wherein a total area (S1) of the well surfaces (80s) is smaller than a total area (S2) of the exposed surfaces (90s).

[0130] [Appendix 6] The semiconductor device (10) according to any one of Appendices 1 to 4, wherein an area ratio (S1 / S2) of a total area (S1) of the well surface (80s) to a total area (S2) of the exposed surface (90s) satisfies 0<S1 / S2≦100.

[0131] [Appendix 7] The semiconductor device (10) according to Appendix 5 or Appendix 6, wherein, at the surface (23s) of the semiconductor layer (23), a first direction length (W1) of the well surface (80s) is shorter than a first direction length (W2) of an exposed surface (90s).

[0132] [Appendix 8] The semiconductor device (10) according to any one of Appendices 1 to 4, wherein a total area (S1) of the well surfaces (80s) is greater than a total area (S2) of the exposed surfaces (90s).

[0133] [Appendix 9] The semiconductor device (10) according to Appendix 8, wherein an area ratio (S1 / S2) of a total area (S1) of the well surface (80s) to a total area (S2) of the exposed surface (90s) satisfies 1 < S1 / S2 ≦ 100.

[0134] [Appendix 10] The semiconductor device (10) according to Appendix 8 or Appendix 9, wherein, at the surface (23s) of the semiconductor layer (23), a first direction length (W1) of the well surface (80s) is longer than a first direction length (W2) of an exposed surface (90s).

[0135] [Appendix 11] The semiconductor device (10) according to any one of appendices 1 to 10, wherein a first direction length (W1) of the well surface (80s) is shorter than a distance (D1) between adjacent trenches (25).

[0136] [Appendix 12] The semiconductor device (10) according to any one of appendices 1 to 10, wherein a first direction length (W1) of the well surface (80s) is longer than a distance (D1) between adjacent trenches (25).

[0137] [Appendix 13] The semiconductor device (10) according to any one of Appendices 1 to 12, wherein a first direction length (W1) of the well surface (80s) is longer than a second direction length (L1) of the trench (25).

[0138] [Appendix 14] The semiconductor device (10) according to any one of appendices 1 to 13, wherein the thickness dimension (HW) of the well region (80) is equal to or less than half the depth dimension (HT) of the trench (25).

[0139] [Appendix 15] The semiconductor device (10) according to any one of Appendices 1 to 14, wherein the insulating layer (33) of the trench (25) has a plurality of first portions (33a) in contact with the well edge (80e) of the well region (80), and a second portion (33b) located between the plurality of first portions (33a) and in contact with the semiconductor layer (23).

[0140] [Supplementary Note 16] Preparing a semiconductor substrate (21) of a first conductivity type having a substrate surface (21s) and a substrate back surface (21r) opposite to the substrate surface (21s); Forming a semiconductor layer (23) of a first conductivity type having a surface (23s) on the substrate surface (21s); Forming a first electrode (42) on the surface (23s) of the semiconductor layer (23); Forming a second electrode (41) on the substrate back surface (21r); Forming a plurality of trenches (25) extending from the surface (23s) of the semiconductor layer (23) in a thickness direction (Z-axis direction) of the semiconductor layer (23) and in a first direction (Y-axis direction) perpendicular to the thickness direction (Z-axis direction) of the semiconductor layer (23), and spaced apart from each other in a second direction (X-axis direction) perpendicular to the thickness direction (Z-axis direction) of the semiconductor layer (23) and the first direction (Y-axis direction), forming an insulating layer (33) so as to cover a bottom wall (25b) and a side wall (25a) of the trench (25); forming a third electrode (34) in the insulating layer (33) in contact with the first electrode (42); and forming a well region (80) of a second conductivity type in an inter-trench region (27) that is a portion of the surface (23s) of the semiconductor layer (23) between adjacent trenches (25), wherein the well region (80) has a well surface (80s) that forms a part of the surface (23s) of the semiconductor layer (23) and a well edge (80e) that contacts the insulating layer (33) of the trench (25), and the well surface (80s) is one of a plurality of well surfaces (80s); A method for manufacturing a semiconductor device (10), comprising forming the first electrode (42) such that the surface (23s) of the semiconductor layer (23) forms an ohmic contact with the first electrode (42) at the well surface (80s) and the surface (23s) of the semiconductor layer (23) forms a Schottky contact with the first electrode (42) at an exposed surface (90s) located between the multiple well surfaces (80s).

[0141] CL...cutting line D1...interval HT...depth dimension HW...thickness dimension L1...width (length in second direction) R1...first region R2...second region W1...width dimension (length in first direction) W2...width dimension (length in first direction) 10...semiconductor device 11...semiconductor chip 11r...chip back surface 11s...chip front surface 12A-12D...first to fourth chip side surfaces 21...semiconductor substrate 21r...substrate back surface 21s...substrate front surface 22...buffer layer 23...drift layer (semiconductor layer) 23s...surface 24...isolation trench 24a...side wall 24b...bottom wall 25...trench 25a...side wall 25b...bottom wall 26...periphery well region 27...inter-trench region 28...trench lateral region 31...isolation insulating film 32...isolation electrode (third electrode) 33...insulating layer 33a...first portion 33b...second portion 34...buried electrode 41...cathode electrode (second electrode) 42...anode electrode (first electrode) 42A...first electrode film 42B...second electrode film 42C...third electrode film 51...active region 52...periphery region 60...surface insulating layer 60A...through hole 61...first insulating film 62...second insulating film 70...surface protective layer 71...opening 80...well region 80e...well edge 80s...well surface 80s1...well surface 80s2...well surface 90s...exposed surface 91s...portion 821...semiconductor wafer 821r...wafer back surface 821s...wafer surface 822...buffer layer 823...drift layer 823s...surface 830...first base electrode film 840...second base electrode film 850... First base insulating film 860... Second base insulating film 861... Through hole 900... Mask 901, 911, 921, 931, 941... Openings 910... First resist mask 920... Second resist mask 930... Third resist mask 940... Fourth resist mask

Claims

1. a semiconductor substrate of a first conductivity type having a substrate surface and a substrate back surface opposite to the substrate surface; a first conductivity type semiconductor layer formed on the substrate surface and having a surface; a first electrode formed on the surface of the semiconductor layer; a second electrode formed on the rear surface of the substrate; a plurality of trenches extending from the surface of the semiconductor layer in a thickness direction of the semiconductor layer and extending in a first direction perpendicular to the thickness direction of the semiconductor layer, and spaced apart in a second direction perpendicular to the thickness direction of the semiconductor layer and the first direction; an insulating layer provided so as to cover the bottom wall and sidewall of each of the trenches; a third electrode formed in the insulating layer and in contact with the first electrode; a well region of a second conductivity type formed in a portion of the surface of the semiconductor layer, the well region is one of a plurality of well regions extending in a direction intersecting the first direction and spaced apart in the first direction, the well region has a well surface forming a portion of the surface of the semiconductor layer and a well edge of the trench contacting the insulating layer, the well surface being one of a plurality of well surfaces; the surface of the semiconductor layer forms an ohmic contact with the first electrode at the well surface, and the surface of the semiconductor layer forms a Schottky contact with the first electrode at an exposed surface located between the multiple well surfaces.

2. The semiconductor device according to claim 1 , wherein the well region extends across the trench in a direction intersecting the first direction.

3. 3. The semiconductor device according to claim 1, wherein the well region extends in the second direction.

4. 2. The semiconductor device according to claim 1, wherein said plurality of well regions are formed spaced apart at equal intervals in said first direction.

5. 2. The semiconductor device according to claim 1, wherein a total area (S1) of said well surfaces is smaller than a total area (S2) of said exposed surfaces.

6. 2. The semiconductor device according to claim 1, wherein an area ratio (S1 / S2) of a total area (S1) of said well surfaces to a total area (S2) of said exposed surfaces satisfies 0<S1 / S2≦100.

7. 2. The semiconductor device according to claim 1, wherein a total area (S1) of said well surfaces is larger than a total area (S2) of said exposed surfaces.

8. 8. The semiconductor device according to claim 7, wherein an area ratio (S1 / S2) of a total area (S1) of said well surfaces to a total area (S2) of said exposed surfaces satisfies 1<S1 / S2≦100.

9. The semiconductor device according to claim 1 , wherein a length in the first direction of said well surface is shorter than a distance between adjacent said trenches.

10. The semiconductor device according to claim 1 , wherein a length in the first direction of said well surface is longer than a distance between adjacent said trenches.

11. The semiconductor device according to claim 1 , wherein a length in a first direction of said well surface is longer than a length in a second direction of said trench.

12. 2. The semiconductor device according to claim 1, wherein the thickness of said well region is equal to or less than half the depth of said trench.

13. The insulating layer in the trench is a plurality of first portions contacting the well edge of the well region; 2. The semiconductor device according to claim 1, further comprising: a second portion positioned between the plurality of first portions and in contact with the semiconductor layer.