High voltage bootstrap diode

Abstract

This invention provides a high-voltage bootstrap diode comprising a plurality of concentrically arranged annular anodes and cathodes, placed on a P-type substrate. The anode comprises a plurality of parallel P-rings, and the cathode comprises a plurality of parallel N-rings. Each P-ring includes a first P+ region, surrounded by a shallow P-type well, and below the shallow P-type well is a first N-type epitaxial layer. The outermost N-ring is surrounded by a second N-type epitaxial layer. Each N-ring includes an N+ region, surrounded by a deep N-type well, located between two N-type epitaxial layers. Below the deep N-type well and the first N-type epitaxial layer is an N-type buried layer. The second N-type epitaxial layer is surrounded by a high-voltage P-type well, and above the high-voltage P-type well is a second P+ region, coupled to the P-type substrate.

Description

Technical Field

[0001] This invention relates to a high-voltage bootstrap diode, and more specifically, to a high-voltage bootstrap diode suitable for high-voltage circuits, characterized by low substrate leakage current, high withstand voltage, and high current. Prior Technology

[0002] Please refer to Figure 1 (https: / / ieeexplore.ieee.org / document / 6694447) Integrating a conventional bootstrap diode 100 into a high-voltage (e.g., 120V) integrated circuit and applying it to high-side operations (such as motor drives, electronic ballasts, and DrMOS drives) has been a challenge for monolithic solutions because a significant leakage current 160 flows from the anode 102 to the substrate (P-type substrate 150 in Figure 1) in the on-mode. Due to voltage limitations, a high-density doped layer (i.e., an n+ buried layer) cannot be used below the anode 102 region, resulting in leakage current 160 in high-voltage devices. As shown in Figure 1, when the body diode is turned on, due to the low doping concentration of the base area of ​​the parasitic P (P-type base / P-type well 122)–N (N-type isolation layer 140)–P (P-type substrate 150) structure 170, the current of the anode 102 will flow to the P-type substrate 150.

[0003] To address the aforementioned issues, dual-chip packaged discrete component solutions and synchronous rectifier solutions are now widely used, as shown in Figures 2 and 3. However, referring to Figure 2 (https: / / www.infineon.com / cms / cn / product / power / gate-driver-ics / ir2104s / ?redirId=67212), the dual-chip packaged discrete component solution requires the use of separate chips and special packaging, such as a separate diode 201, resulting in increased overall costs. Referring to Figure 3 (http: / / www.bdtic.com / st / L6569.html), the synchronous rectifier requires control by a separate charge pump module 301, which also increases chip size and cost.

[0004] Therefore, there is an urgent need for a high-voltage bootstrap diode that has the advantages of low substrate leakage current, high withstand voltage, and high current, while not requiring additional circuit components, thus saving chip size and cost. Summary of the Invention

[0005] One objective of this invention is to provide a high-voltage bootstrap diode comprising a plurality of concentrically arranged annular anodes and cathodes, placed on a P-type substrate. The anode comprises a plurality of parallel P-rings, and the cathode comprises a plurality of parallel N-rings. Each P-ring includes a first P+ region, surrounded by a shallow P-type well, below which lies a first N-type epitaxial layer. The outermost N-ring is surrounded by a second N-type epitaxial layer, above which there are no P-rings or N-rings. Each N-ring includes an N+ region, surrounded by a deep N-type well, located between two of the first N-type epitaxial layers or between one of the first N-type epitaxial layers and the second N-type epitaxial layer. Below the deep N-type well and the first N-type epitaxial layer is an N-type buried layer. The second N-type epitaxial layer is surrounded by a high-voltage P-type well, above which lies a second P+ region, coupled to the P-type substrate.

[0006] In one embodiment, each of the P-rings further includes a plurality of polycrystalline silicon field plates, which are used to adjust the horizontal potential distribution.

[0007] In one embodiment, an oxide is further included between each of the P rings and each of the N rings.

[0008] In one embodiment, the shallow P-type well includes at least one shallow P-type well trench to ensure that the shallow P-type well achieves complete depletion.

[0009] In one embodiment, the N-type buried layer has a high doping concentration to reduce vertical substrate leakage current.

[0010] In one embodiment, the shallow P-type well and the deep N-type well have medium to low doping concentrations to prevent premature voltage collapse.

[0011] In one embodiment, the doping concentration of the deep N-type well is less than the doping concentration of the N-type buried layer.

[0012] In one embodiment, the doping concentration of the N-type buried layer is greater than 10¹³ cm⁻³.

[0013] In one embodiment, the doping concentration of the shallow P-type well is approximately 10¹² to 10¹³ cm⁻³, and the doping concentration of the deep N-type well is less than 10¹³ cm⁻³.

[0014] As can be seen from the above, the high-voltage bootstrap diode provided by the present invention has the advantages of low substrate leakage current, high withstand voltage, and large current, while not requiring additional circuit components, thus saving chip size and cost. Simple Explanation of the Diagram

[0015] The accompanying drawings are provided to enable those skilled in the art to further understand the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and are used, together with the specification, to explain the principles of the invention. A brief description of the figures follows: Figure 1 illustrates the leakage current problem of a high-voltage bootstrap diode. Figure 2 illustrates a bi-chip packaged discrete component solution to the leakage current problem of high-voltage bootstrap diodes. Figure 3 illustrates a synchronous rectifier solution to the leakage current problem of high-voltage bootstrap diodes. Figure 4A is a top view of a high-voltage bootstrap diode according to an embodiment of the present invention. Figure 4B is a cross-sectional view of a high-voltage bootstrap diode according to an embodiment of the present invention. Figure 5A is a cross-sectional view of a conventional high-voltage bootstrap diode. Figure 5B is a cross-sectional view of a high-voltage bootstrap diode according to an embodiment of the present invention. Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making progressive contributions are within the scope of protection of the present invention.

[0017] In view of the above problems, embodiments of the present invention have developed a high-voltage bootstrap diode, which has the advantages of low substrate leakage current, high withstand voltage and high current, while not requiring additional circuit components, thus saving chip size and cost.

[0018] Please refer to Figure 4A. This invention provides a high-voltage bootstrap diode 400, comprising multiple concentrically arranged annular anodes 41 and cathodes 42, placed on a P-type substrate 43. Figure 4B shows a cross-sectional view of Figure 4A from the center to the circumference, where the left side of Figure 4B represents the circumferential direction of Figure 4A, and the right side of Figure 4B represents the central direction of Figure 4A. As shown in Figure 4B, the anode 401 (corresponding to the anode 41 in Figure 4A) comprises multiple P-rings 401a, 401b, ... (two P-rings 401a and 401b are shown in Figure 4B, but this invention is not limited to this). Each P-ring 401a, 401b, ... is connected in parallel to form the anode 401. The cathode 402 (corresponding to cathode 42 in Figure 4A) comprises multiple N-rings 402a, 402b, ... (two N-rings 402a and 402b are shown in Figure 4B, but the invention is not limited thereto), and each N-ring 402a, 402b, ... is connected in parallel to form the cathode 402. Between each P-ring and N-ring is a polycrystalline silicon field plate 412 and an oxide 413, wherein the polycrystalline silicon field plate 412 is used to adjust the horizontal potential distribution.

[0019] The uppermost layer of P-ring 401a is a P+ region 4011, which is surrounded by shallow P-type wells 411a, each containing at least one shallow P-type well trench 4111a. Below the shallow P-type wells 411a is an N-type epitaxial layer 421. Similarly, the uppermost layer of P-ring 401b is a P+ region 4012, which is surrounded by shallow P-type wells 411b, each containing a shallow P-type well trench 4111b. Below the shallow P-type wells 411b is an N-type epitaxial layer 423. The uppermost layer of N-ring 402a is an N+ region 4021, which is surrounded by deep N-type wells 422, located between the N-type epitaxial layers 421 and 423 below P-rings 401a and 401b. Similarly, the uppermost layer of the N-ring 402b is an N+ region 4022, which is surrounded by a deep N-type well 424, located between the N-type epitaxial layer 423 below the P-ring 401b and the N-type epitaxial layer 425 surrounding the outermost N-ring. Below the N-type epitaxial layers 421 and 423 below the P-rings 401a and 401b, and below the deep N-type wells 422 and 424 below the N-rings 402a and 402b, there is an N-type buried layer 430. There is no P-ring or N-ring above the N-type epitaxial layer 425 surrounding the outermost N-ring. Outside the N-type epitaxial layer 425, there is a high-voltage P-type well 426 with a P+ region 4031, coupled to the lowermost P-type substrate 403 (corresponding to the P-type substrate 43 in Figure 4A).

[0020] The high-voltage bootstrap diode 400 shown in Figures 4A and 4B features low substrate leakage current, high withstand voltage, and high current. First, the N-type buried layer 430 has a high doping concentration; in one embodiment, its doping concentration is greater than 10¹³ cm⁻³. In another embodiment, its doping concentration is approximately 1.3 × 10¹³ cm⁻³. This highly doped N-type buried layer, located below the anode P-type well and the cathode N-type well, reduces vertical substrate leakage current. Second, there are medium-to-low doping concentration P-type well regions and N-type well regions below the P-ring and N-ring, respectively, which prevent premature voltage breakdown. In one embodiment, the shallow P-type wells 411a and 411b have a doping concentration of approximately 10¹² to 10¹³ cm⁻³, while the deep N-type wells 422 and 424 have a doping concentration less than 10¹³ cm⁻³. In one embodiment, the doping concentration of shallow P-type wells 411a and 411b is approximately 7 × 10¹² cm⁻³, and the doping concentration of deep N-type wells 422 and 424 is approximately 3.1 × 10¹² cm⁻³. Furthermore, the shallow P-type wells 411a and 411b have shallow P-type well region trenches 4111a and 4111b, ensuring complete depletion of the shallow P-type well region. Each anode P-ring is surrounded by a plurality of polycrystalline silicon field plates 412, which can adjust the horizontal potential distribution. The parallel structure of multiple anode P-rings and cathode N-rings enhances the device's current contribution capability, as detailed below.

[0021] Figure 5A is a cross-sectional view of a conventional high-voltage bootstrap diode with only a single-loop anode P-ring and a single-loop cathode N-ring structure. As shown in Figure 5A, a forward current IForward flows from the anode P-ring 501 to the cathode N-ring 502, while a leakage current Isub is generated by the parasitic PNP structure from the shallow P-type well 511, N-type epitaxial layer 521, N-type buried layer 530 below the P-ring 501 to the bottommost P-type substrate 503. Figure 5B is a cross-sectional view of an embodiment of the present invention, which includes three anode P-rings 551a, 551b, and 551c and three cathode N-rings 552a, 552b, and 552c. As shown in Figure 5B, a forward current IForward flows from each anode P-ring 551a, 551b, 551c to the adjacent (which may include the left and right sides) cathode N-rings 552a, 552b, 552c. Meanwhile, a leakage current Isub is generated from the parasitic PNP structure beneath each P-ring, from the shallow P-type wells (561a, 561b, 561c), the N-type epitaxial layers (571, 573, 575), the N-type buried layer 580 to the bottommost P-type substrate 553. It should be noted that with the same total cross-sectional area in Figures 5A and 5B, the forward current IForward is 1 unit in Figure 5A, while it is 5 units in Figure 5B. Since the total cross-sectional area of ​​the parasitic PNP structure is the same in both Figures 5A and 5B, the leakage current Isub is the same, which is 3 units. Therefore, compared to the structure in Figure 5A, the structure in Figure 5B can effectively increase the ratio of forward current IForward to leakage current Isub. With the leakage current Isub remaining unchanged, the forward current IForward is increased, thereby enhancing the current contribution capability of the component.

[0022] In summary, the high-voltage bootstrap diode provided by this invention has the following characteristics: reduced substrate leakage current, improved withstand voltage, and increased current.

[0023] Firstly, regarding reducing substrate leakage current, in the embodiments of the present invention, the vertical structure below the anode (P-ring) of the element is P (shallow P-type well) – N+ (high-concentration N-type buried layer) – P (P-type substrate). By implanting high-concentration N-type impurities into the N-type buried layer, it is ensured that the N-type impurity concentration in the horizontal direction (i.e., the doping concentration of the deep N-type well) is less than the N-type impurity concentration in the vertical direction (i.e., the doping concentration of the high-concentration N-type buried layer), which can reduce the leakage current caused by the parasitic PNP structure.

[0024] Secondly, regarding improving withstand voltage, since high-concentration N-type buried layers may cause insufficient withstand voltage, embodiments of the present invention adjust the P-type and N-type well regions. The combination of N-type and P-type wells used in conventional medium-voltage diodes (MV diodes) is adjusted to a combination of shallow P-type wells and deep N-type wells with a lower doping concentration. Furthermore, embodiments of the present invention include shallow P-type well region trenches within the shallow P-type wells to adjust the total P-type impurity concentration and the contact surface between N-type and P-type wells, ensuring complete depletion of the P-type well region. Additionally, each P-ring and N-ring has a polycrystalline silicon field plate to adjust the potential distribution in the horizontal direction.

[0025] Finally, in terms of increasing current, the embodiments of the present invention connect multiple anode P rings and cathode N rings in parallel from the inside out, which can effectively increase the forward current and enhance the current contribution capability of the components.

[0026] As can be seen from the above, regarding the leakage current problem of high-voltage bootstrap diodes, compared with conventional solutions, the high-voltage bootstrap diode provided by the present invention has the advantages of low substrate leakage current, high withstand voltage, and large current, while not requiring additional circuit components, thus saving chip size and cost.

[0027] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0028] 100: Bootstrap Diode 101: Cathode 102: Anode 111a, 111b: N+ region 112:P+ area 121a, 121b: N-type wells 122: P-type well 131a, 131b: High-pressure N-type wells 132a, 132b: P-type epitaxial layers 140: N-type isolation layer 141: Normal diffusion current 150: P-type substrate 160: Leakage current 170: Parasitic PNP structure 201: Diode 202: High Voltage 203: Load 301: Charge Pump Module 311: High Voltage 312: Load 321: High-side driver 322: Low-side driver 330: Level Shifter 340: Bias regulator 350: Buffer 360: Logic Circuits 371, 372: Comparators 400: High-voltage bootstrap diode 41: Anode 42: Cathode 43: P-type substrate 401: Anode 401a, 401b: P ring 402: Cathode 402a, 402b: N-ring 4011, 4012: P+ area 4021, 4022: N+ zone 403: P-type substrate 4031:P+ area 411a, 411b: Shallow P-type wells 4111a, 4111b: Shallow P-type well area trenches 412: Polycrystalline silicon field plate 413: Oxides 421, 423, 425: N-type epitaxial layers 422, 424: Deep N-type wells 426: High-voltage P-type well 430: N-type buried layer 501:P ring 502: N ring 5011:P+ area 5021: N+ Zone 503: P-type substrate 5031:P+ area 511: Shallow P-type well 521, 523: N-type epitaxial layers 522: Deep N-type well 524: High-voltage P-type well 530: N-type buried layer IForward: Forward current Isub: Leakage current 551a, 551b, 551c: P ring 552a, 552b, 552c: N-ring 5511, 5512, 5513: P+ area 5521, 5522, 5523: N+ area 553: P-type substrate 5531:P+ area 561a, 561b, 561c: Shallow P-type wells 571, 573, 575, 577: N-type epitaxial layers 572, 574, 576: Deep N-type wells 578: High-voltage P-type well 580: N-type buried layer

Claims

1. A high-voltage bootstrap diode, comprising: Multiple layers of concentrically arranged annular anodes and cathodes are placed on a P-type substrate; The anode comprises a plurality of P-rings connected in parallel, and the cathode comprises a plurality of N-rings connected in parallel. Each P-ring includes a first P+ region surrounded by a shallow P-type well, and below the shallow P-type well is a first N-type epitaxial layer. The outermost N-ring includes a second N-type epitaxial layer, with no P-rings or N-rings above the second N-type epitaxial layer. Each N-ring includes an N+ region surrounded by a deep N-type well, located between two of the first N-type epitaxial layers or between one of the first N-type epitaxial layers and the second N-type epitaxial layer. Below the deep N-type well and the first N-type epitaxial layer is an N-type buried layer. The second N-type epitaxial layer includes a high-voltage P-type well, and above the high-voltage P-type well is a second P+ region coupled to the P-type substrate.

2. The high-voltage bootstrap diode as described in claim 1, wherein, Each of the P-rings further includes a plurality of polycrystalline silicon field plates around its periphery, the polycrystalline silicon field plates being used to adjust the horizontal potential distribution.

3. The high-voltage bootstrap diode as described in claim 1, wherein, Each of the P rings and each of the N rings further includes an oxide.

4. The high-voltage bootstrap diode as described in claim 1, wherein, The shallow P-type well includes at least one shallow P-type well zone trench to ensure that the shallow P-type well achieves complete depletion.

5. The high-voltage bootstrap diode as described in claim 1, wherein, The N-type buried layer has a high doping concentration to reduce vertical substrate leakage.

6. The high-voltage bootstrap diode as described in claim 1, wherein, The shallow P-type well and the deep N-type well have medium to low doping concentrations to prevent premature voltage collapse.

7. The high-voltage bootstrap diode as described in claim 1, wherein, The doping concentration of the deep N-type well is lower than that of the N-type buried layer.

8. The high-voltage bootstrap diode as described in claim 5, wherein, The doping concentration of the N-type buried layer is greater than 10¹³ cm⁻³.

9. The high-voltage bootstrap diode as described in claim 6, wherein, The doping concentration of the shallow P-type well is approximately 10¹² to 10¹³ cm⁻³, while the doping concentration of the deep N-type well is less than 10¹³ cm⁻³.

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