Differential latch circuit, switch driver, and digital-to-analog conversion circuit

Abstract

A differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. The differential latch circuit comprises: a first-stage differential latch circuit (I), a second-stage differential inverting circuit (II), and a low-level shift circuit; a pull-up end of a differential positive end of the second-stage differential inverting circuit (II) comprises a first PMOS transistor (M9) and a second PMOS transistor (M10); a pull-down end of the differential positive end of the second-stage differential inverting circuit (II) comprises a third PMOS transistor (M15) and a first NMOS transistor (M11); and the circuit structure at a differential negative end of the first-stage differential latch circuit (I) is symmetrical to the circuit structure at a differential positive end of the first-stage differential latch circuit (I).

Description

A differential latch circuit, switch driver and digital-to-analog conversion circuit

[0001] Cross-references to related publications

[0002] This disclosure claims priority to a Chinese patent application filed with the State Intellectual Property Office on August 26, 2022, with publication number CN202211043550.2 and invention name “A differential latch circuit, switch driver, and digital-to-analog conversion circuit.” The entire contents of that application are incorporated by reference into this disclosure. Technical Field

[0003] The embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit design, and in particular to a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. Background Art

[0004] Figure 1 is a system block diagram of a digital-to-analog converter (DAC) in the related art. As shown in Figure 1, the DAC includes a data path, a clock path, and a DAC core circuit. The data path includes an interface circuit, a digital data path, a decoder, a serializer, and a switch driver. The clock path includes a clock receiver, a delay locked loop (DLL), a divider, and some clock drivers, while the DAC core circuit includes multiple DAC core slices. For a DAC, the design of the switch driver in the data path is crucial, affecting multiple indicators such as linearity, power consumption, and noise.

[0005] In a data link, input digital signals are first received and processed through the interface circuit and digital data link. The decoder's primary function is to perform DAC segment encoding. Specifically, the DAC high bits are typically encoded using thermometer code, while the low bits are typically encoded using binary code. Furthermore, the decoder can apply algorithms to the data, such as dynamic element matching (DEM), dithering, and rotation. Because the digital data link and decoder are digital P&R modules, high data rates are not possible. Therefore, each DAC bit is typically transmitted in multiple phases within these digital modules. The serializer's primary function is to convert multi-phase data into a single phase or fewer phases. The switch driver's primary function is to synchronize each bit of data, increase drive capability, and reduce intersymbol interference. Depending on the specific architecture and requirements of the DAC core unit, the switch driver may also need to adjust the data crosspoint (i.e., the intersection of the rising and falling edges of the differential output data) and the data high and low levels. These adjustments can significantly impact the linearity, noise, and other performance characteristics of the DAC in which the switch driver is used.

[0006] Figure 2 shows a traditional switch driver structure in related art. It uses the rising edge of the clock for data sampling. To achieve better data synchronization, a three-level latch is used for step-by-step synchronization. The upper two paths transmit the real signal, and the lower two paths transmit dummy data. This is to reduce the impact of signal-related current on DAC performance [1]. At each data sampling point, if the real data does not flip, the dummy data flips; if the real data flips, the dummy data does not flip.

[0007] There are many variations of traditional switch drivers, such as:

[0008] 1. The number of latch levels can be different.

[0009] 2. The latch can also be replaced with a flip-flop (DFF), a multiplexer (MUX) with both data combining and synchronization capabilities, or some other sequential logic. The design may also include some combinational logic.

[0010] 3. There are many ways to implement MUX. It can be a combinational logic MUX, OR / NOR or AND / NAND, a combinational logic MUX plus a clock-triggered latch or DFF, or some other type of clock-triggered MUX that simultaneously completes data combining and synchronization.

[0011] 4. Input data can be regular data, as shown in Figure 2, or Return-to-Zero or Return-to-One data. Different data types may result in different sequential logic circuits, such as latches, DFFs, and multiplexers, and may also result in different combinational logic.

[0012] 5. The Dummy data path can also be implemented in different ways or even deleted.

[0013] 6. Furthermore, multi-mode compatibility can be achieved in the switch driver. Figure 3 shows a traditional multi-mode compatible switch driver structure. Its characteristic is the compatibility between normal mode and mixed mode. In mixed mode, data changes occur on both the rising and falling edges of the clock. The data corresponding to the falling edge is the inverse of the data corresponding to the rising edge, which is equivalent to the mixing effect of the real signal and the clock signal. The resulting DAC output has a bandpass transfer function centered on Fclk, while the normal mode has a lowpass transfer function. This is very helpful for applications with high and medium frequency and low bandwidth.

[0014] While switch drivers have many variations, sequential logic circuits such as latches, DFFs, and multiplexers with synchronization capabilities, as well as some combinational logic circuits, are among the more fundamental elements. Figure 4 shows a schematic diagram of a traditional differential latch structure in related art. It utilizes a CMOS architecture, with rail-to-rail output high and low levels. The front stage is a clock-triggered latch, and the back stage is an inverter to increase the latch's driving capability.

[0015] As shown in Figure 4, its left and right sides are symmetrical. For example, on the left side, when clkp is low and clkn is high, din is sampled by the first-stage latch and transmitted to the output dout through the second-stage inverter. When clkp is high and clkn is low, the din path is disconnected, and dout remains unchanged.

[0016] Traditional Latch also has many variations, such as:

[0017] 1. The inverter at the subsequent stage can also be a buffer.

[0018] 2. The source of the PMOS transistor in the subsequent inverter can be connected to the output of a level-shift circuit instead of the power supply. This way, the inverter's high-level output is a specially designed voltage, not the power supply. Similarly, the source of the NMOS transistor in the inverter can be connected to the output of a level-shift circuit instead of ground. This way, the inverter's low-level output is a specially designed voltage, not ground. Furthermore, the power ground of the preceding latch can also be connected to the output of the level-shift circuit.

[0019] 3. The width-to-length ratio of the PMOS and NMOS in the downstream inverter can be intentionally designed to be asymmetric to adjust the crossover point of the inverter output data. Similarly, the width-to-length ratio of the PMOS and NMOS in the upstream latch can also be intentionally designed to be asymmetric.

[0020] 4. The above variations also exist in the design of DFF and MUX with synchronization function, the design of other sequential logic circuits, and the design of combinational logic circuits.

[0021] Traditional latches have the following disadvantages:

[0022] 1. Adjusting the inverter output data crossover point solely by adjusting the width-to-length ratio of the PMOS and NMOS transistors has limitations. If the width-to-length ratio difference between the PMOS and NMOS transistors is too large, the large MOS transistor will overload the preceding stage, and the large size will result in high current. The layout implementation of the MOS transistor source-drain connection will produce a large IR drop, affecting the MOS transistor's current capability, which in turn affects the adjustment of the output data crossover point and the DAC linearity. Small MOS transistors will result in a slow output data edge, and the large mismatch of small MOS transistors will cause large deviations in the output data edges of different DAC bits, affecting DAC linearity.

[0023] 2. If a level shifter circuit is added to a traditional latch, the adjustment of the output data crosspoint may be further affected because the level shifter circuit may cause a mismatch between the PMOS and NMOS terminals, which in turn affects the output data crosspoint. If the deviation of this crosspoint is contrary to our requirements, it will be difficult to achieve the goal by simply adjusting the width-to-length ratio of the PMOS and NMOS.

[0024] Summary of the Invention

[0025] Embodiments of the present disclosure provide a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit.

[0026] According to one embodiment of the present disclosure, a differential latch circuit is provided, comprising a first-stage differential latch circuit, a second-stage differential inverting circuit, and a low-level shift circuit connected in sequence, wherein the pull-up end of the differential positive end of the second-stage differential inverting circuit comprises a first PMOS transistor and a second PMOS transistor, the gate of the first PMOS transistor being connected to the gate of the second PMOS transistor; the source of the first PMOS transistor being connected to a power supply voltage; the drain of the first PMOS transistor being connected to the source of the second PMOS transistor; the gate of the first PMOS transistor and the gate of the second PMOS transistor being further connected to the data input end of the differential positive end of the second-stage differential inverting circuit, respectively; and the pull-down end of the differential positive end of the second-stage differential inverting circuit. The circuit comprises a third PMOS transistor and a first NMOS transistor, wherein the drain of the third PMOS transistor is connected to the source of the first NMOS transistor, and both are connected to the output end of a level shift circuit; the gate of the third PMOS transistor is connected to the data input end of the differential positive end of the second-stage differential inverter circuit, and the source of the third PMOS transistor is connected to the output end of the pull-down end of the differential negative end of the second-stage differential inverter circuit; the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the first NMOS transistor is connected to the data input end of the differential positive end of the second-stage differential inverter circuit; and the circuit structure of the differential negative end of the first-stage differential latch circuit is symmetrical with the differential positive end of the first-stage differential latch circuit.

[0027] According to another embodiment of the present disclosure, a switch driver is provided, comprising a plurality of switch driver units, wherein each switch driver unit comprises: multiple data transmission links, each data transmission link comprising the differential latch circuit in the above embodiment.

[0028] According to another embodiment of the present disclosure, a digital-to-analog conversion circuit is provided, comprising the switch driver in the above embodiment and a digital-to-analog conversion core circuit connected to the output end of the switch driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a system structure block diagram of a digital-to-analog converter in the related art;

[0030] FIG2 is a schematic diagram of a conventional switch driver structure in the related art;

[0031] FIG3 is a schematic diagram of a conventional multi-mode compatible switch driver structure;

[0032] FIG4 is a schematic diagram of a conventional differential latch structure in the related art;

[0033] FIG5( a ) is a schematic diagram of a differential latch circuit structure according to an embodiment of the present disclosure;

[0034] FIG5( b ) is a schematic diagram of another connection method of the fourth PMOS transistor in the second-stage differential inverting circuit according to an embodiment of the present disclosure;

[0035] FIG5( c ) is a schematic diagram of another connection method of the fourth PMOS transistor in the second-stage differential inverter circuit according to an embodiment of the present disclosure;

[0036] FIG6 is a schematic structural diagram of a differential latch circuit according to another embodiment of the present disclosure;

[0037] FIG7 is a schematic structural diagram of a switch driver according to an embodiment of the present disclosure;

[0038] FIG8 is a schematic structural diagram of a switch driver according to another embodiment of the present disclosure;

[0039] FIG9 is a schematic structural diagram of a multi-mode resistor-type digital-to-analog conversion circuit according to an embodiment of the present disclosure;

[0040] FIG10 is a schematic structural diagram of a multi-mode resistor-type digital-to-analog conversion circuit according to another embodiment of the present disclosure;

[0041] FIG11 is a schematic structural diagram of a multi-mode current steering digital-to-analog conversion circuit according to an embodiment of the present disclosure;

[0042] FIG12 is a schematic structural diagram of a multi-mode current-steering digital-to-analog conversion circuit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0044] Figure 5(a) is a schematic diagram of the structure of a differential latch circuit according to an embodiment of the present disclosure. As shown in Figure 5(a), the differential latch circuit includes a first-stage differential latch circuit I, a second-stage differential inverting circuit II, and a low-level shift circuit.

[0045] The pull-up end of the differential positive end of the second-stage differential inverter circuit II includes a first PMOS transistor M9 and a second PMOS transistor M10, the gate of the first PMOS transistor M9 is connected to the gate of the second PMOS transistor M10; the source of the first PMOS transistor M9 is connected to the power supply voltage; the drain of the first PMOS transistor M9 is connected to the source of the second PMOS transistor M10; the gate of the first PMOS transistor M9 and the gate of the second PMOS transistor M10 are also respectively connected to the data input end of the differential positive end of the second-stage differential inverter circuit; the pull-down end of the differential positive end of the second-stage differential inverter circuit includes a third PMOS transistor M15 and a first NMOS transistor M11, the third PMOS transistor M The drain of the third PMOS transistor M15 is connected to the source of the first NMOS transistor M11, and both are connected to the output end of a level shift circuit; the gate of the third PMOS transistor M15 is connected to the data input end of the differential positive end of the second-stage differential inverter circuit, and the source of the third PMOS transistor M15 is connected to the output end of the pull-down end of the differential negative end of the second-stage differential inverter circuit; the drain of the first NMOS transistor M11 is connected to the drain of the second PMOS transistor M10, and the gate of the first NMOS transistor M11 is connected to the data input end of the differential positive end of the second-stage differential inverter circuit; the circuit structure of the differential negative end of the first-stage differential latch circuit is symmetrical with the differential positive end of the first-stage differential latch circuit.

[0046] In this embodiment, as shown in FIG5( a ), the differential positive end of the second-stage differential inverter circuit further includes: a fourth PMOS transistor M17 , wherein the source of the fourth PMOS transistor M17 is connected to the power supply voltage, the gate of the fourth PMOS transistor M17 is connected to the data input end of the differential negative end of the second-stage differential inverter circuit, and the drain of the fourth PMOS transistor M17 is connected to the first series node between the first PMOS transistor M9 and the second PMOS transistor M10 to adjust the voltage of the series node.

[0047] In one exemplary embodiment, the fourth PMOS transistor may also be connected to the second-stage differential inverter circuit in other ways. As shown in FIG5(b), the source of the fourth PMOS transistor M17 is connected to the source of the fifth PMOS transistor M18, which is located at the negative differential terminal of the second-stage differential inverter circuit and corresponds to the fourth PMOS transistor M17; the gate of the fourth PMOS transistor M17 is connected to the data input terminal of the negative differential terminal of the second-stage differential inverter circuit; and the drain of the fourth PMOS transistor M17 is connected to the first series connection node between the first PMOS transistor M9 and the second PMOS transistor M10.

[0048] In one exemplary embodiment, the fourth PMOS transistor may also be connected to the second-stage differential inverter circuit in other ways. As shown in FIG5(c), the source of the fourth PMOS transistor M17 is connected to the power supply voltage, the gate of the fourth PMOS transistor M17 is connected to the data output terminal of the differential positive terminal of the second-stage differential inverter circuit, and the drain of the fourth PMOS transistor M17 is connected to the first series connection node between the first PMOS transistor M9 and the second PMOS transistor M10.

[0049] In this embodiment, the first series node is located between the drain of the first PMOS transistor M9 and the source of the second PMOS transistor M10.

[0050] FIG6 is a schematic diagram of the structure of a differential latch circuit according to another embodiment of the present disclosure. As shown in FIG6, the pull-up end of the differential positive end of the second-stage differential inverter circuit II includes a first PMOS transistor M9 and a second PMOS transistor M10, the gate of the first PMOS transistor M9 is connected to the gate of the second PMOS transistor M10; the source of the first PMOS transistor M9 is connected to the power supply voltage; the drain of the first PMOS transistor M9 is connected to the source of the second PMOS transistor M10; the gate of the first PMOS transistor M9 and the gate of the second PMOS transistor M10 are also respectively connected to the data input end of the differential positive end of the second-stage differential inverter circuit; the pull-down end of the differential positive end of the second-stage differential inverter circuit includes a third PMOS transistor M15 and a first NMOS transistor M11, the drain of the third PMOS transistor M15 is connected to the source of the first NMOS transistor M11, and together are connected to the output end of a level shift circuit; the third The gate of the PMOS transistor M15 is connected to the data input terminal of the differential positive terminal of the second-stage differential inverter circuit, and the source of the third PMOS transistor M15 is connected to the output terminal of the pull-down terminal of the differential negative terminal of the second-stage differential inverter circuit. The drain of the first NMOS transistor M11 is connected to the drain of the second PMOS transistor M10, and the gate of the first NMOS transistor M11 is connected to the data input terminal of the differential positive terminal of the second-stage differential inverter circuit. In this embodiment, at the differential positive terminal of the second-stage differential inverter circuit, a first series node between the first PMOS transistor M9 and the second PMOS transistor M10 is short-circuited with a second series node located at the differential negative terminal of the second-stage differential inverter circuit and corresponding to the first series node. The circuit structures of the differential negative terminal of the first-stage differential latch circuit are symmetrical with the differential positive terminal of the first-stage differential latch circuit.

[0051] In an exemplary embodiment, the width-to-length ratios of the PMOS and NMOS terminals in the first-stage differential latch circuit are set to be mismatched, and the intersection point of the differential latch circuit output is not located in the middle of the PMOS and NMOS terminals.

[0052] The two PMOS transistors at the pull-up end of the second-stage differential inverter circuit are connected in series, increasing the equivalent PMOS transistor channel length and reducing the equivalent PMOS transistor width-to-length ratio. The pull-down end uses a PMOS and an NMOS transistor structure, lowering the output crosspoint of the second-stage differential inverter. This improves linearity issues caused by the slow rising edge of the inverter output, resolves reliability issues, and addresses inter-symbol interference (ISI) issues. This improves the flexibility of adjusting the output data crosspoint.

[0053] Figure 7 is a schematic diagram of the structure of a switch driver according to an embodiment of the present disclosure. As shown in Figure 7, the switch driver includes multiple switch driver units, wherein each switch driver unit includes: multiple data transmission links, each data transmission link includes the differential latch circuit in the above embodiment.

[0054] In an exemplary embodiment, the multiple data transmission links include a real data transmission link for transmitting real data and a dummy data transmission link for transmitting dummy data.

[0055] FIG8 is a schematic diagram of the structure of a switch driver according to another embodiment of the present disclosure. As shown in FIG8 , in addition to all the structures shown in FIG7 , the switch driver further includes: a plurality of XOR logic units, each having a first input connected to the output of the differential latch circuit in each data transmission link, and a second input connected to the clock input; and a plurality of data selectors, each having a first input connected to the output of the differential latch circuit in each data transmission link, and a second input connected to the output of each XOR logic unit.

[0056] Figure 9 is a schematic diagram of the structure of a multi-mode resistor-type digital-to-analog conversion circuit according to an embodiment of the present disclosure. As shown in Figure 9, the multi-mode resistor-type digital-to-analog conversion circuit includes the switch driver of Figure 7 and a digital-to-analog conversion core circuit connected to the output terminal of the switch driver.

[0057] In an exemplary embodiment, the digital-to-analog conversion core circuit includes multiple digital-to-analog converter core units, each of the digital-to-analog converter core units including: an inverter INV, the input end of the inverter being connected to the output end of the real data transmission link of the switch driver unit; a unit resistor, the first end of the unit resistor being connected to the output end of the inverter, and the second end of the unit resistor being connected to a load resistor; and a first Dummy load, the first Dummy load being connected to the output end of the Dummy data transmission link of the switch driver unit.

[0058] In an exemplary embodiment, as shown in FIG10 , the switch driver in the multi-mode resistive digital-to-analog conversion circuit is the switch driver shown in FIG8 .

[0059] Figure 11 is a structural diagram of a multi-mode current steering type digital-to-analog conversion circuit according to an embodiment of the present disclosure. As shown in Figure 11, the multi-mode current steering type digital-to-analog conversion circuit includes the switch driver of Figure 7 and a digital-to-analog conversion core circuit connected to the output end of the switch driver, wherein the digital-to-analog conversion core circuit includes a plurality of digital-to-analog converter core units, each of the digital-to-analog converter core units including: a sixth PMOS tube, the gate of the sixth PMOS tube is connected to the output end of the real data transmission link of the driver unit, the drain of the sixth PMOS tube is connected to the load resistor and the output end of the digital-to-analog conversion core circuit, and the source of the sixth PMOS tube is connected to the current source output end; a second Dummy load, the second Dummy load is connected to the output end of the Dummy data transmission link of the switch driver unit.

[0060] In an exemplary embodiment, as shown in FIG12 , the switch driver in the multi-mode resistive digital-to-analog conversion circuit is the switch driver shown in FIG8 .

[0061] To facilitate understanding of the technical solutions provided by the present disclosure, embodiments of specific scenarios will be described in detail below.

[0062] To overcome the problems of the prior art, such as the limitations of output data cross point adjustment and the difficulty in coordinating with level shift circuits, which can significantly reduce the linearity of the overall circuit, the present embodiment provides a latch circuit (in this embodiment, the DFF and MUX circuits can also be similarly designed) with flexible output data cross point adjustment and high compatibility with level shift circuits, as well as a high-linearity switch driver circuit using the latch circuit and a high-linearity digital-to-analog converter circuit using the switch driver circuit. Specifically, the operations of the present embodiment include:

[0063] The width-to-length ratios of the PMOS and NMOS terminals of the first-stage differential latch circuit of the latch are intentionally designed to be mismatched, making the crossover point of the latch output higher and the crossover point of the inverter output lower.

[0064] The two PMOS transistors at the pull-up end of the Latch second-stage differential inverter circuit are connected in series to increase the channel length of the equivalent PMOS and reduce the equivalent PMOS width-to-length ratio. The pull-down end adopts a CMOS structure to lower the inverter output cross point and improve the linearity problem caused by the slow rising edge of the inverter output.

[0065] In the pull-up terminal series node of the second-stage differential inverter circuit of the latch, an additional PMOS tube is added to adjust the voltage of the series node to solve the reliability problem and the problem of inter-symbol interference.

[0066] As shown in FIG5( a ), the latch circuit structure in the embodiment of the present disclosure includes the following modules: a first-stage differential latch circuit I and a second-stage differential inverter circuit II.

[0067] In the first-stage differential latch circuit I, the circuits for the differential positive and negative terminals are identical. Taking the differential positive terminal as an example, the latch pull-up terminal consists of two PMOS transistors (M1) and M2, whose gates are connected to the input data (din) and the input clock (clkp), respectively. The latch pull-down terminal consists of two NMOS transistors (M3) and M4, whose gates are connected to the input data (din) and the input clock (clkn), respectively. The pull-up and pull-down terminals can be designed to match each other. Specifically, the width-to-length ratios of the PMOS and NMOS terminals are designed to ensure similar pull-up and pull-down current capabilities, placing the latch output crossover point in the middle.

[0068] In this embodiment, the width-to-length ratios of the PMOS and NMOS terminals can be intentionally mismatched, so that the latch output crossover point is not in the middle. For example, if the pull-up and pull-down capabilities are the same when the PMOS and NMOS width-to-length ratios are equal, the PMOS width-to-length ratio can be designed to be twice that of the NMOS, so that the latch output crossover point is higher.

[0069] In the second-stage differential inverter circuit II, the circuits for the differential positive and negative terminals are identical. Taking the differential positive terminal as an example, the inverter pull-up terminal consists of two PMOS transistors (PMOSs) M9 and M10 connected in series. Specifically, the gates of the two PMOS transistors are short-circuited, the source of one PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the other PMOS transistor, and the drain of the other PMOS transistor is pulled out to connect to the inverter pull-down terminal. At the series node of the two PMOS transistors, an additional PMOS transistor (PMOS) M17 is added. Its source is connected to the power supply voltage, its drain is connected to the series node, and its gate is connected to the input of the inverter at the other end of the differential. This additional PMOS transistor effectively controls the voltage at the series node. The pull-down terminal of the second-stage differential inverter circuit is a CMOS structure, consisting of a PMOS transistor M15 and an NMOS transistor M11. The PMOS transistor drain is connected to the NMOS transistor source and to the output of a level shift circuit, ensuring that the inverter output low voltage is not ground but a value that meets design requirements.

[0070] In an exemplary embodiment, the differential latch includes at least the following variants:

[0071] 1. There are many variations of adjusting the differential output cross-point by connecting PMOS in series at the pull-up end of the inverter. The number of PMOS in series can be multiple. Depending on the design requirements, it can also be changed to NMOS in series, CMOS in series, or a combination of various series connections, and applied to the pull-up end or the pull-down end. In addition, the MOS series method can be applied to the subsequent inverter, the previous latch, both stages, or neither stage.

[0072] Second, there are many variations on the method for controlling the potential of the PMOS series connection point, such as those shown in Figures 5(b), 5(c), and 6. In Figure 6, the series connection points of M9 and M10 and the series connection points of M12 and M13 in the second-stage inverter are directly short-circuited. In Figure 5(b), the source terminals of the two additional PMOS transistors added to the PMOS series connection point are not connected to the power supply but are directly short-circuited together. In Figure 5(c), the gate terminals of the two additional PMOS transistors added to the PMOS series connection point are instead controlled by dout and doutb. In addition to these proposed variations, there are many more readily conceivable methods based on the methods described in this disclosure, all aimed at avoiding the adverse effects caused by the high-impedance state of the PMOS series connection point. Clearly, these methods for controlling the potential of the series connection point can be extended to multiple PMOS series connections, NMOS series connections, CMOS series connections, and various series connection combinations, and can be applied to pull-up or pull-down terminals. Depending on the actual design, some series connection points can be used while others are not. Furthermore, in addition to being applied to the subsequent-stage inverter, they can also be applied to the preceding-stage latch, or to both or neither stage.

[0073] 3. Using a CMOS structure at the pull-down end of the inverter ensures that its pull-down capability under different process corners can have multiple variations. Depending on the design requirements, it can also be changed to a combination of multiple CMOS in series or parallel, and applied to the pull-up end or the pull-down end. In addition, this CMOS structure can be used in the subsequent inverter, the previous latch, or both stages, or neither stage.

[0074] 4. The level shift circuit can be added to the pull-up or pull-down end of the inverter according to the design requirements. The output voltage of the level shift circuit can be higher or lower than the ground voltage, or higher or lower than the power supply voltage. In addition, the level shift circuit can be used in the subsequent inverter or the latch of the previous stage, or in both stages, or neither stage.

[0075] 5. The above points 1 to 4 can be extended to the various traditional latch variations mentioned above, and can also be similarly extended to the design of DFF, MUX and other circuits with synchronization functions and their variations, and can also be extended to the design of other sequential logic circuits, and can also be extended to the design of combinational logic circuits.

[0076] 6. The above points 1 to 4 can be extended to switch drivers that use these latches, DFFs, MUXs, other sequential logic, combinational logic and other circuits and their variants, can also be extended to the various variants of the traditional switch drivers mentioned above, and can also be extended to high-speed digital-to-analog converters (DACs) that use these switch drivers and their variants.

[0077] 7. The above points 1 to 4 can be further extended to all analog circuits and mixed analog and digital circuits that need to use these technologies in whole or in part.

[0078] In an exemplary embodiment, FIG. 5( a ) assumes that the design requirement is that the inverter differential output is a low cross-point, and the present disclosure is implemented in the following manner:

[0079] By intentionally designing the width-to-length ratio of the latch's PMOS and NMOS terminals to be mismatched, the crossover point of the latch output is higher, and the inverter output crossover point is lower.

[0080] The two PMOS M9 and M10 at the pull-up end of the inverter are connected in series, which can effectively increase the channel length of the equivalent PMOS and reduce the width-to-length ratio of the equivalent PMOS, which is beneficial to lowering the inverter output cross point.

[0081] The pull-down end of the inverter is a CMOS structure, including PMOS M15 and NMOS M11. The CMOS structure can better guarantee the pull-down capability of the inverter under different process angles, especially the extreme process conditions of SNFP and FNSP, which is conducive to lowering the inverter output cross point.

[0082] Figure 5(a) assumes that the design requires the inverter output to be at a low level other than ground potential. Therefore, a level shifter circuit's output is introduced at the pull-down terminal. If the output of this level shifter circuit is higher than ground potential, this will reduce the current capability of the inverter's pull-down terminal, hindering the ability to lower the inverter output cross-point. The three methods described above are needed to compensate for this adverse effect. Conversely, if the output of the level shifter circuit is lower than ground potential, it will help lower the inverter output cross-point.

[0083] The differential latch (Latch) circuit in the above embodiment of the present disclosure can be used to implement the switch driver circuit of the embodiment of the present disclosure. As shown in Figure 7, the first switch driver structure of the embodiment of the present disclosure adopts a conventional data format, and data sampling is performed on the rising edge of the clock. The upper two paths transmit real signals, and the lower two paths transmit Dummy data. At each data sampling point, if the real data does not flip, the Dummy data flips; if the real data flips, the Dummy data does not flip. The third-level Latch adopts the latch (Latch) shown in any of Figures 5 (a), 5 (b), 5 (c) or 6 of the present disclosure.

[0084] As shown in Figure 7, in this embodiment, the real data Din and Db_in of the upper two paths pass through the latches of the first two stages, are clocked by Fclk stage by stage, and are sent to the latch of the present disclosure before being output to the next stage. The dummy data Dum_in and Dumb_in of the lower two paths are output to the next stage through the same path.

[0085] FIG8 is a schematic diagram of the second switch driver structure according to an embodiment of the present disclosure, which is characterized by compatibility between the normal mode and the mixing mode. In the mixing mode, data changes will occur on both the rising and falling edges of the clock. The data corresponding to the falling edge is the inverse of the data corresponding to the rising edge, which is equivalent to the mixing effect of the real signal and the clock signal. Finally, a bandpass transfer function centered on Fclk is realized at the DAC output (the normal mode is a low-pass transfer function), which is very helpful for applications with low bandwidth and high-intermediate frequencies. Among them, only one of the Latch, XOR, and MUX can adopt the technology of the embodiment of the present disclosure, or a combination of the technologies of the embodiment of the present disclosure can be adopted.

[0086] In an exemplary embodiment, the first and second switch drivers described above include at least the following variations:

[0087] Since the technology involved in the latch in the embodiment of the present disclosure can be extended to the various traditional latch variations mentioned above, it can also be similarly extended to the design of DFF, MUX and other circuits with synchronization functions and their variations, and can also be extended to the design of other sequential logic circuits and the design of combinational logic circuits. Therefore, as long as the switch driver that applies the technology involved in the latch of the present disclosure, it falls within the protection scope of the embodiment of the present disclosure, including the various traditional switch driver variations mentioned above, and also including the various traditional switch driver variations not mentioned above.

[0088] The differential latch circuits in the aforementioned embodiments of the present disclosure can also be used to implement two multi-mode, low-power, high-linearity digital-to-analog converter (DAC) circuits. The two DAC circuits differ in the structure of the DAC core slices: a multi-mode current-steering DAC circuit of the present disclosure and a multi-mode resistive DAC of the present disclosure. These two DACs are described in detail in the specific implementations below.

[0089] FIG9 is a schematic diagram of a first multi-mode resistive DAC circuit structure according to an embodiment of the present disclosure. FIG9 only includes the first switch driver (Switch Driver) and DAC core circuit (DAC Core) of the present disclosure, and other parts are not included. The switch driver of the present disclosure includes a latch (Latch) of the present disclosure. According to the number of DAC bits and segmentation, the switch driver needs to be divided into multiple units (Slices) for multi-bit data output (N are shown in FIG9). The switch driver unit adopts the switch driver structure of the present disclosure to achieve high speed and high linearity. Similarly, the DAC core circuit will be divided into multiple units (Slices) for data reception.

[0090] As shown in Figure 9, the actual data D output by the switch driver <n:0>and Db <n:0>The inputs of the inverter circuits INV1 and INV2 in the DAC core circuit are connected to select the power supply potential or the ground potential to the left ports of the unit resistors Ru1 and Ru2. The right ports of Ru1 in all DAC core circuit units can be connected together and connected to the load resistor as the positive end of the differential output. The right ports of all Ru2 are connected together as the negative end of the differential output, forming a resistor network as a whole. <n:0>and Db <n:0>The number of Ru1 and Ru2 connected to the power supply / ground potential in the resistor network is different due to the different data, which realizes the linear conversion relationship between the output differential voltage Vout and the input data. <n:0>and Dumb <n:0>After entering the core circuit unit, it is connected to the Dummy load, which is similar to the real data D <n:0>and Db <n:0>The load is consistent.

[0091] FIG10 is a schematic diagram of a second multi-mode resistive DAC circuit structure according to an embodiment of the present disclosure. This diagram only includes the second switch driver and DAC core circuit of the present disclosure; other components are omitted. Except for the switch driver, the other components are consistent with FIG9 .

[0092] In an exemplary embodiment, the first and second multi-mode resistive DACs of the present disclosure include at least the following variations:

[0093] 1. The switch driver of the DAC can be any variation of the switch driver described above.

[0094] Second, the DAC core circuit shown in Figures 9 and 10 is a basic resistive DAC structure. This disclosure is applicable to other resistive DAC variants. Furthermore, the power supply potential and ground potential can be replaced with positive and negative reference potentials, and Ru1 and Ru2 can be set to different resistance values ​​in different DAC core circuit units to achieve different weights.

[0095] 3. To ensure that the loads on the DAC core circuit input are approximately the same as those on the real data, a dummy load is added to the DAC core circuit. This dummy load can be simplified or removed based on actual needs.

[0096] Figure 11 is the first multi-mode current steering DAC circuit structure disclosed in the present invention. The figure only includes the first switch driver (Switch Driver) and DAC core circuit (DAC Core) disclosed in the present invention, and other parts are not included. The switch driver disclosed in the present invention includes the latch (Latch) disclosed in the present invention. According to the number of DAC bits and segmentation, the switch driver needs to be divided into multiple units (Slice) for multi-bit data output (N are shown in Figure 11). The switch driver unit can adopt the switch driver structure disclosed in the present invention to achieve high speed and high linearity. Similarly, the DAC core circuit will be divided into multiple units (Slice) for data reception.

[0097] As shown in Figure 11, the actual data D output by the switch driver <n:0>and Db <n:0>They are connected to the gates of the switch circuits Switch1 and Switch2 in the DAC core circuit respectively, and are used to select the output current of the current source Current Source to the upper port of the load resistor RL1 or RL2 (that is, the positive or negative end of the DAC differential output). The drains of Switch1 of all DAC core circuit units are connected together, and the drains of all Switch2 are connected together. For the entire DAC core circuit, according to D <n:0>and Db <n:0>Due to the different data, the total current flowing to RL1 and the total current flowing to RL2 are different, and the corresponding differential output voltage Vout is also different, which ultimately achieves a linear conversion relationship between the output differential voltage Vout and the input data. <n:0>and Dumb <n:0>After entering the core circuit unit, it is connected to the Dummy load, which is similar to the real data D <n:0>and Db <n:0>The load is consistent.

[0098] Figure 12 shows the second multi-mode current-steering DAC circuit structure of the present disclosure. This diagram only includes the switch driver and DAC core circuit of the second multi-mode current-steering DAC of the present disclosure; other components are omitted. Except for the switch driver, the other components are consistent with those in Figure 11.

[0099] In an exemplary embodiment, the first and second multi-mode current-steering DACs in the present disclosure include at least the following variations:

[0100] 1. The switch driver of the DAC can be any variation of the switch driver described above.

[0101] 2. The DAC core circuit shown in Figures 11 and 12 is a basic current-steering DAC structure. The present disclosure can be extended to other current-steering DAC variant structures.

[0102] Third, to ensure that the loads on the DAC core circuit input are approximately the same as those on the real data, a dummy load is added to the DAC core circuit. This dummy load can be simplified or removed depending on actual needs.

[0103] Through the above-mentioned embodiments of the present disclosure, the two PMOS transistors M9 and M10 connected in series at the pull-up end of the inverter can effectively increase the channel length of the equivalent PMOS, reduce the equivalent PMOS width-to-length ratio, and together with the pull-down end, realize the control of the inverter output cross point. Compared with the method of directly using a single PMOS and reducing its channel width, the two PMOS transistors connected in series can increase the effective area of ​​the equivalent PMOS tube, improve the mismatch problem caused by the small size of the MOS tube at the pull-up end, and the resulting linearity problem; compared with the method of directly using a single PMOS and increasing its channel length, in many small-scale processes, the performance of short-channel length devices is often more optimized, which can improve the linearity problem caused by the slow rising edge of the inverter output.

[0104] In the disclosed embodiment, the additional PMOS M17 at the series node between the two PMOS transistors M9 and M10 effectively controls the voltage at the series node. If the two PMOS series nodes are left untouched, the node will be in a high-impedance state when the inverter input is high. This can easily interfere with the voltage at the series node, causing numerous problems in high-speed designs. For example, when the inverter input voltage rapidly changes from a low level to a high level, the voltage at the series node will also rapidly increase, even exceeding the power supply voltage, leading to design reliability issues. At this time, the series node voltage is in a high-impedance state and requires a long time to recover from a state above the power supply voltage to a normal state (close to the power supply voltage). Two situations may occur in this situation. The first is that during this recovery process, the inverter input voltage rapidly switches from a high level to a low level again. The PMOS series node will first discharge from a state above the power supply voltage. This lowers the PMOS series node voltage, pulling the inverter output node high. Ultimately, both the PMOS series node and the inverter output are close to the power supply voltage. The second situation is that the inverter input voltage remains high for a long time, allowing the PMOS series node to return to a normal state (close to the power supply voltage). At this time, the PMOS series node will discharge from a state close to the power supply voltage, pulling the inverter output node high. In these two situations, the pull-up time of the inverter output is different, which may cause inter-symbol interference problems in high-speed circuit design.

[0105] The aforementioned issues can be resolved by adding an additional PMOS transistor to the series node of the two PMOS transistors. When the voltage at the inverter input on one differential end changes rapidly from a low level to a high level, the voltage at the series node will increase rapidly and may even briefly exceed the power supply voltage. Since the gate of the additional PMOS transistor is connected to the input of the inverter on the other differential end (from a high level to a low level), the PMOS transistor turns on and quickly pulls the voltage at the series node back to the power supply voltage, avoiding the aforementioned reliability and inter-symbol interference issues. When the voltage at the inverter input on one differential end changes rapidly from a high level to a low level, the additional PMOS transistor turns off, without affecting the pull-up characteristics and cross-point control of the inverter PMOS transistor.

[0106] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0107] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations.

[0108] Any modification, equivalent replacement, improvement, etc. should be included in the protection scope of this disclosure.

Claims

1. A differential latch circuit, comprising a first-stage differential latch circuit, a second-stage differential inverting circuit and a low-level shift circuit connected in sequence, wherein: The pull-up end of the differential positive end of the second-stage differential inverting circuit includes a first PMOS tube and a second PMOS tube, the gate of the first PMOS tube is connected to the gate of the second PMOS tube; the source of the first PMOS tube is connected to the power supply voltage; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are also respectively connected to the data input end of the differential positive end of the second-stage differential inverting circuit; The pull-down end of the differential positive end of the second-stage differential inverter circuit includes a third PMOS tube and a first NMOS tube, the drain of the third PMOS tube is connected to the source of the first NMOS tube, and is connected together to the output end of a level shift circuit; the gate of the third PMOS tube is connected to the data input end of the differential positive end of the second-stage differential inverter circuit, and the source of the third PMOS tube is connected to the output end of the pull-down end of the differential negative end of the second-stage differential inverter circuit; the drain of the first NMOS tube is connected to the drain of the second PMOS tube, and the gate of the first NMOS tube is connected to the data input end of the differential positive end of the second-stage differential inverter circuit; the circuit structure of the differential negative end of the first-stage differential latch circuit is symmetrical with the differential positive end of the first-stage differential latch circuit.

2. The circuit according to claim 1, wherein The differential positive terminal of the second-stage differential inverting circuit also includes a fourth PMOS tube, wherein: The source of the fourth PMOS tube is connected to the power supply voltage, the gate of the fourth PMOS tube is connected to the data input terminal of the differential negative terminal of the second-stage differential inverter circuit, and the drain of the fourth PMOS tube is connected to the first series node between the first PMOS tube and the second PMOS tube; or, The source of the fourth PMOS tube is connected to the source of the fifth PMOS tube located at the differential negative end of the second-stage differential inverter circuit and corresponding to the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the data input end of the differential negative end of the second-stage differential inverter circuit, and the drain of the fourth PMOS tube is connected to the first series node between the first PMOS tube and the second PMOS tube; or, The source of the fourth PMOS tube is connected to the power supply voltage, the gate of the fourth PMOS tube is connected to the data output end of the differential positive end of the second-stage differential inversion circuit, and the drain of the fourth PMOS tube is connected to the first series node between the first PMOS tube and the second PMOS tube.

3. The circuit according to claim 1, wherein: A first series node between the first PMOS tube and the second PMOS tube is short-circuited with a second series node located in the differential negative end of the second-stage differential inverter circuit and corresponding to the first series node, wherein the first series node is located between the drain of the first PMOS tube and the source of the second PMOS tube.

4. The circuit according to claim 1, wherein: The width-to-length ratios of the PMOS tube end and the NMOS tube end in the first-stage differential latch circuit are set to be mismatched, and the intersection point of the output of the differential latch circuit is not located in the middle of the PMOS tube end and the NMOS tube end.

5. A switch driver, comprising a plurality of switch driver units, wherein each switch driver unit comprises a plurality of data transmission links, and each data transmission link comprises the differential latch circuit according to any one of claims 1 to 3.

6. The switch driver according to claim 5, wherein: The multiple data transmission links include a real data transmission link for transmitting real data and a dummy data transmission link for transmitting dummy data.

7. The switch driver according to claim 5, further comprising: A plurality of XOR logic units, wherein a first input end of each XOR logic unit is connected to an output end of the differential latch circuit in each data transmission link, and a second input end of the XOR logic unit is connected to a clock input end; A plurality of data selectors, wherein the first input end of each of the data selectors is connected to the output end of the differential latch circuit in each of the data transmission links, and the second input end of each of the data selectors is respectively connected to the output end of the XOR logic unit.

8. A digital-to-analog conversion circuit, comprising the switch driver according to any one of claims 4 to 6 and a digital-to-analog conversion core circuit connected to an output terminal of the switch driver.

9. The digital-to-analog conversion circuit according to claim 8, wherein: The digital-to-analog conversion core circuit includes a plurality of digital-to-analog converter core units, each of which includes: an inverter, the input end of the inverter being connected to the output end of the real data transmission link of the switch driver unit; A first Dummy load is connected to an output end of the Dummy data transmission link of the switch driver unit.

10. The digital-to-analog conversion circuit according to claim 8, wherein: The digital-to-analog conversion core circuit includes a plurality of digital-to-analog converter core units, each of which includes: a sixth PMOS tube, wherein the gate of the sixth PMOS tube is connected to the output end of the real data transmission link of the driver unit, the drain of the sixth PMOS tube is connected to the load resistor and the output end of the digital-to-analog conversion core circuit, and the source of the sixth PMOS tube is connected to the power supply voltage; A second Dummy load is connected to an output end of the Dummy data transmission link of the switch driver unit.

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