Pulse DC power source supply for capacitive load, and operating method therefor

Abstract

A pulse DC power source supply for a capacitive load, and an operating method therefor are disclosed. According to one aspect of the present disclosure, the provided pulse DC power source supply for applying a pulse DC voltage to a capacitive load comprises: a multi-level inverter for converting, into an output voltage having three or more voltage levels, a DC voltage applied from one or more DC voltage sources; and an inductor connected in series between the multi-level inverter and the capacitive load, wherein the multi-level inverter outputs a predefined first reference voltage in a second time interval, and outputs each voltage of polarities differing from that the first reference voltage in a first time interval before the second time interval and in a third time interval after the second time interval, and the pulse DC voltage rises or falls due to resonance between the capacitive load and the inductor.

Description

Pulse DC power supply for capacitive load and operating method thereof

[0001] The present disclosure relates to a pulse DC power supply for a capacitive load and an operating method thereof.

[0002] The content described below merely provides background information related to the present embodiment and does not constitute prior art.

[0003] In order to apply a pulsed DC (Direct Current) voltage to a capacitive load, a pulse-shaped current proportional to the rising slope of the voltage must be supplied.

[0004] When attempting to apply a pulsed DC voltage by switching a voltage source, ringing cannot be avoided due to the resonance of the wiring inductance (or stray inductance) and the capacitive load. For example, the entire system including the voltage source and the capacitive load can be modeled as an RLC circuit in which a resistor (R), an inductor (L), and a capacitor (C) are connected in series, as illustrated in Fig. 1a. In such a system, the pulsed DC voltage applied to the capacitive load has a response characteristic similar to the unit step response illustrated in Fig. 1b. In particular, when the damping ratio (ζ) is sufficiently small, the system exhibits an unamped or under-damped operation.

[0005] To avoid ringing, a method of increasing the voltage with a current source and limiting the output to a specific voltage using a voltage source can be used. Figures 2a and 2b show a current source (I S ) and voltage source (V S) is shown to apply a pulse voltage to a capacitive load and its operating waveform. The voltage source and current source shown in Fig. 2a can be implemented as in Fig. 2c. When using such a circuit, the power supply can only output a symmetrical bipolar pulse having a positive peak and a negative peak of the same size, and a more complex circuit is required to make the sizes of the positive peak and the negative peak of the pulse different. In addition, if there is a wiring inductance (or stray inductance) between the capacitive load and the current source, ringing, such as the response characteristics of the RLC series circuit described above, cannot be avoided.

[0006] The present disclosure aims to provide a pulse DC power supply and an operating method thereof that can apply a pulse DC voltage while minimizing the ringing phenomenon occurring in a capacitive load using a simple circuit structure.

[0007] The present disclosure aims to provide a pulsed DC power supply and a method of operating the same, which can independently control the positive and negative maximum values ​​of a pulse and / or control the amplitude of a pulse for each pulse.

[0008] The present disclosure aims to provide a pulse DC power supply and an operating method thereof that are not affected by wiring inductance (or stray inductance) that must physically exist on a circuit.

[0009] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0010] According to one aspect of the present disclosure, there is provided a pulse DC power supply for applying a pulse DC voltage to a capacitive load, comprising: a multi-level inverter for converting a DC voltage applied from one or more DC voltage sources into an output voltage having three or more voltage levels; and an inductor connected in series between the multi-level inverter and the capacitive load, wherein the multi-level inverter is configured to output a first reference voltage defined in advance in a second time period, and to output a voltage having a different polarity from the first reference voltage in a first time period before the second time period and a third time period after the second time period, respectively, and wherein the pulse DC voltage rises or falls due to resonance between the capacitive load and the inductor.

[0011] According to another aspect of the present disclosure, there is provided a method of operating a pulse DC power supply, comprising: a multi-level inverter that converts a DC voltage applied from one or more DC voltage sources into an output voltage having three or more voltage levels; and an inductor connected in series between a capacitive load, the method comprising: a step in which the multi-level inverter outputs a first voltage having a first polarity with respect to a first reference voltage predefined in a first time period; a step in which the multi-level inverter outputs the first reference voltage in a second time period following the first time period; and a step in which the multi-level inverter outputs a second voltage having a second polarity distinct from the first polarity with respect to the first reference voltage in a third time period following the second time period, wherein the pulse DC voltage applied by the pulse DC power supply to the capacitive load rises or falls due to resonance between the capacitive load and the inductor.

[0012] In some embodiments, the multi-level inverter can output voltages having different absolute values ​​in the second time interval and the third time interval.

[0013] In some embodiments, the pulsed DC voltage may have three or more voltage levels.

[0014] In some embodiments, the pulse DC power supply may further include a controller that controls the multi-level inverter.

[0015] In some embodiments, the length of the second time interval and / or the magnitude of the first reference voltage may be adjusted such that ringing of the pulsed DC voltage applied to the capacitive load is minimized.

[0016] In some embodiments, the multi-level inverter may be configured to output a second reference voltage that is distinct from the first reference voltage in a fourth time interval prior to the first time interval and / or after the third time interval.

[0017] In some embodiments, the multi-level inverter comprises a plurality of inverters, wherein output terminals of the plurality of inverters can be connected in series.

[0018] In some embodiments, at least some of the first inverters among the plurality of inverters may be configured to output a voltage having a first polarity relative to zero voltage during the first time interval. Additionally or alternatively, at least some of the second inverters among the plurality of inverters may be configured to output the zero voltage during the second time interval. Additionally or alternatively, at least some of the third inverters among the plurality of inverters may be configured to output a voltage having a second polarity relative to the zero voltage during the third time interval. The second polarity may be the same as or different from the first polarity. Additionally or alternatively, at least some of the fourth inverters among the plurality of inverters may be configured to output the zero voltage during the fourth time interval.

[0019] In some embodiments, the first polarity, the number of the first inverters, or a combination thereof, may be different from the second polarity, the number of the third inverters, or a combination thereof. Additionally or alternatively, the number of the fourth inverters may be different from the number of the second inverters.

[0020] In some embodiments, the maximum and minimum values ​​of the pulse DC voltage can be independently adjusted based on the number of the first inverters and the number of the third inverters. Additionally or alternatively, the slew rate at the rising edge and the slew rate at the falling edge of the pulse DC voltage can be independently adjusted based on the number of the first to fourth inverters.

[0021] In some embodiments, the pulsed DC voltage may have an amplitude and / or slew rate that gradually changes over a plurality of consecutive pulse periods, each of the plurality of pulse periods including the first time interval, the second time interval, the third time interval, and the fourth time interval.

[0022] In some embodiments, the multi-level inverter can output a different voltage in each of the first time intervals of adjacent pulse periods, each pulse period including the first time interval, the second time interval, and the third time interval, and can output a different voltage in the third time interval of each of the adjacent pulse periods.

[0023] In some embodiments, the number of the first inverters, the number of the second inverters, the number of the third inverters, the number of the fourth inverters, or any combination thereof, corresponding to the adjacent pulse periods may be different from each other.

[0024] In some embodiments, the multi-level inverter may output a reference voltage that is higher than a midpoint voltage between a positive maximum value and a negative maximum value of the pulse DC voltage during one of the second time interval and the fourth time interval during which the capacitive load is charged. Additionally or alternatively, the multi-level inverter may output a reference voltage that is lower than the midpoint voltage during another of the second time interval and the fourth time interval during which the capacitive load is discharged.

[0025] In some embodiments, the plurality of inverters may receive DC voltage from different DC voltage sources, wherein at least some of the DC voltage sources may provide a DC voltage having a voltage level that is distinct from the other DC voltage sources.

[0026] In some embodiments, the difference between the reference voltage and the voltage output by the multi-level inverter in the first time interval may have an absolute value different from the difference between the reference voltage and the voltage output by the multi-level inverter in the third time interval.

[0027] According to an embodiment of the present disclosure, a pulsed DC voltage can be applied to a capacitive load while minimizing the ringing phenomenon.

[0028] According to an embodiment of the present disclosure, a pulsed current can be supplied to a capacitive load by utilizing resonance between an output inductor and a load capacitor.

[0029] According to an embodiment of the present disclosure, by using a plurality of inverters connected in series (e.g., full bridge inverters), the positive and negative maximum values ​​of a pulse can be independently controlled and / or the amplitude of each pulse can be controlled differently.

[0030] According to an embodiment of the present disclosure, by using a plurality of inverters connected in series, the slew rate at the rising edge and the slew rate at the falling edge of a pulse can be independently controlled and / or the slew rate of each pulse can be controlled differently.

[0031] According to an embodiment of the present disclosure, by controlling an intermediate stage voltage for causing resonance of an output inductor and a load capacitor using a plurality of inverters connected in series, voltage ringing occurring in a capacitive load can be minimized despite the attenuation of resonance due to load resistance.

[0032] According to an embodiment of the present disclosure, a high-voltage pulse DC voltage can be supplied to a capacitive load by using a plurality of inverters connected in series.

[0033] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0034] Figures 1a and 1b are exemplary diagrams showing an RLC series circuit and its unit step response.

[0035] Figures 2a to 2c are exemplary diagrams showing a circuit that applies a pulse voltage to a capacitive load using a current source and a voltage source and its operating waveform.

[0036] FIG. 3 is a circuit diagram schematically illustrating a pulse DC power supply according to one embodiment of the present disclosure.

[0037] FIG. 4a and FIG. 4b are diagrams showing an example of a circuit configuration and an operating waveform thereof when a pulse DC power supply according to one embodiment of the present disclosure includes a 3-level inverter.

[0038] FIG. 5a and FIG. 5b are diagrams showing another example of a circuit configuration and an operating waveform thereof when a pulse DC power supply according to one embodiment of the present disclosure includes a 3-level inverter.

[0039] FIG. 6a and FIG. 6b are diagrams showing an example of a circuit configuration and an operating waveform thereof when a pulse DC power supply according to one embodiment of the present disclosure includes an M-level inverter (M is 4 or more).

[0040] FIG. 7a and FIG. 7b are diagrams showing another example of a circuit configuration and an operating waveform thereof when a pulse DC power supply according to one embodiment of the present disclosure includes an M-level inverter (M is 4 or more).

[0041] FIG. 8 is a diagram showing an example of a single-pulse mode operation waveform of a pulse DC power supply according to one embodiment of the present disclosure.

[0042] FIG. 9 is a diagram showing another example of a single-pulse mode operation waveform of a pulse DC power supply according to one embodiment of the present disclosure.

[0043] Hereinafter, some embodiments of the present disclosure will be described in detail using exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings. Furthermore, when describing the present disclosure, detailed descriptions of related known structures or functions will be omitted if they are deemed to obscure the gist of the present disclosure.

[0044] In describing components of embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated otherwise.

[0045] The detailed description set forth below, together with the accompanying drawings, is intended to explain exemplary embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced.

[0046] FIG. 3 is a circuit diagram schematically illustrating a pulse DC power supply according to one embodiment of the present disclosure.

[0047] As shown in Fig. 3, the pulse DC power supply (30) includes a DC voltage source (300), a multi-level inverter (320), and an inductor (L O ), and the controller (340) may be included in whole or in part. Not all blocks illustrated in FIG. 3 are essential components, and some blocks may be added, changed, or deleted in other embodiments. For example, although FIG. 3 illustrates that the pulse DC power supply (30) includes the controller (340), in other examples, the controller (340) may be implemented as an external device configured separately from the pulse DC power supply (30). In other examples, the pulse DC power supply (30) may receive DC voltage from an external DC voltage source.

[0048] The multi-level inverter (320) receives a DC voltage (V) applied from a DC voltage source (300). S ) with an output voltage (V) having three or more voltage levels. INV ) can be converted into a single output voltage (V). Optionally, the multi-level inverter (320) converts multiple DC voltages applied from multiple DC voltage sources into a single output voltage (V INV ) can also be converted to .

[0049] Output voltage (V) of the multi-level inverter (320) INV ) can have three voltage levels: a predetermined positive voltage, a predetermined negative voltage, and an intermediate voltage between the positive and negative voltages. Optionally, the output voltage (V INV) may have one or more voltage levels between the positive and neutral voltages. Additionally or alternatively, the output voltage (V INV ) can have one or more voltage levels between the negative voltage and the intermediate voltage.

[0050] A multi-level inverter (320) may include one or more switching elements. The switching elements may be implemented as, for example, transistors.

[0051] Inductor (L O ) is a multi-level inverter (320) and a capacitive load (C O ) are connected in series between them. For example, an inductor (L O ) is electrically connected to the positive output terminal of the multi-level inverter (320), and the inductor (L O ) is a capacitive load (C O ) is electrically connected to one end of the capacitive load (C O ) can be electrically connected to the negative output terminal of the multi-level inverter (320).

[0052] Capacitive load (C O ) is an inductor (L O ) and capacitive load (C O ) can be charged and discharged by resonance between the capacitors. That is, the capacitive load (C O ) voltage at both ends (hereinafter referred to as 'pulse DC voltage') (V O ) is an inductor (L O ) and capacitive load (C O ) can rise or fall by resonance between them.

[0053] Referring to Fig. 1b, an LC series circuit without resistance has no damping (ζ = 0, undamped), and can repeat resonance infinitely. The resonant period of the LC series circuit is defined by the inductance of the inductor and the capacitance of the capacitor. For example, when the inductance and capacitance are L and C, respectively, the resonant period can be calculated as in mathematical equation 1.

[0054]

[0055] When a voltage that rises momentarily (e.g., step input) is supplied to both ends of an LC series circuit, the voltage across the capacitor increases over time until it reaches half the resonant period (t / T). r =0.5) and then begins to decrease again. Similarly, if a momentary decreasing voltage is supplied to both ends of an LC series circuit, the voltage across the capacitor decreases over time, reaches a minimum at a point corresponding to half the resonant period, and then begins to increase again.

[0056] Therefore, the inductor (L O ) and capacitive load (C O ), i.e., the output voltage (V) of the multi-level inverter (320) INV ) is increased (or decreased) by a certain unit voltage and the inductor (L) O ) and capacitive load (C O ) after maintaining the voltage for half of the resonant period, the output voltage (V INV ) can theoretically completely eliminate the ringing phenomenon by increasing (or decreasing) the voltage by unit voltage.

[0057] The controller (340) can generate a control signal that controls the multi-level inverter (320) (more specifically, the switching elements constituting the multi-level inverter). For example, the controller (340) may include a memory that stores a program, and a processor that generates one or more control signals by executing processing according to a given program. As another example, the controller (340) may include a digital logic circuit configured to generate one or more control signals according to a predetermined logic operation.

[0058] In some examples, the controller (340) varies the switching sequence of the multi-level inverter (320) to change the voltage (V) output by the multi-level inverter (320). INV ) and / or its voltage (V) INV ) can be adjusted to control the length of the time interval in which the pulse DC voltage (V O ) can be adjusted to the degree of ringing that appears.

[0059] In an actual implementation environment, a pulse DC power supply (30) and a capacitive load (C O ) may have wiring inductance due to the wiring connecting them. At this time, the controller (340) considers the wiring inductance and the equivalent inductance and the capacitive load (C O ) for a time corresponding to half the resonant period determined by the capacitance of the capacitive load (C O ) can be charged or discharged to eliminate the influence of wiring inductance.

[0060] Capacitive load (C O ) can be manually performed by a user (or designer) or automatically performed by a controller (340). For example, the controller (340) can vary the charge / discharge time within a predetermined control range and control the inductor (L O ) current flowing in O ) and / or pulsed DC voltage (V O ) can be measured to find the length of the time interval where ringing is minimized. The adjustment range is known in advance for the inductor (L O ) of inductance and capacitive load (C O ) can be set based on the capacitance of the inductor. For example, the adjustment range can be defined as a range between a value with a predetermined positive margin added and a value with a negative margin added at half of the resonant period. For this purpose, the controller (340) controls the inductor (L O ) current flowing in O) and / or pulsed DC voltage (V O ) may further include, but is not limited to, sensors that detect the presence of a target object.

[0061] In some examples, the controller (340) varies the switching sequence of the multi-level inverter (320) to change the voltage (V) output by the multi-level inverter (320). INV ) can be adjusted to control the rising and / or falling width of the capacitive load (C). Through this, the controller (340) can control the capacitive load (C O ) pulse DC voltage (V) applied to O ) can control the amplitude and / or slew rate of the pulse DC voltage (V O ) can independently control the slew rate at the rising edge and the slew rate at the falling edge. Additionally or alternatively, the controller (340) may control the pulse DC voltage (V O ) can independently control the maximum and minimum values. The pulse DC power supply (30) can selectively provide, depending on system requirements, any one of a unipolar pulse DC voltage in which the pulse has only a voltage level of 0 or higher or a voltage level of 0 or lower, a symmetric bipolar pulse DC voltage in which the absolute values ​​of the positive maximum and the negative maximum of the pulse are the same, or an asymmetric bipolar pulse DC voltage in which the absolute values ​​of the positive maximum and the negative maximum of the pulse are different.

[0062] In some examples, the controller (340) can change the operating mode of the pulse DC power supply (30) by varying the switching sequence of the multi-level inverter (320). The operating mode can include, for example, a continuous mode that continuously generates pulses, and a burst mode that temporarily generates a pulse train for a predetermined time with a waiting time between each pulse train. Here, the burst mode may be referred to as an intermittent mode. Additionally or alternatively, the operating mode can include a fixed amplitude mode that outputs a pulse train having a constant amplitude and / or slew rate, and an amplitude modulation mode in which the amplitude and / or slew rate of each pulse is varied. For example, the controller (340) can control the multi-level inverter (320) according to a switching sequence corresponding to any one of the continuous-constant amplitude mode, the continuous-amplitude modulation mode, the intermittent-constant amplitude mode, and the intermittent-amplitude modulation mode.

[0063] Hereinafter, with reference to FIGS. 4a to 8b, various examples of the circuit configuration of the pulse DC power supply (30) and its operating waveforms will be described. In the present disclosure, the operations described as being performed by the pulse DC power supply (30) or the multi-level inverter (320) can be understood as being controlled by a control signal of the controller (340).

[0064] FIG. 4a and FIG. 4b are diagrams showing an example of a circuit configuration and an operating waveform thereof when a pulse DC power supply (30) according to one embodiment of the present disclosure includes a 3-level inverter.

[0065] Referring to FIG. 4A, the multi-level inverter (320) can be implemented as a full bridge inverter. The multi-level inverter (320) can include four switching elements (Q1 to Q4). The first to fourth switching elements (Q1 to Q4) receive a control signal (V) applied from the controller (340). G1 Inland V G4 ) can be turned on or off by a control signal (V) of logic high level. For example, the first to fourth switching elements (Q1 to Q4) can be turned on or off by a control signal (V) of logic high level. G1 Inland V G4 ) is turned on when a low level (logic low level) control signal (V G1 Inland V G4 ) may be turned off when authorized, but is not limited to these examples.

[0066] Among the switching elements (Q1 to Q4), the switching elements (Q1 and Q2) closer to the positive pole of the DC voltage source (300) may be referred to as 'upper switching elements', and the switching elements (Q3 and Q4) closer to the negative pole of the DC voltage source (300) may be referred to as 'lower switching elements'. Meanwhile, a pair of upper switching elements and lower switching elements that are electrically connected to each other may be referred to as a bridge arm. For example, a pair of a first switching element (Q1) and a third switching element (Q3) may be referred to as a first bridge arm, and a pair of a second switching element (Q2) and a fourth switching element (Q4) may be referred to as a second bridge arm.

[0067] Output voltage (V) of the multi-level inverter (320) INV ) can be defined as the potential difference between the contacts of the first switching element (Q1) and the third switching element (Q3) and the contacts of the second switching element (Q2) and the fourth switching element (Q4).

[0068] The switching elements included in the same bridge arm can be switched complementarily to each other. For example, the first switching element (Q1) and the third switching element (Q3) are switched complementarily to each other. The second switching element (Q2) and the fourth switching element (Q4) can be switched complementarily to each other. That is, when the upper switching element (Q1 or Q2) of a specific bridge arm is turned on, the lower switching element (Q3 or Q4) of the corresponding bridge arm is turned off, and conversely, when the upper switching element (Q1 or Q2) is turned off, the lower switching element (Q3 or Q4) can be turned on.

[0069] When the upper switching elements (Q1 and Q2) included in different bridge arms are turned on simultaneously, or the lower switching elements (Q3 and Q4) are turned on simultaneously, the positive and negative output terminals of the multi-level inverter (320) may be electrically short-circuited. Accordingly, the multi-level inverter (320) outputs zero voltage.

[0070] On the other hand, when a pair of diagonal switches included in different bridge arms (i.e., an upper switching element included in one bridge arm and a lower switching element included in the other bridge arm) are turned on simultaneously, the multi-level inverter (320) can output a voltage having a positive or negative polarity with respect to the zero voltage. For example, when the first switching element (Q1) and the fourth switching element (Q4) are turned on, the DC voltage source (300), the first switching element (Q1), and the inductor (L O ), capacitive load (C O ), and a current path including a fourth switching element (Q4) is formed, and the multi-level inverter (320) is supplied with a power supply voltage (+V) having a positive polarity. S) is output. As another example, when the second switching element (Q2) and the third switching element (Q3) are turned on, the DC voltage source (300), the second switching element (Q2), and the capacitive load (C O ), inductor (L O ), and a current path including a third switching element (Q3) is formed, and the multi-level inverter (320) supplies a power voltage (-V) having a negative polarity. S ) will be printed.

[0071] Table 1 shows the output voltage (V) according to the switching state of the switching elements (Q1 to Q4). INV ) is shown.

[0072] Switching state output voltage (V INV )DistinctionQ1Q3Q2Q4S1ONOFFOFFON+V S S2ONOFFONOFF0VS3OFFONOFFONS4OFFONONOFF-V S

[0073] As shown in Table 1, the switching states of the switching elements (Q1 to Q4) can have four combinations, and the output voltage (V) of the multi-level inverter (320) INV ) is the positive power supply voltage (+V S ), zero voltage (0 [V]), and negative supply voltage (-V S ) can have three voltage levels.

[0074] The pulse DC power supply (30) is a capacitive load (C O ) and inductor (L O ) with a zero voltage maintenance interval corresponding to half of the resonance period of the multi-level inverter (320) in between, the output voltage (V INV ) by reversing the polarity of the pulse DC voltage (V O ) can minimize ringing.

[0075] For example, referring to FIG. 4b, the multi-level inverter (320) is connected to a positive power supply voltage (+V S), zero voltage (0 [V]), negative supply voltage (-V S ), and zero voltage (0 [V]) can be output sequentially. One pulse cycle (T cycle ) can be divided into first to fourth time sections (T1 to T4) depending on the output voltage (or switching state) of the multi-level inverter (320). One cycle of pulse DC voltage (V O ) may include {S1, S3, S4, S2}, {S1, S2, S4, S2}, {S1, S3, S4, S3}, or {S1, S2, S4, S3}.

[0076] In the first time interval (T1), the pulse DC voltage (V O ) is the negative supply voltage (+V S ), the output voltage (V) of the multi-level inverter (320) at the start of the second time interval (T2) is maintained. INV ) is the power supply voltage (V S ) decreases by the size of the pulse DC voltage (V ) for a time corresponding to half the resonant period. O ) is the power supply voltage (V S ) is reduced by twice the pulse DC voltage (V) during the second time interval (T2). That is, during the second time interval (T2), the pulse DC voltage (V O ) is the positive power supply voltage (+V S ) at negative supply voltage (-V S ) decreases to .

[0077] At the end of the second time interval (T2), the pulse DC voltage (V O ) is the minimum (i.e. negative supply voltage (-V S )) is reached, and the switching state of the multi-level inverter (320) is switched, so that the voltage applied to the series circuit of the inductor (LO) and the capacitive load (CO) (i.e., the output voltage (V) of the multi-level inverter (320) INV )) and the voltage across the capacitive load (CO) (i.e., pulse DC voltage (V O)) become the same. Accordingly, in the third time interval (T3), the pulse DC voltage (V O ) is the negative supply voltage (-V S ) can be maintained at a constant level.

[0078] Afterwards, at the start of the fourth time interval (T4), the output voltage (V) of the multi-level inverter (320) INV ) is the power supply voltage (V S ) increases by the size of the pulse DC voltage (V ) for a time corresponding to half the resonant period. O ) is the power supply voltage (V S ) increases by twice as much. That is, during the fourth time interval (T4), the pulse DC voltage (V O ) is the negative supply voltage (-V S ) from the positive power supply voltage (+V S ) decreases to .

[0079] At the end of the fourth time interval (T4), the pulse DC voltage (V O ) is the maximum (i.e. positive supply voltage (+V S ) is reached, and the switching state of the multi-level inverter (320) is switched so that the voltage applied to the series circuit of the inductor (LO) and the capacitive load (CO) (i.e., the output voltage (V) of the multi-level inverter (320) INV )) and the voltage across the capacitive load (CO) (i.e., pulse DC voltage (V O )) become the same. Accordingly, in the third time interval (T3), the pulse DC voltage (V O ) is the negative supply voltage (-V S ) can be maintained at a constant level.

[0080] FIG. 5a and FIG. 5b are diagrams showing another example of a circuit configuration and an operating waveform thereof when a pulse DC power supply (30) according to one embodiment of the present disclosure includes a 3-level inverter.

[0081] Figures 5a and 5b illustrate the capacitive load (C) in the example described above in Figures 4a and 4b. O) to the load resistance (R) O ) is connected. Meanwhile, below, the equivalent circuit diagram and operating waveform are shown. O ) to the load resistance (R) O ) are connected in parallel, but the present disclosure is not limited thereto. In another example, the load resistance (R O ) is a capacitive load (C O ) can be connected in series, in which case the current flowing in the inductor (L O ) may have different waveforms.

[0082] When a resistance component exists on the output side of the multi-level inverter (320), an attenuation phenomenon appears in the response characteristics of the circuit, which leads to a decrease in the amplitude of the signal. That is, the load resistance (R O ) exists, the output voltage (V) of the multi-level inverter (320) INV ) to a given unit voltage (e.g., V S ) even after half the time corresponding to the resonant period has elapsed from the point of increasing (or decreasing) the pulse DC voltage (V O ) does not rise (or fall) by twice the unit voltage. For example, referring to Fig. 5b, the pulse DC voltage (V) at the end of the second time interval (t1) and the end of the fourth time interval (t2) O ) is a negative supply voltage (-V S ) and / or positive supply voltage (+V S ) does not reach.

[0083] Due to this, the output voltage (V) of the multi-level inverter (320) after that point INV ) is increased (or decreased) by a unit voltage, ringing occurs. This ringing occurs when the output voltage (V of the multi-level inverter (320) INV )(e.g., negative supply voltage (-V S ) or positive power supply voltage (+V S ))) and pulse DC voltage (VO ) is due to the step response corresponding to the difference in the DC voltage source and the load circuit, and has a much lower level than the ringing (e.g., the under damped case of Fig. 1b) that occurs when applying a pulse by selectively conducting (or blocking) the DC voltage source and the load circuit.

[0084] Meanwhile, the voltage (V) that the pulse DC power supply (30) must output O ) is large, switching with a single switching element may be difficult. In this case, switching elements must be connected in series to perform switching, or full-bridge inverters must be connected to isolated DC voltages and their outputs must be connected in series. Both methods have advantages and disadvantages, but the second method, which is less sensitive to differences in switching element characteristics, is more suitable for high-frequency switching.

[0085] FIG. 6a and FIG. 6b are diagrams showing an example of a circuit configuration and an operating waveform thereof when a pulse DC power supply (30) according to one embodiment of the present disclosure includes an M-level inverter (M is 4 or more).

[0086] The multi-level inverter (320) can be implemented as a cascaded multi-level inverter.

[0087] For example, referring to FIG. 6A, a multi-level inverter (320) may include a plurality of inverters (322-1 to 322-N). The plurality of inverters (322-1 to 322-N) may each receive DC voltages from different DC voltage sources (300-1 to 300-N). The outputs of the plurality of inverters (322-1 to 322-N) may be connected in series. Accordingly, the output voltage (V) of the multi-level inverter (320) INV ) is the voltage (V) output by multiple inverters (322-1 to 322-N). SUB1 Inland V SUBN ) can be defined as the sum of .

[0088] Each inverter (322-1 to 322-N) may be a full-bridge inverter. The circuit configuration and switching operation of the full-bridge inverter correspond to the circuit configuration and switching operation of the full-bridge inverter described above in Fig. 4a, and therefore, further detailed description is omitted.

[0089] Each inverter (322-1 to 322-N) can have an independent switching state.

[0090] The DC voltage supplied to the ith inverter among multiple inverters and the switching state of the ith inverter are respectively V Si and s i When this is said, the output voltage (V) of the multi-level inverter (320) INV ) can be expressed as in mathematical expression 2.

[0091]

[0092] Here, [·] is an operator that has a value of 1 if the internal proposition is true, and 0 if it is false.

[0093] DC voltage (V) applied to each inverter (322-1 to 322-N) S1 Inland V SN ) can be adjusted independently.

[0094] For example, at least one inverter (322-1 to 322-N) has a DC voltage (V) that is distinct from the other inverters (322-1 to 322-N). S1 Inland V SN ) can be provided.

[0095] As another example, each inverter (322-1 to 322-N) receives a DC voltage of the same magnitude (e.g., V) from different DC voltage sources (300-1 to 300-N). S ) may be provided. At any point in time, the number of inverters with switching state S1 and the number of inverters with switching state S4 are N, respectively. positive and N negativeWhen the output voltage (V) of the multi-level inverter (320) at that point in time INV ) can be expressed as in mathematical formula 3.

[0096]

[0097] In this case, the output voltage (V) of the multi-level inverter (320) INV ) is [-N·V S , +N·V S ] can have 2N+1 voltage levels within the range.

[0098] Optionally, in any time interval, the non-zero voltages that each of the plurality of inverters can output may have the same polarity. For example, in one time interval, each of the plurality of inverters may be controlled to output only zero voltage or positive voltage, and in another time interval, each of the plurality of inverters may be controlled to output only zero voltage or negative voltage. In this case, the output voltage (V) of the multi-level inverter (320) in each time interval INV ) can be expressed as mathematical expressions 4 and 5, respectively.

[0099]

[0100]

[0101] Referring to Fig. 6b, the pulse DC power supply (30) has a capacitive load (C O ) and inductor (L O ) with a reference voltage maintenance period (T2 or T4) corresponding to half of the resonance period of the multi-level inverter (320) in between, the output voltage (V INV ) to a given unit voltage (V) STEP ) by increasing (or decreasing) the pulse DC voltage (V O ) can minimize the ringing. The output voltage (V) of the multi-level inverter (320) INV ) pulse DC voltage (V O) is the same or corresponding to that described above in Fig. 4b, so a detailed description thereof is omitted.

[0102] In the reference voltage maintenance section (T2 or T4), the multi-level inverter (320) is subjected to a capacitive load (C O ) to be applied pulse DC voltage (V O ) maximum value (V P ) and minimum (-V N ) between the median voltage ((V) P- V N ) / 2) can output a voltage corresponding to the pulse DC voltage (V O ) maximum value (V P ) and minimum (-V N ) is the voltage (V) output by the multi-level inverter (320) in the time section before and after the reference voltage maintenance section (T2 or T4). INV ) can be determined based on.

[0103] The pulse DC power supply (30) is a capacitive load (C O ) pulse DC voltage (V) applied to O ) maximum value (V P ) and minimum (-V N ) can be independently controlled. Optionally, the voltage (V) output by the multi-level inverter (320) in the time intervals (T1 or T4) before and after the reference voltage maintenance interval (T2 or T4) INV ) can have different absolute values.

[0104] DC voltage (V) applied to at least one inverter (322-1 to 322-N) S1 Inland V SN ) are different, the pulse DC power supply (30) can differently control the combination of inverters that output non-zero voltage in the first time section (T1) and the fourth time section (T4). For example, the magnitude of the negative voltage level (V N ) is the magnitude of the positive voltage level (V P), the inverter(s) receiving a higher DC voltage source than the inverter(s) outputting a positive voltage in the first time period (T1) can be controlled to output a negative voltage in the third time period (T3).

[0105] Additionally or alternatively, the pulse DC power supply (30) can adjust the number of inverters that output non-zero voltage differently in the first time period (T1) and the fourth time period (T4).

[0106] For example, multiple inverters (322-1 to 322-N) all have the same magnitude of DC voltage (V S ) is input, and the pulse DC voltage (V O ) has both positive and negative voltage levels, but the magnitude of the negative voltage level (V N ) is the magnitude of the positive voltage level (V P ) must be greater than. In this case, the pulse DC power supply (30) can control a larger number of inverters to output a negative voltage in the third time period (T3) than the number of inverters that output a positive voltage in the first time period (T1). In addition, in this case, since the intermediate voltage must have a negative voltage level, the pulse DC power supply (30) can control some inverters to output a negative voltage and the remaining inverters to output a zero voltage in the second time period (T2) and the fourth time period (T4).

[0107] As another example, the magnitude of the positive voltage level (V P ) is the magnitude of the negative voltage level (V N), the pulse DC power supply (30) can control a larger number of inverters to output positive voltage in the first time section (T1) than the number of inverters that output negative voltage in the third time section (T3). In addition, in this case, since the intermediate voltage must have a positive voltage level, the pulse DC power supply (30) can control some inverters to output positive voltage and the remaining inverters to output zero voltage in the second time section (T2) and the fourth time section (T4).

[0108] As another example, pulsed DC voltage (V O ) has a voltage level of 0 or higher, the pulse DC power supply (30) can control a greater number of inverters to output a positive voltage in the first time period (T1) than the number of inverters that output a positive voltage in the third time period (T3). In addition, in this case, since the intermediate voltage must have a positive voltage level, the pulse DC power supply (30) can control some inverters to output a positive voltage and the remaining inverters to output a zero voltage in the second time period (T2) and the fourth time period (T4).

[0109] As another example, pulsed DC voltage (V O ) has a voltage level of 0 or less, the pulse DC power supply (30) can control a number of inverters greater than the number of inverters that output a negative voltage in the first time period (T1) to output a negative voltage in the third time period (T3). In addition, in this case, since the intermediate voltage must have a negative voltage level, the pulse DC power supply (30) can control some inverters to output a negative voltage and the remaining inverters to output a zero voltage in the second time period (T2) and the fourth time period (T4).

[0110] As described above, a pulse DC power supply (30) having multiple inverters (322-1 to 322-N) capable of independently controlling voltage generates a pulse DC voltage (VO ) can independently adjust the maximum and minimum values. The input DC voltage of each inverter (322-1 to 322-N) can be independently adjusted to an appropriate value. In addition, the pulse DC power supply (30) can output a pulse DC voltage (V O ), the number of inverters that will output a non-zero voltage in each time interval and / or their combination can be determined according to the characteristics required for the pulse DC power supply (30) (e.g., maximum, minimum, rising slope, and / or falling slope, etc.). Through this, the pulse DC power supply (30) can supply an asymmetric bipolar pulse DC voltage in which the absolute values ​​of the positive maximum and negative maximum of the pulse are different and / or a unipolar pulse DC voltage in which the pulse only has a voltage level of 0 or more or a voltage level of 0 or less.

[0111] FIG. 7a and FIG. 7b are diagrams showing another example of a circuit configuration and an operating waveform thereof when a pulse DC power supply (30) according to one embodiment of the present disclosure includes an M-level inverter (M is 4 or more).

[0112] Figures 7a and 7b illustrate the load resistance (R) to the capacitive load (CO) in the example described above in Figures 6a and 6b. O ) is connected, and the equivalent circuit diagram and load resistance (R) O ) to minimize ringing caused by capacitive load (C). Meanwhile, below, the operating waveform of the pulse DC power supply (30) is shown. O ) to the load resistance (R) O ) are connected in parallel, but the present disclosure is not limited thereto. In another example, the load resistance (R O ) is a capacitive load (C O ) can be connected in series, in which case the operating waveform may be different.

[0113] As mentioned above, the load resistance (R) on the load side O) exists, a resonance with loss occurs due to damping. This causes a capacitive load (C O ) voltage at both ends (V) O ) does not reach the target voltage, and the step response corresponding to the voltage deficiency may appear as a transient phenomenon, causing ringing.

[0114] The pulse DC power supply (30) increases the output voltage (V) of the multi-level inverter (320) by different unit voltages before and after the reference voltage maintenance period (T2 or T4). INV ) by increasing (or decreasing) the pulse DC voltage (V ) due to the attenuation. O ) can compensate for the deficiency.

[0115] For example, as shown in Fig. 7b, the pulse DC power supply (30) outputs the output voltage (V) of the multi-level inverter (320) at the start of the fourth time period (T4). INV ) as the first unit voltage (V STEP1 ) can be increased by the first unit voltage (V STEP1 ) is the pulse DC voltage (V O ) is half the amplitude ((V P +V N ) / 2) may be greater than that. That is, in the fourth time interval (T4), the multi-level inverter (320) generates a pulse DC voltage (V O ) maximum value (V P ) and minimum (-V N ) between the median voltage ((V) P -V N ) / 2) can output a first reference voltage higher than the first unit voltage (V STEP1 ) is the load resistance (R O ) under resonant conditions with losses due to the damping of the pulsed DC voltage (V O ) to the target amplitude (V P +V N ) can be a voltage that can be changed by as much as the inductor (L O ) and capacitive load (C O) when half the resonance period has elapsed (t2), the pulse DC voltage (V O ) is the target maximum (V P ) can be reached. Afterwards, the pulse DC power supply (30) outputs the output voltage (V of the multi-level inverter (320) INV ) to the second unit voltage (V STEP2 ) can be increased by the second unit voltage (V STEP2 ) is the target amplitude (V P +V N ) and the first unit voltage (V STEP1 ) may have a size corresponding to the difference in time. Accordingly, in the first time interval (T1), the multi-level inverter (320) has a capacitive load (C O ) voltage at both ends (V) O ) outputs the same voltage as the pulse DC voltage (V O ) is the target maximum (V) without ringing P ) can be maintained at a constant level.

[0116] Similarly, the pulse DC power supply (30) outputs the output voltage (V) of the multi-level inverter (320) at the start of the second time period (T2). INV ) as the first unit voltage (V STEP1 ) can be reduced by the first unit voltage (V STEP1 ) is the pulse DC voltage (V O ) is half of the target amplitude ((V P +V N ) / 2) may be greater than that. That is, in the second time interval (T2), the multi-level inverter (320) generates a pulse DC voltage (V O ) maximum value (V P ) and minimum (-V N ) between the median voltage ((V) P -V N ) / 2) can output a second reference voltage lower than the first unit voltage (V STEP1 ) is the load resistance (R O ) under resonant conditions with losses due to the damping of the pulsed DC voltage (V O ) to the target amplitude (VP +V N ) can be a voltage that can be changed by as much as the inductor (L O ) and capacitive load (C O ) when half the resonance period has elapsed (t1), the pulse DC voltage (V O ) is the target minimum (V N ) can be reached. Afterwards, the pulse DC power supply (30) outputs the output voltage (V of the multi-level inverter (320) INV ) to the second unit voltage (V STEP2 ) can be reduced by the second unit voltage (V STEP2 ) is the target amplitude (V P +V N ) and the first unit voltage (V STEP1 ) may have a size corresponding to the difference in time. Accordingly, in the third time interval (T3), the multi-level inverter (320) is a capacitive load (C O ) voltage at both ends (V) O ) outputs the same voltage as the pulse DC voltage (V O ) is the target minimum (-V) without ringing N ) can be maintained at a constant level.

[0117] In the second and fourth time intervals (T2 or T4), the pulse DC power supply (30) can control the multi-level inverter (320) to output different reference voltages by varying the number and / or combination of inverters that output non-zero voltages. For example, the pulse DC power supply (30) can adjust the output voltage of one or more of the plurality of inverters (322-1 to 322-N) differently to output the first and second unit voltages (V STEP1 and V STEP2 ) can be precisely adjusted.

[0118] Meanwhile, the first unit voltage (V STEP1) can be performed manually by a user (or designer) or automatically by a pulse DC power supply (30) (specifically, a controller (340)). For example, the pulse DC power supply (30) can determine a first unit voltage (V) within a predetermined adjustment range. STEP1 ) by varying the size of the inductor (L) O ) current flowing in O ) and / or pulsed DC voltage (V O ) to measure the first unit voltage (V) at which ringing is minimized. STEP1 ) can be found. The adjustment range is pulse DC voltage (V O ) is half of the target amplitude ((V P +V N ) / 2) can be set to a voltage level greater than that of the target amplitude. For example, the control range is half of the target amplitude ((V P +V N ) / 2) and a range between the values ​​with a predetermined amount of margin added thereto. For this purpose, the controller (340) is configured to control the inductor (L O ) current flowing in O ) and / or pulsed DC voltage (V O ) may further include, but is not limited to, sensors that detect the presence of a target object.

[0119] As described above, the pulse DC power supply (30) uses a plurality of inverters (322-1 to 322-N) that can independently control the voltage, and an inductor (L O ) and capacitive load (C O ) to cause resonance of unit voltage (V STEP1 ) can be adjusted in size. Accordingly, ringing due to voltage deficiency at the point where charging and / or discharging due to resonance ends can be minimized.

[0120] Fig. 8 is a diagram showing an example of a single-pulse mode operation waveform of a pulse DC power supply (30) according to one embodiment of the present disclosure. Fig. 9 is a diagram showing another example of a single-pulse mode operation waveform of a pulse DC power supply (30) according to one embodiment of the present disclosure.

[0121] The pulse DC power supply (30) can operate in a single-pulse mode.

[0122] The intermittent mode may include a fixed amplitude mode that outputs a pulse train with a constant amplitude and / or slew rate. For example, referring to FIG. 8, one cycle of the intermittent mode operation may include a burst duration that outputs a pulse train with a constant amplitude and / or slew rate, and an idle duration that does not output pulses. The burst duration and the idle duration may each include one or more pulse cycles. For example, assuming that one cycle of the intermittent mode operation includes 100 pulse cycles and the pulse DC power supply (30) operates in the intermittent mode with a duty ratio of 40%, the burst duration and the idle duration may each include 60 pulse cycles. The pulse DC power supply (30) may vary the output of the multi-level inverter (320) according to a predetermined switching sequence during the burst duration, and control the multi-level inverter (320) to output a constant voltage during the idle duration.

[0123] Additionally or alternatively, the burst mode may include an amplitude modulation mode in which the amplitude and / or slew rate of each pulse is varied. For example, the pulse DC power supply (30) may be controlled so that the amplitude and slew rate gradually increase as the pulse progresses in the front end of the burst period, as illustrated in FIG. 9, and the amplitude and slew rate gradually decrease as the pulse progresses in the back end of the burst period. The pulse DC power supply (30) may be controlled so that the voltage (V) output by the multi-level inverter (320) in each pulse cycle within the burst period INV ) can be varied to gradually change the amplitude and / or slew rate of the pulse. For example, when the multi-level inverter (320) includes a plurality of cascaded inverters (322-1 to 322-N), the pulse DC power supply (30) can control one inverter to output a non-zero voltage in the first time section (T1) of the first pulse cycle, and control three inverters to output non-zero voltage in the first time section (T1) of the second pulse cycle. Additionally or alternatively, the pulse DC power supply (30) can control three inverters to output non-zero voltage in the third time section (T3) of the first pulse cycle, and control five inverters to output non-zero voltage in the third time section (T3) of the second pulse cycle. Optionally, for applications where a certain degree of ringing is allowed, a certain number of inverters can be used within a single pulse cycle. For example, in the first time section (T1) and the third time section (T3) of the first pulse cycle, one inverter can be controlled to output a non-zero voltage, and in the first time section (T1) and the third time section (T3) of the second pulse cycle, two inverters can be controlled to output a non-zero voltage. That is, the number of inverters used in each pulse cycle (or each time section included therein) is the pulse DC voltage (V) to be formed. O) may vary depending on the shape of the envelope.

[0124] Each component of the device or method according to the present invention may be implemented in hardware, software, or a combination of hardware and software. Furthermore, the functions of each component may be implemented in software, with a microprocessor executing the software functions corresponding to each component.

[0125] Various implementations of the systems and techniques described herein can be implemented as digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), computer hardware, firmware, software, artificial intelligence, and / or combinations thereof. These various implementations can include implementations of one or more computer programs executable on a programmable system. The programmable system includes at least one programmable processor (which may be a special purpose processor or a general purpose processor) coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Computer programs (also known as programs, software, software applications, or code) include instructions for the programmable processor and are stored on a "computer-readable recording medium."

[0126] A computer-readable recording medium includes any type of recording device that stores data that can be read by a computer system. Such a computer-readable recording medium may be a non-volatile or non-transitory medium such as a ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, storage device, and may further include a transitory medium such as a data transmission medium. Furthermore, the computer-readable recording medium may be distributed across network-connected computer systems, so that computer-readable code can be stored and executed in a distributed manner.

[0127] Although the flowchart / timing diagram of this specification describes each process as being executed sequentially, this is merely an illustrative description of the technical idea of ​​one embodiment of the present disclosure. In other words, a person of ordinary skill in the art to which one embodiment of the present disclosure belongs may modify and apply various modifications and variations by changing the order described in the flowchart / timing diagram without departing from the essential characteristics of one embodiment of the present disclosure, or by executing one or more of the processes in parallel. Therefore, the flowchart / timing diagram is not limited to a chronological order.

[0128] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

[0129]

[0130] CROSS-REFERENCE TO RELATED APPLICATION

[0131] This patent application claims priority to Korean Patent Application No. 10-2023-0034017, filed in Korea on March 15, 2023, and Korean Patent Application No. 10-2024-0034018, filed in Korea on March 11, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A pulse DC power supply for applying pulse DC voltage to a capacitive load, A multi-level inverter that converts a DC voltage applied from one or more DC voltage sources into an output voltage having three or more voltage levels; and Including an inductor connected in series between the multi-level inverter and the capacitive load, The multi-level inverter is configured to output a predefined first reference voltage in a second time period, and to output voltages having different polarities compared to the first reference voltage in a first time period before the second time period and a third time period after the second time period, respectively. A pulse DC power supply in which the pulse DC voltage rises or falls due to resonance between the capacitive load and the inductor.

2. In paragraph 1, Further comprising a controller for controlling the above multi-level inverter, A pulse DC power supply device, wherein the controller adjusts the length of the second time interval and / or the magnitude of the first reference voltage so as to minimize ringing of the pulse DC voltage applied to the capacitive load.

3. In paragraph 1, The above multi-level inverter is a pulse DC power supply including a plurality of inverters, wherein the output terminals of the plurality of inverters are connected in series.

4. In paragraph 3, The above plurality of inverters receive DC voltage from different DC voltage sources, A pulsed DC power supply, wherein at least some of the DC voltage sources provide a DC voltage having a voltage level that is distinct from other DC voltage sources.

5. In paragraph 3, In the first time period, at least some of the first inverters among the plurality of inverters are configured to output a voltage having a first polarity with respect to zero voltage, A pulse DC power supply device, wherein in the third time period, at least some of the third inverters among the plurality of inverters are configured to output a voltage having a second polarity relative to the zero voltage.

6. In paragraph 5, The first polarity, the number of the first inverters, or a combination thereof, A pulse DC power supply having a different second polarity, a different number of third inverters, or a different combination thereof.

7. In paragraph 3, A pulse DC power supply device, wherein the multi-level inverter is configured to output a second reference voltage that is distinct from the first reference voltage in a fourth time period before the first time period and / or after the third time period.

8. In paragraph 7, In the second time period, at least some of the second inverters among the plurality of inverters are configured to output zero voltage, In the fourth time period, at least some of the fourth inverters among the plurality of inverters are configured to output the zero voltage, A pulse DC power supply device, wherein the number of the fourth inverters is different from the number of the second inverters.

9. In paragraph 7, The above first reference voltage is lower than the median voltage between the maximum and minimum values ​​of the pulse DC voltage, A pulse DC power supply device wherein the second reference voltage exceeds the intermediate voltage.

10. In paragraph 1, A pulse DC power supply, wherein the pulse DC voltage has an amplitude and / or slew rate that gradually changes during a plurality of consecutive pulse periods, each of the plurality of pulse periods including the first time period, the second time period, and the third time period.

11. In paragraph 1, The above multi-level inverter, Adjacent pulse periods, each pulse period including the first time interval, the second time interval, and the third time interval, outputting a different voltage in each of the first time intervals, A pulse DC power supply that outputs a different voltage in each of the third time intervals of the adjacent pulse cycles.

12. In paragraph 1, A pulse DC power supply device, wherein the maximum and minimum values ​​of the pulse DC voltage are independently controlled based on the voltages output by the multi-level inverter in the first and third time periods.

13. In paragraph 1, A pulse DC power supply device, wherein the difference between the reference voltage and the voltage output by the multi-level inverter in the first time interval has an absolute value different from the difference between the reference voltage and the voltage output by the multi-level inverter in the third time interval.

14. A pulse DC power supply according to claim 1, wherein the pulse DC voltage has a voltage level of 3 or more.

15. A method of operating a pulse DC power supply, comprising a multi-level inverter that converts a DC voltage applied from one or more DC voltage sources into an output voltage having three or more voltage levels, and an inductor connected in series between the multi-level inverter and a capacitive load, A process in which the multi-level inverter outputs a first voltage having a first polarity relative to a predefined first reference voltage; The process of the multi-level inverter outputting the first reference voltage in a second time period after the first time period; and The multi-level inverter includes a process of outputting a second voltage having a second polarity that is distinct from the first polarity compared to the first reference voltage in a third time period after the second time period, A method in which the pulse DC voltage applied by the pulse DC power supply to the capacitive load rises or falls due to resonance between the capacitive load and the inductor.

16. In paragraph 15, A method wherein the length of the second time interval and / or the magnitude of the first reference voltage are adjusted so as to minimize ringing of the pulse DC voltage applied to the capacitive load.

17. In paragraph 15, The above multi-level inverter comprises a plurality of inverters, wherein the output terminals of the plurality of inverters are connected in series, The process of outputting the first voltage includes a process of controlling each of at least some of the first inverters among the plurality of inverters to output a first sub-voltage having a third polarity with respect to zero voltage, The process of outputting the first reference voltage includes a process of controlling each of at least some of the second inverters among the plurality of inverters to output the zero voltage, A method wherein the process of outputting the second voltage includes a process of controlling each of at least some third inverters among the plurality of inverters to output a second sub-voltage having a fourth polarity relative to the zero voltage.

18. In paragraph 15, A method further comprising a step of the multi-level inverter outputting a second reference voltage that is distinct from the first reference voltage in a fourth time period before the first time period and / or after the third time period.

19. In paragraph 18, The above multi-level inverter comprises a plurality of inverters, wherein the output terminals of the plurality of inverters are connected in series, The process of outputting the second reference voltage includes a process of controlling at least some of the fourth inverters among the plurality of inverters to output zero voltage, A method wherein the number of the fourth inverters is different from the number of the second inverters.

20. In paragraph 18, The above multi-level inverter, In any one of the second and fourth time periods during which the capacitive load is charged, a reference voltage exceeding the median voltage between the maximum and minimum values ​​of the pulse DC voltage is output, A method for outputting a reference voltage lower than the intermediate voltage in another time period during which the capacitive load is discharged among the second time period and the fourth time period.

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