Voltage control method, device, and storage medium

Abstract

Provided are a voltage control method, a device, and a storage medium, applied to the technical field of terminals. The method is applied to an electronic device having a pixel circuit, the pixel circuit comprises a driving module, a control end of the driving module is connected to a first node (N1), and a source end of the driving module is connected to a second node (N2). The method comprises: when driving to display a first region of a first frame image, controlling the voltage of the first node (N1) to be a first voltage (V1), and controlling the voltage of the second node (N2) to be a second voltage (V2); and when driving to display a second region of the first frame image, controlling the voltage of the first node (N1) to be a third voltage (V3), and controlling the voltage of the second node (N2) to be a fourth voltage (V4); wherein the voltage difference between the first voltage (V1) and the second voltage (V2) is greater than the voltage difference between the third voltage (V3) and the fourth voltage (V4); and the refresh rate of the first region is a first refresh rate, the refresh rate of the second region is a second refresh rate, and the first refresh rate is lower than the second refresh rate. In this way, the probability of flickering on a display panel of the electronic device can be reduced.

Description

Voltage control method, device and storage medium

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 12, 2023, with application number 202310695264.2 and application name “Voltage Control Method, Device and Storage Medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of terminal technology, and in particular to a voltage control method, device, and storage medium. Background Art

[0003] With the development of terminal technology, electronic devices provide the function of displaying dynamic images in one area of ​​the display panel and static images in other areas of the display panel. In order to reduce power consumption of electronic devices, the refresh rate of the static image display area is lower than the refresh rate of the dynamic image display area.

[0004] However, when the static image display area switches to display a dynamic image, or when the dynamic image display area switches to display a static image, the display panel of the electronic device may flicker.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a voltage control method, device and storage medium, which are applied to the field of terminal technology. Since the image may be refreshed at a high refresh rate when a dynamic image is displayed, and the image may be refreshed at a low refresh rate when a static image is displayed, by controlling the gate voltage of the driving thin film transistor in the pixel circuit, the gate voltage of the driving thin film transistor in the light-emitting stage when the image is refreshed at a low refresh rate is reduced, and the gate voltage difference between the driving thin film transistor in the light-emitting stage when the image is refreshed at a high refresh rate is reduced. This can reduce the brightness difference between the static image display area and the dynamic image display area within the surface of the display panel, thereby reducing the probability of the display panel flickering when the refresh rate of the display area is switched.

[0007] In a first aspect, embodiments of the present application provide a voltage control method, which is applied to an electronic device having a pixel circuit, wherein the pixel circuit includes a driving module, wherein a control terminal of the driving module is connected to a first node, and a source terminal of the driving module is connected to a second node; the method includes:

[0008] When driving the first area to display the first frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage;

[0009] When driving the second area to display the first frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage;

[0010] Among them, the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first area is the first refresh rate, the refresh rate of the second area is the second refresh rate, and the first refresh rate is lower than the second refresh rate.

[0011] In this way, when the electronic device drives to display an image, the difference between the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0012] In a possible implementation, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

[0013] In this way, when the electronic device drives to display an image, the difference between the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0014] In one possible implementation, the pixel circuit further includes a data writing unit connected to the second node; when the first region and the second region of the first frame image are displayed, the data writing unit is enabled; and the method further includes:

[0015] When driving the first area to display the second frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the second frame image, disabling the data writing unit;

[0016] When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

[0017] In this way, when the electronic device drives to display an image, the difference between the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0018] In one possible implementation, the method further includes:

[0019] When driving the first area to display the third frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the third frame image, disabling the data writing unit;

[0020] When driving the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the third frame image, the data writing unit is enabled.

[0021] In this way, when the electronic device drives to display an image, the difference between the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced.

[0022] In one possible implementation, the method further includes:

[0023] When driving the first area to display the fourth frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the fourth frame image, disabling the data writing unit;

[0024] When driving the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the fourth frame image, the data writing unit is enabled.

[0025] In this way, when the electronic device drives to display an image, the power consumption of the electronic device can be reduced.

[0026] In one possible implementation, the pixel circuit further includes a data writing unit connected to the second node; when the first region and the second region of the first frame image are displayed, the data writing unit is enabled; and the method further includes:

[0027] When driving the first area to display the second frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the second frame image, disabling the data writing unit;

[0028] When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

[0029] In this way, when the electronic device drives to display an image, the power consumption of the electronic device can be reduced.

[0030] In one possible implementation, the method further includes:

[0031] Determining a starting position and an ending position of the first region based on an identifier of a pixel circuit corresponding to the first region;

[0032] Based on the identifier of the pixel circuit corresponding to the second area, a starting position and an ending position of the second area are determined.

[0033] In this way, when the electronic device drives and displays an image, the accuracy and integrity of the image display can be improved.

[0034] In one possible implementation, the method further includes:

[0035] When driving the third area to display the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; the refresh rate of the third area is the third refresh rate, which is lower than the second refresh rate.

[0036] In this way, images can be displayed in multiple display areas, improving the user experience of the electronic device.

[0037] In a possible implementation, the driving module includes a driving thin film transistor DTFT, a drain terminal of the DTFT is connected to the third node, and the DTFT is configured to output current to the third node under the control of the first node;

[0038] The pixel circuit also includes:

[0039] A first reset unit, connected to the first node, for applying a first initialization voltage to the first node in response to a first reset signal;

[0040] a storage capacitor, one end of which is connected to the first node and the other end of which is connected to the positive electrode of the power supply;

[0041] a first light-emitting control unit connected to the positive electrode of the power supply and the second node, and configured to load a first power supply voltage of the positive electrode of the power supply to the second node in response to a light-emitting control signal;

[0042] a threshold compensation unit connected to the first node and the third node, and configured to connect the third node to the first node in response to the first scan signal;

[0043] a second light emitting control unit connected to the third node and the fourth node, and configured to conduct the third node and the fourth node in response to a light emitting control signal;

[0044] a light emitting element, one end of which is connected to the fourth node, and the other end of which is connected to the negative electrode of the power supply so as to be loaded with the second power supply voltage of the negative electrode of the power supply;

[0045] a second reset unit connected to the fourth node and configured to load a second initialization voltage to the fourth node in response to a second reset signal;

[0046] a data writing unit connected to the second node and configured to load a data voltage to the second node in response to a second scanning signal;

[0047] The third reset unit is connected to the second node and is used for applying a third initialization voltage to the second node in response to the second reset signal.

[0048] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced, thereby reducing the probability of flickering of the display panel of the electronic device.

[0049] In one possible implementation, the first reset unit includes a first reset transistor, the first light-emitting control unit includes a first light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light-emitting control unit includes a second light-emitting control transistor, the light-emitting element includes an organic light-emitting diode OLED, the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.

[0050] In this way, when the electronic device drives to display an image, the voltage difference between the first node and the second node of the driving module corresponding to the first area and the voltage difference between the first node and the second node of the driving module corresponding to the second area can be reduced, thereby reducing the probability of flickering of the display panel of the electronic device.

[0051] In a second aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a display driver chip DDIC, a pixel circuit, and a memory;

[0052] Memory stores computer-executable instructions;

[0053] The processor instructs the display driver chip to drive the pixel circuit;

[0054] The display driver chip executes the computer-executable instructions stored in the memory, so that the electronic device executes the method of the first aspect and drives the pixel circuit.

[0055] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which, when executed by a display driver chip (DDIC), implements the method of the first aspect.

[0056] In a fourth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is run, it enables the computer to execute the method of the first aspect.

[0057] In a fifth aspect, an embodiment of the present application provides a chip, the chip including a processor, the processor being used to call a computer program in a memory to execute the method of the first aspect.

[0058] It should be understood that the second to fifth aspects of the present application correspond to the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0060] FIG2 is a first schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0061] FIG3 is a schematic diagram of the level timing of each signal provided in an embodiment of the present application;

[0062] FIG4 is a comparison diagram of the number of times the transistor T4 is enabled in the high-frequency display area and the low-frequency display area when the electronic device according to an embodiment of the present application refreshes an image;

[0063] FIG5 is a level timing diagram of each signal corresponding to the low-frequency display area and a schematic diagram of each initialization voltage provided in an embodiment of the present application;

[0064] FIG6 is a level timing diagram of each signal corresponding to the high-frequency display area and a schematic diagram of each initialization voltage provided by an embodiment of the present application;

[0065] FIG7 is a first timing diagram of bias voltage when an electronic device refreshes an image according to an embodiment of the present application;

[0066] FIG8 is a second timing diagram of bias voltage when refreshing an image in an electronic device according to an embodiment of the present application;

[0067] FIG9 is a second schematic diagram of the level timing diagram of each signal corresponding to the low-frequency display area and each initialization voltage according to an embodiment of the present application;

[0068] FIG10 is a third timing diagram of bias voltage when refreshing an image in an electronic device provided by an embodiment of the present application;

[0069] FIG11 is a fourth timing diagram of bias voltage when refreshing an image in an electronic device provided by an embodiment of the present application;

[0070] FIG12 is a third schematic diagram of the level timing diagram of each signal corresponding to the low-frequency display area and each initialization voltage according to an embodiment of the present application;

[0071] FIG13 is a fifth timing diagram of bias voltage when refreshing an image in an electronic device provided by an embodiment of the present application;

[0072] FIG14 is a sixth timing diagram of bias voltage when refreshing an image in an electronic device provided by an embodiment of the present application;

[0073] FIG15 is a second schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0074] FIG16 is a schematic structural diagram of an electronic device 100 provided in an embodiment of the present application;

[0075] FIG17 is a block diagram of the software structure of the electronic device 100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0076] To facilitate a clear description of the technical solutions of the embodiments of the present application, some of the terms and technologies involved in the embodiments of the present application are briefly introduced below:

[0077] 1. Some terms

[0078] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the terms "first chip" and "second chip" are used solely to distinguish between different chips and do not define their order. Those skilled in the art will understand that terms such as "first" and "second" do not define the quantity or execution order, and do not necessarily define differences.

[0079] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0080] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, c can be single or multiple.

[0081] It should be noted that the "at..." in the embodiments of the present application can be the instant when a certain situation occurs, or it can be a period of time after the situation occurs, and the embodiments of the present application do not specifically limit this. In addition, the display interface provided in the embodiments of the present application is only an example, and the display interface can also include more or less content.

[0082] 2. Electronic devices

[0083] The electronic devices of the embodiments of the present application may include handheld devices, vehicle-mounted devices, etc. with image processing functions. For example, some electronic devices include: mobile phones, tablet computers, PDAs, laptop computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving cars, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks. The terminal equipment in the network (PLMN), etc., is not limited to this in the embodiments of the present application.

[0084] As an example and not a limitation, in the embodiments of the present application, the electronic device may also be a wearable device. Wearable devices may also be referred to as wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as hearing aids, glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are fully functional, large in size, and can achieve complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0085] In addition, in the embodiments of the present application, the electronic device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0086] The electronic devices in the embodiments of the present application may also be referred to as: user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent or user device, etc.

[0087] In the embodiments of the present application, the electronic device or each network device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also known as main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as the Linux operating system, the Unix operating system, the Android operating system, the iOS operating system, or the Windows operating system. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0088] In a possible implementation, an electronic device includes a display panel. FIG1 shows a schematic structural diagram of a display panel. As shown in FIG1 , the display panel includes a light-emission control signal generating unit, a first reset signal generating unit, a second scan signal generating unit, a display area for displaying an image, a second scan signal generating unit, a first scan signal generating unit, a second reset signal generating unit, and a display driver integrated circuit (DDIC). The display area includes a plurality of pixel circuits in an array. The light-emission control signal generating unit, the first reset signal generating unit, the second scan signal generating unit, the display area for displaying an image, the second scan signal generating unit, the first scan signal generating unit, the second reset signal generating unit, and the display driver chip can each transmit corresponding signals to each pixel circuit via leads. The display driver chip can control the transmission of corresponding signals to the light-emission control signal generating unit, the first reset signal generating unit, the second scan signal generating unit, the display area for displaying an image, the second scan signal generating unit, the first scan signal generating unit, and the second reset signal generating unit. The pixel circuit includes a driving thin-film transistor and a light-emitting element. The driving thin-film transistor is used to drive the light-emitting element to emit light. The light-emitting element can serve as a sub-pixel of the display panel. The electronic device realizes the function of displaying dynamic images and static images on the display panel by driving and controlling the pixel circuits corresponding to the display area.

[0089] The display area may include a high-frequency display area and a low-frequency display area. The high-frequency display area refreshes the image at a high-frequency refresh rate. The low-frequency display area refreshes the image at a low-frequency refresh rate. When a dynamic image is displayed, the image may be refreshed at a high refresh rate. When a static image is displayed, the image may be refreshed at a low refresh rate. In a possible implementation, under the same data voltage, there is a difference between the brightness of the display area at a low refresh rate and the brightness of the display area at a high refresh rate. When the refresh rate of the display area is switched from a low refresh rate to a high refresh rate, or when the refresh rate of the display area is switched from a high refresh rate to a low refresh rate, the display area where the refresh rate is switched will flicker, and the display panel of the electronic device will also flicker.

[0090] In view of this, an embodiment of the present application provides a voltage control method, which controls the gate voltage of the driving thin film transistor to reduce the difference between the gate voltage of the driving thin film transistor during low-frequency display and the gate voltage of the driving thin film transistor during high-frequency display. This can reduce the brightness difference between the high-frequency and low-frequency display areas within the surface of the display panel, thereby reducing the probability of the display panel flickering when the refresh rate of the display area is switched.

[0091] The voltage control method provided in the embodiments of the present application is described below with reference to some embodiments.

[0092] FIG2 is a first schematic diagram of a pixel circuit according to an embodiment of the present invention. As shown in FIG2 , the pixel circuit includes a plurality of thin film transistors (TFTs), a capacitor C1, and a light-emitting element. The light-emitting element may include an organic light-emitting diode (OLED).

[0093] In the embodiments of the present application, a thin film transistor may be referred to as a transistor or a TFT transistor for short.

[0094] A plurality of thin film transistors, such as the transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , and the transistor T8 shown in FIG. 2 .

[0095] Transistor T3 is a driving thin-film transistor (DTFT) that drives the light-emitting element to emit light. Transistor T2 is a compensation transistor that controls the charging of capacitor C1 and the conduction of transistor T3. Transistors T1 and T2 may include oxide transistors. Other transistors may include transistors using low-temperature polysilicon (LTPS) technology.

[0096] As shown in FIG2 , transistor T1 is connected to a first node N1 and is configured to apply a first initialization voltage to the first node N1 in response to a first reset signal. The first reset signal may be referred to as ResetN. The first initialization voltage may be referred to as Vinit1.

[0097] The capacitor C1 has one end connected to the first node N1 and the other end connected to the positive power supply VDD. The first node N1 may be referred to as the N1 node or the N1 point.

[0098] Transistor T5 is connected to the positive power supply VDD and the second node N2 and is configured to apply a first power supply voltage of the positive power supply VDD to the second node N2 in response to a light emitting control signal. The light emitting control signal may be referred to as EM. The second node N2 may be referred to as an N2 node or an N2 point.

[0099] The transistor T3 is connected to the first node N1, the second node N2 and the third node N3, and is configured to output current to the third node N3 under the control of the first node N1. The third node N3 may be referred to as an N3 node or an N3 point.

[0100] The transistor T2 is connected to the first node N1 and the third node N3 and is configured to conduct the third node N3 and the first node N1 in response to a first scan signal, which may be referred to as GateN.

[0101] The transistor T6 is connected to the third node N3 and the fourth node N4 and is configured to conduct electricity between the third node N3 and the fourth node N4 in response to the light emitting control signal.

[0102] The light emitting element has one end connected to the fourth node N4 and the other end connected to the negative power supply electrode VSS to load the second power supply voltage of the negative power supply electrode VSS.

[0103] The transistor T7 is connected to the fourth node N4 and is configured to apply a second initialization voltage to the fourth node N4 in response to a second reset signal. The second reset signal may be referred to as ResetP. The second initialization voltage may be referred to as Vinit2.

[0104] The transistor T4 is connected to the second node N2 and is configured to apply a data voltage to the second node N2 in response to a second scan signal. The second scan signal may be referred to as GateP. The data voltage may be referred to as Vdata.

[0105] The transistor T8 is connected to the second node N2 and is configured to apply a third initialization voltage to the second node N2 in response to the second reset signal. The third initialization voltage may be referred to as Vinit3.

[0106] In the embodiments of the present application, the "on" state of a transistor refers to a state in which the source and drain of the transistor are electrically connected. The "off" state of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected. It is understood that when a transistor is off, leakage current may still exist. The on-state conditions for transistors T1 and T2 are: Vgs>Vth. The on-state conditions for the remaining transistors are: Vgs<Vth. The high level in the embodiments of the present application satisfies the on-state conditions for transistors T1 and T2, and the low level in the embodiments of the present application satisfies the on-state conditions for the remaining transistors. When transistor T4 is turned on and applies the data voltage to the second node N2, it can be referred to as transistor T4 being enabled. When transistor T4 is not turned on or is in the off state and no data voltage is applied to the second node N2, it can be referred to as transistor T4 being disabled. When transistor T2 is turned on, it can be referred to as transistor T2 being enabled. When transistor T2 is not turned on or is in the off state, it can be referred to as transistor T2 being disabled. When the transistor T1 is turned on, it can be said that the transistor T1 is enabled. When the transistor T1 is not turned on or is in the off state, it can be said that the transistor T1 is disabled.

[0107] When an electronic device refreshes an image frame for display on a display panel, it can drive and control the pixel circuits using either a row drive mode or a column drive mode. The principles of both modes are similar. The following uses the example of an electronic device driving and controlling the pixel circuits using a row drive mode as an example.

[0108] Every time the electronic device refreshes a frame of image, the operation of the pixel circuit may include a reset phase, a write phase, a light-emitting waiting phase, and a light-emitting phase.

[0109] Figure 3 is a schematic diagram of the level timing of each signal provided by an embodiment of the present application. The following describes the various stages of the pixel circuit operation when an electronic device refreshes a frame of image, in conjunction with Figures 2 and 3 .

[0110] When an electronic device refreshes a frame of image, if transistors T1, T4, and T2 are enabled, the display area of ​​this frame of image corresponds to the various stages of operation of the pixel circuit as shown in (1.1)-(1.4) below.

[0111] (1.1) Reset phase:

[0112] The light emitting control signal (EM) is at a high level, and the transistors T5 and T6 are in a cut-off state.

[0113] The first reset signal (ResetN) changes from a low level to a high level. The high level of the first reset signal turns on the transistor T1.

[0114] The second reset signal (ResetP) changes from high to low, and then from low to high. The low start time of the second reset signal (ResetP) is earlier than the high start time of the first reset signal (ResetN). The low level of the second reset signal turns on transistors T8 and T7.

[0115] The first scanning signal (GateN) changes from high to low, and then from low to high. The low-level start and end times are both within the high-level period of the first reset signal. The high level of the first scanning signal turns on transistor T2, thereby turning on nodes N1 and N3.

[0116] The second scanning signal (GateP) is at a high level, and the transistor T4 is in a cut-off state.

[0117] The turned-on transistor T1 applies the first initialization voltage Vinit1 to point N1, resetting it and clearing the potential written in the previous frame. This also writes the first initialization voltage Vinit1 to capacitor C1. The turned-on transistor T2 also applies the first initialization voltage Vinit1 to point N3, resetting it and clearing any residual signal from the previous stage.

[0118] The turned-on transistor T8 applies the third initialization voltage Vinit3 to point N2, writing the initial state voltage Vinit3 to point N2. At this point, the gate-source voltage difference Vgs of transistor T3 is the voltage difference between points N1 and N2, that is, Vgs is the voltage difference between Vinit1 and Vinit3. Vgs is greater than the threshold voltage Vth of transistor T3, rendering transistor T3 non-conductive.

[0119] The turned-on transistor T7 applies the second initialization voltage Vinit2 to the point N4, and writes the initial state voltage Vinit2 into the point N4.

[0120] (1.2) Writing phase:

[0121] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0122] The first reset signal (ResetN) changes from a high level to a low level, so that the transistor T1 is in a cut-off state.

[0123] The second reset signal (ResetP) maintains a high level, and both the transistor T8 and the transistor T7 are in the cut-off state.

[0124] The first scanning signal (GateN) maintains a high level. The high level of the first scanning signal (GateN) turns on transistor T2, and further turns on N1 and N3.

[0125] The second scanning signal (GateP) changes from a high level to a low level, and then from a low level to a high level. The low level of the second scanning signal (GateP) turns on transistor T4. The turned-on transistor T4 loads the data voltage Vdata to the N2 node. Since capacitor C1 can discharge to transistor T3, transistor T3 is turned on. Therefore, the turned-on transistor T4 can feed back the data voltage Vdata to N1 through transistors T3 and T2, and charge capacitor C1. The voltage at point N1 is Vdata + Vth. Vth is the threshold voltage of transistor T3. When transistor T4 is turned on, the voltage at point N2 is Vdata.

[0126] (1.3) Luminous waiting stage:

[0127] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0128] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0129] The second reset signal (ResetP) changes from high level to low level and then changes from low level to high level. The low level of the second reset signal turns on transistors T8 and T7. The high level of the second reset signal turns off transistors T8 and T7.

[0130] The first scanning signal (GateN) is at a low level, so that the transistor T2 is in a cut-off state.

[0131] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0132] The turned-on transistor T8 applies the third initialization voltage Vinit3 to the point N2, and writes the initial state voltage Vinit3 into the point N2.

[0133] The turned-on transistor T7 applies the second initialization voltage Vinit2 to the N4 node, writing the initial state voltage Vinit2 to the N4 node. This facilitates resetting the light emitting element before it emits light, thereby reducing the influence of the residual signal in the previous stage on the light emitting element.

[0134] The capacitor C1 can discharge the transistor T3 , and the gate-source voltage difference of the transistor T3 is greater than the threshold voltage Vth of the transistor T3 , so the transistor T3 is not turned on.

[0135] (1.4) Lighting stage:

[0136] Capacitor C1 can maintain the N1 voltage of transistor T3.

[0137] The emission control signal (EM) changes from high to low. The low level of the emission control signal turns on transistors T5 and T6. The first power supply voltage of the positive power supply (VDD) is written to the N2 node. Vgs of transistor T3 is less than Vth, and transistor T3 is turned on.

[0138] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0139] The second reset signal (ResetP) maintains a high level, and transistors T7 and T8 are in a cut-off state.

[0140] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0141] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0142] The turned-on transistor T5 applies the first power supply voltage at the positive terminal of the power supply to point N2. Transistor T3 also turns on. The turned-on transistor T6 connects points N3 and N4. The second power supply voltage at the negative terminal of the power supply is applied to one end of the light-emitting element. The light-emitting element begins to emit light.

[0143] When the light-emitting element emits light, transistor T3 divides the voltage, controlling the brightness of the light-emitting element. The voltage division of transistor T3 is affected by the gate voltage of transistor T3, i.e., the voltage of N1. For example, a larger gate-source voltage difference between transistor T3 and transistor T3 results in a smaller current flowing through transistor T3. Consequently, when the light-emitting element is connected in series with transistor T3, the current flowing through the light-emitting element also decreases, leading to a lower brightness of the light-emitting element.

[0144] When an electronic device refreshes a frame of image, if transistors T1, T4, and T2 are disabled, the display area of ​​this frame of image corresponds to the various stages of operation of the pixel circuit as shown in (2.1) to (2.4).

[0145] (2.1) Reset phase:

[0146] The light emitting control signal (EM) is at a high level, and the transistors T5 and T6 are in a cut-off state.

[0147] The first reset signal (ResetN) remains at a low level, and the transistor T1 remains in the off state.

[0148] The second reset signal (ResetP) changes from high to low, and then from low to high. Similar to the reset phase shown in (1.1), the low level of the second reset signal turns on transistors T8 and T7. The turned-on transistor T8 applies the third initialization voltage Vinit3 to point N2, writing the third initialization voltage Vinit3 to point N2. The turned-on transistor T7 applies the second initialization voltage Vinit2 to point N4, writing the initial state voltage Vinit2 to point N4.

[0149] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0150] The second scanning signal (GateP) is at a high level, and the transistor T4 remains in the off state.

[0151] Capacitor C1 can discharge to transistor T3, and transistor T3 is in the cut-off state. The gate voltage of transistor T3 is the voltage at point N1.

[0152] (2.2) Writing phase:

[0153] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0154] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0155] The second reset signal (ResetP) maintains a high level, and transistors T7 and T8 are in a cut-off state.

[0156] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0157] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0158] Capacitor C1 can discharge to transistor T3, and transistor T3 is in the cut-off state. The gate voltage of transistor T3 is the voltage at point N1.

[0159] (2.3) Luminous waiting stage:

[0160] The light emission control signal (EM) maintains a high level, and the transistors T5 and T6 are in a cut-off state.

[0161] The first reset signal (ResetN) maintains a low level, and the transistor T1 is in a cut-off state.

[0162] The second reset signal (ResetP) changes from high level to low level and then changes from low level to high level. The low level of the second reset signal turns on transistors T8 and T7. The high level of the second reset signal turns off transistors T8 and T7.

[0163] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0164] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0165] The turned-on transistor T8 applies the third initialization voltage Vinit3 to the point N2, and writes the initial state voltage Vinit3 into the point N2.

[0166] The turned-on transistor T7 applies the second initialization voltage Vinit2 to the N4 node, writing the initial state voltage Vinit2 to the N4 node. This facilitates resetting the light emitting element before it emits light, thereby reducing the influence of the residual signal in the previous stage on the light emitting element.

[0167] Capacitor C1 can discharge transistor T3, and transistor T3 is in the cut-off state. The gate voltage of transistor T3 is the voltage at point N1.

[0168] (2.4) Lighting stage:

[0169] Capacitor C1 can maintain the N1 voltage of transistor T3.

[0170] The emission control signal (EM) changes from high to low. The low level of the emission control signal turns on transistors T5 and T6. The first power supply voltage of the positive power supply (VDD) is written to the N2 node. Vgs of transistor T3 is less than Vth, and transistor T3 is turned on.

[0171] The first reset signal (ResetN) remains at a low level, and the transistor T1 remains in the off state.

[0172] The second reset signal (ResetP) maintains a high level, and transistors T7 and T8 are in a cut-off state.

[0173] The first scanning signal (GateN) maintains a low level, and the transistor T2 is in a cut-off state.

[0174] The second scanning signal (GateP) maintains a high level, and the transistor T4 is in a cut-off state.

[0175] The turned-on transistor T5 applies the first power supply voltage at the positive terminal of the power supply to point N2. Transistor T3 also turns on. The turned-on transistor T6 connects points N3 and N4. The second power supply voltage at the negative terminal of the power supply is applied to one end of the light-emitting element. The light-emitting element begins to emit light.

[0176] When the light-emitting element emits light, transistor T3 divides the voltage, controlling the brightness of the light-emitting element. The voltage division of transistor T3 is affected by the voltage at point N1 maintained by capacitor C1. The voltage at point N1 is affected by the potential of capacitor C1. The potential of capacitor C1 is the residual potential after capacitor C1 discharges at the end of the previous phase. For example, the lower the voltage at point N1, the smaller the gate-source voltage difference of transistor T3, the greater the current flowing through transistor T3. The light-emitting element is connected in series with transistor T3, and the current flowing through the light-emitting element also increases, resulting in a higher brightness of the light-emitting element.

[0177] As can be seen from the above, when the electronic device refreshes a frame of image, if the transistors T1 , T4 and T2 corresponding to the display area are enabled, the capacitor C1 corresponding to the display area is charged during the reset phase.

[0178] When an electronic device refreshes a frame of image, if transistors T1, T4, and T2 corresponding to the display area are disabled, the potential of capacitor C1 corresponding to the display area maintains the gate voltage of transistor T3 during the reset, write, and light-emitting phases. Alternatively, the potential of capacitor C1 corresponding to the display area remains in a discharged state during the reset, write, and light-emitting phases, rather than being charged. The initial voltage of capacitor C1 corresponding to the display area is the voltage remaining after discharge from the previous frame.

[0179] Generally, when an electronic device refreshes an image, the refresh rate of a high-frequency display area is higher than the refresh rate of a low-frequency display area.

[0180] For ease of understanding, the embodiment of the present application is described by taking the refresh rate of the low-frequency display area as 10 Hz and the refresh rate of the high-frequency display area as 120 Hz as an example.

[0181] The refresh rate can be equal to the number of times transistors T1, T4, and T2 are enabled per unit time when the electronic device refreshes the image. A higher refresh rate indicates a greater number of times transistors T1, T4, and T2 are enabled. Therefore, within the same time period, transistors T1, T4, and T2 corresponding to high-frequency display areas are enabled more times than transistors T1, T4, and T2 corresponding to low-frequency display areas.

[0182] Figure 4 shows a comparison of the number of times transistors T4 and T2 are enabled in the high-frequency display area and the low-frequency display area when an electronic device refreshes an image within one second. The low-frequency display area is shown as the first area in Figure 4. The high-frequency display area is shown as the second area in Figure 4. The refresh rate of the low-frequency display area, or the first area, is 120 Hz. The refresh rate of the high-frequency display area, or the second area, is 10 Hz.

[0183] As can be seen from Figures 2 and 3, when the electronic device refreshes a frame of image, transistors T1, T4, and T2 are enabled once or zero times. As shown in Figure 4, when the electronic device refreshes 120 frames of image within 1 second, the refresh rate of the high-frequency display area is 120Hz, and the refresh rate of the low-frequency display area is 10Hz. The high-frequency display area corresponds to transistors T1, T4, and T2 being enabled 120 times. The low-frequency display area corresponds to transistors T1, T4, and T2 being enabled 10 times, with an interval of 11 frames of image between two enables. The image sequence numbers of the 120 frames of image refreshed by the electronic device within 1 second are F1, F2, ..., F120 in Figure 4.

[0184] As can be seen from Figures 2 and 3, when an electronic device refreshes a frame of image, if the transistors T1, T2, and T4 corresponding to the display area of ​​this frame of image are enabled, the capacitor C1 corresponding to the display area of ​​this frame of image is charged during the writing phase. As shown in the embodiments shown in Figures 2 and 3, when the electronic device refreshes 120 frames of image within 1 second and the refresh rate of the high-frequency display area is 120Hz, within 1 second, the capacitor C1 corresponding to the high-frequency display area is charged 120 times, or the frequency of writing Vdata to point N1 in the high-frequency display area is 120Hz. When the electronic device refreshes 120 frames of image within 1 second and the refresh rate of the low-frequency display area is 10Hz, within 1 second, the capacitor C1 corresponding to the low-frequency display area is charged 10 times, or the frequency of writing Vdata to point N1 in the low-frequency display area is 10Hz.

[0185] In a possible implementation, the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage of the high-frequency display area are the same as the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage of the low-frequency display area. Combining Figures 2, 3, and 4, it can be seen that the brightness of the high-frequency display area and the brightness of the low-frequency display area have the following differences:

[0186] When an electronic device refreshes 120 frames of image per second, the refresh rate of the low-frequency display area is low, and the capacitor C1 corresponding to the low-frequency display area is charged less frequently. The amount of charge in capacitor C1 when transistors T1, T4, and T2 are enabled is needed to provide the gate voltage for transistor T3 during the display of the image frame in which transistors T1, T4, and T2 are enabled, as well as for the subsequent display of 11 consecutive image frames in which transistors T1, T4, and T2 are disabled. While capacitor C1 provides the gate voltage for transistor T3 during the display of 11 consecutive image frames in which transistors T1, T4, and T2 are disabled, capacitor C1 remains discharged and uncharged. As capacitor C1 discharges, the potential at point N1 decreases. When the light-emitting element emits light, the gate voltage of transistor T3 decreases, and the gate-source voltage difference of transistor T3 decreases. As the light-emitting element emits light, the current flowing through transistor T3 increases. Since the light-emitting element is connected in series with transistor T3, the current flowing through the light-emitting element also increases, increasing the brightness of the light-emitting element, and thus the brightness of the low-frequency display area.

[0187] Accordingly, when the electronic device refreshes 120 frames of images within 1 second, the high-frequency display area has a high refresh rate, and the capacitor C1 corresponding to the high-frequency display area is charged more times. In addition, the amount of electricity obtained by capacitor C1 when transistors T1, T4, and T2 are enabled is only needed to provide the gate voltage for transistor T3 when the image frame in which transistors T1, T4, and T2 are enabled is displayed. When the light-emitting element emits light, the current flowing through transistor T3 is small. The light-emitting element is connected in series with transistor T3, and the current flowing through the light-emitting element is small, which makes the brightness of the light-emitting element low, thereby making the brightness of the high-frequency display area low and constant.

[0188] It can be seen that when the voltage values ​​of the first initialization voltage, the second initialization voltage and the third initialization voltage of the high-frequency display area are the same as the voltage values ​​of the first initialization voltage, the second initialization voltage and the third initialization voltage of the low-frequency display area, when the light-emitting element emits light or in the light-emitting stage, the greater the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area, the greater the difference in brightness between the low-frequency display area and the high-frequency display area. When the refresh rate of the display area is switched, the display panel of the electronic device will flicker.

[0189] Therefore, when the electronic device refreshes the image, the amount of electricity charged in the capacitor C1 corresponding to the low-frequency display area when the transistors T1, T4 and T2 are enabled can be increased, and the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light can be reduced, or the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area during the light-emitting stage can be reduced. This can reduce the difference in brightness between the low-frequency display area and the high-frequency display area, thereby reducing the probability of flickering on the display panel of the electronic device.

[0190] In this regard, FIG5 shows a second schematic diagram of the level timing of each signal provided in an embodiment of the present application, and FIG6 shows a third schematic diagram of the level timing of each signal provided in an embodiment of the present application.

[0191] Figure 5 shows a timing diagram of the levels of various signals corresponding to the low-frequency display area when the electronic device refreshes an image, and a schematic diagram of various initialization voltages. As shown in Figure 5, when the electronic device refreshes an image, if transistors T1, T4, and T2 are enabled, the DDIC of the electronic device can control the first initialization voltage Vinit1 to V1 and the third initialization voltage Vinit3 to V2.

[0192] Figure 6 shows a timing diagram of the signal levels corresponding to the high-frequency display area and a schematic diagram of the initialization voltages when the electronic device refreshes an image. As shown in Figure 6, when the electronic device refreshes an image, if transistors T1, T4, and T2 are enabled, the DDIC of the electronic device can control the first initialization voltage Vinit1 to V3 and the third initialization voltage Vinit3 to V4.

[0193] Among them, V1>V3 and V2<V4.

[0194] Alternatively, V1 may be equal to V3.

[0195] Alternatively, V2 may be equal to V4.

[0196] If V1>V3 and V2≤V4, and the transistors T1, T4 and T2 in the low-frequency display area are enabled, when the electronic device refreshes a frame of image, in the reset phase, the voltage V1 is written to the capacitor C1, so that the potential of C1 is reset and initialized, the voltage at point N1 is V1, the voltage at point N2 is V2, and the gate-source voltage difference of the transistor T3 is the voltage difference between V1 and V2.

[0197] In the write phase, when transistor T4 is turned on, Vdata is loaded to point N2 and capacitor C1 is charged. The duration of the second scan signal remaining low during the write phase is fixed, and the duration of transistor T4 remaining in the on state is fixed. The amount of electricity charged to capacitor C1 during the write phase is related to the transient characteristics of transistor T3, or the value of Vdata written to capacitor C1 during the write phase is related to the transient characteristics of transistor T3. The transient characteristics of transistor T3 are determined by the gate-source voltage difference Vgs-1 of transistor T3 during the reset phase, that is, the voltage difference between V1 and V2. For example, the Vth of transistor T3 is affected by the gate-source voltage difference of transistor T3. The more positive the gate-source voltage difference of transistor T3, the more positive the Vth of transistor T3. The more negative the gate-source voltage difference of transistor T3, the more negative the Vth of transistor T3.

[0198] If V1>V3 and V2≤V4, and the transistors T1, T4 and T2 in the high-frequency display area are enabled, when the electronic device refreshes a frame of image, in the reset phase, the voltage V3 is written to the capacitor C1, so that the potential of C1 is reset and initialized, the voltage at point N1 is V3, the voltage at point N2 is V4, and the gate-source voltage difference of the transistor T3 is the voltage difference between V3 and V4.

[0199] During the write phase, when transistor T4 is turned on, Vdata is loaded to point N2 and capacitor C1 is charged. Similarly, if the duration of transistor T4 remaining on is fixed, the amount of charge charged to capacitor C1 during the write phase is related to the transient characteristics of transistor T3, or the value of Vdata written to capacitor C1 during the write phase is related to the transient characteristics of transistor T3. The transient characteristics of transistor T3 are determined by the gate-source voltage difference Vgs-h of transistor T3 during the reset phase, that is, the voltage difference between V3 and V4.

[0200] During the write phase, when charging capacitor C1, the greater the gate-source voltage difference of transistor T3, the more positively shifted Vth of transistor T3, the greater the current flowing through transistor T3, the more charge is charged into capacitor C1, or the more sufficient Vdata is written into C1. Correspondingly, during the write phase, when charging capacitor C1, the smaller the gate-source voltage difference of transistor T3, the more negatively shifted Vth of transistor T3, the smaller the current flowing through transistor T3, the less charge is charged into capacitor C1, or the less sufficient Vdata is written into C1.

[0201] Since Vgs-l>Vgs-h, the amount of electricity charged for the capacitor C1 when the transistors T1, T4 and T2 in the low-frequency display area are enabled is greater than the amount of electricity charged for the capacitor C1 when the transistors T1, T4 and T2 in the high-frequency display area are enabled, or the Vdata written into the capacitor C1 when the transistors T1, T4 and T2 in the low-frequency display area are enabled is more sufficient than the Vdata written into the capacitor C1 when the transistors T1, T4 and T2 in the high-frequency display area are enabled.

[0202] In this way, when the electronic device refreshes the image, the amount of charge each time of the capacitor C1 corresponding to the low-frequency display area is increased, which can reduce the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light.

[0203] In addition, for the low-frequency display area, since the transient characteristics of transistor T3 are affected by the gate-source voltage difference of transistor T3, when the electronic device refreshes 120 frames of images in 1 second (F1-F120 as shown in Figure 4), the display brightness of the corresponding images when transistors T1, T4 and T2 are enabled and when transistors T1, T4 and T2 are disabled changes as follows:

[0204] When F1 is displayed, the corresponding transistors T1, T4 and T2 are enabled. When F2-F12 are displayed, the corresponding transistors T1, T4 and T2 are disabled. The display brightness of F1-F12 will become brighter and brighter.

[0205] Compared to F12, when F13 is displayed, the corresponding transistors T1, T4, and T2 are enabled, and the display brightness of F13 is comparable to that of F1, both lower than the display brightness of F12. When F14-F24 are displayed, the corresponding transistors T1, T4, and T2 are disabled, and the display brightness of F13-F24 will gradually brighten.

[0206] Similarly, the display brightness of F25-F36 will become brighter and brighter;...; the display brightness of F109-F120 will become brighter and brighter.

[0207] Due to the gate-source voltage difference of transistor T3 and the changes in the transient characteristics of transistor T3, there may be a large difference in brightness between two adjacent frames of images during the display process of F1-F120, resulting in flicker. For example, the display brightness of F1 and F2 may differ significantly, resulting in flicker; the display brightness of F3 and F4 may differ significantly, resulting in flicker; or the display brightness of F12 and F13 may differ significantly, resulting in flicker.

[0208] When the low-frequency display area displays an image, flickering may occur in the low-frequency display area due to a large difference in brightness between two adjacent frames of the image.

[0209] Therefore, when the electronic device refreshes an image, increasing the amount of charge each time of the capacitor C1 corresponding to the low-frequency display area can also reduce the brightness difference between two adjacent frames of images displayed in the low-frequency display area.

[0210] Similarly, if V1 ≥ V3 and V2 < V4, transistors T1, T4, and T2 are enabled, when the electronic device refreshes a frame of image, since V2 < V4, the amount of charge of the capacitor C1 corresponding to the low-frequency display area during the reset phase is greater than the amount of charge of the capacitor C1 corresponding to the high-frequency display area during the reset phase, or, the Vdata written into the capacitor C1 when the transistors T1, T4, and T2 in the low-frequency display area are enabled is more sufficient than the Vdata written into the capacitor C1 when the transistors T1, T4, and T2 in the high-frequency display area are enabled.

[0211] Thus, when the electronic device refreshes an image, the amount of charge applied to capacitor C1 corresponding to the low-frequency display region is also increased, reducing the difference between the gate voltage of transistor T3 corresponding to the low-frequency display region and the gate voltage of transistor T3 corresponding to the high-frequency display region when the light-emitting element emits light. Furthermore, increasing the amount of charge applied to capacitor C1 corresponding to the low-frequency display region can also reduce the brightness difference between two adjacent frames of images displayed in the low-frequency display region.

[0212] Reducing the brightness difference between the high-frequency display area and the low-frequency display area, as well as reducing the brightness difference between two adjacent frames of images displayed in the low-frequency display area, can make the display within the surface of the electronic device display panel more uniform, and can improve the user experience of using the electronic device with the display surface.

[0213] Alternatively, as shown in Figures 5 and 6, when the electronic device is displaying a frame of image, if transistors T1, T4, and T2 are disabled and capacitor C1 is not charged, the DDIC of the electronic device can control the first initialization voltage Vinit1 to V3 and the third initialization voltage Vinit3 to V4. This can reduce the power consumption of the electronic device.

[0214] When the electronic device refreshes each frame of the image, the voltage difference between points N1 and N2 during the reset phase is also called the bias voltage of transistor T3. As can be seen from the above, the bias voltage affects the charge of capacitor C1 during the write phase.

[0215] Figure 7 shows a first timing diagram of the bias voltage when an electronic device refreshes an image. Figure 8 shows a second timing diagram of the bias voltage when an electronic device refreshes an image. As shown in Figures 7 and 8, the first area can be a low-frequency display area, with a refresh rate of, for example, 10 Hz, and the second area can be a high-frequency display area, with a refresh rate of, for example, 120 Hz.

[0216] The electronic device refreshes a frame of image row by row from t0 to t3. As shown in Figure 7, during the time period 0-t1, the electronic device drives the display of the first area of ​​the frame. During the time period t1-t2, the electronic device drives the display of the second area of ​​the frame. During the time period t2-t3, the electronic device drives the display of the first area of ​​the frame. As shown in Figure 8, during the time period 0-t1, the electronic device drives the display of the first area of ​​the frame. During the time period t1-t3, the electronic device drives the display of the second area of ​​the frame.

[0217] As shown in Figures 5, 6, 7, and 8, when the electronic device refreshes the first frame image, such as F1, transistors T1, T4, and T2 corresponding to the first and second regions of F1 are all enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first region of F1 is higher than the bias voltage when driving the second region of F1.

[0218] The implementation principle of DDIC by controlling the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1 is similar to the implementation principle of the embodiments shown in Figures 5 and 6 and will not be repeated here.

[0219] When the electronic device refreshes the second frame image such as F2, the transistors T1, T4 and T2 corresponding to the first area of ​​F2 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F2 to be displayed is equal to the bias voltage when driving the second area of ​​F2 to be displayed.

[0220] Similarly, when the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F3 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F3 to be displayed is equal to the bias voltage when driving the second area of ​​F3 to be displayed.

[0221] Similarly, when the electronic device refreshes the thirteenth frame image, such as F13, the transistors T1, T4 and T2 corresponding to the first area and the second area of ​​F13 are all enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area to display F13 is higher than the bias voltage when driving the second area to display F13.

[0222] Similarly, when the electronic device refreshes the fourteenth frame image, such as F14, the transistors T1, T4 and T2 corresponding to the first area of ​​F14 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F14 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F14 to be displayed is equal to the bias voltage when driving the second area of ​​F14 to be displayed.

[0223] In this way, the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light can be reduced, thereby reducing the difference in brightness between the first area and the second area, thereby reducing the probability of flickering in the first area when the refresh rate of the first area is switched, and / or reducing the probability of flickering in the second area when the refresh rate of the second area is switched, thereby reducing the probability of flickering in the display panel of the electronic device. In addition, the brightness uniformity of the first area can be improved, reducing the probability of flickering in the first area due to the brightness difference between two adjacent frames of images, further reducing the probability of flickering in the display panel of the electronic device.

[0224] The refresh rate of the first region is switched, for example, the refresh rate of the first region is switched to the refresh rate of the second region.

[0225] The refresh rate of the second region is switched, for example, the refresh rate of the second region is switched to the refresh rate of the first region.

[0226] In one possible implementation, FIG9 shows a level timing diagram of each signal corresponding to the low-frequency display area when the electronic device refreshes the image and a schematic diagram of each initialization voltage. FIG10 shows a timing diagram of the bias voltage when the electronic device refreshes the image. FIG11 shows a timing diagram of the bias voltage when the electronic device refreshes the image. As shown in FIG10 and FIG11, the first area may be a low-frequency display area. The refresh rate of the first area is, for example, 10 Hz. The second area may be a high-frequency display area. The refresh rate of the second area is, for example, 120 Hz. The level timing diagram of each signal corresponding to the high-frequency display area (or the second area) and a schematic diagram of each initialization voltage when the electronic device refreshes the image are shown in FIG6.

[0227] The electronic device refreshes a frame of image row by row from t0 to t3. As shown in Figure 10, during the time period 0-t1, the electronic device drives the display of the first area of ​​the frame. During the time period t1-t2, the electronic device drives the display of the second area of ​​the frame. During the time period t2-t3, the electronic device drives the display of the first area of ​​the frame. As shown in Figure 11, during the time period 0-t1, the electronic device drives the display of the first area of ​​the frame. During the time period t1-t3, the electronic device drives the display of the second area of ​​the frame.

[0228] As shown in Figures 6, 9, 10, and 11, when the electronic device refreshes the first frame image, such as F1, transistors T1, T4, and T2 corresponding to the first and second regions of F1 are all enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first region of F1 is higher than the bias voltage when driving the second region of F1.

[0229] The implementation principle of DDIC by controlling the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1 is similar to the implementation principle of the embodiments shown in Figures 5 and 6 and will not be repeated here.

[0230] When the electronic device refreshes the second frame image such as F2, the transistors T1, T4 and T2 corresponding to the first area of ​​F2 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F2 to be displayed is higher than the bias voltage when driving the second area of ​​F2 to be displayed.

[0231] Similarly, when the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F3 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F3 to be displayed is equal to the bias voltage when driving the second area of ​​F3 to be displayed.

[0232] Similarly, when the electronic device refreshes the fourth frame image, such as F4, the transistors T1, T4 and T2 corresponding to the first area of ​​F4 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F4 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F4 to be displayed is equal to the bias voltage when driving the second area of ​​F4 to be displayed.

[0233] Similar to when the electronic device refreshes the first frame image, such as F1, when the electronic device refreshes the thirteenth frame image, such as F13, transistors T1, T4, and T2 corresponding to the first and second regions of F13 are all enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first region of F13 is higher than the bias voltage when driving the second region of F13.

[0234] Similar to when the electronic device refreshes the second frame image such as F2, when the electronic device refreshes the fourteenth frame image such as F14, the transistors T1, T4 and T2 corresponding to the first area of ​​F14 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F14 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F14 to be displayed is higher than the bias voltage when driving the second area of ​​F14 to be displayed.

[0235] Similar to when the electronic device refreshes the third frame image such as F3, when the electronic device refreshes the fifteenth frame image such as F15, the transistors T1, T4 and T2 corresponding to the first area of ​​F15 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F15 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F15 to be displayed is equal to the bias voltage when driving the second area of ​​F15 to be displayed.

[0236] In this way, the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light can be reduced, thereby reducing the difference in brightness between the first area and the second area, and improving the brightness uniformity of the first area. Experimental verification shows that the voltage control method provided in this embodiment can reduce the probability of flickering on the display panel of an electronic device.

[0237] In one possible implementation, Figure 12 shows a level timing diagram of each signal corresponding to the low-frequency display area when the electronic device refreshes the image and a schematic diagram of each initialization voltage three. Figure 13 shows a timing diagram five of the bias voltage when the electronic device refreshes the image. Figure 14 shows a timing diagram six of the bias voltage when the electronic device refreshes the image. As shown in Figures 13 and 14, the first area can be a low-frequency display area. The refresh rate of the first area is, for example, 10Hz. The second area can be a high-frequency display area. The refresh rate of the second area is, for example, 120Hz. The level timing diagram of each signal corresponding to the high-frequency display area (or second area) and a schematic diagram of each initialization voltage when the electronic device refreshes the image are shown in Figure 6.

[0238] The electronic device refreshes a frame of image row by row from t0 to t3. As shown in Figure 13, during the time period 0-t1, the electronic device drives the display of the first area of ​​the frame. During the time period t1-t2, the electronic device drives the display of the second area of ​​the frame. During the time period t2-t3, the electronic device drives the display of the first area of ​​the frame. As shown in Figure 14, during the time period 0-t1, the electronic device drives the display of the first area of ​​the frame. During the time period t1-t3, the electronic device drives the display of the second area of ​​the frame.

[0239] As shown in Figures 6, 12, 13, and 14, when the electronic device refreshes the first frame image, such as F1, transistors T1, T4, and T2 corresponding to the first and second regions of F1 are all enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first region of F1 is higher than the bias voltage when driving the second region of F1.

[0240] The implementation principle of DDIC is similar to the implementation principle of the embodiments shown in Figures 5 and 6, and will not be repeated here.

[0241] When the electronic device refreshes the second frame image, such as F2, the transistors T1, T4, and T2 corresponding to the first area of ​​F2 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of ​​F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F2 to be displayed is higher than the bias voltage when driving the second area of ​​F2 to be displayed.

[0242] When the electronic device refreshes the third frame image, such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F3 to be displayed is higher than the bias voltage when driving the second area of ​​F3 to be displayed.

[0243] When the electronic device refreshes the fourth frame image, such as F4, the transistors T1, T4 and T2 corresponding to the first area of ​​F4 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F4 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F4 to be displayed is equal to the bias voltage when driving the second area of ​​F4 to be displayed.

[0244] When the electronic device refreshes the fifth frame image, such as F5, the transistors T1, T4 and T2 corresponding to the first area of ​​F5 are not enabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F5 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 so that the bias voltage when driving the first area of ​​F5 to be displayed is equal to the bias voltage when driving the second area of ​​F5 to be displayed.

[0245] The bias voltage of the first area when the electronic device refreshes the thirteenth frame image, such as F13, is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the first frame image, such as F1. The bias voltage of the first area when the electronic device refreshes the fourteenth frame image, such as F14, is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the second frame image, such as F2. The bias voltage of the first area when the electronic device refreshes the fifteenth frame image, such as F15, is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the third frame image, such as F3. The bias voltage of the first area when the electronic device refreshes the sixteenth frame image, such as F16, is similar to the control method and effect of the bias voltage of the first area when the electronic device refreshes the fourth frame image, such as F4. No further details will be given.

[0246] In this way, the difference between the gate voltage of the transistor T3 corresponding to the static image display area and the gate voltage of the transistor T3 corresponding to the dynamic image display area when the light-emitting element emits light can be reduced, thereby reducing the difference in brightness between the first area and the second area, and improving the brightness uniformity of the first area. Experimental verification shows that the voltage control method provided in this embodiment can reduce the probability of flickering on the display panel of an electronic device.

[0247] The voltage control method provided in the embodiment of the present application is described below with reference to Figures 15, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14.

[0248] FIG15 is a second schematic diagram of a pixel circuit provided in an embodiment of the present application. As shown in FIG15 , the pixel circuit includes:

[0249] Driving module 13. The control terminal of driving module 13 is connected to the first node N1, and the source terminal of driving module 13 is connected to the second node N2. Driving module 13 may include a driving thin film transistor (DTFT). The drain terminal of the DTFT is connected to the third node N3. The DTFT is configured to output current to the third node N3 under the control of the first node N1. The DTFT may include the transistor T3 shown in Figure 2.

[0250] The first reset unit 10 is connected to the first node N1 and is configured to apply a first initialization voltage to the first node N1 in response to a first reset signal. The first reset unit 10 may include a first reset transistor, which may be the transistor T1 shown in FIG2 .

[0251] The storage capacitor 11 has one end connected to the first node N1 and the other end connected to the positive power supply (VDD). The storage capacitor 11 may include the capacitor C1 shown in FIG.

[0252] The first light-emitting control unit 12 is connected to the positive electrode of the power supply and the second node N2, and is configured to apply a first power supply voltage from the positive electrode of the power supply to the second node N2 in response to the light-emitting control signal. The first light-emitting control unit 12 may include a first light-emitting control transistor, such as transistor T5 in FIG2 .

[0253] The threshold compensation unit 14 is connected to the first node N1 and the third node N3 and is configured to conduct the third node N3 to the first node N1 in response to the first scan signal. The threshold compensation unit 14 may include a threshold compensation transistor, such as the transistor T2 shown in FIG2 .

[0254] The second light emitting control unit 15 is connected to the third node N3 and the fourth node N4, and is configured to conduct the third node N3 and the fourth node N4 in response to the light emitting control signal. The second light emitting control unit 15 may include a second light emitting control transistor, which is the transistor T6 shown in FIG2 .

[0255] The light emitting element 16 has one end connected to the fourth node and the other end connected to the negative electrode of the power supply to apply the second power supply voltage of the negative electrode of the power supply. The light emitting element 16 may include an organic light emitting diode (OLED).

[0256] The second reset unit 17 is connected to the fourth node N4 and is configured to apply a second initialization voltage to the fourth node N4 in response to a second reset signal. The second reset unit 17 may include a second reset transistor, which may be the transistor T7 shown in FIG2 .

[0257] The data writing unit 18 is connected to the second node N2 and is configured to load a data voltage to the second node N2 in response to the second scan signal. The data writing unit 18 may include a data writing transistor, such as the transistor T4 shown in FIG2 .

[0258] The first reset unit 10 is turned on, which can be referred to as the first reset unit 10 being enabled. The first reset unit 10 is not turned on, which can be referred to as the first reset unit 10 being disabled. The data write unit 18 applies a data voltage to the second node N2 in response to the second scan signal, which can be referred to as the data write unit 18 being enabled. The data write unit 18 does not apply a data voltage to the second node N2, which can be referred to as the data write unit 18 being disabled. The threshold compensation unit 14 causes the third node N3 to be conductive with the first node N1 in response to the first scan signal, which can be referred to as the threshold compensation unit 14 being enabled. The threshold compensation unit 14 causes the third node N3 to be conductive with the first node N1 to be disconnected, which can be referred to as the threshold compensation unit 14 being disabled.

[0259] The third reset unit 19 is connected to the second node N2 and is configured to apply a third initialization voltage to the second node N2 in response to the second reset signal. The third reset unit 19 may include a third reset transistor, which may be the transistor T8 shown in FIG2 .

[0260] As shown in Figures 4, 5, 6, 7, and 8, when the electronic device drives the first area to display the first frame image, the voltage of the first node is controlled to be a first voltage, and the voltage of the second node is controlled to be a second voltage. The first voltage may include V1. The second voltage may include V2.

[0261] When driving the second area to display the first frame image, the electronic device controls the voltage of the first node to be a third voltage and controls the voltage of the second node to be a fourth voltage. The third voltage may include V3. The fourth voltage may include V4.

[0262] The voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage. The refresh rate of the first region is a first refresh rate, and the refresh rate of the second region is a second refresh rate, where the first refresh rate is lower than the second refresh rate. The first refresh rate is, for example, 10 Hz. The second refresh rate is, for example, 120 Hz.

[0263] Optionally, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

[0264] Furthermore, as shown in FIG15 , the pixel circuit further includes a data writing unit 18, and the data writing unit 18 is connected to the second node N2. As shown in FIG3 and FIG4 , when the electronic device displays the first region and the second region of the first frame image, the data writing unit 18 is enabled. The voltage control method provided in this embodiment further includes:

[0265] 5 , when the electronic device drives the first region to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first region of the second frame image, the data writing unit 18 is disabled.

[0266] 6 , when the electronic device drives the second region to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second region of the second frame image, the data writing unit 18 is enabled.

[0267] Optionally, as shown in FIG15 , the pixel circuit further includes a data writing unit 18 and a threshold compensation unit 14. As shown in FIG3 and FIG4 , when the electronic device displays the first region and the second region of the first frame image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in this embodiment further includes:

[0268] As shown in FIG5 , when the electronic device drives the first region of the second frame image to be displayed, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first region of the second frame image, the first reset unit 10, the data write unit 18, and the threshold compensation unit 14 are disabled.

[0269] As shown in Figure 6, when the electronic device drives the second region of the second frame image to be displayed, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second region of the second frame image, the first reset unit 10, the data write unit 18, and the threshold compensation unit 14 are enabled.

[0270] Optionally, the display area on the display panel of the electronic device may further include a third area. When driving the third area to display the first frame image, the electronic device controls the voltage of the first node to be the first voltage and the voltage of the second node to be the second voltage. The refresh rate of the third area is a third refresh rate, which is lower than the second refresh rate.

[0271] Optionally, the third refresh rate may be the same as the first refresh rate, or may be different from the first refresh rate. When the third refresh rate is the same as the first refresh rate, the third region may be the first region corresponding to the t2-t3 period shown in FIG. 7 , FIG. 10 , and FIG. 13 .

[0272] It is understood that the first refresh rate and the third refresh rate in the embodiment of the present application may include but are not limited to 10 Hz. The second refresh rate in the embodiment of the present application may include but are not limited to 120 Hz. For example, the third refresh rate may also be 30 Hz or 60 Hz.

[0273] Optionally, when refreshing a frame of image, the electronic device may determine the starting position and ending position of the first region based on the identifier of the pixel circuit corresponding to the first region, and may determine the starting position and ending position of the second region based on the identifier of the pixel circuit corresponding to the second region.

[0274] For example, the DDIC may determine the starting position and ending position of the second area through the position information of the second area indicated by the application processor (AP) of the electronic device, and further determine the starting position and ending position of the first area. The position information of the second area indicated by the AP may be the relative position information of the second area indicated by the AP, or the real position information of the second area indicated by the AP. The real position information of the second area indicated by the AP may include an identifier of a pixel circuit corresponding to the starting position of the second area and an identifier of a pixel circuit corresponding to the ending position.

[0275] The location information of the second area indicated by the AP is determined by the AP based on the application type or application scenario to which the image data generated by the AP belongs. The image data generated by the AP refers to the data corresponding to Vdata when transistors T4 and T2 are enabled. If the image data generated by the AP is dynamic image data of application A, the location information of the second area indicated by the AP may be determined based on the location information of the area displaying the dynamic image on the display interface of application A.

[0276] The specific implementation principle and technical effects of this embodiment are similar to those of the embodiments shown in Figures 2, 5, 6, 7 and 8, and will not be repeated here.

[0277] As shown in FIG15 , FIG4 , FIG6 , FIG9 , FIG10 and FIG11 , when the electronic device displays the first region and the second region of the first frame image, the data writing unit 18 is enabled. The voltage control method provided in this embodiment further includes:

[0278] When the electronic device drives the first area to display the second frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is disabled.

[0279] When the electronic device drives the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is enabled.

[0280] The specific implementation principle and technical effects of this embodiment are similar to those of the embodiments shown in Figures 6, 9, 10 and 11, and will not be repeated here.

[0281] For example, as shown in Figures 15, 4, 6, 9, 10, and 11, when the electronic device displays the first region and the second region of the first frame image, the first reset unit 10 is enabled, the data write unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in this embodiment also includes:

[0282] When the electronic device drives and displays the first area of ​​the second frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.

[0283] When the electronic device drives the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0284] The specific implementation principle and technical effects of this embodiment are similar to those of the embodiments shown in Figures 6, 9, 10 and 11, and will not be repeated here.

[0285] As shown in FIG15 , FIG4 , FIG6 , FIG12 , FIG13 and FIG14 , the voltage control method provided in this embodiment further includes:

[0286] When the electronic device drives the first area to display the third frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the third frame image, the data writing unit 18 is disabled.

[0287] When the electronic device drives the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the third frame image, the data writing unit 18 is enabled.

[0288] When the electronic device drives the first area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the fourth frame image, the data writing unit 18 is disabled;

[0289] When the electronic device drives the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the fourth frame image, the data writing unit 18 is enabled.

[0290] The specific implementation principle and technical effects of this embodiment are similar to those of the embodiments shown in Figures 6, 12, 13 and 14, and will not be repeated here.

[0291] For example, as shown in FIG15 , FIG4 , FIG6 , FIG12 , FIG13 and FIG14 , the voltage control method provided in this embodiment further includes:

[0292] When the electronic device drives the first area to display the third frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When the electronic device displays the first area of ​​the third frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.

[0293] When the electronic device drives the second area of ​​the third frame image to be displayed, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the third frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0294] When the electronic device drives and displays the first area of ​​the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the first area of ​​the fourth frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled;

[0295] When the electronic device drives the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. When the electronic device displays the second area of ​​the fourth frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0296] The specific implementation principle and technical effects of this embodiment are similar to those of the embodiments shown in Figures 6, 12, 13 and 14, and will not be repeated here.

[0297] In order to better understand the embodiment of the present application, the structure of the electronic device of the embodiment of the present application is described below with reference to FIG. 16 and FIG. 17 .

[0298] FIG16 shows a schematic structural diagram of the electronic device 100 .

[0299] The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0300] It should be understood that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0301] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0302] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0303] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly retrieve it from the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0304] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0305] It is understood that the interface connection relationship between the modules illustrated in the embodiment of the present invention is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods from the above embodiments, or a combination of multiple interface connection methods.

[0306] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also provide power to the electronic device via the power management module 141.

[0307] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0308] The wireless communication function of the electronic device 100 can be implemented by the antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor shown in Figure 16.

[0309] Antenna 1 and antenna 2 shown in Figure 16 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0310] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0311] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.) or displays an image or video through the display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0312] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0313] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, so that electronic device 100 can communicate with a network and other devices via wireless communication technology. Wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. GNSS may include the global positioning system (GPS), the global navigation satellite system (GLONASS), the Beidou navigation satellite system (BDS), the quasi-zenith satellite system (QZSS) and / or the satellite based augmentation system (SBAS).

[0314] Electronic device 100 implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0315] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, electronic device 100 may include one or N display screens 194, where N is a positive integer greater than one.

[0316] The electronic device 100 can implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor.

[0317] The ISP processes data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and transformed into a visible image. The ISP can also perform algorithmic optimization on image noise, brightness, and skin tone. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 193.

[0318] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then passes the electrical signal to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0319] The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0320] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. This allows electronic device 100 to play or record videos in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, and MPEG4.

[0321] The NPU is a neural network (NN) computing processor. Drawing on the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it rapidly processes input information and can continuously self-learn. The NPU can enable intelligent cognitive applications in electronic device 100, such as image recognition, face recognition, speech recognition, and text comprehension.

[0322] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 via the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0323] The internal memory 121 can be used to store computer executable program codes, and the executable program codes include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor.

[0324] The electronic device 100 can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0325] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0326] The speaker 170A, also called a "speaker", is used to convert audio electrical signals into sound signals. The electronic device 100 can listen to music or listen to hands-free calls through the speaker 170A.

[0327] The receiver 170B, also called a "handset", is used to convert audio electrical signals into sound signals. When the electronic device 100 receives a call or a voice message, the user can place the receiver 170B close to the ear to hear the voice.

[0328] Microphone 170C, also known as "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the source of sound, realize directional recording function, etc.

[0329] The headphone jack 170D is used to connect a wired headphone and can be the USB interface 130 or a 3.5mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0330] The buttons 190 include a power button, a volume button, and the like. The buttons 190 may be mechanical buttons or touch buttons. The electronic device 100 may receive key inputs and generate key signal inputs related to user settings and function control of the electronic device 100.

[0331] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (such as taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example: time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0332] The indicator 192 may be an indicator light, which may be used to indicate the charging status, power level changes, messages, missed calls, notifications, etc.

[0333] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to or removed from the electronic device 100 by inserting it into or removing it from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0334] The software system of the electronic device 100 can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture. In the embodiment of the present invention, the Android system with a layered architecture is used as an example to illustrate the software structure of the electronic device 100.

[0335] FIG17 is a block diagram of the software structure of the electronic device 100 according to an embodiment of the present invention.

[0336] A layered architecture divides software into several layers, each with distinct roles and responsibilities. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0337] The application layer can include a series of application packages.

[0338] As shown in FIG17 , the application package may include applications such as camera, gallery, game, call, map, navigation, WLAN, Bluetooth, music, video, and short message.

[0339] The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0340] As shown in FIG17 , the application framework layer may include a window manager, a content provider, a view system, a telephony manager, a resource manager, a notification manager, and the like.

[0341] The window manager is used to manage window programs. The window manager can obtain the display size, determine whether there is a status bar, lock the screen, take screenshots, etc.

[0342] Content providers are used to store and retrieve data and make it accessible to applications. This data can include videos, images, audio, calls made and received, browsing history and bookmarks, phone books, etc.

[0343] The view system includes visual controls, such as those for displaying text and images. The view system is used to build applications. A display panel can be composed of one or more views. For example, a display panel containing a text notification icon can include a view for displaying text and a view for displaying an image.

[0344] The phone manager is used to provide communication functions of the electronic device 100, such as management of call status (including answering, hanging up, etc.).

[0345] The resource manager provides various resources for applications, such as localized strings, icons, images, layout files, video files, and so on.

[0346] The Notification Manager allows applications to display notifications in the status bar. These messages can be displayed briefly and then disappear automatically without user interaction. For example, the Notification Manager is used to notify users of completed downloads and message reminders. The Notification Manager can also display notifications in the top status bar of the system as icons or scrolling text, such as notifications from background applications, or as dialog windows on the screen. Examples include displaying text messages in the status bar, emitting alert sounds, vibrating electronic devices, or flashing indicator lights.

[0347] Android Runtime includes core libraries and a virtual machine. Android runtime is responsible for scheduling and management of the Android system.

[0348] The core library consists of two parts: one is the function that needs to be called by the Java language, and the other is the Android core library.

[0349] The application layer and application framework layer run in a virtual machine. The virtual machine executes Java files in the application layer and application framework layer as binary files. The virtual machine manages object lifecycles, stack management, thread management, security and exception management, and garbage collection.

[0350] The system library can include multiple functional modules, such as surface manager, media library, 3D graphics processing library (such as OpenGL ES), 2D graphics engine (such as SGL), etc.

[0351] The surface manager is used to manage the display subsystem and provide fusion of 2D and 3D layers for multiple applications.

[0352] The media library supports playback and recording of a variety of common audio and video formats, as well as static image files. The media library can support a variety of audio and video encoding formats, such as: MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc.

[0353] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0354] A 2D graphics engine is a drawing engine for 2D drawings.

[0355] The kernel layer is the layer between hardware and software. The kernel layer includes at least display driver, camera driver, audio driver, and sensor driver.

[0356] The following describes the workflow of the software and hardware of the electronic device 100 in conjunction with capturing a photo scene.

[0357] When the touch sensor 180K receives a touch operation, the corresponding hardware interrupt is sent to the kernel layer. The kernel layer processes the touch operation into a raw input event (including touch coordinates, touch operation timestamp, and other information). The raw input event is stored in the kernel layer. The application framework layer obtains the raw input event from the kernel layer and identifies the control corresponding to the input event. For example, if the touch operation is a touch single-click operation and the control corresponding to the single-click operation is the control of the camera application icon, the camera application calls the interface of the application framework layer to start the camera application, and then starts the camera driver by calling the kernel layer to capture a still image or video through the camera 193.

[0358] The voltage control method provided in the embodiment of the present application can be applied to electronic devices with communication functions. The electronic devices include terminal devices. The specific device form of the terminal device can refer to the above related descriptions and will not be repeated here.

[0359] An embodiment of the present application provides an electronic device comprising: a processor, a display driver chip (DDIC), a pixel circuit, and a memory. The memory stores computer-executable instructions. The processor instructs the display driver chip to drive the pixel circuit. The display driver chip executes the computer-executable instructions stored in the memory, causing the electronic device to perform the above-described method and drive the pixel circuit.

[0360] The present embodiment provides a chip. The chip includes a processor configured to invoke a computer program stored in a memory to execute the technical solution of the above embodiment. The implementation principles and technical effects are similar to those of the above-mentioned related embodiments and will not be further described here.

[0361] The embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program. The above method is implemented when the computer program is executed by the display driver chip (DDIC). The method described in the above embodiment can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium or transmitted on a computer-readable medium. Computer-readable media may include computer storage media and communication media, and may also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium that can be accessed by a computer.

[0362] In one possible implementation, computer-readable media may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium designed to carry or store the desired program code in the form of instructions or data structures and accessible by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of medium. Disk and optical disk as used herein include optical disk, laser disk, optical disk, digital versatile disk (DVD), floppy disk and Blu-ray disk, where disks generally reproduce data magnetically, while optical disks reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0363] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above method.

[0364] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application.It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processing unit of general-purpose computer, special-purpose computer, embedded processing machine or other programmable device to produce a machine, so that the instruction executed by the processing unit of computer or other programmable data processing device produces the device for realizing the function specified in one flow chart flow or multiple flows and / or one block or multiple blocks of block diagram.

[0365] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A voltage control method, characterized in that: Applicable to an electronic device having a pixel circuit, the pixel circuit comprising a driving module, a control end of the driving module being connected to a first node, and a source end of the driving module being connected to a second node; the method comprising: When driving the first area to display the first frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; When driving the second area to display the first frame image, controlling the voltage of the first node to be a third voltage, and controlling the voltage of the second node to be a fourth voltage; Among them, the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first area is the first refresh rate, the refresh rate of the second area is the second refresh rate, and the first refresh rate is lower than the second refresh rate.

2. The method according to claim 1, characterized in that: The first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

3. The method according to claim 1 or 2, characterized in that: The pixel circuit further includes a data writing unit, wherein the data writing unit is connected to the second node; When the first area and the second area of ​​the first frame image are displayed, the data writing unit is enabled; The method further comprises: When driving the first area to display a second frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the second frame of image, the data writing unit is not enabled; When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

4. The method according to claim 3, characterized in that The method further comprises: When driving the first area to display the third frame image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage; when displaying the first area of ​​the third frame image, the data writing unit is not enabled; When driving the second area to display the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the third frame image, the data writing unit is enabled.

5. The method according to claim 4, characterized in that The method further comprises: When driving the first area to display a fourth frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the fourth frame of image, the data writing unit is not enabled; When driving the second area to display the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the fourth frame image, the data writing unit is enabled.

6. The method according to claim 1 or 2, characterized in that: The pixel circuit further includes a data writing unit, wherein the data writing unit is connected to the second node; When the first area and the second area of ​​the first frame image are displayed, the data writing unit is enabled; The method further comprises: When driving the first area to display the second frame image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage; when displaying the first area of ​​the second frame image, the data writing unit is not enabled; When driving the second area to display the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the second frame image, the data writing unit is enabled.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: Determining a starting position and an ending position of the first area based on an identifier of the pixel circuit corresponding to the first area; Based on the identifier of the pixel circuit corresponding to the second area, a starting position and an ending position of the second area are determined.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: When driving the third area to display the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; the refresh rate of the third area is the third refresh rate, and the third refresh rate is lower than the second refresh rate.

9. The method according to any one of claims 1 to 8, characterized in that The driving module comprises a driving thin film transistor DTFT, a drain terminal of the DTFT is connected to a third node, and the DTFT is used to output current to the third node under the control of the first node; The pixel circuit further includes: A first reset unit, connected to the first node, for responding to a first reset signal to load a first initialization voltage to the first node; A storage capacitor, one end of which is connected to the first node, and the other end of which is connected to the positive electrode of the power supply; A first light-emitting control unit, connected to the positive electrode of the power supply and the second node, for loading a first power supply voltage of the positive electrode of the power supply to the second node in response to a light-emitting control signal; a threshold compensation unit, connected to the first node and the third node, and configured to make the third node conductive with the first node in response to a first scanning signal; a second light emitting control unit, connected to the third node and the fourth node, and configured to conduct the third node and the fourth node in response to a light emitting control signal; a light emitting element, one end of which is connected to the fourth node, and the other end of which is connected to the negative electrode of the power supply so as to load the second power supply voltage of the negative electrode of the power supply; A second reset unit, connected to the fourth node, and configured to load a second initialization voltage to the fourth node in response to a second reset signal; a data writing unit connected to the second node and configured to load a data voltage to the second node in response to a second scanning signal; The third reset unit is connected to the second node and is used for loading a third initialization voltage to the second node in response to a second reset signal.

10. The method according to claim 9, characterized in that The first reset unit includes a first reset transistor, the first light emitting control unit includes a first light emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light emitting control unit includes a second light emitting control transistor, the light emitting element includes an organic light emitting diode OLED, the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.

11. An electronic device, characterized in that: include: Processor, display driver chip DDIC, pixel circuit and memory; The memory stores computer-executable instructions; The processor instructs the display driver chip to drive the pixel circuit; The display driver chip executes the computer-executable instructions stored in the memory, so that the electronic device executes the method according to any one of claims 1 to 10 and drives the pixel circuit.

12. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the display driver chip DDIC, the method according to any one of claims 1 to 10 is implemented.

13. A computer program product, characterized in that The invention comprises a computer program, which, when being executed, enables a computer to execute the method according to any one of claims 1 to 10.

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