Isolation structure and integrated circuit

Abstract

The present invention relates to an isolation structure, comprising: a junction terminal comprising a plurality of junction terminal floating field plates; and a lateral double-diffused metal-oxide-semiconductor (LDMOS) field effect transistor comprising a plurality of LDMOS floating field plates, wherein each LDMOS floating field plate is electrically connected to at least one junction terminal floating field plate, and the length of each junction terminal floating field plate is greater than the length of the LDMOS floating field plate electrically connected to the junction terminal floating field plate.

Description

Isolation structure and integrated circuit

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 2023107143293, filed on June 15, 2023, entitled “Isolation Structure and Integrated Circuit,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to an isolation structure and an integrated circuit. Background Art

[0004] High-voltage integrated circuits contain both high-voltage and low-voltage semiconductor devices, meaning they have high-voltage and low-voltage regions. Therefore, a high-low voltage isolation structure is required to isolate the potential between the high-voltage and low-voltage regions. This isolation structure includes junction terminations, isolation rings, and a lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS). The LDMOS acts as a gateway for transmitting electrical signals between the high-voltage and low-voltage regions, making it a vulnerable point to breakdown when subjected to high voltage. By employing technical means to evenly distribute the internal potential and avoid potential line concentration, the breakdown voltage of the LDMOS can be increased.

[0005] Summary of the Invention

[0006] According to some embodiments, an isolation structure is provided.

[0007] An isolation structure includes: a junction terminal including a plurality of junction terminal floating field plates; and a lateral double diffused metal oxide semiconductor field effect transistor including a plurality of LDMOS floating field plates, each LDMOS floating field plate being electrically connected to at least one junction terminal floating field plate, and each junction terminal floating field plate being longer than the LDMOS floating field plate to which it is electrically connected. The junction terminal floating field plates and the LDMOS floating field plates are formed of a conductive material.

[0008] The above isolation structure can be applied in integrated circuits. When the devices in the integrated circuit are operating, the junction terminal floating field plate can generate an induced potential on the junction terminal. Because the LDMOS floating field plate is electrically connected to the junction terminal floating field plate, this induced potential can affect the potential of the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate. After each junction terminal floating field plate induces a certain potential at the junction terminal and transmits it to the lateral double diffused metal oxide semiconductor field effect transistor through the LDMOS floating field plate, for the lateral double diffused metal oxide semiconductor field effect transistor, each junction terminal floating field plate is equivalent to an external "voltage source". The potential within the lateral double diffused metal oxide semiconductor field effect transistor will be controlled by the junction terminal floating field plate and the LDMOS floating field plate. Therefore, by controlling the spacing of each LDMOS floating field plate, the potential distribution within the lateral double diffused metal oxide semiconductor field effect transistor can be indirectly controlled. The spacing of the LDMOS floating field plates can also be flexibly adjusted according to design requirements, thus achieving free control of the internal potential of the lateral double diffused metal oxide semiconductor field effect transistor, making the internal potential distribution of the LDMOS uniform and improving the breakdown voltage of the LDMOS.

[0009] In one embodiment, the isolation structure further includes an isolation ring surrounding the LDMOS field effect transistor, wherein the isolation ring is used to isolate the LDMOS field effect transistor from the junction terminal.

[0010] In one embodiment, the isolation ring further includes a plurality of isolation ring floating field plates, each LDMOS floating field plate is electrically connected to a corresponding junction terminal floating field plate through an isolation ring floating field plate, and one end of each isolation ring floating field plate extends to a corresponding junction terminal floating field plate, and the other end extends to a corresponding LDMOS floating field plate.

[0011] In one embodiment, the lateral double diffused metal oxide semiconductor field effect transistor further includes a source region, a drain region, a gate, a drift region and a field region insulating layer, at least a portion of the drift region is located between the source region and the drain region, the field region insulating layer is located on the drift region, one side of the gate is close to the source region and the other side is close to the drain region, the number of the LDMOS floating field plates is the same as the number of the junction terminal floating field plates, and the multiple LDMOS floating field plates are electrically connected to the multiple junction terminal floating field plates in a one-to-one correspondence; the LD The MOS floating field plate includes a first field plate disposed near the source region, a second field plate disposed near the drain region, and a third field plate located between the first and second field plates, wherein the spacing between adjacent third field plates is less than a2, the spacing between one of the second field plates farthest from the drain region and an adjacent third field plate is greater than a3, and the spacing between adjacent second field plates is greater than a3, the spacing between one of the first field plates farthest from the source region and an adjacent third field plate is greater than a4, and the spacing between adjacent first field plates is greater than a4; a2 <a3,a2<a4。

[0012] In one embodiment, the lateral double diffused metal oxide semiconductor field effect transistor includes an NLDMOS and a PLDMOS, the isolation ring includes a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS, and the length of each of the junction terminal floating field plates is the sum of the lengths of the corresponding LDMOS floating field plate of the NLDMOS and the corresponding LDMOS floating field plate of the PLDMOS.

[0013] In one embodiment, the junction terminal further includes a first insulating layer, and the plurality of junction terminal floating field plates are located on the first insulating layer.

[0014] In one embodiment, the junction terminal further includes a cathode region and an anode region, the conductivity type of the cathode region and the anode region being the same as the conductivity type of the drain region of the NLDMOS, the cathode region being electrically connected to the potential of the source region of the NLDMOS through a metal connection, and the anode region being electrically connected to the potential of the drain region of the NLDMOS through a metal connection.

[0015] In one embodiment, each junction terminal floating field plate is connected to a corresponding isolation ring floating field plate and a corresponding LDMOS floating field plate to form a closed loop.

[0016] In one embodiment, the isolation ring further includes an isolation junction, a protection well and a second insulating layer, the multiple isolation ring floating field plates are located on the second insulating layer, the second insulating layer is located on the isolation junction and the protection well, the conductivity type of the isolation junction and the protection well is opposite to the conductivity type of the drain region of the NLDMOS, and the doping concentration of the protection well is greater than the doping concentration of the isolation junction.

[0017] In one embodiment, each isolation ring floating field plate includes a junction terminal connection portion, an LDMOS connection portion and an intermediate portion, one end of the intermediate portion is connected to the junction terminal connection portion, and the angle between the intermediate portion and the extension line of the junction terminal connection portion on the plane is greater than zero degrees and less than 80 degrees, the other end of the intermediate portion is connected to the LDMOS connection portion, and the angle between the intermediate portion and the extension line of the LDMOS connection portion on the plane is greater than zero degrees and less than 80 degrees; the protection well is provided directly below the connection position between at least part of the junction terminal connection portion and the intermediate portion, and the protection well is provided directly below the connection position between at least part of the LDMOS connection portion and the intermediate portion.

[0018] The protection well includes strip-shaped doped regions arranged at the connection positions of the multiple junction terminal connection portions and the middle portion, and strip-shaped doped regions arranged at the connection positions of the multiple LDMOS connection portions and the middle portion; and / or the protection well includes point-shaped doped regions arranged in a column at the connection positions of the multiple junction terminal connection portions and the middle portion, and point-shaped doped regions arranged in a column at the connection positions of the multiple LDMOS connection portions and the middle portion.

[0019] In one embodiment, the distance between the connection position of the junction terminal connection portion and the middle portion and the edge of the isolation ring is b1, and the distance between the connection position of the LDMOS connection portion and the middle portion and the edge of the isolation ring is b2, b1 is 10% to 30% of the width of the isolation ring, and b2 is 10% to 30% of the width of the isolation ring.

[0020] In one embodiment, the junction terminal floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate are made of the same material and are manufactured in the same manufacturing step.

[0021] In one embodiment, the gate is made of the same material as the junction terminal floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate, and are manufactured in the same manufacturing step.

[0022] In one embodiment, the junction terminal floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate are made of doped polysilicon.

[0023] In one embodiment, the spacing between adjacent junction-terminated floating field plates is equal.

[0024] In one embodiment, the spacing between adjacent junction terminal floating field plates is a1, a2 <a1<a3,a2<a1<a4。

[0025] In one embodiment, the spacing between adjacent junction terminal floating field plates is 1.0-3.2 μm, the spacing between adjacent third field plates is 0.5-3.0 μm, the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and an adjacent third field plate is 1.2-4.0 μm, and the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and an adjacent third field plate is 1.2-4.0 μm.

[0026] It would also be necessary to provide an integrated circuit.

[0027] An integrated circuit includes a first voltage region, a second voltage region, and an isolation structure located between the first voltage region and the second voltage region, wherein the isolation structure is the isolation structure described in any of the aforementioned embodiments.

[0028] An operating voltage of the device in the second voltage region is greater than an operating voltage of the device in the first voltage region.

[0029] In the integrated circuit described above, when devices in the first and second voltage regions operate, the junction terminal floating field plate on the junction terminal can generate an induced potential. Because the LDMOS floating field plate is electrically connected to the junction terminal floating field plate, this induced potential affects the potential of the lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) through the LDMOS floating field plate. Because the potential lines of the LDMOS are relatively concentrated at the source and drain, by setting a wider spacing between the first and second field plates located near the source and drain regions and a narrower spacing between the third field plates located in the middle of the drift region, the potential gradient of the LDMOS near the source and drain regions can be reduced, while the potential gradient near the middle of the drift region can be increased. This results in a more uniform potential distribution across the LDMOS and improves the breakdown voltage of the LDMOS.

[0030] In one embodiment, the drain of the NLDMOS is connected to the potential of the second voltage region, and the source of the NLDMOS is grounded. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0032] FIG1 is a front view of an integrated circuit according to an embodiment;

[0033] FIG2 is a cross-sectional view taken along line AA' of FIG1;

[0034] FIG3 is a cross-sectional view taken along line BB' of FIG1;

[0035] FIG4 is a cross-sectional view taken along line CC' of FIG1;

[0036] FIG5 is a cross-sectional view taken along line DD' in FIG1;

[0037] FIG6 is a cross-sectional view taken along line EE' in FIG1;

[0038] FIG7 is a partial enlarged view of the first isolation ring in FIG1;

[0039] FIG8 is a partial enlarged view near the first isolation ring in one embodiment;

[0040] FIG9 is a cross-sectional view along line DD' in FIG1 in an embodiment with a protection well;

[0041] FIG10 is a cross-sectional view along line EE' in FIG1 in an embodiment having a protection well;

[0042] 11 is a cross-sectional view along line DD' in FIG. 1 in another embodiment having a protection well;

[0043] FIG12 is a cross-sectional view along line EE' in FIG1 in another embodiment having a protection well;

[0044] FIG13 is a partial enlarged view near the first isolation ring in another embodiment;

[0045] FIG14 is a partial enlarged view near the first isolation ring in yet another embodiment. DETAILED DESCRIPTION

[0046] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. In this specification, "connected" should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0050] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It will also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0052] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0053] According to some embodiments, a semiconductor high-low voltage isolation structure is proposed. By controlling the potential of the LDMOS within the isolation structure through a variable-pitch field plate, the potential distribution and surface electric field distribution within the LDMOS drift region can be regulated, thereby preventing the LDMOS from becoming a weak point in the isolation structure and obtaining a high-low voltage isolation structure with better isolation capability. Figure 1 is a schematic structural diagram of an integrated circuit in one embodiment, including a low-voltage region 100, a high-voltage region 300, and an isolation structure located between the low-voltage region 100 and the high-voltage region 300. The operating voltage of the device in the high-voltage region 300 is greater than the operating voltage of the device in the low-voltage region 100, and the isolation structure is used to isolate the potential between the high-voltage region 300 and the low-voltage region 100.

[0054] In one embodiment, the isolation structure includes a junction termination 210 and a LDMOS field effect transistor.

[0055] The junction terminal 210 includes a plurality of junction terminal floating field plates 211. The lateral double diffused metal oxide semiconductor field effect transistor includes a plurality of LDMOS floating field plates 251. Each LDMOS floating field plate 251 is electrically connected to at least one junction terminal floating field plate 211. The length of each junction terminal floating field plate 211 is greater than the length of the LDMOS floating field plate 251 to which it is electrically connected. Each junction terminal floating field plate 211 and the LDMOS floating field plate 251 are made of a conductive material.

[0056] In this embodiment, multiple LDMOS floating field plates 251 are electrically connected to multiple junction terminal floating field plates 211 in a one-to-one correspondence, i.e., one LDMOS floating field plate 251 is electrically connected to one junction terminal floating field plate 211. In other embodiments, one junction terminal floating field plate 211 may be connected to multiple LDMOS floating field plates 251, i.e., the LDMOS floating field plate 251 electrically connected to a particular junction terminal floating field plate 211 may be bifurcated into multiple LDMOS floating field plates 251 in the LDMO region. Alternatively, one LDMOS floating field plate 251 may be connected to multiple junction terminal floating field plates 211, i.e., the junction terminal floating field plate 211 electrically connected to a particular LDMOS floating field plate 251 may be bifurcated into multiple LDMOS floating field plates in the junction terminal region.

[0057] When the devices in the integrated circuit (i.e., the low-voltage devices in the low-voltage region 100 and the high-voltage devices in the high-voltage region 300) are operating, an induced potential is generated by the junction terminal floating field plate 211 on the junction terminal 210. Because the LDMOS floating field plate 251 is electrically connected to the junction terminal floating field plate 211, the induced potential affects the potential of the LDMOS field-effect transistor through the LDMOS floating field plate 251. After each junction terminal floating field plate 211 induces a certain potential on the junction terminal 210 and transmits it to the lateral double diffused metal oxide semiconductor field effect transistor through the junction terminal floating field plate 211 and the LDMOS floating field plate 251, for the lateral double diffused metal oxide semiconductor field effect transistor, each junction terminal floating field plate 211 is equivalent to an external "voltage source". The potential within the lateral double diffused metal oxide semiconductor field effect transistor will be controlled by the junction terminal floating field plate 211 and the LDMOS floating field plate 251. Therefore, by simply controlling the spacing of each LDMOS floating field plate 251, the potential distribution within the lateral double diffused metal oxide semiconductor field effect transistor can be indirectly controlled. The spacing of the LDMOS floating field plates 251 can also be flexibly adjusted according to design requirements, thereby achieving free control of the internal potential of the lateral double diffused metal oxide semiconductor field effect transistor.

[0058] The isolation structure shown in FIG1 also includes an isolation ring surrounding the LDMOS transistor. The isolation ring is used to isolate the LDMOS transistor from the junction terminal 210. The isolation ring is connected to the LDMOS transistor and the junction terminal 210. In the embodiment shown in FIG1 , the isolation ring includes a first isolation ring 230 and a second isolation ring 250. The LDMOS transistor includes an NLDMOS 220 and a PLDMOS 240. The first isolation ring 230 surrounds the NLDMOS 220, and the second isolation ring 250 surrounds the PLDMOS 240. A floating field plate refers to a field plate that is not connected to a potential. The primary structure of the first isolation ring 230 and the second isolation ring 250 is an isolation junction 233 (see FIG5 ). In one embodiment of the present application, the isolation junction is a P-type doped region.

[0059] FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1. Please refer to FIGS. 1 and 2 together. In one embodiment, the NLDMOS 220 includes a source region 222, a drain region 224, a gate 226, a drift region 223, a field region insulating layer 32, and an LDMOS floating field plate 251. At least a part of the drift region 223 is located between the source region 222 and the drain region 224, and the field region insulating layer 32 is located on the drift region 223. One side of the gate 226 is close to the source region 222 and the other side is close to the drain region 224. The source region 222 and the gate 226 are arranged close to the low voltage region 100, and the drain region 224 is arranged close to the high voltage region 300. The number of LDMOS floating field plates 251 is the same as the number of junction terminal floating field plates 211, and the multiple LDMOS floating field plates 251 are electrically connected to the multiple junction terminal floating field plates 211 in one-to-one correspondence. Each LDMOS floating field plate 251 includes a first field plate arranged close to the source region 222, a second field plate arranged close to the drain region 224, and a third field plate located between the first field plate and the second field plate. In the embodiment shown in FIGS. 1 and 2, the number of LDMOS floating field plates 251 is N. Starting from the LDMOS floating field plate 251 closest to the drain region 224, the 1st to the p-1th are the second field plates, the pth to the N-mth are the third field plates, and the N-m+1th to the Nth are the first field plates. The distance between adjacent third field plates is less than a2. The distance between the farthest one (i.e., p-1) of the multiple second field plates from the drain region 224 and an adjacent third field plate (i.e., p) is greater than a3, and the distance between adjacent second field plates is greater than a3. The distance between the farthest one (i.e., N-m+1) of the multiple first field plates from the source region 222 and an adjacent third field plate (i.e., N-m) is greater than a4, and the distance between adjacent first field plates is greater than a4. The relationship among a2, a3, and a4 is: a2 < a3, a2 < a4. That is, the distance between the first field plate arranged close to the source region 222 and the second field plate arranged close to the drain region 224 is set wider, and the distance between the third field plates located at the middle position in the drift region 223 is set narrower.

[0060] FIG. 3 is a cross-sectional view taken along line B-B' of FIG. 1. Please refer to FIGS. 1 and 3 together. In one embodiment, the PLDMOS 240 includes a source region 242, a drain region 244, a gate 246, a drift region 243, a field region insulating layer 34, and an LDMOS floating field plate 251. At least a part of the drift region 243 is located between the source region 242 and the drain region 244, and the field region insulating layer 34 is located on the drift region 243. One side of the gate 246 is close to the source region 242, and the other side is close to the drain region 244. The source region 242 and the gate 246 are arranged close to the high voltage region 300, and the drain region 244 is arranged close to the low voltage region 100. The number of LDMOS floating field plates 251 is the same as the number of junction terminal floating field plates 211, and the multiple LDMOS floating field plates 251 are electrically connected to the multiple junction terminal floating field plates 211 in one-to-one correspondence. Each LDMOS floating field plate 251 includes a first field plate arranged close to the source region 242, a second field plate arranged close to the drain region 244, and a third field plate located between the first field plate and the second field plate. In the embodiment shown in FIGS. 1 and 3, the number of LDMOS floating field plates 251 is N. Starting from the LDMOS floating field plate 251 closest to the source region 244, the 1st to the (p - 1)th are the first field plates, the pth to the (N - m)th are the third field plates, and the (N - m + 1)th to the Nth are the second field plates. The spacing between adjacent third field plates is less than a2. The spacing between the second field plate farthest from the drain region 244 among the multiple second field plates (i.e., the (N - m + 1)th) and the adjacent third field plate (i.e., the (N - m)th) is greater than a3, and the spacing between adjacent second field plates is greater than a3. The spacing between the first field plate farthest from the source region 242 among the multiple first field plates (i.e., the (p - 1)th) and the adjacent third field plate (i.e., the pth) is greater than a4, and the spacing between adjacent first field plates is greater than a4; then the relationship among a2, a3, and a4 is: a2 < a3, a2 < a4. That is, the spacing between the first field plate arranged close to the source region 242 and the second field plate arranged close to the drain region 244 is set wider, and the spacing between the third field plates located at the middle position of the drift region 243 is set narrower.

[0061] The length of each junction terminal floating field plate 211 is greater than the length of the corresponding LDMOS floating field plate to ensure that the potential of the junction terminal floating field plate 211 is dominant. Taking FIG. 1 as an example, that is, the length of each junction terminal floating field plate 211 is greater than the sum of the lengths of the LDMOS floating field plates 251 in the corresponding NLDMOS 220 and the LDMOS floating field plates 251 in the PLDMOS 240.

[0062] Since the potential lines at the source and drain of a lateral double-diffused metal oxide semiconductor field-effect transistor are relatively concentrated, by setting the spacing of the first field plate / second field plate near the source region / drain region wider and the spacing of the third field plate at the middle position of the drift region narrower, the potential gradient near the source region / drain region of the lateral double-diffused metal oxide semiconductor field-effect transistor can be reduced, and the potential gradient near the middle of the drift region can be increased, so that the potential distribution of the lateral double-diffused metal oxide semiconductor field-effect transistor becomes more uniform, and the breakdown voltage of the LDMOS in the isolation structure is improved.

[0063] In the embodiment shown in FIG. 1, the isolation ring further includes a plurality of isolation ring floating field plates 231 having the same number as the junction terminal floating field plates 211. Each junction terminal floating field plate 211 is electrically connected to a corresponding LDMOS floating field plate 251 through a corresponding isolation ring floating field plate 231. One end of each isolation ring floating field plate 231 extends to a corresponding junction terminal floating field plate 211, and the other end extends to a corresponding LDMOS floating field plate 251.

[0064] In one embodiment, the spacing between adjacent junction terminal floating field plates is a1, and a2 < a1 < a3, a2 < a1 < a4. On the basis of satisfying the foregoing conditions a2 < a1 < a3, a2 < a1 < a4, the spacing between adjacent junction terminal floating field plates 211 is 1.0 - 3.2 μm, the spacing between adjacent third field plates is 0.5 - 3.0 μm, the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and an adjacent third field plate are 1.2 - 4.0 μm, and the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and an adjacent third field plate are 1.2 - 4.0 μm.

[0065] In an embodiment of the present application, the adjacent junction terminal floating field plates 211 are equally spaced at a spacing L1. In the NLDMOS 220, the first to pth LDMOS floating field plates 251 near the drain region 224 are equally spaced at a spacing L3, the (N - m)th to Nth LDMOS floating field plates 251 near the source region 222 are equally spaced at a spacing L4, and the remaining pth to (N - m)th LDMOS floating field plates 251 are equally spaced at a spacing L2. In the PLDMOS 240, the first to pth LDMOS floating field plates 251 near the source region 242 are equally spaced at a spacing L6, the (N - m)th to Nth LDMOS floating field plates 251 near the drain region 244 are equally spaced at a spacing L7, and the remaining pth to (N - m)th LDMOS floating field plates 251 are equally spaced at a spacing L5. And the relationship is satisfied: L1 > L2, L1 > L5, L3 > L1, L4 > L1, L6 > L1, L7 > L1.

[0066] In one embodiment, the total number N of the plurality of floating field plates ranges from 10 to 100, the values ​​of p and m range from 2 to 15, and the value of Npm ranges from 1 to 96.

[0067] In one embodiment, the source region 222 and drain region 224 of the NLDMOS 220 are N+ regions, and the drift region 223 is an N-type drift region. The source region 242 and drain region 244 of the PLDMOS 240 are P+ regions, and the drift region 243 is a P-type drift region.

[0068] In the embodiment shown in FIG2 , the NLDMOS 220 further includes a body region 221, a P-well 225, an N-well 227, a deep N-well 229, and a P-type buried layer 228. The body region 221 and the source region 222 are connected through contact holes and then short-circuited. The body region 221 and the source region 222 are located in the P-well 225. The drain region 224 is located in the N-well 227. The field insulating layer 32 of the NLDMOS 220 is located between the source region 222 and the drain region 224. The P-type buried layer 228 is located below the drift region 223 and the P-well 225. The deep N-well 229 is located below the drift region 223 and the N-well 227.

[0069] In the embodiment shown in FIG3 , PLDMOS 240 further includes a body region 241, a P-well 245, an N-well 247, a deep N-well 249, and a P-type buried layer 248. The body region 241 and the source region 242 are connected through contact holes and then short-circuited. The body region 241 and the source region 242 are located in the N-well 247. The drain region 244 is located in the P-well 245. The field insulating layer 34 of PLDMOS 240 is located between the source region 242 and the drain region 244. The deep N-well 249 is located below the drift region 243 and the N-well 247. The P-type buried layer 248 is located in the deep N-well 249 and below the drift region 243 and the P-well 245.

[0070] In one embodiment, the drain of NLDMOS 220 is connected to the potential of high voltage region 300 and the source of NLDMOS 220 is grounded. In one embodiment, the source of PLDMOS 240 is connected to the potential of high voltage region 300 and the drain of PLDMOS 240 is grounded.

[0071] In one embodiment, the isolation structure (including the junction terminal 210, the isolation ring, and the LDMOS field-effect transistor) further includes a substrate 10 at the bottom and a passivation layer 20 at the top surface of the device. In the embodiment shown in FIG1 , the substrate 10 is made of P-type doped single crystal silicon.

[0072] In one embodiment, the junction terminal floating field plate 211, the isolation ring floating field plate 231, and the LDMOS floating field plate 251 are made of the same material and are fabricated in the same process. In one embodiment, the junction terminal floating field plate 211, the isolation ring floating field plate 231, and the LDMOS floating field plate 251 are made of doped polysilicon. In one embodiment, the gates of the lateral double diffused metal oxide semiconductor field effect transistors (including NLDMOS 220 and PLDMOS 240) are made of doped polysilicon. In one embodiment, the junction terminal floating field plate 211, the isolation ring floating field plate 231, the LDMOS floating field plate 251, the gates 226, and the gates 246 can be fabricated in the same process.

[0073] 4 is a cross-sectional view along line CC' of FIG1 . Referring to FIG1 and FIG4 , in one embodiment, the junction terminal 210 further includes a first insulating layer 31 , and each junction terminal floating field plate 211 is located on the first insulating layer 31 .

[0074] In one embodiment, the first insulating layer 31 , the field insulating layer 32 , and the field insulating layer 34 may be made of silicon oxide, such as silicon dioxide.

[0075] In the embodiment shown in FIG4 , the junction terminal 210 further includes a cathode region 212 and an anode region 214. The conductivity type of the cathode region 212 and the anode region 214 is the same as that of the drain region 224 of the NLDMOS 220, i.e., both are N+ regions. The cathode region 212 is electrically connected to the potential of the source region 222 of the NLDMOS 220 via a metal connection (not shown) extending from a contact hole, and the anode region 214 is electrically connected to the potential of the drain region 224 of the NLDMOS 220 via a metal connection (not shown) extending from a contact hole. Providing a structure similar to an NLDMOS without a gate in the junction terminal 210 facilitates isolation between the high-voltage region 300 and the low-voltage region 100.

[0076] In the embodiment shown in Figure 4, the junction terminal 210 further includes an N-type region 213. At least a portion of the N-type region 213 is located between the cathode region 212 and the anode region 214, and the first insulating layer 31 is located on the N-type region 213. The N-type region 213 functions similarly to a drift region.

[0077] In the embodiment shown in FIG4 , the junction termination 210 further includes a terminal isolation junction 271. The terminal isolation junction 271 is located between the N-type region 213 and the low-voltage region 100, and between the N-type region 213 and the high-voltage region 300. The terminal isolation junction 271 has the same conductivity type as the substrate 10. In an embodiment where the substrate 10 is a P-type substrate, the terminal isolation junction 271 is a P-type doped region.

[0078] In one embodiment, junction terminal 210 further includes a body region 216, a P-well 215, an N-well 217, a deep N-well 219, and a P-type buried layer 218. The body region 216 and the cathode region 212 are connected through contact holes and then short-circuited. The body region 216 and the cathode region 212 are located in the P-well 215. The anode region 214 is located in the N-well 217. A first insulating layer 31 is located between the P-well 215 and the N-well 217. The P-type buried layer 218 is located below the N-type region 213 and the P-well 215. The deep N-well 219 is located below the N-type region 213 and the N-well 217.

[0079] Referring to Figure 1 , in one embodiment, each junction terminal floating field plate 211, along with the corresponding isolation ring floating field plate 231 and LDMOS floating field plate 251, is connected in a plane to form a closed loop, known as a closed floating field plate. This loop can be understood as starting from the junction terminal 210, crossing the isolation ring, and passing to the NLDMOS 220 and PLDMOS 240, where they are connected end to end. The N floating field plates on the junction terminal 210 are evenly spaced at a spacing L1. When the devices in the high-voltage region 300 and the low-voltage region 100 begin to operate, the potential between the high-voltage region 300 and the low-voltage region 100 is separated by the isolation structure. At this time, the drain (i.e., anode region 214) and source (i.e., cathode region 212) of the junction terminal 210, the source and drain of the PLDMOS 240, and the drain and source of the NLDMOS 220 are subjected to the voltage between the high-voltage region 300 and the low-voltage region 100. The potential inside the junction terminal 210, NLDMOS 220, and PLDMOS 240 decreases from the high-voltage potential to the ground potential. Since the floating field plate is a highly doped polysilicon field plate with a large number of free electrons inside, the floating field plate will have a certain induced potential in the electric field. The N junction terminal floating field plates 211 on the junction terminal 210 will be affected by the potential distribution inside the junction terminal 210, and will induce potentials V1, V2, ..., V NThe induced potential of each floating field plate is determined by its location and is nearly equal to the potential of the junction termination region below it. Therefore, the potential distribution within the junction termination 210 controls the induced potential of each floating field plate 211 at the junction termination. When the floating field plate is transferred to the NLDMOS 220 and PLDMOS 240, the potential distribution within the NLDMOS 220 and PLDMOS 240 also has a corresponding impact on the induced potential of the floating field plate. In the isolation structure, the area occupied by the junction termination 210 is much larger than that occupied by the LDMOS. Accordingly, each closed floating field plate passes through a much larger junction termination region than the LDMOS region (see Figure 1). Furthermore, each closed floating field plate can only have a specific induced potential. In other words, each closed floating field plate is an equipotential body in the electric field. Therefore, the potential distribution within the junction termination 210 has an absolute dominant influence on the induced potential generated by the closed floating field plate. Therefore, the induced potential of each closed floating field plate can be considered to be determined by the junction termination 210. Since LDMOS is not sufficient to change the induced potential of each closed floating field plate, each field plate extending from the junction terminal 210 is equivalent to an external "voltage source" for LDMOS, and the floating field plate forces the area of ​​the LDMOS portion below it to be close to the potential of the floating field plate.

[0080] In summary, the semiconductor high-low voltage isolation structure proposed in the above embodiments forms a potential control system with a floating field plate. The potential distribution within the junction terminal 210 controls the induced potential of the closed floating field plate, and the induced potential of the closed floating field plate controls the potential distribution within the LDMOS.

[0081] Based on the above principles, the above embodiment achieves potential control of the LDMOS in the isolation structure using variable-pitch floating field plates. First, the potential distribution within the NLDMOS 220 and PLDMOS 240 is brought close to the junction terminal 210. If two adjacent field plates among the N floating field plates are transmitted to the LDMOS region at a uniform spacing L1, the potential distribution within the LDMOS is clamped by the floating field plates, thus approaching the potential distribution within the junction terminal 210. By varying the spacing of the LDMOS floating field plates 251 on the LDMOS, the potential distribution within the LDMOS is further controlled as required, varying the electric field strength in different regions within the LDMOS. This application utilizes variable-pitch field plates, shifting the N junction terminal floating field plates 211, originally distributed at equal spacing L1 on the junction terminal 210, to be "shifted" on the isolation ring in the form of tilted field plates. Subsequently, these N floating field plates are distributed on the LDMOS at a spacing different from L1. Each floating field plate has a certain electric potential before being transferred to the LDMOS region, so the potential difference between them is also certain. Changing the spacing between the field plates changes the gradient of the electric potential between them. Correspondingly, the gradient of the electric potential of the LDMOS region covered by the variable-spacing LDMOS floating field plates 251 will also change. The electric field strength is the gradient of the electric potential, so changing the spacing of the LDMOS floating field plates 251 in a certain area is equivalent to changing the magnitude of the electric field strength in the corresponding area, thereby achieving control over the internal potential and surface electric field strength of the LDMOS.

[0082] That is, the purpose of the variable spacing field plate is to control the potential distribution of LDMOS with the potential distribution of the junction terminal 210, so that the performance of LDMOS is improved, and therefore the isolation capability of the entire isolation structure is also improved, and the closed floating field plate is an external control for its beneficiary device LDMOS. What is better than the traditional field plate technology is that: the present application can eliminate the potential line concentration point, and the variable spacing field plate can control the potential gradient of each part in the drift region of LDMOS to be almost equal, which means that the potential change is uniform and will not change sharply in some areas, so LDMOS will not become a weak point of breakdown of the isolation structure. The present application has a comprehensive control over the internal potential of LDMOS, and the variable spacing field plate can realize the potential control of the entire drift region of LDMOS, rather than being limited to a part of it. On the other hand, the solution does not lead to the complication of the process and structure, that is, it avoids increasing the manufacturing cost. The closed floating field plate in the above-mentioned embodiment can be a polysilicon field plate. Polysilicon technology is a common process for forming the gates of various device types in the manufacturing of high- and low-voltage isolation structures. Therefore, the closed floating field plate can be formed in the same process as the polysilicon gate, without increasing the number of manufacturing steps. Furthermore, the closed floating field plate does not require changes to the internal structure of the LDMOS when controlling the LDMOS potential, thus reducing the complexity of LDMOS design and manufacturing.

[0083] Figure 5 is a cross-sectional view taken along line D-D' in Figure 1 , Figure 6 is a cross-sectional view taken along line E-E' in Figure 1 , and Figure 7 is a partially enlarged view of the first isolation ring 230 in Figure 1 . In one embodiment, the isolation ring further includes a second insulating layer 33 . Each isolation ring floating field plate 231 is located on the second insulating layer 33 , and the second insulating layer 33 is located on the isolation junction 233 . In one embodiment, the second insulating layer 33 can be made of silicon oxide, such as silicon dioxide. The isolation junction 233 has the same conductivity type as the substrate 10 . In embodiments where the substrate 10 is a P-type substrate, the isolation junction 233 is a P-type doped region.

[0084] Referring to FIG7 , each isolation ring floating field plate 231 includes a junction terminal connection portion 231a, an LDMOS connection portion 231c, and an intermediate portion 231b. One end of the intermediate portion 231b is connected to the junction terminal connection portion 231a, and the angle β between the intermediate portion 231b and the extension of the junction terminal connection portion 231a in a plane is greater than zero degrees and less than 80 degrees. The other end of the intermediate portion 231b is connected to the LDMOS connection portion 231c, and the angle θ between the intermediate portion 231b and the extension of the LDMOS connection portion 231c in a plane is greater than zero degrees and less than 80 degrees. For closed floating field plates, to ensure a more uniform potential distribution across the LDMOS field-effect transistor in the isolation structure, the spacing between adjacent LDMOS floating field plates 251 is different from the spacing between adjacent junction terminal floating field plates 211. By using the aforementioned inclined field plates on the isolation ring to perform “track change”, the spacing of the floating field plates is changed from the junction terminal floating field plates 211 to the spacing distribution of the LDMOS floating field plates 251 .

[0085] In one embodiment, the distance b1 between the junction terminal connection 231a and the middle portion 231b and the edge of the isolation ring is set to b1, and the distance b2 between the junction terminal connection 231c and the middle portion 231b and the edge of the isolation ring is set to b2. b1 is 10% to 30% of the width of the isolation ring, and b2 is 10% to 30% of the width of the isolation ring. That is, the connection between the middle portion 231b and the junction terminal connection 231a / LDMOS connection 231c should maintain a certain distance from the edge of the isolation ring. This is because the corners of the slanted field plate (i.e., at angles β and θ) can cause electric lines of force to converge, generating a strong electric field. Setting the corners a certain distance from the isolation ring edge can improve the isolation ring's withstand voltage (i.e., increase the breakdown voltage) compared to setting the corners at the isolation ring edge, thereby preventing punchthrough between the LDMOS field-effect transistor and the junction terminal 210. In the embodiment shown in FIG7 , the corners of the slanted field plate are located at the D-D' line and the EE' line.

[0086] In one embodiment, the isolation ring further includes a protection well 235, and the second insulating layer 33 is located on the isolation junction 233 and the protection well 235. The conductivity type of the protection well 235 is opposite to the conductivity type of the drain region 222 of the NLDMOS, and the doping concentration of the protection well 235 is greater than the doping concentration of the isolation junction 233. In one embodiment, the protection well 235 is a P+ doped region. The provision of the protection well 235 can further improve the withstand voltage of the isolation ring and prevent potential line concentration from causing the isolation ring to break down. In one embodiment, the protection well 235 is provided directly below the connection location between at least part of the junction terminal connection 231a and the middle portion 231b, and the protection well 235 is provided directly below the connection location between at least part of the LDMOS connection 231c and the middle portion 231b. This is because the corners of the inclined field plate can cause electric lines to concentrate, so arranging the protection well 235 directly below the corners of the inclined field plate can achieve a better effect of improving the withstand voltage of the isolation ring.

[0087] Figure 8 is a partial enlarged view of the isolation structure near the first isolation ring 230 in one embodiment. The protection well 235 in the figure is rendered translucent. In this embodiment, the protection well 235 is a monolithic P+ structure. For ion implantation of the protection well 235, in one embodiment, the width of the implantation window of the protection well 235 should be 100%-110% of the distance between the two ends of the slanted field plates, and the length should be 100%-110% of the maximum distance between the first and Nth field plates, so that it can be positioned beneath the corners of all slanted field plates. Region 100a in Figure 8 has the same structure as part of the low-voltage region 100, and region 300a has the same structure as part of the high-voltage region 300. Figure 9 is a cross-sectional view of the embodiment with the protection well 235 taken along line D-D' in Figure 1, and Figure 10 is a cross-sectional view of the embodiment with the protection well 235 taken along line EE' in Figure 1. Figure 9 is a comparison with the embodiment shown in Figure 5, and Figure 10 is a comparison with the embodiment shown in Figure 6, in which the protection well 235 is added.

[0088] In some embodiments, the protection well 235 may also act only on a portion of the isolation ring floating field plates 231, for example, only on the high-side field plates, as shown in Figures 11 and 12. In the embodiments shown in Figures 11 and 12, the protection well 235 is disposed beneath a portion of the isolation ring floating field plates 231 near the high-voltage region 300, while no protection well 235 is disposed beneath the remaining isolation ring floating field plates 231. In the embodiment shown in Figure 12, the protection well 235 is disposed beneath multiple isolation ring floating field plates 231 spaced apart by a distance L3 (i.e., the first through pth isolation ring floating field plates 231 near the high-voltage region 300). In some embodiments, the length of the protection well 235 is 100%-110% of the maximum distance between the first through pth field plates. For the embodiment in which the protection well 235 is only arranged below some of the isolation ring floating field plates 231, the isolation ring floating field plates 231 acting as the protection well 235 are selected as several isolation ring floating field plates 231 close to the high-voltage area 300, which can achieve a better effect of improving the isolation ring's voltage resistance; in other embodiments, the isolation ring floating field plates 231 can also be arranged below other isolation ring floating field plates 231.

[0089] Figure 13 is an enlarged view of a portion near the first isolation ring 230 in another embodiment, showing a semi-transparent protection well 235. The primary difference from the embodiment shown in Figure 8 is that protection well 235 is a strip-shaped P+-type doped region located at a corner. In one embodiment, where protection well 235 is formed using ion implantation, the implantation window width of protection well 235 is 2%-5% of the isolation ring width C, and the length is 100%-110% of the maximum distance between the first and Nth field plates, ensuring that it fits beneath the corners of all inclined field plates.

[0090] Figure 14 is an enlarged view of a portion near the first isolation ring 230 in another embodiment. The protective well 235 in this figure is rendered semi-transparent. The primary difference from the embodiment shown in Figure 8 is that the protective well 235 is a dot-shaped P+-type doped region arranged in a row at the corner. In one embodiment, where the protective well 235 is formed using ion implantation, the implantation window width of the protective well 235 is 2%-5% of the isolation ring width.

[0091] In one embodiment, the protection well 235 is implanted in the same implantation process as the junction terminal 210 and the P+ implantation process in the LDMOS field-effect transistor. That is, the implantation lithography prior to the ion implantation of the protection well 235 uses the same lithography plate as the body region 221 of the NLDMOS 220, the source region 242 and the drain region 244 of the PLDMOS 240, and the body region 216 of the junction terminal 210. The implantation window lithography is completed in the same lithography step. Therefore, the formation of the protection well 235 does not add any additional manufacturing steps, which helps save costs.

[0092] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0093] Each technical feature of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of each technical feature in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An isolation structure, comprising: A junction terminal, including a plurality of junction terminal floating field plates; A lateral double diffused metal oxide semiconductor field effect transistor includes a plurality of LDMOS floating field plates, each of which is electrically connected to at least one junction terminal floating field plate, and the length of each junction terminal floating field plate is greater than the length of the LDMOS floating field plate electrically connected to the junction terminal floating field plate.

2. The isolation structure according to claim 1, characterized in that: The invention also includes an isolation ring surrounding the lateral double diffused metal oxide semiconductor field effect transistor, wherein the isolation ring is used to isolate the lateral double diffused metal oxide semiconductor field effect transistor from the junction terminal.

3. The isolation structure according to claim 2, characterized in that: The isolation ring also includes multiple isolation ring floating field plates, each LDMOS floating field plate is electrically connected to the corresponding junction terminal floating field plate through an isolation ring floating field plate, one end of each isolation ring floating field plate extends to the corresponding junction terminal floating field plate, and the other end of each isolation ring floating field plate extends to the corresponding LDMOS floating field plate.

4. The isolation structure according to claim 3, characterized in that: The lateral double diffused metal oxide semiconductor field effect transistor also includes a source region, a drain region, a gate, a drift region and a field region insulating layer, at least a portion of the drift region is located between the source region and the drain region, the field region insulating layer is located on the drift region, one side of the gate is close to the source region, and the other side is close to the drain region, the number of the LDMOS floating field plates is the same as the junction terminal floating field plates, and the multiple LDMOS floating field plates are electrically connected to the multiple junction terminal floating field plates in a one-to-one correspondence; the LDMOS floating field plates include The first field plate is arranged near the source region, the second field plate is arranged near the drain region, and the third field plate is arranged between the first field plate and the second field plate, the spacing between adjacent third field plates is less than a2, the spacing between a second field plate farthest from the drain region and the adjacent third field plate among the plurality of second field plates is greater than a3, and the spacing between adjacent second field plates is greater than a3, the spacing between a first field plate farthest from the source region and the adjacent third field plate among the plurality of first field plates is greater than a4, and the spacing between adjacent first field plates is greater than a4; a2 <a3,a2<a4。 5. The isolation structure according to claim 4, characterized in that: The lateral double diffused metal oxide semiconductor field effect transistor includes NLDMOS and PLDMOS, the isolation ring includes a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS, and the length of each of the junction terminal floating field plates is the sum of the lengths of the corresponding LDMOS floating field plate of the NLDMOS and the corresponding LDMOS floating field plate of the PLDMOS.

6. The isolation structure according to claim 5, characterized in that: The junction terminal further includes a first insulating layer, and the plurality of junction terminal floating field plates are located on the first insulating layer.

7. The isolation structure according to claim 6, characterized in that: The junction terminal also includes a cathode region and an anode region, the cathode region and the anode region are N-type regions, the cathode region is electrically connected to the potential of the source region of the NLDMOS through a metal connection, and the anode region is electrically connected to the potential of the drain region of the NLDMOS through a metal connection.

8. The isolation structure according to claim 3, characterized in that: Each of the junction terminal floating field plates is connected with the corresponding isolation ring floating field plate and the corresponding LDMOS floating field plate to form a closed loop.

9. The isolation structure according to claim 7, characterized in that: The isolation ring further comprises an isolation junction, a protection well and a second insulating layer, the plurality of isolation ring floating field plates are located on the second insulating layer, the second insulating layer is located on the isolation junction and the protection well, the isolation junction and the protection well are P-type regions, and the doping concentration of the protection well is greater than the doping concentration of the isolation junction; Each isolation ring floating field plate includes a junction terminal connection portion, an LDMOS connection portion and an intermediate portion, one end of the intermediate portion is connected to the junction terminal connection portion, and the angle between the intermediate portion and the extension line of the junction terminal connection portion on a plane is greater than zero degrees and less than 80 degrees, the other end of the intermediate portion is connected to the LDMOS connection portion, and the angle between the intermediate portion and the extension line of the LDMOS connection portion on a plane is greater than zero degrees and less than 80 degrees; the protection well is provided directly below the connection position between at least part of the junction terminal connection portion and the intermediate portion, and the protection well is provided directly below the connection position between at least part of the LDMOS connection portion and the intermediate portion.

10. The isolation structure according to claim 9, characterized in that: The protection well includes a strip-shaped doped region disposed at a connection position between the plurality of junction terminal connection portions and the middle portion, and a strip-shaped doped region disposed at a connection position between the plurality of LDMOS connection portions and the middle portion.

11. The isolation structure according to claim 9, characterized in that: The protection well includes dot-shaped doped regions arranged in a row at connection positions between the plurality of junction terminal connection portions and the middle portion, and dot-shaped doped regions arranged in a row at connection positions between the plurality of LDMOS connection portions and the middle portion.

12. The isolation structure according to claim 9, characterized in that: The distance between the connection position of the junction terminal connection part and the middle part and the edge of the isolation ring is b1, and the distance between the connection position of the LDMOS connection part and the middle part and the edge of the isolation ring is b2, b1 is 10% to 30% of the width of the isolation ring, and b2 is 10% to 30% of the width of the isolation ring.

13. The isolation structure according to claim 3, characterized in that: The junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate are made of the same material.

14. The isolation structure according to claim 13, characterized in that: The material of the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate is doped polysilicon.

15. The isolation structure according to claim 4, characterized in that: The material of the gate is the same as that of the junction terminal floating field plate, the isolation ring floating field plate and the LDMOS floating field plate.

16. The isolation structure according to claim 4, characterized in that: The spacing between adjacent junction terminal floating field plates is a1, and a2 <a1<a3,a2<a1<a4。 17. The isolation structure according to claim 4, characterized in that: The spacing between adjacent junction terminal floating field plates is equal.

18. The isolation structure according to claim 4, characterized in that: The spacing between adjacent junction terminal floating field plates is 1.0-3.2μm, the spacing between adjacent third field plates is 0.5-3.0μm, the spacing between adjacent first field plates and the spacing between the first field plate farthest from the source region and an adjacent third field plate is 1.2-4.0μm, the spacing between adjacent second field plates and the spacing between the second field plate farthest from the drain region and an adjacent third field plate is 1.2-4.0μm.

19. An integrated circuit comprising a first voltage region, a second voltage region, and an isolation structure according to any one of claims 1 to 18 located between the first voltage region and the second voltage region.

20. The integrated circuit according to claim 19, characterized in that An operating voltage of the device in the second voltage region is greater than an operating voltage of the device in the first voltage region.

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