Circuit board and chip package comprising same

Abstract

A circuit board according to an embodiment of the present invention comprises a first metal layer and a second metal layer disposed on the first metal layer, wherein: the first metal layer includes an oxide layer formed by oxidizing regions starting from the bottom surface of the first metal layer to a predetermined depth; the first metal layer and the second metal layer include a plurality of electrode patterns spaced apart from each other on the oxide layer; and the oxide layer insulates the plurality of electrode patterns from each other.

Description

Circuit board and chip package including same

[0001] The present invention relates to a circuit board, and more particularly to a circuit board applicable to a smart IC and a chip package including the same.

[0002] A smart IC card is a card with at least one integrated circuit chip or chip module built into it. More specifically, a smart IC card is a device that is manufactured in the shape of a thin card, typically made of plastic resin, and has a central processing unit, such as a microprocessor, that can input and output information as well as process information without a separate power source, and a memory device that can store a certain amount of information, so that it can perform simple tasks on its own. In order to implement such a smart IC card, a thin semiconductor chip is mounted on a circuit pattern of a printed circuit board, and on the opposite side of the printed circuit board, a chip package is required in which a circuit pattern electrically connected to the semiconductor chip is formed with contact terminals for contact or non-contact connection to an external card reader, etc., and a card body on which the chip package is mounted.

[0003] Smart IC cards, such as the above, are widely used in various fields, including credit cards, SIM cards, security cards, and identification cards. The circuit board used in these smart IC cards includes an insulating layer and a circuit pattern layer disposed on the insulating layer.

[0004] At this time, the circuit pattern layer includes a bonding portion and a contact portion. The bonding portion refers to the upper surface of the circuit pattern layer. For example, the bonding portion refers to the surface of the circuit pattern layer that is connected to the IC chip. In addition, the contact portion refers to the lower surface or second surface of the circuit pattern layer. For example, the contact portion refers to the surface of the circuit pattern layer that comes into contact with an external device (e.g., a card reader).

[0005] And a surface treatment layer is disposed on each of the bonding portion and contact portion of the circuit pattern layer. The surface treatment layer is formed to impart a certain level of wire bondability, corrosion resistance, oxidation resistance, wear resistance, and hardness to the bonding portion and contact portion of the circuit pattern layer.

[0006] However, conventional circuit boards such as the above require the formation of a surface treatment layer on the circuit pattern layer, which complicates the circuit board manufacturing process and increases manufacturing costs. Furthermore, conventional circuit boards have the problem that their overall thickness increases by the thickness of the surface treatment layer.

[0007] (Patent Document 1) KR 10-2002-0011361 A

[0008] The embodiment seeks to provide a circuit board of a novel structure and a chip package including the same.

[0009] In addition, the embodiment seeks to provide a circuit board from which a surface treatment layer on at least one of a bonding portion and a contact portion of a circuit pattern layer is removed, and a chip package including the same.

[0010] In addition, the embodiment seeks to provide a circuit board and a chip package including the same that can be made slim by drastically reducing the overall thickness.

[0011] In addition, the embodiment seeks to provide a circuit board capable of removing an insulating layer included in an existing circuit board and a chip package including the same.

[0012] In addition, the embodiment seeks to provide a circuit board and a chip package including the same that can improve adhesion between an insulating layer and a circuit pattern layer.

[0013] In addition, the embodiment seeks to provide a circuit board including a circuit pattern layer having different surface roughnesses on the upper surface, side surface, and lower surface, and a chip package including the same.

[0014] A circuit board according to an embodiment includes a first metal layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer includes an oxide layer formed by oxidizing a region of a predetermined depth from a lower surface of the first metal layer, and the first metal layer and the second metal layer include a plurality of electrode patterns spaced apart from each other on the oxide layer, and the oxide layer insulates between the plurality of electrode patterns.

[0015] In addition, the organic layer is further disposed on the lower surface of the oxide layer, and the organic layer functions as an insulating layer that insulates between the plurality of electrode patterns together with the oxide layer.

[0016] In addition, the second metal layer is an alloy layer containing nickel (Ni) and iron (Fe), and the first metal layer is a metal layer plated or deposited on the lower surface of the second metal layer.

[0017] In addition, the second metal layer includes a first metal having a content in the range of 60 wt% to 80 wt%, a second metal having a content in the range of 10 wt% to 22 wt%, a third metal having a content in the range of 3 wt% to 20 wt%, and a fourth metal having a content in the range of 3 wt% to 10 wt%, wherein the first metal includes one of nickel (Ni) and iron (Fe), the second metal includes chromium (Cr), the third metal includes one of nickel (Ni) and iron (Fe) other than the first metal, and the fourth metal includes one of silver (Ag), silicon (Si), and a silver (Ag)-silicon (Si) alloy.

[0018] Additionally, the first metal layer includes copper (Cu).

[0019] In addition, the total thickness of the first metal layer including the oxide layer is in the range of 7 µm to 15 µm, the thickness of the oxide layer in the first metal layer is in the range of 3 µm to 5 µm, and the thickness of the second metal layer is in the range of 100 µm to 200 µm.

[0020] In addition, the total thickness of the first metal layer including the oxide layer has a range of 2 µm to 10 µm, the thickness of the oxide layer in the first metal layer has a range of 0.2 µm to 5 µm, and the thickness of the second metal layer has a range of 20 µm to 50 µm.

[0021] In addition, the oxide layer includes at least one opening, the first metal layer includes a first region vertically overlapping the opening, and a second region excluding the first region, a recess connected to the opening is formed in the first region of the first metal layer, and a thickness of the first region of the first metal layer is smaller than a thickness of the second region of the first metal layer.

[0022] In addition, the second metal layer includes a third region vertically overlapping the opening and the recess and a fourth region excluding the third region, the recess penetrating the upper and lower surfaces of the first metal layer, and the lower surface of the third region of the second metal layer is exposed without contacting the first metal layer and the oxide layer.

[0023] Additionally, the circuit board includes a first adhesive layer disposed between the oxide layer and the organic layer, the organic layer including at least one through hole, and the first adhesive layer including an open area vertically overlapping the through hole.

[0024] Additionally, the lower surface of the oxide layer of the first metal layer has an arithmetic mean roughness (Ra) of between 0.5 µm and 0.9 µm or a 10-point average roughness (Rz) of between 1.5 µm and 2.5 µm.

[0025] Meanwhile, a chip package according to an embodiment includes an insulating layer including at least one through hole; a circuit pattern layer disposed on the insulating layer; an adhesive layer disposed on a lower surface of the insulating layer; an IC chip attached to the adhesive layer; and a connecting member connecting a lower surface of the circuit pattern layer vertically overlapping the through hole and the IC chip, wherein the circuit pattern layer includes a first metal layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer is formed by oxidizing a region at a predetermined depth from the lower surface of the first metal layer and includes an oxide layer corresponding to the insulating layer, and the second metal layer is an alloy layer including nickel (Ni) and iron (Fe).

[0026] Additionally, the adhesive layer is disposed on the lower surface of the oxide layer.

[0027] Additionally, the chip package includes an organic layer disposed under the oxide layer, and the adhesive layer is disposed on a lower surface of the organic layer.

[0028] In addition, the chip package includes a first surface layer including nickel (Ni) disposed on a lower surface of the first metal layer vertically overlapping the through hole; and a second surface layer including gold (Au) disposed on a lower surface of the first surface layer, wherein one end of the connecting member is connected to a terminal of the IC chip, and the other end of the connecting member is connected to the second surface layer.

[0029] A circuit board of an embodiment includes an insulating layer and a circuit pattern layer disposed on the insulating layer. The circuit pattern layer includes a first metal layer and a second metal layer. The second metal layer is a rolled alloy layer, and the first metal layer is a metal layer formed on one surface of the rolled alloy layer. At this time, an oxide layer is formed by oxidizing the surface of the first metal layer at an interface between the first metal layer and the insulating layer. At this time, the oxide layer has a needle-like structure and can improve adhesion between the first metal layer and the insulating layer.

[0030] Accordingly, the embodiment can solve the reliability problem of the circuit pattern layer including the first metal layer being peeled off from the insulating layer by improving the adhesion between the insulating layer and the first metal layer.

[0031] Furthermore, the embodiment can further improve the insulating properties of the circuit board by using an oxide layer disposed between the first metal layer and the insulating layer.

[0032] Meanwhile, in the embodiment, the second metal layer of the circuit pattern layer is formed using an alloy including nickel (Ni)-chromium (Cr)-iron (Fe) and at least one metal selected from the group consisting of silver (Ag), silicon (Si) and alloys thereof. Accordingly, the second metal layer in the embodiment can have a certain level or higher of wear resistance, corrosion resistance, oxidation resistance and hardness. Through this, in the embodiment, the surface treatment layer to be formed on the contact portion of the circuit pattern layer can be omitted or removed, thereby simplifying the manufacturing process of the circuit board and reducing the manufacturing cost.

[0033] Meanwhile, the first metal layer of the embodiment includes a recess formed in a region vertically overlapping the through hole of the insulating layer. Furthermore, the recess can address electrical reliability issues that arise due to the remaining oxide layer in the bonding portion of the circuit pattern layer. Accordingly, the embodiment can improve the electrical reliability of the circuit board and chip package, and further enhance product reliability.

[0034] In addition, the recess of the first metal layer may have a structure that penetrates the first metal layer. Accordingly, the lower surface of the second metal layer that vertically overlaps the recess of the first metal layer may function as a bonding portion of the circuit pattern layer. At this time, the second metal layer of the circuit pattern layer in the embodiment may have a wire bonding property of a certain level or higher. Accordingly, in the embodiment, not only the surface treatment layer that should be formed in the contact portion of the circuit pattern layer, but also the surface treatment layer that should be formed in the bonding portion of the circuit pattern layer can be omitted or removed. Through this, the embodiment can further simplify the manufacturing process of the circuit board accordingly, and can further reduce the manufacturing cost.

[0035] Furthermore, in the embodiment, the insulating layer can be formed using only the oxide layer formed on the lower surface of the first metal layer. That is, in the embodiment, the insulating layer of the organic material is removed while allowing the metal oxide layer to function as the insulating layer.

[0036] That is, the insulating layer of the circuit board of the embodiment may be composed solely of an oxide layer formed on the lower surface of the first metal layer. Accordingly, the embodiment may further reduce the thickness of the circuit board by performing the function of the insulating layer using the oxide layer.

[0037] Furthermore, in the embodiment, by removing the insulating layer of the organic material, the thickness of the second metal layer of the circuit pattern layer can be increased by the thickness of the insulating layer of the organic material. At this time, the second metal layer is a rolled alloy. At this time, when the rolled alloy is manufactured to a thickness of 100㎛ or less, an additional rolling process is required, which increases the manufacturing cost. Accordingly, the embodiment can eliminate the additional rolling process for reducing the thickness of the rolled alloy under the condition that the product thickness is not increased. Through this, the embodiment can simplify the manufacturing process of the circuit board, thereby reducing the manufacturing cost. Furthermore, the embodiment can improve the overall bending characteristics of the circuit board by increasing the thickness of the second metal layer.

[0038] Figure 1 is a drawing showing a chip package according to a comparative example.

[0039] FIG. 2 is a drawing showing a circuit board according to the first embodiment, FIG. 3 is a plan view of the circuit board of FIG. 2 as viewed from above, and FIG. 4 is a plan view of the circuit board of FIG. 2 as viewed from below.

[0040] Fig. 5 is a drawing showing a first modified example of the circuit board of Fig. 2.

[0041] Fig. 6 is a drawing showing a third modified example of the circuit board of Fig. 2.

[0042] Fig. 7 is a drawing showing a fourth modified example of the circuit board of Fig. 2.

[0043] Figure 8 is a drawing showing a chip package according to the first embodiment.

[0044] Figure 9 is a drawing showing a circuit board according to the second embodiment.

[0045] Fig. 10 is a drawing showing a modified example of the circuit board of the second embodiment of Fig. 9.

[0046] Fig. 11 is a drawing showing a chip package of the second embodiment.

[0047] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably only for the convenience of writing the specification, and do not in themselves have distinct meanings or roles. In addition, when describing the embodiments disclosed in this specification, if it is determined that a specific description of a related known technology may obscure the gist of the embodiments disclosed in this specification, a detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

[0048] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0049] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0050] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0051] In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0053]

[0054] - Comparison example -

[0055] Before describing the embodiment, a comparative example that is compared to the circuit board of the embodiment of the present invention will be described.

[0056]

[0057] Figure 1 is a drawing showing a chip package according to a comparative example.

[0058] Referring to FIG. 1, a chip package according to a comparative example includes an insulating layer (10), a circuit pattern layer (20), a first surface treatment layer (30), a second surface treatment layer (40), an adhesive layer (50), an IC chip (60), and a connecting member (70).

[0059] The chip package of the comparative example includes an insulating layer (10), and a circuit pattern layer (20) is arranged on at least one surface of the insulating layer (10).

[0060] At this time, the circuit pattern layer (20) in the comparative example is a copper layer containing pure copper.

[0061] The above insulating layer (10) includes at least one through hole (15). And, the circuit pattern layer (20) includes a bonding portion that vertically overlaps the through hole (15). For example, at least a portion of the circuit pattern layer (20) vertically overlaps the through hole (15), and the lower surface of the circuit pattern layer (20) that vertically overlaps the through hole (15) functions as a bonding portion that is electrically connected to an IC chip (60).

[0062] Additionally, the upper surface of the circuit pattern layer (20) functions as a contact portion such as a connector that comes into contact with an external device (e.g., a card reader).

[0063] At this time, different characteristics are required for the bonding portion and contact portion of the circuit pattern layer (20).

[0064] For example, the bonding portion of the circuit pattern layer (20) requires a wire bonding property of a certain level or higher for bonding the connecting member (70) that is electrically connected to the IC chip (60).

[0065] In addition, the contact portion of the circuit pattern layer (20) is exposed to the outside of the chip package, and therefore requires a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness for continuous connection with an external device.

[0066] Accordingly, the circuit board of the comparative example has a first surface treatment layer (30) formed on the bonding portion of the circuit pattern layer (20), and a second surface treatment layer (40) formed on the contact portion of the circuit pattern layer (20). The first surface treatment layer (30) and the second surface treatment layer (40) include a nickel metal layer (Ni) and a gold metal layer (Au), respectively.

[0067] The nickel metal layer functions as a barrier to prevent oxidation of copper (Cu) forming the circuit pattern layer (20) and to prevent diffusion of the copper (Cu) into the gold metal layer. In addition, the gold metal layer of the first surface treatment layer (30) is formed on the outermost surface of the bonding portion of the circuit pattern layer (20), thereby providing a certain level or higher of wire bondability to the bonding portion. In addition, the gold metal layer of the second surface treatment layer (40) is formed on the outermost surface of the contact portion of the circuit pattern layer (20), thereby providing a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness to the contact portion.

[0068] However, the circuit board of the comparative example as described above must necessarily form a first surface treatment layer (30) and a second surface treatment layer (40) on the bonding portion and contact portion of the circuit pattern layer (20), respectively, and there is a problem that the manufacturing process becomes complicated and the manufacturing cost increases.

[0069] In addition, the circuit board of the comparative example reduces the thickness of the gold metal layer of the second surface treatment layer (40) for the purpose of reducing the manufacturing cost. However, when the thickness of the gold metal layer is reduced, there is a problem that the gold metal layer wears out during long-term use of the circuit board, thereby damaging the product design.

[0070] Meanwhile, in the comparative example, the circuit pattern layer (20) is formed of an aluminum alloy to remove at least one of the first and second surface treatment layers as described above. However, the aluminum alloy has a low strength characteristic. Accordingly, in order for the contact portion of the circuit pattern layer to have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness, the thickness of the aluminum alloy must be 80 ㎛ or more.

[0071] And, when the thickness of the aluminum alloy exceeds 80㎛, the overall thickness of the circuit board increases accordingly, and the line width or pitch of the circuit pattern layer (20) increases, thereby reducing the circuit integration.

[0072]

[0073] - Example -

[0074] FIG. 2 is a drawing showing a circuit board according to the first embodiment, FIG. 3 is a plan view of the circuit board of FIG. 2 as viewed from above, and FIG. 4 is a plan view of the circuit board of FIG. 2 as viewed from below.

[0075] Hereinafter, the circuit board of the first embodiment will be described with reference to FIGS. 2 to 4.

[0076]

[0077] Referring to FIGS. 2 to 4, the circuit board of the first embodiment includes an insulating layer (110) and a circuit pattern layer.

[0078] Specifically, the circuit pattern layer includes a first metal layer (120) disposed on the insulating layer (110) and a second metal layer (130) disposed on the first metal layer (120). Furthermore, one surface of the first metal layer (120) includes an oxide layer (125) formed using an oxide. For example, the oxide layer (125) of the first metal layer (120) is formed between the first metal layer (120) and the insulating layer (110).

[0079] The above oxide layer (125) can function to improve the adhesion between the circuit pattern layer and the insulating layer (110). In addition, the oxide layer (125) can function as the insulating layer (110). For example, the oxide layer (125) formed on the surface of the first metal layer (120) has non-conductivity. Therefore, the oxide layer (125) can also be said to be an insulator that functions as an insulating agent together with the insulating layer (110) in the circuit board of the first embodiment.

[0080] At this time, the drawing shows that the oxide layer (125) is a separate layer from the first metal layer (120), but in reality, the oxide layer (125) means a part of the first metal layer (120).

[0081] Accordingly, the insulating layer of the circuit board of the first embodiment may include a 'first insulating layer' corresponding to the insulating layer (110) and a 'second insulating layer' corresponding to the oxide layer (125) of the first metal layer (120).

[0082] The insulating layer (110) includes an insulating material.

[0083] The above insulating layer (110) has a thickness in the range of 60 µm to 120 µm, or a thickness in the range of 70 µm to 110 µm, or a thickness in the range of 80 µm to 100 µm.

[0084] If the thickness of the insulating layer (110) is less than 60 μm, the rigidity of the circuit board may be weakened, and thus the bending characteristics of the circuit board may be degraded. If the thickness of the insulating layer is less than 60 μm, the circuit pattern layer may not be stably formed on the circuit board. For example, if the thickness of the insulating layer (110) is less than 60 μm, the processability in the patterning process for forming the circuit pattern layer is degraded.

[0085] If the thickness of the above insulating layer (110) exceeds 120 μm, the overall thickness of the circuit board increases, and accordingly, the thickness of the chip package increases.

[0086] The above insulating layer (110) includes at least one through hole (110T).

[0087] The above through hole (110T) penetrates the upper and lower surfaces of the insulating layer (110).

[0088] A circuit pattern layer is formed on the insulating layer (110). The circuit pattern layer is formed on the upper surface of the insulating layer (110). However, the embodiment is not limited thereto, and the circuit pattern layer may be formed on the lower surface of the insulating layer (110).

[0089] The above circuit pattern layer includes a plurality of metal layers.

[0090] For example, the circuit pattern layer includes a first metal layer (120) disposed on the upper surface of the insulating layer (110). In addition, the circuit pattern layer includes a second metal layer (130) disposed on the upper surface of the first metal layer (120).

[0091] The second metal layer (130) is an alloy layer. In addition, the first metal layer (120) may be a plated or deposited metal layer formed on one surface of the second metal layer (130), which is the alloy layer. The first metal layer (120) is disposed with a certain thickness on the lower surface of the second metal layer (130) to form the oxide layer (125).

[0092] That is, the second metal layer (130) is an alloy layer manufactured by a rolling method. Accordingly, due to the characteristics of the alloy layer manufactured by a rolling method, the surface roughness of the second metal layer (130) can have a very low value. The first metal layer (120) can be a plating layer formed by an electroless plating method on one surface of the second metal layer (130) or a deposition layer deposited by a sputtering method.

[0093] The first metal layer (120) above includes copper. However, the embodiment is not limited thereto, and the first metal layer (120) may be formed by plating or depositing a metal layer other than copper on one surface of the second metal layer (130).

[0094] The first metal layer (120) has an arithmetic mean roughness (Ra) of an oxide layer (125) ranging from 0.5 µm to 0.9 µm. In addition, the oxide layer (125) of the first metal layer (120) may have a 10-point average roughness (Rz) ranging from 1.5 µm to 2.5 µm. At this time, the oxide layer (125) is a part of the first metal layer (120), and thus, the arithmetic mean roughness (Ra) and the 10-point average roughness (Rz) of the oxide layer (125) may also be referred to as the surface roughness of the lower surface of the first metal layer (120).

[0095] By this, the embodiment can improve the adhesion between the circuit pattern layer and the insulating layer (110) by having the oxide layer (125) of the first metal layer (120) have a surface roughness within the above range.

[0096] At this time, the first metal layer (120) includes an oxide layer (125) formed on the lower surface in contact with the insulating layer (110). Specifically, the first embodiment includes an oxide layer (125) formed at the interface between the first metal layer (120) and the insulating layer (110). The oxide layer (125) is formed by oxidizing a certain depth region of the lower surface of the first metal layer (120) using an oxide material. The oxide layer (125) has a needle-like structure. In addition, the embodiment can improve adhesion with the insulating layer (110) by having the needle-like structure of the oxide layer (125). Accordingly, the embodiment can solve the problem of the circuit pattern layer being peeled off from the insulating layer (110).

[0097] In addition, the oxide layer (125) of the first metal layer (120) has insulating properties. Therefore, the embodiment can further improve the insulating properties between the circuit pattern layer including the first metal layer (120) and the insulating layer (110). Accordingly, the embodiment can improve the electrical reliability of the circuit pattern layer.

[0098] The above oxide layer (125) includes an opening (125T). For example, the oxide layer (125) is partially formed on the lower surface of the first metal layer (120). For example, the oxide layer (125) includes an opening (125T) that vertically overlaps with a through hole (110T) of the insulating layer (110) on the lower surface of the first metal layer (120). Accordingly, at least a portion of the first metal layer (120) vertically overlaps with the through hole (110T) of the insulating layer (110) and the opening (125T) of the oxide layer (125).

[0099] In addition, in the first embodiment, at least a portion of the oxide layer (125) does not vertically overlap the first metal layer (120) and the second metal layer (130). For example, the first metal layer (120) and the second metal layer (130) include a plurality of electrode patterns (not shown) that are horizontally spaced apart from each other on the insulating layer (110). And, the oxide layer (125) of the first embodiment is disposed on the upper surface of the insulating layer (110) between the plurality of electrode patterns. Through this, the first embodiment can further improve the insulating characteristics between the plurality of electrode patterns by using the oxide layer (125).

[0100] In the first embodiment, the thickness of the first metal layer (120) satisfies the range of 2 µm to 10 µm. Preferably, the thickness of the first metal layer (120) satisfies the range of 2.5 µm to 9.5 µm. More preferably, the thickness of the first metal layer (120) satisfies the range of 3 µm to 9 µm. In this case, the thickness of the first metal layer (120) means the total thickness including the thickness of the oxide layer (125).

[0101] If the thickness of the first metal layer (120) is less than 2 µm, the oxide layer (125) of the first metal layer (120) may not have the target level of surface roughness, and thus the adhesion between the first metal layer (120) and the insulating layer (110) may be reduced. In addition, if the thickness of the first metal layer (120) is less than 2 µm, the oxide layer (125) may not have the target thickness. In addition, when the oxide layer (125) does not have the target thickness, the adhesion between the first metal layer (120) and the insulating layer (110) may be reduced, or the insulating properties of the circuit board may be reduced.

[0102] In addition, if the thickness of the first metal layer (120) exceeds 10 μm, the thickness of the circuit pattern layer and the thickness of the circuit board may increase corresponding to the thickness of the first metal layer (120). Accordingly, it may be difficult to slim down the circuit board and chip package.

[0103] The thickness of the oxide layer (125) in the first metal layer (120) satisfies a range of 0.2 µm to 5 µm. Preferably, the thickness of the oxide layer (125) satisfies a range of 0.22 µm to 4.8 µm. More preferably, the thickness of the oxide layer (125) satisfies a range of 0.25 µm to 4.5 µm.

[0104] If the thickness of the oxide layer (125) in the first metal layer (120) is less than 0.2 µm, the insulation properties between the circuit pattern layer and the insulating layer (110) due to the oxide layer (125) may deteriorate. In addition, if the thickness of the oxide layer (125) exceeds 5 µm, the strength of the oxide layer (125) may be reduced, resulting in the problem of the oxide layer (125) breaking. Furthermore, when the strength of the oxide layer (125) is reduced, the adhesion between the insulating layer (110) and the first metal layer (120) may be reduced, resulting in the problem of the first metal layer (120) being peeled off from the insulating layer (110).

[0105] The second metal layer (130) is disposed on the first metal layer (120). The second metal layer (130) is an alloy layer. For example, the second metal layer (130) is formed of an alloy containing nickel (Ni) or iron (Fe) as a main component. For example, the second metal layer (130) may be an alloy layer formed by rolling.

[0106] The second metal layer (130) has a thickness in the range of 20 μm to 50 μm. For example, the second metal layer (130) has a thickness in the range of 25 μm to 45 μm. For example, the second metal layer (130) has a thickness in the range of 30 μm to 40 μm. If the thickness of the second metal layer (130) is less than 20 μm, the resistance value of the second metal layer (130) may increase, and thus signal loss may increase. For example, if the thickness of the second metal layer (130) is less than 20 μm, the signal transmission characteristics of the circuit board may deteriorate. If the thickness of the second metal layer (130) exceeds 50 μm, the overall thickness of the circuit board may increase.

[0107] At this time, in the embodiment, the thickness of the second metal layer (130) is 50 ㎛ or less, and the surface treatment layer formed on the contact portion of the second metal layer (130) can be omitted or removed. This can be achieved by the characteristics of the alloy forming the second metal layer (130), which will be described below.

[0108] The circuit pattern layer including the first metal layer (120) and the second metal layer (130) includes an upper surface and a lower surface. The upper surface of the circuit pattern layer refers to the upper surface of the second metal layer (130). And the lower surface of the circuit pattern layer refers to the lower surface of the first metal layer (120).

[0109] Specifically, the contact portion of the circuit pattern layer refers to the upper surface of the second metal layer (130). In addition, the contact portion of the circuit pattern layer refers to an area that is positioned at the outermost portion of a circuit board and a chip package including the circuit board. For example, the contact portion of the circuit pattern layer refers to an area that is exposed to the outside of a circuit board and a chip package.

[0110] In addition, the bonding portion of the circuit pattern layer refers to an area connected to the IC chip (170) in the chip package. For example, the bonding portion of the circuit pattern layer refers to an area vertically overlapping with the through hole (110T) of the insulating layer (110). At this time, the oxide layer (125) of the first metal layer (120) is partially formed on the lower surface of the first metal layer (120). For example, the oxide layer (125) is formed in an area remaining on the lower surface of the first metal layer (120) except for the area vertically overlapping with the through hole (110T). Accordingly, the oxide layer (125) includes an opening (125T) vertically overlapping with the through hole (110T) of the insulating layer (110). And, the area of ​​the lower surface of the first metal layer (120) that vertically overlaps the through hole (110T) of the insulating layer (110) and the opening (125T) of the oxide layer (125) functions as the bonding portion.

[0111] At this time, the second metal layer (130) is required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness. For example, the contact portion of the circuit pattern layer corresponding to the upper surface of the second metal layer (130) is required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0112] Accordingly, in the comparative example, a second surface treatment layer (40) was formed on the contact portion of the circuit pattern layer.

[0113] In contrast, in the embodiment, the second metal layer (130) is formed using one of the first and second alloys having a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, hardness, and Y-bonding properties. Through this, in the embodiment, the surface treatment layer formed on the contact portion of the second metal layer (130) can be omitted or removed.

[0114] That is, in the embodiment, by changing the content of metals in the alloy forming the second metal layer (130), the second metal layer (130) itself has a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties even without the surface treatment layer. This is achieved by the types and contents of metals forming the second metal layer (130), which will be described below.

[0115] Below, the composition ratio of metals in the alloy forming the second metal layer (130) will be described.

[0116] At this time, the second metal layer (130) is formed from either the first alloy or the second alloy. The first alloy has nickel (Ni) as its main component, and the second alloy has iron (Fe) as its main component.

[0117]

[0118] - First alloy -

[0119] The second metal layer (130) can be formed of a first alloy containing nickel (Ni) as a main component.

[0120] The first alloy has a certain level of corrosion resistance, oxidation resistance, wear resistance, hardness and wire bondability.

[0121] That is, the first alloy forming the second metal layer (130) contains nickel (Ni) as its main component. For example, the content of nickel (Ni) in the first alloy forming the second metal layer (130) satisfies a range of 60 wt% to 80 wt%. For example, the content of nickel (Ni) in the first alloy is 65 wt% to 78 wt% or 70 wt% to 75 wt%.

[0122] If the nickel (Ni) content in the first alloy is less than 60 wt%, the corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bondability of the second metal layer (130) decrease. Accordingly, a surface treatment layer must be formed on the contact portion of the second metal layer (130), which complicates the manufacturing process, increases the thickness of the circuit board, and increases the manufacturing cost.

[0123] Specifically, when the content of nickel (Ni) in the first alloy is less than 60 wt%, the surface roughness change rate (%) of the second metal layer (130) exceeds 10%. The surface roughness change rate (%) is related to the corrosion resistance, oxidation resistance, and wear resistance of the second metal layer (130).

[0124] Accordingly, the content of nickel (Ni) in the first alloy forming the second metal layer (130) is in the range of 60 wt% to 80 wt%, whereby the surface roughness change rate (%) is 10% or less, preferably 8% or less, and more preferably 5% or less.

[0125] In addition, when the content of nickel (Ni) in the first alloy exceeds 80 wt%, the etching rate (μm / min) in the process of forming the second metal layer (130) using the first alloy decreases. That is, when the content of nickel (Ni) in the first alloy exceeds 80 wt%, the hardness of the first alloy is too high, so that an etching rate (μm / min) within a certain range is not achieved in the process of forming the second metal layer (130). In addition, when the content of nickel (Ni) in the first alloy exceeds 80 wt%, a problem occurs in which nickel ions are eluted onto the surface of the second metal layer (130) formed from the first alloy.

[0126] Meanwhile, the first alloy forming the second metal layer (130) contains chromium (Cr). The content of chromium (Cr) in the first alloy satisfies a range of 10 wt% to 22 wt%. For example, the content of chromium (Cr) in the first alloy satisfies a range of 11 wt% to 21 wt%, or 12 wt% to 18 wt%.

[0127] When the content of chromium (Cr) in the first alloy is less than 10 wt%, the amount of nickel elution to the surface of the second metal layer (130) formed from the first alloy increases.

[0128] At this time, if the content of chromium (Cr) in the first alloy is less than 10 wt%, the effect of preventing nickel (Ni) from dissolving due to chromium (Cr) is reduced, and thus, product reliability problems occur due to nickel ions dissolving to the outside. Accordingly, the first alloy forming the second metal layer (130) in the embodiment includes chromium (Cr) in a content of 10 wt% or more.

[0129] Meanwhile, when the content of chromium (Cr) in the first alloy exceeds 22 wt%, the hardness of the second metal layer (130) increases, and accordingly, the etching rate (㎛ / min) of the second metal layer (130) decreases. In addition, when the content of chromium (Cr) in the second metal layer (130) exceeds 22 wt%, the wire bondability of the second metal layer (130) decreases.

[0130] In addition, when the content of chromium (Cr) in the first alloy is less than 10 wt% or more than 22 wt%, the content of another metal (e.g., nickel or iron) decreases or increases by the corresponding amount, which causes a problem in that the content of the other metal does not satisfy the optimal range described herein.

[0131] Meanwhile, the first alloy forming the second metal layer (130) includes iron (Fe). The content of iron (Fe) in the first alloy satisfies a range of 3 wt% to 20 wt%. The content of iron (Fe) in the first alloy may satisfy a range of 5 wt% to 15 wt%, or 7 wt% to 11 wt%. In the first embodiment, the iron (Fe) functions to improve the rollability (or ductility) of the first alloy.

[0132] At this time, if the content of iron (Fe) in the first alloy is less than 3 wt%, the rollability of the first alloy is reduced, and accordingly, it is difficult to manufacture the thickness of the first alloy, and further, the thickness of the second metal layer (130), to be 50 µm or less.

[0133] In addition, when the content of iron (Fe) in the first alloy exceeds 20 wt%, the content of nickel (Ni) or iron (Fe) decreases accordingly, and the amount of nickel elution increases accordingly or the rate of change (%) in surface roughness increases.

[0134] Meanwhile, the first alloy forming the second metal layer (130) includes any one of silver (Ag), silicon (Si), and a silver (Ag)-silicon (Si) alloy. The silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) can enable the first alloy to have a wire bondability of a certain level or higher.

[0135] Accordingly, the first alloy may be any one of a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag) alloy, a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Si) alloy, and a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag)-silicon (Si) alloy.

[0136] In the first alloy, any one of silver (Ag), silicon (Si) and a silver (Ag)-silicon (Si) alloy has a content in the range of 3 wt% to 10 wt%.

[0137] When the content of any one of silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy in the first alloy is less than 3 wt%, the wire bondability of the second metal layer (130) is less than 4 gf.

[0138] In the first alloy constituting the second metal layer (130), if the content of any one of silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy exceeds 10 wt%, the content of nickel (Ni), chromium (Cr), or iron (Fe) correspondingly decreases, and thus a problem occurs in at least one of the characteristics of the resistance (Ω), etching rate (㎛ / min), surface roughness change rate, and nickel elution amount of the circuit pattern layer.

[0139] Meanwhile, the first alloy constituting the second metal layer (130) includes at least one additive.

[0140] For example, the first alloy forming the second metal layer (130) includes an additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy containing at least two of these. For example, the additive selected from manganese (Mn), tin (Sn), zinc (Zn), and an alloy containing at least two of these is added to refine the structure of the alloy forming the second metal layer (130) to achieve solid solution strengthening.

[0141] Specifically, the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn) and an alloy containing at least two of these satisfies a range of 1 wt% to 5 wt%.

[0142] That is, if the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn) and an alloy containing at least two of these is less than 1 wt%, the solid solution strengthening effect is insufficient, and thus the wear resistance, oxidation resistance and corrosion resistance of the second metal layer (130) are reduced.

[0143] In addition, when the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn) and an alloy including at least two of these exceeds 5 wt%, the resistance characteristics of the second metal layer (130) increase, and thus signal loss increases.

[0144] In addition, when the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn) and an alloy including at least two of these exceeds 5 wt%, the hardness of the second metal layer (130) increases, and the etching rate (㎛ / min) decreases accordingly.

[0145]

[0146] - Second alloy -

[0147] Meanwhile, the second metal layer (130) can be formed of a second alloy containing iron (Fe) as a main component.

[0148] At this time, the second alloy includes the metals that make up the first alloy. However, the content of each metal in the second alloy is different from the content of each metal in the first alloy. For example, the first alloy has nickel as a main component, and the second alloy has iron as a main component. Accordingly, the contents of nickel (Ni), iron (Fe), and chromium (Cr) in the second alloy are different from the contents of nickel (Ni), iron (Fe), and chromium (Cr) in the first alloy.

[0149] That is, the second alloy forming the second metal layer (130) contains iron (Fe) as its main component. For example, the content of iron (Fe) in the second alloy satisfies a range of 60 wt% to 80 wt%, or 61 wt% to 78 wt%, or 63 wt% to 75 wt%. The optimal range of the content of iron (Fe) in the second alloy is 63 wt% to 75 wt%.

[0150] When the content of iron (Fe) in the second alloy is less than 60 wt%, the rollability of the second alloy is reduced, and accordingly, the thickness of the second alloy increases, and further, the thickness of the second metal layer (130) increases. When the content of iron (Fe) in the second alloy exceeds 80 wt%, the wear resistance, corrosion resistance, and oxidation resistance of the second metal layer (130) formed of the second alloy are reduced. In addition, when the content of iron (Fe) in the second alloy exceeds 80 wt%, the resistance (Ω) of the second metal layer (130) formed of the second alloy increases, and thus, signal transmission loss increases. In addition, when the content of iron (Fe) in the second alloy is less than 60 wt% or more than 80 wt%, the content of another metal (e.g., nickel or chromium) decreases or increases by the corresponding amount, which causes a problem in that the content of the other metal does not satisfy the optimal range described herein.

[0151] Meanwhile, the content of chromium (Cr) in the second alloy satisfies a range of 10 wt% to 22 wt%, or 13 wt% to 21 wt%, or 15 wt% to 20 wt%. That is, the optimal range of the content of chromium (Cr) in the second alloy is 15 wt% to 20 wt%.

[0152] When the content of chromium (Cr) in the second alloy is less than 10 wt%, the amount of nickel elution onto the surface of the second alloy increases. In addition, when the content of chromium (Cr) in the second alloy is less than 10 wt%, the hardness of the second metal layer (130) formed from the second alloy decreases. In addition, when the content of chromium (Cr) in the second alloy exceeds 22 wt%, the wire bondability deteriorates.

[0153] Meanwhile, the content of nickel (Ni) in the second alloy satisfies a range of 3 wt% to 20 wt%, or 5 wt% to 18 wt%, or 7 wt% to 15 wt%. That is, the optimal range of the content of nickel (Ni) in the second alloy is 7 wt% to 15 wt%.

[0154] When the content of nickel (Ni) in the second alloy is less than 3 wt%, the surface roughness change rate (%) of the second metal layer (130) exceeds 10%. In addition, when the content of nickel (Ni) in the second alloy exceeds 20 wt%, the etching rate (㎛ / min) in the etching process for forming the second metal layer (130) using the second alloy decreases.

[0155]

[0156] Fig. 5 is a drawing showing a first modified example of the circuit board of Fig. 2.

[0157] Referring to FIG. 5, the circuit board of the first modified example includes an insulating layer (110) and a circuit pattern layer. The circuit pattern layer includes a first metal layer (120) disposed on the insulating layer (110) and including an oxide layer (125). In addition, the circuit pattern layer includes a second metal layer (130) disposed on the first metal layer (120).

[0158] At this time, the lower surface of the first metal layer (120) of the circuit board of Fig. 2 had the same height over the entire area. For example, the lower surface of the first metal layer (120) of the circuit board of Fig. 2 did not have a step.

[0159] In contrast, the circuit board of the first modified example has a lower surface of the first metal layer (120) with a step. For example, the lower surface of the first metal layer (120) includes a first region vertically overlapping with the through hole (110T) of the insulating layer (110) and a second region excluding the first region. In addition, the height of the first region of the lower surface of the first metal layer (120) is different from the height of the second region of the lower surface of the first metal layer (120). Preferably, the height of the first region of the lower surface of the first metal layer (120) is positioned higher than the height of the second region of the lower surface of the first metal layer (120).

[0160] For example, the thickness of the first region of the first metal layer (120) is smaller than the thickness of the second region. Specifically, the lower surface of the first metal layer (120) includes a recess (120S) that vertically overlaps with the through hole (110T) of the insulating layer (110) and the opening (125T) of the oxide layer (125). The recess (120S) is formed by removing a portion of the lower surface of the first metal layer (120) in the process of forming the through hole (110T) of the insulating layer (110) and the opening (125T) of the oxide layer (125). At this time, when the recess (120S) does not exist, the oxide layer (125) may remain in at least a portion of the region of the lower surface of the first metal layer (120) that vertically overlaps with the through hole (110T). And if the oxide layer (125) remains in the area overlapping the through hole (110T), the electrical reliability between the IC chip (170) and the circuit pattern layer may be reduced. Accordingly, in the first modified example, a recess (120S) is formed on the lower surface of the first metal layer (120) in the process of forming the through hole (110T) and the opening (125T). Through this, the embodiment improves the electrical reliability between the bonding portion of the circuit pattern layer and the IC chip (170).

[0161]

[0162] At this time, in the first modified example, the recess (120S) is described as being formed by removing a part of the first metal layer (120), but is not limited thereto.

[0163] For example, the recess (120S) in the second modified example has a through hole type that penetrates the upper and lower surfaces of the first metal layer (120). Accordingly, the lower surface of the second metal layer (130) in the region vertically overlapping the through hole (110T) of the insulating layer (110), the opening (125T) of the oxide layer (125), and the recess (120S) of the first metal layer (120) is exposed. And the exposed lower surface of the second metal layer (130) functions as a bonding portion.

[0164] At this time, in the first embodiment and the first modified example, the lower surface of the first metal layer (120) functions as a bonding portion of the circuit pattern layer. Accordingly, in the first embodiment and the first modified example, a surface treatment layer must be formed on the lower surface of the bonding portion to ensure wire bonding with the IC chip (170).

[0165] In contrast, as in the second modified example, when the recess (120S) penetrates the first metal layer (120), the lower surface of the second metal layer (130) functions as a bonding portion of the circuit pattern layer. In addition, the second metal layer (130) is formed of a first alloy or a second alloy having a wire bonding property of a certain level or higher. Accordingly, the circuit board of the second modified example can be removed up to the surface treatment layer disposed on the bonding portion of the circuit pattern layer.

[0166]

[0167] Fig. 6 is a drawing showing a third modified example of the circuit board of Fig. 2.

[0168] Referring to FIG. 6, the circuit board of the third modified example includes an insulating layer (110), a first metal layer (120), and a second metal layer (130). At this time, the insulating layer (110), the first metal layer (120), and the second metal layer (130) may have substantially the same structure as the first embodiment. Accordingly, a detailed description thereof will be omitted.

[0169] At this time, the oxide layer (125) in the first embodiment included only an opening (125T) formed in an area vertically overlapping with the through hole (110T) of the insulating layer (110).

[0170] In contrast, the oxide layer (125a) of the circuit board of the third modified example includes a first opening (125T1) and a second opening (125T2).

[0171] The first opening (125T1) of the above oxide layer (125a) is formed in an area that vertically overlaps the through hole (110T). The first opening (125T1) corresponds to the opening (125T) of the previous embodiment.

[0172] In addition, the second opening (125T2) of the oxide layer (125a) is formed in an area between the plurality of electrode patterns of the circuit pattern layer in the oxide layer (125a). For example, in the third modified example, in the process of forming the plurality of electrode patterns of the circuit pattern layer, the oxide layer (125a) is removed together with the first metal layer (120) and the second metal layer (130). Accordingly, the oxide layer (125a) further includes the second opening (125T2) between the plurality of electrode patterns.

[0173]

[0174] Fig. 7 is a drawing showing a fourth modified example of the circuit board of Fig. 2.

[0175] Referring to Fig. 7, the circuit board includes an insulating layer (110), a first metal layer (120), and a second metal layer (130) corresponding to the circuit board of Fig. 2. In addition, an oxide layer (125) is formed on the lower surface of the first metal layer (120).

[0176] At this time, the circuit board of the fourth modified example includes a first adhesive layer (140) disposed between the oxide layer (125) of the first metal layer (120) and the insulating layer (110).

[0177] The first adhesive layer (140) may be a bonding sheet. The first adhesive layer (140) may be an epoxy-based bonding sheet, but is not limited thereto.

[0178] The first adhesive layer (140) is positioned between the oxide layer (125) of the first metal layer (120) and the insulating layer (110). Accordingly, in the fourth modified example, the adhesion between the circuit pattern layer and the insulating layer (110) can be further improved.

[0179] The first adhesive layer (140) may have the same planar area as the insulating layer (110). For example, the first adhesive layer (140) may include an open area (140T) corresponding to the through hole (110T) of the insulating layer (110).

[0180] In the fourth modified example, the adhesion between the insulating layer (110) and the circuit pattern layer can be further improved by placing a first adhesive layer (140) between the oxide layer (125) of the first metal layer (120) and the insulating layer (110). As a result, the embodiment can prevent the circuit pattern layer from being peeled off from the insulating layer (110), and thereby further improve the electrical reliability of the circuit pattern layer.

[0181]

[0182] FIG. 8 is a diagram illustrating a chip package according to a first embodiment. The chip package according to the first embodiment may include the circuit board of FIG. 7. However, the embodiment is not limited thereto. For example, the chip package according to the first embodiment may include a circuit board of another embodiment other than the circuit board of FIG. 7.

[0183] The chip package of the first embodiment includes a surface treatment layer (150). The surface treatment layer (150) is formed in an area vertically overlapping with the through hole (110T) of the insulating layer (110) and the opening (125T) of the oxide layer (125) on the lower surface of the circuit pattern layer. The surface treatment layer (150) is formed in a bonding portion of the circuit pattern layer. Preferably, the surface treatment layer (150) is formed on the lower surface of the first metal layer (120) vertically overlapping with the through hole (110T) and the opening (125T).

[0184] At this time, if the recess (120S) in the second modified example has a through hole structure penetrating the first metal layer (120), the surface treatment layer (150) may be omitted. Specifically, the second metal layer (130) has a wire bonding property of a certain level or higher. At this time, if the recess (120S) penetrates the first metal layer (120), the lower surface of the second metal layer (130), not the lower surface of the first metal layer (120), may function as a bonding portion of the circuit pattern layer. Accordingly, the surface treatment layer (150) may also be omitted or removed.

[0185]

[0186] Meanwhile, when the surface treatment layer (150) is formed on the bonding portion, the surface treatment layer (150) includes a metal having a certain level or higher of wire bondability. To this end, the surface treatment layer (150) includes a plurality of surface layers. For example, the surface treatment layer (150) includes a first surface layer including nickel. In addition, the surface treatment layer (150) includes a second surface treatment layer disposed under the first surface layer and including gold. The first surface layer may have a thickness in the range of 2 μm to 3 μm. If the thickness of the first surface layer is less than 2 μm, the bonding reliability between the first metal layer (120) and the second surface layer may be deteriorated. In addition, if the thickness of the first surface layer exceeds 3 μm, the manufacturing cost may increase. Meanwhile, the second surface layer may have a thickness in the range of 0.2 μm to 0.5 μm. If the thickness of the second surface layer is less than 0.2 μm, the wire bondability may be deteriorated. If the thickness of the second surface layer exceeds 0.5 μm, manufacturing costs may increase.

[0187] The chip package includes a second adhesive layer (160) disposed on the lower surface of the insulating layer (110) of the circuit board. The second adhesive layer (160) is for bonding an IC chip (170) to the lower surface of the insulating layer (110). The second adhesive layer (160) may be, but is not limited to, an epoxy, a thermosetting adhesive, or an ultraviolet adhesive.

[0188] An IC chip (170) is attached to the second adhesive layer (160). The IC chip (170) includes a terminal (180). In addition, the terminal (180) of the IC chip (170) is electrically connected to a bonding portion of a circuit pattern layer (specifically, a surface treatment layer (150)) through a connecting member (190) such as a wire. Specifically, the connecting member (190) has one end connected to the terminal (180) of the IC chip (170), and the other end connected to the lower surface of the surface treatment layer (150).

[0189] Meanwhile, the chip package includes a molding layer. The molding layer may be, but is not limited to, EMC (Epoxy Molding Compound). The molding layer is disposed on the lower surface of the insulating layer (110). The molding layer molds the IC chip (170) and the connecting member (190).

[0190]

[0191] Figure 9 is a drawing showing a circuit board according to the second embodiment.

[0192] Below, a circuit board according to the second embodiment will be described.

[0193] At this time, the circuit board of the first embodiment included an insulating layer (110). The insulating layer (110) was an insulating layer of an organic material.

[0194] In contrast, the circuit board of the second embodiment removes the insulating layer (110) included in the circuit board of the first embodiment.

[0195] Referring to FIG. 9, the circuit board includes a first metal layer (220) and a second metal layer (230) disposed on the first metal layer (220).

[0196] At this time, the first metal layer (220) of the second embodiment corresponds to the first metal layer (120) of the first embodiment, and further, the second metal layer (230) of the second embodiment corresponds to the second metal layer (130) of the first embodiment.

[0197] However, the circuit board of the second embodiment has a structure in which the insulating layer (110) is removed from the circuit board of the first embodiment. Accordingly, the first metal layer (220) and the second metal layer (230) in the circuit board of the second embodiment have different thicknesses from the first metal layer and the second metal layer of the first embodiment.

[0198] Specifically, the insulating layer of the circuit board of the second embodiment includes only an oxide layer (225) formed by oxidizing a portion of the first metal layer (220). That is, in the second embodiment, the oxide layer (225) is made to perform the function of the insulating layer (110) of the circuit board of the first embodiment.

[0199] That is, the insulating layer of the circuit board of the second embodiment is an oxide layer (225) formed by oxidizing a portion of the first metal layer (220). In addition, the second embodiment performs the function of the insulating layer by utilizing the oxide layer (225), thereby further reducing the thickness of the product compared to the circuit board of the first embodiment.

[0200] Furthermore, when the circuit board of the second embodiment has the same thickness as the circuit board of the first embodiment, the thickness of the second metal layer (230) can be increased compared to the first embodiment. At this time, the second metal layer (230) is a rolled alloy. At this time, when the rolled alloy is manufactured to a thickness of 100㎛ or less, an additional rolling process is required, which increases the manufacturing cost. In contrast, the circuit board of the second embodiment can eliminate the additional rolling process, thereby simplifying the manufacturing process and reducing the manufacturing cost. Furthermore, the circuit board of the second embodiment can increase the thickness of the second metal layer while maintaining the same thickness as the first embodiment, thereby improving the overall bending characteristics of the circuit board.

[0201] The first metal layer (220) has a thickness in the range of 7 µm to 15 µm. If the first metal layer (220) is less than 7 µm, it is difficult to form an oxide layer (225) of a certain thickness or more on the lower surface of the first metal layer (220), thereby deteriorating the insulating properties of the circuit board. In addition, if the thickness of the first metal layer (220) exceeds 5 µm, the overall thickness of the circuit board increases.

[0202] The oxide layer (225) in the first metal layer (220) satisfies a thickness in the range of 3 µm to 5 µm. If the thickness of the oxide layer (225) in the first metal layer (220) is 3 µm or less, the insulating properties deteriorate and the electrical reliability of the circuit board deteriorates. In addition, if the thickness of the oxide layer (225) exceeds 5 µm, a breakage problem may occur due to a decrease in the strength of the oxide layer (225).

[0203] The above oxide layer (225) includes an opening (225T). The opening (225T) is formed to correspond to an area of ​​the lower surface of the first metal layer (220) that functions as a bonding portion. The opening (225T) is formed by removing a portion of the oxide layer (225) formed on the lower surface of the first metal layer (220).

[0204] The second metal layer (230) has a thickness in the range of 100 μm to 200 μm. If the thickness of the second metal layer (230) is less than 100 μm, the bending characteristics of the circuit board deteriorate. In addition, if the thickness of the second metal layer (230) is less than 100 μm, an additional process is required in the process of manufacturing the second metal layer (230) by rolling. If the thickness of the second metal layer (230) exceeds 200 μm, the overall thickness of the circuit board increases.

[0205]

[0206] Fig. 10 is a drawing showing a modified example of the circuit board of the second embodiment of Fig. 9.

[0207] Referring to FIG. 10, a circuit board of a modified example of the second embodiment includes a recess (220S) formed in an area vertically overlapping with an opening (225T) of the oxide layer (225) on the lower surface of the first metal layer (220).

[0208] The above recess (220S) has a shape that is sunken from the lower surface of the first metal layer (220) toward the upper surface.

[0209] The above recess (220S) is formed to correspond to the opening (225T) of the above oxide layer (225).

[0210] In addition, the recess (220S) has the function of completely removing the oxide layer (225) remaining on the lower surface of the first metal layer (220) that functions as the bonding portion.

[0211] At this time, the recess (220S) in another modified example may have a structure penetrating the first metal layer (220).

[0212]

[0213] Fig. 11 is a drawing showing a chip package of the second embodiment.

[0214] Referring to FIG. 11, the chip package of the second embodiment may include the circuit board of FIG. 9 or FIG. 10.

[0215] The chip package of the second embodiment includes a surface treatment layer (250). The surface treatment layer (250) is formed on the lower surface of the first metal layer (220) vertically overlapping the opening (225T).

[0216] For example, the surface treatment layer (250) is disposed within the recess (220S) of the first metal layer (220). The surface treatment layer (250) includes a first surface layer containing nickel and a second surface layer containing gold.

[0217] The above chip package includes an adhesive layer (260) disposed on the lower surface of the oxide layer (225) of the circuit board.

[0218] An IC chip (270) is attached to the adhesive layer (260). The IC chip (270) includes a terminal (280). In addition, the terminal (280) of the IC chip (270) is electrically connected to a bonding portion of the circuit pattern layer (specifically, a surface treatment layer (250)) through a connecting member (290) such as a wire.

[0219] Meanwhile, the chip package includes a molding layer.

[0220] In the second embodiment, the insulating layer function of the circuit board is achieved by using only the oxide layer formed on the lower surface of the first metal layer.

[0221] A circuit board of an embodiment includes an insulating layer and a circuit pattern layer disposed on the insulating layer. The circuit pattern layer includes a first metal layer and a second metal layer. The second metal layer is a rolled alloy layer, and the first metal layer is a metal layer formed on one surface of the rolled alloy layer. At this time, an oxide layer is formed by oxidizing the surface of the first metal layer at an interface between the first metal layer and the insulating layer. At this time, the oxide layer has a needle-like structure and can improve adhesion between the first metal layer and the insulating layer.

[0222] Accordingly, the embodiment can solve the reliability problem of the circuit pattern layer including the first metal layer being peeled off from the insulating layer by improving the adhesion between the insulating layer and the first metal layer.

[0223] Furthermore, the embodiment can further improve the insulating properties of the circuit board by using an oxide layer disposed between the first metal layer and the insulating layer.

[0224] Meanwhile, in the embodiment, the second metal layer of the circuit pattern layer is formed using an alloy including nickel (Ni)-chromium (Cr)-iron (Fe) and at least one metal selected from the group consisting of silver (Ag), silicon (Si) and alloys thereof. Accordingly, the second metal layer in the embodiment can have a certain level or higher of wear resistance, corrosion resistance, oxidation resistance and hardness. Through this, in the embodiment, the surface treatment layer to be formed on the contact portion of the circuit pattern layer can be omitted or removed, thereby simplifying the manufacturing process of the circuit board and reducing the manufacturing cost.

[0225] Meanwhile, the first metal layer of the embodiment includes a recess formed in a region vertically overlapping the through hole of the insulating layer. Furthermore, the recess can address electrical reliability issues that arise due to the remaining oxide layer in the bonding portion of the circuit pattern layer. Accordingly, the embodiment can improve the electrical reliability of the circuit board and chip package, and further enhance product reliability.

[0226] In addition, the recess of the first metal layer may have a structure that penetrates the first metal layer. Accordingly, the lower surface of the second metal layer that vertically overlaps the recess of the first metal layer may function as a bonding portion of the circuit pattern layer. At this time, the second metal layer of the circuit pattern layer in the embodiment may have a wire bonding property of a certain level or higher. Accordingly, in the embodiment, not only the surface treatment layer that should be formed in the contact portion of the circuit pattern layer, but also the surface treatment layer that should be formed in the bonding portion of the circuit pattern layer can be omitted or removed. Through this, the embodiment can further simplify the manufacturing process of the circuit board accordingly, and can further reduce the manufacturing cost.

[0227] Furthermore, in the embodiment, the insulating layer can be formed using only the oxide layer formed on the lower surface of the first metal layer. That is, in the embodiment, the insulating layer of the organic material is removed while allowing the metal oxide layer to function as the insulating layer.

[0228] That is, the insulating layer of the circuit board of the embodiment may be composed solely of an oxide layer formed on the lower surface of the first metal layer. Accordingly, the embodiment may further reduce the thickness of the circuit board by performing the function of the insulating layer using the oxide layer.

[0229] Furthermore, in the embodiment, by removing the insulating layer of the organic material, the thickness of the second metal layer of the circuit pattern layer can be increased by the thickness of the insulating layer of the organic material. At this time, the second metal layer is a rolled alloy. At this time, when the rolled alloy is manufactured to a thickness of 100㎛ or less, an additional rolling process is required, which increases the manufacturing cost. Accordingly, the embodiment can eliminate the additional rolling process for reducing the thickness of the rolled alloy under the condition that the product thickness is not increased. Through this, the embodiment can simplify the manufacturing process of the circuit board, thereby reducing the manufacturing cost. Furthermore, the embodiment can improve the overall bending characteristics of the circuit board by increasing the thickness of the second metal layer.

[0230] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0231] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First metal layer; and A second metal layer disposed on the first metal layer, The above first metal layer It includes an oxide layer formed by oxidizing a certain depth area from the lower surface of the first metal layer, The first metal layer and the second metal layer include a plurality of electrode patterns spaced apart from each other on the oxide layer, A circuit board, wherein the oxide layer insulates between the plurality of electrode patterns.

2. In paragraph 1, Further comprising an organic layer disposed on the lower surface of the above oxide layer, A circuit board, wherein the organic layer functions as an insulating layer that insulates between the plurality of electrode patterns together with the oxide layer.

3. In paragraph 1 or 2, The second metal layer is an alloy layer containing nickel (Ni) and iron (Fe), A circuit board, wherein the first metal layer is a metal layer plated or deposited on the lower surface of the second metal layer.

4. In paragraph 3, The second metal layer is, A first metal having a content in the range of 60 wt% to 80 wt%, A second metal having a content in the range of 10 wt% to 22 wt%, A third metal having a content in the range of 3 wt% to 20 wt%, Containing a fourth metal having a content in the range of 3 wt% to 10 wt%, The first metal comprises one of nickel (Ni) and iron (Fe), The second metal includes chromium (Cr), The third metal comprises one metal other than the first metal among nickel (Ni) and iron (Fe), A circuit board, wherein the fourth metal comprises any one of silver (Ag), silicon (Si), and a silver (Ag)-silicon (Si) alloy.

5. In paragraph 4, A circuit board, wherein the first metal layer comprises copper (Cu).

6. In paragraph 1, The total thickness of the first metal layer including the oxide layer is in the range of 7 µm to 15 µm, The thickness of the oxide layer in the first metal layer has a range of 3 µm to 5 µm, A circuit board, wherein the thickness of the second metal layer is in the range of 100 ㎛ to 200 ㎛.

7. In paragraph 2, The total thickness of the first metal layer including the oxide layer has a range of 2 µm to 10 µm, The thickness of the oxide layer in the first metal layer has a range of 0.2 μm to 5 μm, A circuit board, wherein the thickness of the second metal layer is in the range of 20 ㎛ to 50 ㎛.

8. In paragraph 1 or 2, wherein the oxide layer comprises at least one opening, The above first metal layer is, a first region vertically overlapping the above opening, and Including a second area excluding the first area, A recess is formed in the first region of the first metal layer to be connected to the opening, A circuit board, wherein the thickness of the first region of the first metal layer is smaller than the thickness of the second region of the first metal layer.

9. In paragraph 8, The second metal layer includes a third region vertically overlapping the opening and the recess, and a fourth region excluding the third region, The above recess penetrates the upper and lower surfaces of the first metal layer, A circuit board, wherein the lower surface of the third region of the second metal layer is exposed without contacting the first metal layer and the oxide layer.

10. In paragraph 2, A first adhesive layer disposed between the oxide layer and the organic layer, wherein the organic layer comprises at least one through hole, The first adhesive layer includes an open area vertically overlapping the through hole, Circuit board.

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