Smart IC substrate, smart IC module, and IC card comprising same

Abstract

A smart IC substrate according to an embodiment of the present invention comprises: a substrate including a first surface and a second surface opposite to the first surface; a bonding layer disposed on the first surface; a buffer layer disposed on the bonding layer; a metal layer disposed on the buffer layer; and a plating layer disposed on the other surface of the metal layer, wherein the metal layer includes an alloy including nickel (Ni), iron (Fe), and chromium (Cr), the buffer layer includes a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the second buffer layer and the metal layer, the second buffer layer includes a 2-1 buffer layer and a 2-2 buffer layer, wherein the 2-1 buffer layer is disposed between the first buffer layer and the 2-2 buffer layer, and the surface roughness of the 2-2 buffer layer is greater than the surface roughness of the 2-1 buffer layer.

Description

Smart IC substrate, smart IC module and IC card including the same

[0001] The embodiments relate to a smart IC substrate, a smart IC module, and an IC card including the same.

[0002] An IC card is a plastic card with an integrated circuit chip capable of storing and processing information. An IC card contains the necessary information, which is then transmitted to a reader in the form of an electrical signal.

[0003] The above IC card is manufactured by inserting a smart IC module into the main body of the card.

[0004] The above smart IC module is classified into a single type or a dual type depending on the arrangement of the metal layers. The single type has the metal layer and plating layer arranged on only one side of the substrate. In addition, the dual type has the metal layer and plating layer arranged on both sides of the substrate.

[0005] Additionally, the smart IC module is categorized into contact, contactless, hybrid, and combi cards depending on how the card is used. The contact card transmits and receives information through physical contact. Furthermore, the contactless card transmits and receives information without physical contact. Furthermore, the hybrid card and combi card include both the contact and contactless functions.

[0006] Accordingly, the smart IC module includes a contact surface and a bonding surface. The contact surface is in contact with an external device, and a chip is placed on the bonding surface. The bonding surface is inserted into the interior of the card body.

[0007] The chip positioned on the bonding surface and the conductive pattern positioned on the contact surface are electrically connected by wire bonding. Accordingly, the smart IC module includes a plurality of holes. The chip and the conductive pattern are wire bonded through the holes.

[0008] A metal layer is disposed on the contact surface. If the metal layer is exposed to the outside, it may corrode. Furthermore, the metal layer may be damaged by external impact. Accordingly, a plating layer may be disposed on the metal layer on the contact surface.

[0009] The above plating layer can increase the manufacturing process of smart IC modules. Furthermore, the plating layer requires expensive materials such as gold (Au). Consequently, process costs may increase.

[0010] Therefore, a new structure of a smart IC substrate, a smart IC module, and an IC card including the same that can solve the above problems is required.

[0011] As a prior art related to the above smart IC substrate, it is disclosed in Korean Patent Publication No. KR10-2022-0110247.

[0012] The present invention provides a smart IC substrate having improved electrical characteristics and reliability.

[0013] A smart IC substrate according to an embodiment comprises a substrate including a first surface and a second surface opposite to the first surface; a bonding layer disposed on the first surface; a buffer layer disposed on the bonding layer; a metal layer disposed on the buffer layer; and a plating layer disposed on the other surface of the metal layer, wherein the metal layer includes an alloy including nickel (Ni), iron (Fe), and chromium (Cr), the buffer layer includes the first buffer layer and the second buffer layer, the first buffer layer is disposed between the second buffer layer and the metal layer, the second buffer layer includes a 2-1 buffer layer and a 2-2 buffer layer, the 2-1 buffer layer is disposed between the first buffer layer and the 2-2 buffer layer, and a surface roughness of the 2-2 buffer layer is greater than a surface roughness of the 2-1 buffer layer.

[0014] A smart IC substrate according to an embodiment includes a metal layer forming a circuit pattern. The metal layer includes an alloy. Specifically, the metal layer includes an alloy containing iron, nickel, and chromium in predetermined proportions. Accordingly, the metal layer has enhanced corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0015] Accordingly, even if the metal layer is exposed to the outside, corrosion of the metal layer can be prevented. Furthermore, even if the metal layer is exposed to the outside, damage to the metal layer due to external impact can be prevented.

[0016] Accordingly, a separate plating layer disposed on the second surface (contact surface) of the metal layer can be omitted. Accordingly, the thickness of the smart IC substrate is reduced. In addition, the process efficiency of the smart IC substrate is improved.

[0017] Additionally, the smart IC substrate according to the first embodiment includes a buffer layer. The buffer layer is disposed between the metal layer and the bonding layer. The buffer layer includes a first buffer layer and a second buffer layer. The buffer layer has a surface roughness within a set range by the second buffer layer.

[0018] The metal layer comprises the alloy, and the alloy is formed by a rolling process. Accordingly, the surface roughness of the metal layer can be reduced. Accordingly, the buffer layer having a surface roughness of a predetermined size is disposed between the metal layer and the bonding layer. This enhances the adhesive strength between the metal layer and the bonding layer. Consequently, the reliability of the smart IC substrate is enhanced.

[0019] In addition, the smart IC substrate according to the first embodiment includes a metal layer. The metal layer defines a first region and a second region. The first region does not overlap the hole, and the second region overlaps the hole. The buffer layer is not disposed on the second region. The second region is not a region where the metal layer and the buffer layer are adhered. Therefore, even if the buffer layer is not disposed on the second region, the adhesion between the metal layer and the buffer layer is maintained.

[0020] Additionally, the plating layer can be in direct contact with the metal layer. Accordingly, signals transmitted from the chip can be easily transmitted to the metal layer. Accordingly, the electrical characteristics of the smart IC substrate can be improved.

[0021] FIG. 1 is a top view of a first surface of a smart IC substrate according to a first embodiment.

[0022] FIG. 2 is a top view of a second surface of a smart IC substrate according to the first embodiment.

[0023] Figure 3 is a cross-sectional view taken along area AA' of Figure 2.

[0024] Figure 4 is an enlarged view of area A of Figure 3.

[0025] Figure 5 is an enlarged view of area B of Figure 3.

[0026] Figure 6 is another cross-sectional view taken along area AA' of Figure 2.

[0027] Figure 7 is an enlarged view of area C of Figure 6.

[0028] Figure 8 is another enlarged view of area C of Figure 6.

[0029] Figure 9 is another cross-sectional view taken along area AA' of Figure 2.

[0030] Figure 10 is an enlarged view of area D of Figure 9.

[0031] Figure 11 is another cross-sectional view taken along area AA' of Figure 2.

[0032] Figure 12 is an enlarged view of area E of Figure 11.

[0033] Figure 13 is another cross-sectional view taken along area AA' of Figure 2.

[0034] Figure 14 is an enlarged view of area F of Figure 13.

[0035] Figure 15 is another cross-sectional view taken along area AA' of Figure 2.

[0036] Figure 16 is an enlarged view of area G of Figure 15.

[0037] Fig. 17 is a top view of a second side of a smart IC module according to an embodiment.

[0038] Fig. 18 is a cross-sectional view taken along the BB' area of ​​Fig. 17.

[0039] Fig. 19 is an exploded perspective view of a smart IC card according to an embodiment.

[0040] Fig. 20 is a drawing for explaining the combination of a smart IC module according to an embodiment.

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0042] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0043] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0044] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0045] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0046] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0047] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0048]

[0049] Hereinafter, a smart IC substrate, a smart IC module, and a smart IC card including the same according to an embodiment will be described with reference to the drawings.

[0050]

[0051] A smart IC substrate (1000) according to the first embodiment will be described with reference to FIGS. 1 to 5.

[0052] Referring to FIGS. 1 to 5, a smart IC substrate according to the first embodiment includes a substrate (100), a bonding layer (200), a metal layer (300), a buffer layer (400), and a plating layer (500).

[0053] The above-described substrate (100) includes a first side (1S) and a second side (2S). The first side (1S) and the second side (2S) are opposite sides.

[0054] The first surface (1S) is defined as a contact surface. Specifically, the first surface (1S) is a surface that recognizes information of the smart IC module through direct or indirect contact. In addition, the second surface (2S) is defined as a bonding surface. Specifically, the second surface (2S) is a surface on which a chip is mounted. The second surface (2S) is a surface that is bonded to the main body of the IC card.

[0055] The above substrate (100) comprises a resin material. The substrate (100) may comprise a prepreg comprising glass fibers. Specifically, the substrate (100) may comprise a material in which glass fibers and a silicon-based filler (Si filler) are dispersed within an epoxy resin.

[0056] Alternatively, the substrate (100) may be rigid or flexible. For example, the substrate (100) may include glass or plastic. Specifically, the substrate (100) may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. Alternatively, the substrate (100) may include polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0057] Alternatively, the substrate (100) may include an optically isotropic film. For example, the substrate (100) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0058] Alternatively, the substrate (100) may be bent while having a partially curved surface. That is, the substrate (100) may be bent while having a partially flat surface and a partially curved surface. In detail, the end of the substrate (100) may be bent while having a curved surface. Alternatively, the substrate (100) may be bent while having a random curvature.

[0059] The substrate (100) may have a thickness within a set range. For example, the thickness of the substrate (100) may be 80 μm to 150 μm, 90 μm to 140 μm, or 100 μm to 120 μm. When the thickness of the substrate (100) is less than 80 μm, the support capacity of the substrate (100) decreases. In addition, when the thickness of the substrate (100) exceeds 150 μm, the thickness of the smart IC substrate (1000) may increase. As a result, the size of the smart IC card increases.

[0060] The above substrate (100) has insulating properties. As a result, the substrate (100) prevents short circuits between circuits. In addition, the substrate (100) serves to support the circuit during the process of forming the circuit.

[0061]

[0062] The above-mentioned substrate (100) includes a hole. In detail, the above-mentioned substrate (100) includes a plurality of holes (H).

[0063] At least one of the plurality of holes is a region for wire bonding. The plating layer (500) is arranged in a region corresponding to the hole. For example, all of the plurality of holes are regions for wire bonding. Alternatively, some of the plurality of holes are regions for wire bonding, and other some of the holes are regions for non-wire bonding. The chip (C) and the plating layer are wire bonded through the hole (H).

[0064] The above hole (H) has a width within a set range. The width of the hole (H) can be defined as the diameter of the hole or the minimum distance between the inner sides of the hole. For example, the width of the hole (H) can be 500 ㎛ to 1000 ㎛, 600 ㎛ to 900 ㎛, or 700 ㎛ to 800 ㎛. When the width of the hole (H) is less than 500 ㎛, wire bonding through the hole (H) becomes difficult. In addition, when the width of the hole (H) exceeds 1000 ㎛, the support capacity of the substrate (100) decreases.

[0065]

[0066] The above bonding layer (200) is disposed on the above substrate (100). In detail, the above bonding layer (200) is disposed on the first surface (1S).

[0067] The bonding layer (200) comprises a resin material. For example, the bonding layer (200) may comprise at least one of an epoxy resin, an acrylic resin, and a polyimide resin. In addition, the bonding layer (200) may comprise at least one additive selected from the group consisting of natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. This enhances the flexibility of the bonding layer (200).

[0068] The bonding layer (200) may have a thickness within a set range. For example, the thickness of the bonding layer (200) may be 15 μm to 35 μm, 20 μm to 30 μm, or 22 μm to 28 μm. When the thickness of the bonding layer (200) is less than 15 μm, the adhesive strength of the bonding layer (200) decreases. As a result, the metal layer on the bonding layer (200) may be delaminated. In addition, when the thickness of the bonding layer (200) exceeds 35 μm, the thickness of the smart IC substrate (1000) may increase. As a result, the size of the smart IC card increases.

[0069]

[0070] The smart IC substrate (1000) includes a plurality of conductive patterns (P). The conductive patterns (P) are arranged on the first surface (1S). The conductive patterns (P) are arranged on the bonding layer (200). The conductive patterns (P) are arranged on the contact surface. The conductive patterns (P) may be circuit patterns of the smart IC substrate (1000).

[0071] The above conductive patterns (P) are arranged spaced apart from each other. The holes (H) are arranged on an area corresponding to each conductive pattern (P).

[0072] The above conductive pattern (P) is formed by the metal layer (300).

[0073] The metal layer (300) is disposed on the substrate (100). The metal layer (300) is disposed on the bonding layer (200). The metal layer (300) includes a metal material. Specifically, the metal layer (300) may include an alloy. More specifically, the metal layer (300) may include a binary alloy or a ternary alloy.

[0074] The metal layer (300) may have a thickness within a set range. For example, the thickness of the metal layer (300) may be 30 μm to 75 μm, 40 μm to 65 μm, or 50 μm to 60 μm. When the thickness of the metal layer (300) is less than 30 μm, the resistance of the metal layer (300) increases. In addition, when the thickness of the metal layer (300) exceeds 75 μm, the thickness of the smart IC substrate (1000) may increase. As a result, the size of the smart IC card increases. In addition, process efficiency may decrease.

[0075]

[0076] The buffer layer (400) is disposed on the substrate (100). The buffer layer (400) is disposed on the bonding layer (200). The buffer layer (400) is disposed below the metal layer (300). The buffer layer (400) is disposed between the bonding layer (200) and the metal layer (300).

[0077] The above buffer layer (400) may include a first buffer layer (410) and a second buffer layer (420). The second buffer layer (420) is disposed on the bonding layer (200), and the first buffer layer (410) is disposed on the second buffer layer (420). That is, the first buffer layer (410) is disposed between the second buffer layer (420) and the metal layer (300).

[0078] The above buffer layer (400) can improve the adhesive strength between the bonding layer (200) and the metal layer (300).

[0079]

[0080] As previously explained, the metal layer (300) may include an alloy.

[0081] The above metal layer (300) may include an alloy containing nickel (Ni), iron (Fe), and chromium (Cr).

[0082] For example, the metal layer (300) may include a Monel series alloy or an Inconel series alloy. Specifically, the metal layer (300) may include a nickel (Ni)-chromium (Cr)-iron (Fe) first alloy containing nickel as a main component and chromium and iron. In the alloy, the main component is defined as a metal having the largest weight percent among the plurality of metals constituting the alloy.

[0083] For example, the first alloy may include nickel in an amount of 60 wt% to 80 wt%, 65 wt% to 78 wt%, or 70 wt% to 75 wt%. Since the first alloy includes nickel in the above weight percent range, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (300) may be improved.

[0084] Additionally, the first alloy may include 10 wt% to 22 wt%, 11 wt% to 21 wt%, or 12 wt% to 18 wt% of chromium. Since the first alloy includes chromium in the above wt% range, the nickel dissolution amount of the metal layer may be reduced.

[0085] Additionally, the first alloy may include 3 wt% to 20 wt%, 5 wt% to 15 wt%, or 7 wt% to 11 wt% of iron. Since the first alloy includes iron in the above wt% range, the rollability (or ductility) of the metal layer may be increased. Accordingly, the thickness of the metal layer may be reduced. Additionally, the surface roughness of the metal layer may be made uniform.

[0086]

[0087] Alternatively, the metal layer (300) may include a sus series alloy. Specifically, the metal layer (300) may include an iron (Fe)-chromium (Cr)-nickel (Ni) secondary alloy containing iron as a main component and chromium and nickel.

[0088] For example, the second alloy may include iron in an amount of 60 wt% to 80 wt%, 61 wt% to 78 wt%, or 63 wt% to 75 wt%. Since the second alloy includes iron in the above weight percent range, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (300) may be improved. In addition, the rollability (or ductility) of the metal layer may be increased.

[0089] Additionally, the first alloy may include 10 wt% to 22 wt%, 13 wt% to 21 wt%, or 15 wt% to 10 wt% of chromium. Since the first alloy includes chromium in the above wt% range, the nickel dissolution amount of the metal layer may be reduced.

[0090] Additionally, the first alloy may include nickel in an amount of 3 wt% to 20 wt%, 5 wt% to 18 wt%, or 7 wt% to 15 wt%. Since the first alloy includes nickel in the above wt% range, the surface roughness change rate of the metal layer may be reduced. Additionally, the etching rate of the metal layer may be improved.

[0091] The above metal layer (300) may include the first alloy or the second alloy.

[0092] Accordingly, the plating layer disposed on the metal layer (300) can be omitted. In detail, the metal layer (300) includes a first surface (301) facing the buffer layer (400) and a second surface (302) opposite to the first surface (301).

[0093] Conventionally, a separate plating layer was placed on the second surface (302). The plating layer served to prevent corrosion of the metal layer (300). In addition, it served to improve the aesthetics of the contact surface exposed to the user.

[0094] The plating layer includes a plurality of metal layers. For example, the plating layer is formed by placing a gold (Au) layer on a nickel layer. Alternatively, the plating layer is formed by placing a palladium (Pd) layer on a nickel layer. Alternatively, the plating layer is formed by placing a silver (Ag) layer on a nickel layer.

[0095] There was a problem that the manufacturing process time of the smart IC substrate increased and the process cost increased due to the process of forming the above plating layer.

[0096] The smart IC substrate according to the first embodiment includes a metal layer comprising the first alloy or the second alloy. Accordingly, the plating layer disposed on the second surface (302) can be omitted.

[0097] In detail, since the metal layer includes the first alloy or the second alloy, the corrosion resistance of the metal layer is improved. Accordingly, even if the metal layer is directly exposed to the outside, corrosion of the metal layer can be prevented.

[0098] Additionally, since the metal layer includes the first alloy or the second alloy, the nickel dissolution amount of the metal layer is reduced. Accordingly, even if the metal layer is directly exposed to the outside, the user can be prevented from coming into contact with nickel.

[0099] Therefore, the smart IC substrate according to the first embodiment has improved process efficiency. Furthermore, since a separate plating layer is eliminated, the thickness of the smart IC substrate is reduced.

[0100] Meanwhile, a metal layer (300) including one of the first alloy and the second alloy may have the following characteristics.

[0101]

[0102] *82 In detail, the metal layer (300) including any one of the first alloy and the second alloy may have a resistance of 0.07Ω to 0.35Ω. In addition, the metal layer (300) including any one of the first alloy and the second alloy may have an etching rate (㎛ / min) of 30㎛ / min to 70㎛ / min. In addition, the metal layer (300) including any one of the first alloy and the second alloy may have a surface roughness change rate of 0.2% to 6.0%. In addition, the metal layer (300) including any one of the first alloy and the second alloy may have a wire bondability of 4gf or more. In addition, the metal layer (300) including any one of the first alloy and the second alloy may have a resistance of 0 to 0.28㎍ / cm 2 / week nickel dissolution amount. In addition, the metal layer (300) including any one of the first alloy and the second alloy may have a plating adhesion of 5B or more.

[0103]

[0104] Meanwhile, the first alloy or the second alloy is formed by a rolling process. Accordingly, the surface roughness of the metal layer (300) is reduced. Accordingly, the adhesive strength between the metal layer (300) and the bonding layer is reduced.

[0105] To solve this, the smart IC substrate according to the first embodiment includes a buffer layer (400). The buffer layer (400) is disposed between the first surface (301) and the bonding layer (200).

[0106] The buffer layer (400) may include a first buffer layer (410) and a second buffer layer (420). The second buffer layer (420) is disposed on the bonding layer (200). The first buffer layer (410) is disposed on the second buffer layer (420). That is, the first buffer layer (410) is disposed between the second buffer layer (420) and the metal layer (300).

[0107] The first buffer layer (410) may include a metal. For example, the first buffer layer (410) may include nickel. The adhesion between the metal layer (300) and the second buffer layer (420) is improved by the first buffer layer (410).

[0108] The second buffer layer (420) may include a metal. For example, the second buffer layer (420) may include copper (Cu). The adhesive strength between the metal layer (300) and the bonding layer (200) is improved by the second buffer layer (420).

[0109] Referring to FIG. 4, the second buffer layer (420) may include a 2-1 buffer layer (421) and a 2-2 buffer layer (422). The 2-1 buffer layer (421) is disposed between the first buffer layer (410) and the 2-2 buffer layer (422).

[0110] The above 2-1 buffer layer (421) and the above 2-2 buffer layer (422) are formed integrally.

[0111] The above 2-1 buffer layer (421) may include a metal. That is, the 2-1 buffer layer (421) is a metal layer. For example, the 2-1 buffer layer (421) may include copper. The 2-2 buffer layer (422) may include a metal oxide. That is, the 2-2 buffer layer (422) is a metal oxide layer. For example, the 2-2 buffer layer (422) may include copper oxide.

[0112] The above 2-2 buffer layer (422) may be formed by oxidizing a portion of the 2-2 buffer layer (420). The surface roughness of the 2-2 buffer layer (422) increases by the oxidation process. That is, the surface roughness of the 2-2 buffer layer (422) facing the bonding layer (200) may be greater than the surface roughness of the 2-1 buffer layer (421).

[0113] In detail, the surface roughness of the 2-2 buffer layer (422) may be greater than the surface roughness of the metal layer (300). In addition, the surface roughness of the 2-2 buffer layer (422) may be greater than the surface roughness of the first buffer layer. In addition, the surface roughness of the 2-2 buffer layer (422) may be greater than the surface roughness of the plating layer. In detail, the surface roughness of the 2-2 buffer layer (422) may be greater than the surface roughness of the first plating layer (510). In addition, the surface roughness of the 2-2 buffer layer (422) may be greater than the surface roughness of the second plating layer (520). In addition, the surface roughness of the 2-2 buffer layer (422) may be greater than the surface roughness of the substrate (100).

[0114] The surface roughness between the 2-2 buffer layer (422) and one surface of the bonding layer (200) may be greater than the surface roughness between the 2-1 buffer layer (421) and the 2-2 buffer layer (422). In addition, the surface roughness between the 2-2 buffer layer (422) and one surface of the bonding layer (200) may be greater than the surface roughness between the first surface (1S) of the substrate and the other surface of the bonding layer (200). In addition, the surface roughness between the 2-2 buffer layer (422) and one surface of the bonding layer (200) may be greater than the surface roughness between the metal layer (300) and the first buffer layer (420).

[0115]

[0116] The thickness of the 2-2 buffer layer (422) may be smaller than the thickness of the 2-1 buffer layer (421). For example, the thickness of the 2-2 buffer layer (422) may be 20% or less, 10% or less, or 5% or less of the thickness of the 2nd buffer layer.

[0117] The adhesive strength of the metal layer (300) and the bonding layer (200) can be improved by the buffer layer (400). Specifically, the buffer layer (400) includes the 2-2 buffer layer (422). The 2-2 buffer layer (422) faces the bonding layer (200). Accordingly, the bonding area of ​​the buffer layer (400) and the bonding layer (200) is increased by the 2-2 buffer layer (422). Accordingly, the adhesive strength of the metal layer (300) and the bonding layer (200) is improved. Accordingly, the metal layer (300) can be easily formed. In addition, the de-filming of the metal layer (300) can be prevented. Accordingly, the process efficiency and reliability of the smart IC substrate can be improved.

[0118]

[0119] The plating layer (500) is disposed on the lower portion of the metal layer (300). In detail, the plating layer (500) is disposed on the first surface (301) of the metal layer. The plating layer (500) is disposed on an area overlapping the hole (H).

[0120] The above plating layer (500) is connected to a wire connected to the chip. That is, the chip and the plating layer are wire bonded. As a result, the chip and the metal layer (300) are electrically connected to the chip.

[0121] The above plating layer (500) may include a first plating layer (510) and a second plating layer (520). The first plating layer (510) is disposed below the first surface (301), and the second plating layer (520) is disposed below the first plating layer (510). That is, the first plating layer (510) is disposed between the metal layer (300) and the second plating layer (520).

[0122] The first plating layer (510) may include a metal. The first plating layer (510) may include the same material as the first buffer layer (410). For example, the first plating layer (510) may include nickel. The adhesion between the metal layer (300) and the second plating layer (520) may be improved by the first plating layer (510). That is, the first plating layer (510) may be a buffer layer.

[0123] The second plating layer (520) may include a metal. The second plating layer (520) may include at least one metal selected from the group consisting of gold, silver, and palladium. The plating layer (500) and the wire may be bonded by the second plating layer (520).

[0124] The above buffer layer (400) can be partially removed.

[0125] In detail, the metal layer (300) may be divided into a plurality of regions. In detail, the metal layer (300) may include a first region (1A) and a second region (2A). The first region (1A) is a region that does not overlap with the hole (H). The second region (2A) is a region that overlaps with the hole (H).

[0126] The buffer layer (400) is disposed on the first region (1A). In addition, the buffer layer (400) is not disposed on the second region (2A). That is, the buffer layer (400) is not disposed inside the hole (H). Accordingly, the plating layer (500) can be in direct contact with the metal layer (300).

[0127] The buffer layer (400) above is a layer for adhesion between the metal layer (300) and the bonding layer (200). The metal layer (300) is not adhered to the bonding layer (200) in the area overlapping the hole (H). Therefore, even if the buffer layer (400) of the second area (2A) is removed, the adhesion between the metal layer (300) and the bonding layer (200) can be maintained.

[0128] In addition, since the buffer layer (400) of the second region (2A) is removed, the distance between the plating layer (500) and the metal layer (300) can be shortened. Accordingly, a signal transmitted from the chip can be easily transmitted to the metal layer (300).

[0129]

[0130] Meanwhile, the first buffer layer (410), the second buffer layer (420), the first plating layer (510), and the second plating layer (520) may have a set thickness.

[0131] The thickness (T1) of the first buffer layer may be smaller than the thickness (T2) of the second buffer layer. The thickness (T1) of the first buffer layer may be smaller than the thickness (T3) of the first plating layer. The thickness (T1) of the first buffer layer may be larger than the thickness (T4) of the second plating layer.

[0132] The thickness (T2) of the second buffer layer may be the same as the thickness (T3) of the first plating layer. Alternatively, the thickness (T2) of the second buffer layer may be greater than the thickness (T3) of the first plating layer. Alternatively, the thickness (T2) of the second buffer layer may be less than the thickness (T3) of the first plating layer.

[0133] The thickness (T1) of the first buffer layer may be 1 μm or less. For example, the thickness (T1) of the first buffer layer may be 0.6 μm to 1 μm, 0.7 μm to 1 μm, or 0.8 μm to 1 μm.

[0134] If the thickness (T1) of the first buffer layer is less than 0.6 μm, the adhesive strength between the first buffer layer (410) and the second buffer layer (420) may decrease. As a result, the adhesive strength between the metal layer (300) and the buffer layer (400) may decrease. In addition, if the thickness (T1) of the first buffer layer exceeds 1 μm, the process efficiency of forming the buffer layer may decrease. In addition, the process time for removing the buffer layer of the second region (2A) may increase.

[0135] The thickness (T2) of the second buffer layer may be 3 µm to 8 µm, 3.5 µm to 7 µm, or 4 µm to 6 µm.

[0136] If the thickness (T2) of the second buffer layer is less than 3 μm, the process of forming the second-second buffer layer (422) may be difficult. As a result, a surface roughness having a desired size may not be formed in the second buffer layer (420). As a result, the adhesive strength between the metal layer (300) and the bonding layer (200) may be reduced. In addition, if the thickness (T2) of the second buffer layer exceeds 8 μm, the process efficiency of forming the buffer layer may be reduced. In addition, the process time for removing the buffer layer of the second region (2A) may increase.

[0137] The thickness (T3) of the first plating layer may be 2 µm to 9 µm, 3 µm to 8 µm, or 4 µm to 7 µm.

[0138]

[0139] *118 If the thickness (T3) of the first plating layer is less than 2 ㎛, the adhesive strength between the first plating layer (510) and the second plating layer (520) may decrease. As a result, the adhesive strength between the metal layer (300) and the plating layer (500) may decrease. In addition, when wire bonding the chip and the plating layer, the plating layer may be damaged by heat and pressure.

[0140] In addition, if the thickness (T3) of the first plating layer exceeds 9 μm, the process efficiency of forming the plating layer may decrease.

[0141] The thickness (T4) of the second plating layer may be 0.5 μm or less. Specifically, the thickness (T4) of the second plating layer may be 0.1 μm to 0.5 μm, 0.15 μm to 0.4 μm, or 0.2 μm to 0.35 μm. If the thickness (T4) of the second plating layer is less than 0.1 μm, the bonding force between the wire and the second plating layer (520) may be reduced. If the thickness (T4) of the second plating layer exceeds 0.5 μm, the process cost may increase and the process efficiency may be reduced.

[0142]

[0143] A smart IC substrate according to the first embodiment includes a metal layer forming a circuit pattern. The metal layer includes an alloy. Specifically, the metal layer includes an alloy containing iron, nickel, and chromium in set proportions. Accordingly, the metal layer has enhanced corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0144] Accordingly, even if the metal layer is exposed to the outside, corrosion of the metal layer can be prevented. Furthermore, even if the metal layer is exposed to the outside, damage to the metal layer due to external impact can be prevented.

[0145] Accordingly, a separate plating layer disposed on the second surface (contact surface) of the metal layer can be omitted. Accordingly, the thickness of the smart IC substrate is reduced. In addition, the process efficiency of the smart IC substrate is improved.

[0146] Additionally, the smart IC substrate according to the first embodiment includes a buffer layer. The buffer layer is disposed between the metal layer and the bonding layer. The buffer layer includes a first buffer layer and a second buffer layer. The buffer layer has a surface roughness within a set range by the second buffer layer.

[0147] The metal layer comprises the alloy, and the alloy is formed by a rolling process. Accordingly, the surface roughness of the metal layer can be reduced. Accordingly, the buffer layer having a surface roughness of a predetermined size is disposed between the metal layer and the bonding layer. This enhances the adhesive strength between the metal layer and the bonding layer. Consequently, the reliability of the smart IC substrate is enhanced.

[0148] In addition, the smart IC substrate according to the first embodiment includes a metal layer. The metal layer defines a first region and a second region. The first region does not overlap the hole, and the second region overlaps the hole. The buffer layer is not disposed on the second region. The second region is not a region where the metal layer and the buffer layer are adhered. Therefore, even if the buffer layer is not disposed on the second region, the adhesion between the metal layer and the buffer layer is maintained.

[0149] Additionally, the plating layer can be in direct contact with the metal layer. Accordingly, signals transmitted from the chip can be easily transmitted to the metal layer. Accordingly, the electrical characteristics of the smart IC substrate can be improved.

[0150]

[0151] Hereinafter, a smart IC substrate according to a second embodiment will be described with reference to FIGS. 6 to 8. Descriptions identical or similar to those of the first embodiment will be omitted. Components identical to those of the first embodiment are given the same drawing reference numerals.

[0152] Referring to FIGS. 6 and 7, the buffer layer (400) can be partially removed.

[0153] In detail, the metal layer (300) may be divided into a plurality of regions. In detail, the metal layer (300) may include a first region (1A) and a second region (2A). The first region (1A) is a region that does not overlap with the hole (H). The second region (2A) is a region that overlaps with the hole (H).

[0154] The buffer layer (400) is disposed on the first region (1A). Specifically, the first buffer layer (410) and the second buffer layer (420) are disposed on the first region (1A). In addition, the buffer layer (400) is partially disposed on the second region (2A). Specifically, the first buffer layer (410) is disposed on the second region (2A). In addition, the second buffer layer (420) is partially disposed on the second region (2A). In detail, the 2-2 buffer layer (422) on the second region (2A) is removed. As a result, the first buffer layer (410) and the 2-1 buffer layer (421) are disposed on the second region (2A). By this, the plating layer (500) can come into contact with the 2-1 buffer layer (421).

[0155] The above 2-2 buffer layer (422) is an oxide metal layer. Accordingly, the 2-2 buffer layer (422) may have little or no electrical conductivity. Accordingly, the plating layer (500) and the metal layer (300) may be insulated by the 2-2 buffer layer (422). Accordingly, the 2-2 buffer layer (422) may be removed, and the metal layer (300) and the plating layer (500) may be electrically connected.

[0156] The above buffer layer (400) is a layer for adhesion between the metal layer (300) and the bonding layer (200). The metal layer (300) is not adhered to the bonding layer (200) in the area overlapping the hole (H). Therefore, even if the 2-2 buffer layer (422) of the second area (2A) is removed, the adhesion between the metal layer (300) and the bonding layer (200) can be maintained.

[0157]

[0158] The plating layer (500) is disposed on an area overlapping the hole (H). The plating layer (500) is disposed on the metal layer (300). Specifically, the plating layer (500) is disposed on the buffer layer (400). Specifically, the plating layer (500) is disposed on the 2-1 buffer layer (421).

[0159] The above plating layer (500) is connected to a wire connected to the chip. That is, the chip and the plating layer are wire bonded. As a result, the chip and the metal layer (300) are electrically connected to the chip.

[0160] The first buffer layer (410) and the second-first buffer layer (421) remain between the plating layer (500) and the metal layer (300).

[0161] Accordingly, the strength of the wire-bonded region can be increased. The chip and the plating layer can be wire-bonded by heat and pressure. Accordingly, the plating layer can be damaged during the wire bonding process. The smart IC substrate according to the second embodiment can prevent this. That is, the first buffer layer (410) and the second-first buffer layer (421) remain between the plating layer (500) and the metal layer (300).

[0162] Accordingly, the strength of the wire-bonded region can be improved. Consequently, damage to the plating layer can be prevented during the wire bonding process. Consequently, the reliability of the smart IC substrate can be improved.

[0163]

[0164] Meanwhile, referring to FIG. 8, the thickness of the 2-1 buffer layer (421) may vary from region to region. Specifically, the thickness (T1-1) of the 2-1 buffer layer of the first region (1A) and the thickness (T1-2) of the 2-1 buffer layer of the second region (2A) may be different. Specifically, the thickness (T1-2) of the 2-1 buffer layer of the second region (2A) may be greater than the thickness (T1-1) of the 2-1 buffer layer of the first region (1A). Specifically, the thickness (T1-2) of the 2-1 buffer layer may be greater than the thickness (T1-1) of the 2-1 buffer layer of the first region (1A) by the thickness of the 2-2 buffer layer.

[0165] The above-mentioned 2-2 buffer layer (422) can be formed by selective oxidation. For example, after masking on the second region (2A), the second buffer layer (420) can be oxidized. Accordingly, the 2-2 buffer layer (422) is formed only on the first region (1A) and not on the second region (2A).

[0166] Accordingly, the thickness of the 2-1 buffer layer (421) varies from region to region. Specifically, the 2-2 buffer layer (422), which is an oxidation region, is not formed in the 2nd region (2A). Accordingly, the thickness of the 2-1 buffer layer (421) of the 2nd region (2A) may be greater than the thickness of the 2-1 buffer layer (421) of the 1st region (1A).

[0167] Accordingly, the thickness of the wire-bonded region increases. This can enhance the strength of the wire-bonded region. Consequently, damage to the plating layer can be prevented during the wire-bonding process. Consequently, the reliability of the smart IC substrate can be enhanced.

[0168]

[0169] Hereinafter, a smart IC substrate according to a third embodiment will be described with reference to FIGS. 9 and 10. Descriptions identical or similar to those of the first embodiment will be omitted. Components identical to those of the first embodiment are given the same reference numerals.

[0170] Referring to FIGS. 9 and 10, the buffer layer (400) includes the first buffer layer (410) and the second buffer layer (420). The first buffer layer (410) and the second buffer layer (420) may have a set thickness.

[0171] The thickness (T1) of the first buffer layer may be greater than the thickness (T2) of the second buffer layer. The thickness (T1) of the first buffer layer may be greater than the thickness (T4) of the second plating layer.

[0172] The thickness (T1) of the first buffer layer may be 6 μm or more. For example, the thickness (T1) of the first buffer layer may be 6 μm to 11 μm, 7 μm to 10 μm, or 8 μm to 9 μm.

[0173] If the thickness (T1) of the first buffer layer is less than 6 μm, the adhesive strength between the first buffer layer (410) and the second plating layer (520) may decrease. As a result, the adhesive strength between the metal layer (300) and the second plating layer (520) may decrease. In addition, when wire bonding the second plating layer (520) and the chip, a crack may be formed in the first buffer layer (410).

[0174] In addition, if the thickness (T1) of the first buffer layer exceeds 11 μm, the process efficiency of forming the buffer layer may decrease. In addition, the thickness of the smart IC substrate may increase.

[0175] The thickness (T2) of the second buffer layer may be 3 µm to 8 µm, 3.5 µm to 7 µm, or 4 µm to 6 µm.

[0176] If the thickness (T2) of the second buffer layer is less than 3 μm, the process of forming the second-second buffer layer (422) may be difficult. As a result, a surface roughness having a desired size may not be formed in the second buffer layer (420). As a result, the adhesive strength between the metal layer (300) and the bonding layer (200) may be reduced. In addition, if the thickness (T2) of the second buffer layer exceeds 8 μm, the process efficiency of forming the buffer layer may be reduced. In addition, the process time for removing the buffer layer of the second region (2A) may increase.

[0177] The thickness of the first buffer layer may be greater than the thickness of the second buffer layer within the above range.

[0178]

[0179] The above buffer layer (400) can be partially removed.

[0180] In detail, the metal layer (300) may be divided into a plurality of regions. In detail, the metal layer (300) may include a first region (1A) and a second region (2A). The first region (1A) is a region that does not overlap with the hole (H). The second region (2A) is a region that overlaps with the hole (H).

[0181] The buffer layer (400) is disposed on the first region (1A). Specifically, the first buffer layer (410) and the second buffer layer (420) are disposed on the first region (1A). In addition, the buffer layer (400) is partially disposed on the second region (2A). Specifically, the first buffer layer (410) is disposed on the second region (2A). In addition, the second buffer layer (420) is not disposed on the second region (2A). Specifically, the second buffer layer (420) on the second region (2A) is removed. As a result, only the first buffer layer (410) is disposed on the second region (2A). Accordingly, one surface of the first buffer layer (410) may be exposed in the hole (H). Therefore, the plating layer is in contact with the first buffer layer (410).

[0182] The above buffer layer (400) is a layer for adhesion between the metal layer (300) and the bonding layer (200). The metal layer (300) is not adhered to the bonding layer (200) in the area overlapping the hole (H). Therefore, even if the second buffer layer (420) of the second area (2A) is removed, the adhesion between the metal layer (300) and the bonding layer (200) can be maintained.

[0183]

[0184] The plating layer is disposed on an area overlapping the hole (H). The plating layer may include only the second plating layer (520). That is, the first plating layer (510) is omitted.

[0185] The second plating layer (520) is disposed on the metal layer (300). In detail, the second plating layer (520) is disposed on the first buffer layer (410).

[0186] The first buffer layer (410) may include a material identical or similar to that of the first plating layer (510). Accordingly, the second plating layer (520) can be easily bonded to the first buffer layer (410).

[0187] The second plating layer (520) is connected to a wire connected to the chip. That is, the chip and the second plating layer (520) are wire bonded. As a result, the chip and the metal layer (300) are electrically connected to the chip.

[0188] The first buffer layer (410) remains between the second plating layer (520) and the metal layer (300). The first buffer layer (410) includes a material identical or similar to that of the first plating layer (510). Accordingly, the second plating layer (520) is easily bonded to the first buffer layer (410). In addition, the first buffer layer (410) is formed to a thickness within a set range. For example, the thickness (T1) of the first buffer layer may be greater than the thickness (T2) of the second buffer layer. Accordingly, when bonding a wire to the second plating layer (520), it is possible to prevent the second plating layer or the first buffer layer from being damaged by heat and pressure.

[0189] Therefore, when wire bonding the chip and the plating layer, the process of forming the first plating layer can be omitted. Accordingly, the process efficiency of the smart IC substrate can be improved.

[0190]

[0191] Hereinafter, a smart IC substrate according to a fourth embodiment will be described with reference to FIGS. 11 and 12. Descriptions identical or similar to those of the first embodiment will be omitted. Components identical to those of the first embodiment are given the same reference numerals.

[0192] Referring to FIGS. 11 and 12, the buffer layer (400) can be partially removed.

[0193] In detail, the metal layer (300) may be divided into a plurality of regions. In detail, the metal layer (300) may include a first region (1A) and a second region (2A). The first region (1A) is a region that does not overlap with the hole (H). The second region (2A) is a region that overlaps with the hole (H).

[0194] The buffer layer (400) is disposed on the first region (1A). Specifically, the first buffer layer (410) and the second buffer layer (420) are disposed on the first region (1A). In addition, the buffer layer (400) is partially disposed on the second region (2A). Specifically, the first buffer layer (410) is disposed on the second region (2A). In addition, the second buffer layer (420) is not disposed on the second region (2A). Specifically, the second buffer layer (420) on the second region (2A) is removed. As a result, only the first buffer layer (410) is disposed on the second region (2A). Accordingly, one surface of the first buffer layer (410) may be exposed in the hole (H).

[0195] The above 2-2 buffer layer (422) is an oxide metal layer. Accordingly, the 2-2 buffer layer (422) may have little or no electrical conductivity. Accordingly, the plating layer (500) and the metal layer (300) may be insulated by the 2-2 buffer layer (422). Accordingly, the 2nd buffer layer (420) including the 2-2 buffer layer (422) is removed.

[0196] The above buffer layer (400) is a layer for adhesion between the metal layer (300) and the bonding layer (200). The metal layer (300) is not adhered to the bonding layer (200) in the area overlapping the hole (H). Therefore, even if the second buffer layer (420) of the second area (2A) is removed, the adhesion between the metal layer (300) and the bonding layer (200) can be maintained.

[0197] The plating layer (500) is disposed on an area overlapping the hole (H). The plating layer (500) is disposed on the metal layer (300). Specifically, the plating layer (500) is disposed on the buffer layer (400). Specifically, the plating layer (500) is disposed on the first buffer layer (410). Accordingly, the first plating layer (510) is in contact with the first buffer layer (410).

[0198] The above plating layer (500) is connected to a wire connected to the chip. That is, the chip and the plating layer are wire bonded. As a result, the chip and the metal layer (300) are electrically connected to the chip.

[0199] The first buffer layer (410) remains between the plating layer (500) and the metal layer (300). The first buffer layer (410) and the first plating layer (510) may contain the same material. For example, the first buffer layer (410) and the first plating layer (510) may contain nickel.

[0200] Accordingly, the thickness of the first plating layer (510) can be reduced. That is, since the first buffer layer (510) remains between the metal layer (300) and the first plating layer (510), the thickness of the first plating layer (510) can be reduced. Accordingly, the process time for forming the first plating layer (510) can be shortened.

[0201] In addition, since the first buffer layer (410) and the first plating layer (510) contain the same material, signals transmitted from the chip do not interfere at the interface between the first buffer layer (410) and the first plating layer (510). Accordingly, the electrical characteristics of the smart IC substrate can be improved.

[0202]

[0203] Hereinafter, a smart IC substrate according to a fifth embodiment will be described with reference to FIGS. 13 to 16. Descriptions identical or similar to those of the first embodiment will be omitted. Components identical to those of the first embodiment are assigned the same drawing reference numerals.

[0204] Referring to FIGS. 13 and 14, the metal layer (300) and the buffer layer (400) can be partially removed.

[0205] In detail, the metal layer (300) may be divided into a plurality of regions. In detail, the metal layer (300) may include a first region (1A) and a second region (2A). The first region (1A) is a region that does not overlap with the hole (H). The second region (2A) is a region that overlaps with the hole (H).

[0206] The buffer layer (400) is disposed on the first region (1A). In addition, the buffer layer (400) is not disposed on the second region (2A). The buffer layer on the second region (2A) is removed. Therefore, the buffer layer (400) is not disposed inside the hole (H).

[0207] The buffer layer (400) above is a layer for adhesion between the metal layer (300) and the bonding layer (200). The metal layer (300) is not adhered to the bonding layer (200) in the area overlapping the hole (H). Therefore, even if the buffer layer (400) of the second area (2A) is removed, the adhesion between the metal layer (300) and the bonding layer (200) can be maintained.

[0208] In addition, the metal layer (300) on the second region (2A) can be partially removed. Accordingly, the thickness (T5-1) of the metal layer on the first region (1A) and the thickness (T5-2) of the metal layer on the second region (2A) can be different. In detail, the thickness (T5-1) of the metal layer on the first region (1A) can be greater than the thickness (T5-2) of the metal layer on the second region (2A).

[0209] Since the metal layer on the second region (2A) is partially removed, the metal layer (300) may include a groove (R). The groove (R) is formed on the second region (2A). The groove (R) is formed in an area corresponding to the hole (H). The groove (R) is connected to the hole (H).

[0210]

[0211] The above plating layer (500) is disposed on an area overlapping the hole (H). The above plating layer (500) is disposed on the above metal layer (300).

[0212] The plating layer (500) is formed in a portion of the hole (H) and the interior of the groove (R). The plating layer (500) is arranged to fill the interior of the groove (R). Accordingly, a portion of the side surface of the plating layer (500) is in contact with the metal layer (300).

[0213] The above plating layer (500) is connected to a wire connected to the chip. That is, the chip and the plating layer are wire bonded. As a result, the chip and the metal layer (300) are electrically connected to the chip.

[0214] The side surface of the plating layer (500) is in contact with the metal layer (300). Accordingly, the contact area between the plating layer (500) and the metal layer (300) increases. Accordingly, the area through which signals transmitted from the chip move increases. Accordingly, the electrical characteristics of the smart IC substrate can be improved.

[0215] In addition, since the contact area between the plating layer (500) and the metal layer (300) increases, the bonding strength between the plating layer (500) and the metal layer (300) can be improved.

[0216] In addition, since the buffer layer (400) of the second region (2A) is removed, the distance between the plating layer (500) and the metal layer (300) can be shortened. Accordingly, a signal transmitted from the chip can be easily transmitted to the metal layer (300).

[0217]

[0218] Meanwhile, referring to FIGS. 15 and 16, the plating layer (500) can be placed only inside the groove portion (R). That is, the plating layer (500) can be embedded inside the groove portion (G).

[0219] Accordingly, the entire outer surface of the plating layer (500) comes into contact with the metal layer (300). Accordingly, the contact area between the plating layer (500) and the metal layer (300) increases. Accordingly, the electrical characteristics and bonding strength of the smart IC substrate can be improved.

[0220]

[0221] Below, a smart IC module is described with reference to FIGS. 17 and 18.

[0222] Referring to FIGS. 17 and 18, the smart IC module (2000) includes a smart IC substrate (1000) and a chip (C) according to the embodiments described above.

[0223] The above chip (C) is placed on the second surface (2S). In detail, the chip (C) is placed on the bonding surface.

[0224] The chip (C) is connected to the second plating layer (520). In detail, the chip (C) and the second plating layer (520) are bonded by a wire (W). Accordingly, the chip (C) and the conductive patterns (P) are electrically connected.

[0225] The above wire (W) comprises a metal. In detail, the wire (W) may comprise a material different from the second plating layer (520). For example, the wire (W) may comprise gold, copper, or aluminum.

[0226] A molding member (M) may be placed on the chip (C). The molding member (M) is placed so as to cover the chip (C) and the wire (W). Accordingly, damage to the wire bonding due to external impact can be prevented.

[0227]

[0228] Hereinafter, a smart IC card according to an embodiment will be described with reference to FIGS. 19 and 20.

[0229] Referring to FIGS. 19 and 20, the smart IC card (3000) may include a main body (3100), a first protective layer (3210), and a second protective layer (3220).

[0230] The above main body (3100) includes a receiving portion (3110). The smart IC module (2000) is placed inside the receiving portion (3110).

[0231] The above IC card can be operated in various modes. For example, the above IC card can be operated as a contact card.

[0232] Alternatively, an antenna pattern (not shown) may be arranged on the main body (3100). Specifically, the antenna pattern may be arranged in a coil shape at the edge of the main body (3100). Accordingly, the IC card may be operated as a contactless card, a combination card, or a hybrid card.

[0233] The smart IC module (2000) is inserted into the interior of the receiving portion (3110). The smart IC module (2000) and the main body (3100) are bonded by an adhesive layer (3120). As a result, the smart IC module (2000) is inserted into and fixed in the receiving portion (3110).

[0234] The first protective layer (3210) is disposed on the upper portion of the main body (3100). The first protective layer (3210) may include a transparent material. The first protective layer (3210) may include a transparent resin material. The first protective layer (3210) may be disposed as at least one layer. That is, the first protective layer (3210) may include a plurality of layers.

[0235] The second protective layer (3220) is disposed at the lower portion of the main body (3100). A magnetic stripe may be disposed on the second protective layer (3220). The second protective layer (3220) may include a transparent material. The second protective layer (3220) may include a transparent resin material. The second protective layer (3220) may be disposed as at least one layer. That is, the second protective layer (3220) may include a plurality of layers.

[0236] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0237] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A substrate comprising a first side and a second side opposite to the first side; A bonding layer disposed on the first surface; A buffer layer disposed on the above bonding layer; A metal layer disposed on the buffer layer; and Including a plating layer disposed on the other surface of the above metal layer, The above metal layer comprises an alloy containing nickel (Ni), iron (Fe) and chromium (Cr), The buffer layer includes the first buffer layer and the second buffer layer, The first buffer layer is disposed between the second buffer layer and the metal layer, The second buffer layer includes a 2-1 buffer layer and a 2-2 buffer layer, The above 2-1 buffer layer is disposed between the first buffer layer and the 2-2 buffer layer, A smart IC substrate wherein the surface roughness of the above 2-2 buffer layer is greater than the surface roughness of the above 2-1 buffer layer.

2. In paragraph 1, The first buffer layer and the second-first buffer layer comprise metal, The above 2-2 buffer layer is a smart IC substrate including an oxide metal.

3. In paragraph 1, The plating layer includes a first plating layer disposed under the metal layer and a second plating layer under the first plating layer, A smart IC substrate comprising the first buffer layer and the first plating layer made of the same metal.

4. In paragraph 3, A smart IC substrate wherein the thickness of the first plating layer is greater than the thickness of the first buffer layer.

5. In paragraph 1, A plurality of holes are formed penetrating the above substrate and the bonding layer, The metal layer includes a first region that does not overlap the hole and a second region that overlaps the hole, The buffer layer is arranged on the first region, The buffer layer is not placed on the second area, A smart IC substrate in which the plating layer is in contact with the metal layer.

6. In paragraph 1, A plurality of holes are formed penetrating the above substrate and the bonding layer, The metal layer includes a first region that does not overlap the hole and a second region that overlaps the hole, A first buffer layer and a second buffer layer are arranged on the first region, The first buffer layer and the second-first buffer layer are arranged on the second region, A smart IC substrate in which the plating layer is in contact with the 2-1 buffer layer.

7. In paragraph 6, A smart IC substrate wherein the thickness of the 2-1 buffer layer of the second region is greater than the thickness of the 2-1 buffer layer of the first region.

8. In paragraph 1, The plating layer includes a second plating layer disposed under the metal layer, The second plating layer comprises at least one of gold, silver and palladium, A smart IC substrate wherein the thickness of the first buffer layer is greater than the thickness of the second buffer layer and the second plating layer.

9. In paragraph 8, A plurality of holes are formed penetrating the above substrate and the bonding layer, The metal layer includes a first region that does not overlap the hole and a second region that overlaps the hole, A first buffer layer and a second buffer layer are arranged on the first region, The first buffer layer is arranged on the second region, A smart IC substrate in which the second plating layer is in contact with the first buffer layer.

10. In paragraph 1, A plurality of holes are formed penetrating the above substrate and the bonding layer, The metal layer includes a first region that does not overlap the hole and a second region that overlaps the hole, A first buffer layer and a second buffer layer are arranged on the first region, The first buffer layer is arranged on the second region, A smart IC substrate, wherein the plating layer comprises a first plating layer in contact with the first buffer layer and a second plating layer under the first plating layer.

Images