HEMT device and preparation method therefor

Abstract

The present invention provides an HEMT device and a preparation method therefor. The HEMT device comprises a substrate, a laminated structure, a first dielectric layer, a gate conductive layer, a second dielectric layer, drain contact holes, a gate contact hole, a drain, a gate and a source, wherein trenches are formed in the substrate; the laminated structure comprises a channel layer and a barrier layer and covers the exposed surfaces of the trenches and the upper surface of the substrate; the first dielectric layer fills the trenches and covers the laminated structure, and gate holes are formed in the first dielectric layer; the gate conductive layer fills the gate holes; the second dielectric layer covers the first dielectric layer and the gate conductive layer; the drain contact holes penetrate through the second dielectric layer, the bottom surfaces of the drain contact holes at least expose the barrier layer above the substrate, and the gate contact hole penetrates through the second dielectric layer and exposes the gate conductive layer; the drain and the gate fill the drain contact holes and the gate contact hole, respectively; and the source is electrically connected to the substrate and the channel layer. According to the present invention, the laminated structure is formed in the trenches with inclined inner walls, the source is formed at the bottoms of the trenches, and the drain is formed above the substrate, thereby reducing the on-resistance per unit area of the device.

Description

HEMT device and preparation method thereof Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a HEMT device and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN), a third-generation semiconductor material, offers significant advantages over first-generation semiconductor materials such as silicon and second-generation semiconductor materials such as gallium arsenide (GaAs). AlGaN / GaN high electron mobility transistors (HEMTs) feature a large bandgap, high peak saturation electron velocity, a high concentration of two-dimensional electron gas, and high electron mobility, making them widely used in radio frequency (RF), microwave, and power switching power supplies.

[0003] AlGaN / GaN HEMTs are planar channel field-effect transistors. When a high voltage is applied to the drain, a large electric field spike is generated near the drain edge of the gate. This can cause local dielectric degradation and lead to time-dependent breakdown (TDDB), severely impacting device reliability. To address this severe electric field spike, existing technologies typically place one or more field plates at the gate of the AlGaN / GaN HEMT to suppress the spike height and improve device reliability.

[0004] The planar channel structure of AlGaN / GaN HEMT and the multiple field plates in its device structure have caused many problems. For example, a HEMT device disclosed in patent publication number CN1938859A is shown in Figure 1, which includes a substrate 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a source 05, a first dielectric layer 06, a second dielectric layer 061, a drain 07 and a gate 08. In order for the device to withstand high voltage, multiple field plates are required to suppress electric field spikes. However, in order to suppress electric field spikes, the distance between the gate electrode and the field plate and the drain electrode needs to be sufficiently large. The increase in the gate-drain spacing of the planar channel structure of AlGaN / GaN HEMT will directly lead to an increase in the horizontal source-drain spacing, which in turn leads to an increase in the on-resistance R per unit area in the device. onThe field plates are too high, and in order to realize multiple field plates, multiple dielectric layers are needed to form field plates of multiple heights, which adds an extra 2 to 5 process steps, thereby increasing the process complexity and processing cost. At the same time, too many process steps increase the risk of defects introduced into the process, affecting the reliability of the device. In addition, due to the AlGaN / GaN The HEMT's planar channel structure connects a large number of evenly distributed functional units in parallel on the chip surface. These functional units each include a source, drain, and gate. Consequently, the chip surface is densely covered with a large number of source, drain, and gate electrodes. This necessitates two to four electrode rerouting operations to centrally arrange the electrodes for subsequent bonding or chip placement, increasing electrode processing costs and parasitic capacitance. Another HEMT device disclosed in patent publication number CN104332498A is shown in FIG2 . It includes a substrate 01, a buffer layer 02, a nucleation layer 021, a channel layer 03, a barrier layer 04, a source 05, a first dielectric layer 06, a drain 07, a gate 08, and a field plate 081. The slanted field plate arrangement simplifies the field plate fabrication process, but the electrode wiring process remains complex, and the spacing between the source and drain electrodes is large, resulting in a high on-resistance per unit area.

[0005] Therefore, there is an urgent need to find a method for preparing a HEMT device that reduces the on-resistance per unit area of ​​the device while simplifying the field plate manufacturing process and the electrode manufacturing process of the device.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a HEMT device and a method for manufacturing the same, which are used to solve the problems of the prior art HEMT device, such as the complex multi-field plate manufacturing process, the complex electrode wiring process, and the high on-resistance per unit area.

[0008] To achieve the above and other related objectives, the present invention provides a method for preparing a HEMT device, comprising the following steps:

[0009] Providing a substrate, and forming a plurality of grooves spaced apart on a surface layer of the substrate;

[0010] forming a stacked structure with a predetermined thickness on the exposed surface of the trench and the upper surface of the substrate, wherein the stacked structure includes a buffer layer, a channel layer, and a barrier layer stacked in sequence;

[0011] forming a first dielectric layer filling the trench and covering the exposed surface of the stacked structure, and forming a gate hole in the first dielectric layer located in the trench, wherein the bottom surface and inner wall of the gate hole are spaced a predetermined distance from the stacked structure;

[0012] forming a gate conductive layer filling the gate hole, and forming a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer;

[0013] forming a drain contact hole and a gate contact hole penetrating the second dielectric layer, wherein the bottom of the drain contact hole at least exposes the barrier layer above the substrate between two adjacent trenches, and the bottom of the gate contact hole exposes the gate conductive layer;

[0014] forming a drain electrode filling the drain contact hole, and forming a gate electrode filling the gate contact hole;

[0015] A source electrode electrically connected to at least the substrate and the channel layer is formed.

[0016] Optionally, the angle between the inner wall of the groove and the bottom surface of the groove ranges from 90° to 150°.

[0017] Optionally, the stacked structure further includes a nucleation layer located at the bottom layer of the stacked structure, and the nucleation layer covers the exposed surface of the groove and the upper surface of the substrate.

[0018] Optionally, after forming the stacked structure and before forming the first dielectric layer, the method further includes forming a source contact hole located at the bottom of the trench and penetrating the stacked structure, and the source electrode fills the source contact hole.

[0019] Optionally, after forming the stacked structure and before forming the first dielectric layer, the step of forming a third dielectric layer and a conductive block is also included, wherein the third dielectric layer covers the exposed upper surface of the stacked structure, the conductive block is located on the surface of the third dielectric layer above the inner wall of the groove, and the bottom surface of the gate hole exposes the conductive block.

[0020] Optionally, the gate holes located in the trenches are connected to each other.

[0021] Optionally, an angle between an inner wall of the gate hole and a bottom surface of the gate hole is not less than 90° and not greater than an angle between a bottom surface of the groove and an inner wall of the groove.

[0022] Optionally, the drain electrode further covers an upper surface of the second dielectric layer, and the gate electrode is spaced apart from the drain electrode by a preset distance.

[0023] Optionally, after forming the drain and the gate, the step of thinning the substrate from the bottom surface of the substrate is also included, and after thinning the substrate, the bottom surface of the device at least exposes the channel layer above the bottom surface of the trench, and the source at least covers the bottom surface of the substrate and the exposed surface of the channel layer.

[0024] Optionally, after forming the gate and the drain, a step of forming a source contact hole at the bottom of the substrate is also included, the bottom of the source contact hole at least exposes the channel layer above the bottom surface of the trench, and the source at least fills the source contact hole.

[0025] The present invention also provides a HEMT device, comprising:

[0026] A substrate having a plurality of grooves spaced apart from each other;

[0027] a stacked structure comprising a buffer layer, a channel layer, and a barrier layer stacked in sequence, the stacked structure covering the exposed surface of the trench and the upper surface of the substrate;

[0028] a first dielectric layer filling the trench and covering the exposed surface of the stacked structure, wherein the first dielectric layer is provided with a gate hole located in the trench, and a bottom surface and an inner wall of the gate hole are spaced a predetermined distance from the stacked structure;

[0029] a gate conductive layer, filling the gate hole;

[0030] a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer;

[0031] a drain contact hole and a gate contact hole, wherein the drain contact hole penetrates the second dielectric layer and the bottom of the drain contact hole at least exposes the barrier layer above the substrate between two adjacent trenches, and the gate contact hole penetrates the second dielectric layer and the bottom of the gate conductive layer;

[0032] a drain electrode and a gate electrode, wherein the drain electrode fills the drain contact hole, and the gate electrode fills the gate contact hole;

[0033] The source is electrically connected to at least the substrate and the channel layer.

[0034] As described above, the HEMT device and its preparation method of the present invention improve the device manufacturing process, form the trench in the substrate, and form the stacked structure covering the inner wall of the trench, the bottom surface of the trench, and the upper surface of the substrate, form the first dielectric layer filling the trench in the trench, form the gate hole and the gate conductive layer filling the gate hole in the first dielectric layer located in the trench, simultaneously form the drain electrode electrically connected to the stacked structure located on the upper surface of the substrate and the gate electrode electrically connected to the gate conductive layer, and form the source electrode electrically connected to the stacked structure located at the bottom of the trench, thereby making the source electrode and the drain electrode located in different planes, simplifying the wiring process of the device electrodes, increasing the arrangement area of ​​each electrode, reducing the difficulty of manufacturing the device electrodes, and improving the thermal conductivity of the device. Since the source electrode is electrically connected to the substrate, the source-drain parasitic capacitance C of the device can be effectively reduced. ds , thereby effectively improving the switching characteristics of the device, and by electrically connecting the substrate to the source, the dynamic resistance increase of the device can also be reduced; due to the inclined inner wall of the trench, the effective area of ​​the two-dimensional electron gas in the device is increased, reducing the on-resistance per unit area of ​​the device, and at the same time, the horizontal distance between the source and the drain can be shortened, thereby reducing the size of the device; the gate hole is formed in the trench, and by adjusting the angle between the inner wall of the gate hole and the bottom surface of the gate hole, the distance between the gate conductive layer and the barrier layer is regulated, while the electric field strength of the conductive channel near the drain end on both sides of the gate conductive layer is reduced, thereby increasing the breakdown voltage of the device, suppressing the current collapse effect of the device, and simplifying the gate field plate manufacturing process of the device; in addition, by forming the third dielectric layer and the conductive block located on the third dielectric layer on the inner wall of the trench and electrically connected to the gate conductive layer, the control capability of the gate can be enhanced, further improving the performance of the device, and having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic diagram showing a cross-sectional structure of a HEMT device.

[0036] FIG2 is a schematic diagram showing the cross-sectional structure of another HEMT device.

[0037] FIG3 is a schematic diagram showing the cross-sectional structure of a substrate in the method for preparing a HEMT device according to the present invention.

[0038] FIG4 is a schematic diagram showing a cross-sectional structure of a HEMT device after trench formation in the method for preparing the HEMT device of the present invention.

[0039] FIG5 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a stacked structure in the method for preparing the HEMT device of the present invention.

[0040] FIG6 is a schematic cross-sectional view showing a HEMT device fabrication method according to the present invention after forming a source electrode at the bottom of a trench before forming a first dielectric layer.

[0041] FIG. 7 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a third dielectric layer and a conductive block in the method for manufacturing the HEMT device of the present invention.

[0042] FIG8 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a first dielectric layer in the method for manufacturing the HEMT device of the present invention.

[0043] FIG9 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a gate hole in the method for manufacturing the HEMT device according to the present invention.

[0044] FIG10 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a gate conductive layer in the method for preparing the HEMT device of the present invention.

[0045] FIG11 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a second dielectric layer in the method for manufacturing the HEMT device of the present invention.

[0046] FIG12 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a drain contact hole and a gate contact hole in the method for manufacturing the HEMT device according to the present invention.

[0047] FIG13 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a conductive material layer in the method for preparing the HEMT device of the present invention.

[0048] FIG14 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a gate and a drain in the method for manufacturing the HEMT device of the present invention.

[0049] FIG. 15 is another schematic cross-sectional view showing the HEMT device fabrication method of the present invention after forming the gate and drain.

[0050] FIG. 16 is a schematic diagram showing the distribution of gate and drain electrodes in the fabrication method of a HEMT device according to the present invention.

[0051] FIG17 is a schematic diagram showing a cross-sectional structure of a HEMT device after forming a source electrode at the bottom of the substrate in the method for manufacturing the HEMT device of the present invention.

[0052] FIG. 18 is a schematic diagram showing another cross-sectional structure of the HEMT device fabrication method according to the present invention after forming a source electrode at the bottom of the substrate.

[0053] FIG. 19 is a schematic diagram showing a third cross-sectional structure after forming a source electrode at the bottom of the substrate in the method for manufacturing a HEMT device according to the present invention.

[0054] FIG. 20 is a schematic diagram showing a fourth cross-sectional structure after forming a source electrode at the bottom of the substrate in the method for manufacturing a HEMT device according to the present invention.

[0055] FIG21 is a schematic diagram showing the three-dimensional structure of the HEMT device of the present invention.

[0056] DESCRIPTION OF REFERENCE NUCLEAR NUCLEARING LAYER 01 Substrate 02 Buffer Layer 021 Nucleation Layer 03 Channel Layer 04 Barrier Layer 05 Source 06 First Dielectric Layer 061 Second Dielectric Layer 07 Drain 08 Gate 081 Field Plate 1 Substrate 11 Trench 12 Source Contact Hole 13 Source 2 Stacked Structure 20 Nucleation Layer 21 Buffer Layer 22 Channel Layer 23 Barrier Layer 3 First Dielectric Layer 31 Gate Hole 4 Third Dielectric Layer 41 Conductive Block 5 Gate Conductive Layer 6 Second Dielectric Layer 61 Drain Contact Hole 62 Gate Contact Hole 7 Drain 70 Conductive Material Layer 8 Gate DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] Please refer to Figures 3 to 21. It should be noted that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the figures only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may also be more complex.

[0059] Example 1

[0060] This embodiment provides a method for preparing a HMET device, comprising the following steps:

[0061] S1: providing a substrate, and forming a plurality of grooves spaced apart on a surface layer of the substrate;

[0062] S2: forming a stacked structure with a predetermined thickness on the exposed surface of the trench and the upper surface of the substrate, wherein the stacked structure includes a buffer layer, a channel layer, and a barrier layer stacked in sequence;

[0063] S3: forming a first dielectric layer filling the trench and covering the exposed surface of the stacked structure, forming a gate hole in the first dielectric layer and located in the trench, wherein the bottom surface and inner wall of the gate hole are spaced a predetermined distance from the stacked structure;

[0064] S4: forming a gate conductive layer filling the gate hole, and forming a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer;

[0065] S5: forming a drain contact hole and a gate contact hole penetrating the second dielectric layer, wherein the bottom of the drain contact hole at least exposes the barrier layer above the substrate between two adjacent trenches, and the bottom of the gate contact hole exposes the gate conductive layer;

[0066] S6: forming a drain electrode filling the drain contact hole, and forming a gate electrode filling the gate contact hole;

[0067] S7: forming a source electrode electrically connected to at least the substrate and the channel layer.

[0068] Referring to Figures 3 to 7 , steps S1 and S2 are performed. S1: Providing a substrate 1, and forming a plurality of spaced trenches 11 on the surface of the substrate 1; S2: Forming a stacked structure 2 of a predetermined thickness on the exposed surfaces of the trenches 11 and the upper surface of the substrate 1. The stacked structure 2 includes a buffer layer 21, a channel layer 22, and a barrier layer 23 stacked in sequence.

[0069] Specifically, as shown in FIG3 , which is a schematic diagram of the cross-sectional structure of the substrate 1 , the size, thickness and shape of the substrate 1 can be selected according to actual conditions while ensuring device performance, and are not limited here.

[0070] Specifically, as shown in Figure 4, which is a schematic diagram of the cross-sectional structure after the groove 11 is formed, the formation of the groove 11 includes the following steps: forming a patterned first shielding layer (not shown) on the upper surface of the substrate 1, and patterning the first shielding layer; etching the substrate 1 based on the patterned first shielding layer to obtain the groove 11.

[0071] Specifically, the first shielding layer includes photoresist or other suitable developing materials. In this embodiment, photoresist is used as the first shielding layer.

[0072] Specifically, the method of forming the first shielding layer and patterning the first shielding layer is a conventional photoresist formation and development method, which will not be described in detail here.

[0073] Specifically, the method of etching the substrate 1 includes dry etching, wet etching or other suitable methods.

[0074] Specifically, the depth of the groove 11 ranges from 5 μm to 30 μm, where “depth” refers to the distance from the bottom surface of the groove 11 to the opening of the groove 11 (the upper surface of the substrate 1 ).

[0075] As an example, the angle between the inner wall of the groove 11 and the bottom surface of the groove 11 ranges from 90° to 150°, such as 90°, 100°, 110°, 120°, 130°, 140°, and 150°.

[0076] Specifically, while ensuring device performance, the opening size of the trench 11 and the distance between two adjacent trenches 11 can be selected according to actual conditions and are not limited here.

[0077] As an example, as shown in Figure 5, which is a schematic diagram of the cross-sectional structure after the stacked structure 2 is formed, the stacked structure 2 also includes a nucleation layer 20 located at the bottom of the stacked structure 2, and the nucleation layer 20 covers the exposed surface of the groove 11 and the upper surface of the substrate 1.

[0078] Specifically, the buffer layer 21 is located on the nucleation layer 20 . The buffer layer 21 can hinder the diffusion of ions and can also be used to bond other semiconductor material layers that need to be grown thereon.

[0079] Specifically, the channel layer 22 is located on the buffer layer 21, and the barrier layer 23 is located on the channel layer 22. The barrier layer 23 and the channel layer 22 form a heterojunction structure, thereby forming a two-dimensional electron gas (2DEG) channel at the heterojunction interface between the barrier layer 23 and the channel layer 22.

[0080] Specifically, the nucleation layer 20 , the buffer layer 21 , the channel layer 22 and the barrier layer 23 are formed by adopting a common film epitaxial process, which will not be described in detail here.

[0081] As an example, after forming the stacked structure 2 and before forming the first dielectric layer 3, the step of forming a source contact hole 12 located at the bottom of the groove 11 and passing through the stacked structure 2 is also included, and the source 13 fills the source contact hole 12, that is, after executing the step S2 and before executing the step S3, the step S7 is executed: forming a source 13 electrically connected to at least the substrate 1 and the channel layer 22.

[0082] Specifically, forming the source contact hole 12 includes the following steps: forming a patterned second shielding layer (not shown) on the exposed surface of the stacked structure 2; etching the stacked structure 2 located at the bottom of the groove 11 based on the patterned second shielding layer to form the source contact hole 12 passing through the stacked structure 2, and the bottom surface of the source contact hole 12 exposes the substrate 12, so as to facilitate the electrical connection between the source 13 and the substrate 1.

[0083] Specifically, the material of the second shielding layer includes photoresist or other suitable developing materials; the method of forming the second shielding layer and patterning the second shielding layer is a conventional photoresist forming and developing method, which will not be described in detail here.

[0084] Specifically, while ensuring device performance, the depth and opening size of the source contact hole 12 can be selected according to actual conditions and are not limited here.

[0085] As an example, as shown in Figure 6, it is a schematic diagram of the cross-sectional structure after the source 13 is formed at the bottom of the groove 11 before the first dielectric layer 3 is formed. The material of the source 13 includes one or more of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum and other suitable conductive materials.

[0086] Specifically, the method of forming the source 13 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0087] Specifically, after forming the source 13 in the source contact hole 12 and before forming the first dielectric layer 3, a step of removing the second shielding layer is also included; the method for removing the second shielding layer is a common photoresist stripping method, which will not be repeated here.

[0088] As an example, as shown in Figure 7, it is a schematic diagram of the cross-sectional structure after the third dielectric layer 4 and the conductive block 41 are formed. After the stacked structure 2 is formed and before the first dielectric layer 3 is formed, the step of forming the third dielectric layer 4 and the conductive block 41 is also included. The third dielectric layer 4 covers the stacked structure 2 to expose the upper surface. The conductive block 41 is located on the surface of the third dielectric layer 4 above the inner wall of the groove 11, and the bottom surface of the gate hole 31 exposes the conductive block 41.

[0089] Specifically, the method of forming the third dielectric layer 4 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0090] Specifically, while ensuring device performance, the thickness of the third dielectric layer 4 can be selected according to actual conditions and is not limited here.

[0091] Specifically, the method of forming the conductive block 41 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0092] Specifically, while ensuring device performance and the bottom surface of the subsequently formed gate hole (see FIG. 10 ) exposing the conductive block 41 , the thickness, size and shape of the conductive block 41 can be selected according to actual conditions and are not limited here.

[0093] 8 to 9 , step S3 is performed: forming a first dielectric layer 3 filling the trench 11 and covering the exposed surface of the stacked structure 2, forming a gate hole 31 in the trench 11 in the first dielectric layer 3, and the bottom surface and inner wall of the gate hole 31 are spaced a preset distance from the stacked structure 2.

[0094] Specifically, as shown in Figure 8, which is a schematic diagram of the cross-sectional structure after the first dielectric layer 3 is formed, after the stacked structure 2 is formed, the first dielectric layer 3 is directly formed to fill the groove 11 and cover the exposed surface of the stacked structure 2. The method of forming the first dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0095] Specifically, since the first dielectric layer 3 fills the groove 11, after the first dielectric layer 3 is formed, the upper surface of the first dielectric layer 3 will be uneven. Therefore, after the first dielectric layer 3 is formed, the upper surface of the first dielectric layer 3 needs to be planarized to make the upper surface of the first dielectric layer 3 smooth. At the same time, the first dielectric layer 3 can be thinned so that the first dielectric layer 3 located on the upper surface of the substrate 1 reaches a preset thickness.

[0096] Specifically, the method for planarizing the first dielectric layer 3 includes chemical mechanical polishing or other suitable methods.

[0097] Specifically, while ensuring device performance, after planarization, the thickness of the first dielectric layer 3 located above the substrate 1 can be selected according to actual conditions and is not limited here.

[0098] Specifically, as shown in Figure 9, which is a schematic diagram of the cross-sectional structure after the gate hole 31 is formed, the formation of the gate hole 31 includes the following steps: forming a patterned third shielding layer (not shown) on the upper surface of the first dielectric layer 3, and etching the first dielectric layer 3 based on the patterned third shielding layer to obtain the gate hole 31 located in the groove 11.

[0099] Specifically, the material of the third shielding layer includes photoresist or other suitable developing materials; the method of forming the third shielding layer and patterning the third shielding layer is a conventional photoresist forming and developing method, which will not be described in detail here.

[0100] Specifically, the method of etching the first dielectric layer 3 includes dry etching, wet etching or other suitable methods.

[0101] As an example, the angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31 is not less than 90° and not greater than the angle between the bottom surface of the groove 11 and the inner wall of the groove 11 .

[0102] Specifically, while ensuring device performance, the opening size and depth of the gate hole 31 can be selected based on actual conditions and are not limited here. The distance between the inner wall of the gate hole 31 and the inner wall of the trench 11, as well as the distance between the bottom surface of the gate hole 31 and the upper surface of the stacked structure 2 located below the gate hole 31, can be selected based on actual conditions and are not limited here. The "depth" here refers to the distance from the bottom surface of the gate hole 31 to the opening of the gate hole 31.

[0103] As an example, the gate holes 31 located in the trenches 11 are interconnected to facilitate the extraction of the gate of the device.

[0104] Please refer to Figures 10 to 16 to perform steps S4, S5, and S6. S4: Forming a gate conductive layer 5 that fills the gate hole 31, and forming a second dielectric layer 6 that covers the first dielectric layer 3 and the exposed upper surface of the gate conductive layer 5; S5: Forming a drain contact hole 61 and a gate contact hole 62 that penetrate the second dielectric layer 6, with the bottom of the drain contact hole 61 at least exposing the barrier layer 23 above the substrate 1 between two adjacent trenches 11, and the bottom of the gate contact hole 62 exposing the gate conductive layer 5; S6: Forming a drain 7 that fills the drain contact hole 61, and forming a gate 8 that fills the gate contact hole 62.

[0105] Specifically, as shown in Figure 10, which is a schematic diagram of the cross-sectional structure after the gate conductive layer 5 is formed, the method of forming the gate conductive layer 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0106] Specifically, after forming the gate conductive layer 5 and before forming the second dielectric layer 6, the process further includes removing the third shielding layer. The method for removing the third shielding layer is a common photoresist stripping method, which will not be described in detail here.

[0107] Specifically, as shown in FIG11 , which is a schematic diagram of a cross-sectional structure after the second dielectric layer 6 is formed, the method of forming the second dielectric layer 6 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0108] Specifically, while ensuring device performance, the thickness, size and shape of the second dielectric layer 6 can be selected according to actual conditions and are not limited here.

[0109] Specifically, as shown in Figure 12, which is a schematic diagram of the cross-sectional structure after the drain contact hole 61 and the gate contact hole 62 are formed, the formation of the drain contact hole 61 and the gate contact hole 62 includes the following steps: forming a patterned fourth shielding layer (not shown) on the upper surface of the second dielectric layer 6; etching the second dielectric layer 6 based on the patterned fourth shielding layer to obtain the drain contact hole 61 that penetrates the second dielectric layer 6 and the bottom surface of which at least exposes the barrier layer 23, and the gate contact hole 62 whose bottom surface exposes the gate conductive layer 5.

[0110] Specifically, the material of the fourth shielding layer includes photoresist or other suitable developing materials; the method of forming the fourth shielding layer and patterning the fourth shielding layer is a conventional photoresist forming and developing method, which will not be described in detail here.

[0111] Specifically, while ensuring device performance, the drain contact hole 61 and the gate contact hole 62 may also be formed in steps, that is, the drain contact hole 61 and the gate contact hole 62 are formed separately.

[0112] Specifically, the method of forming the drain contact hole 61 and the gate contact hole 62 includes dry etching, wet etching or other suitable methods.

[0113] Specifically, while ensuring that the formed drain electrode forms an ohmic contact with the barrier layer 23 and is electrically insulated from the substrate 1, the depth of the drain contact hole 61 can be selected based on actual conditions. For example, the bottom surface of the drain contact hole 61 can expose the barrier layer 23 above the substrate 1, the channel layer 22 above the substrate 1, the buffer layer 21 above the substrate 1, or penetrate the stacked structure 2. However, when the drain contact hole 61 penetrates the stacked structure 2, since the substrate 1 is a non-insulating substrate, in order to ensure device performance, an insulating material is required to be formed on the bottom surface of the drain contact hole 61 where the drain electrode 7 is formed to isolate the drain electrode 7 from the substrate 1 to ensure device performance. The depth here refers to the distance between the bottom surface of the drain contact hole 61 and the opening of the drain contact hole 61.

[0114] Specifically, when the third dielectric layer 4 is formed on the upper surface of the stacked structure 2 , the drain contact hole 61 also penetrates the third dielectric layer 4 .

[0115] Specifically, after forming the drain contact hole 61 and the gate contact hole 62, and before forming the gate 8 and the drain 7, a step of removing the fourth shielding layer is also included. The method for removing the fourth shielding layer is a commonly used photoresist stripping method, which will not be repeated here.

[0116] Specifically, Figures 13, 14, 15, and 16 are schematic cross-sectional views of a conductive material layer 70 after forming the drain electrode 7 and the gate electrode 8, a schematic cross-sectional view of another cross-sectional view of the drain electrode 7 and the gate electrode 8, and a schematic view of the distribution of the gate electrode 8 and the drain electrode 7, respectively. The drain electrode 7 may be formed by magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The gate electrode 8 may be formed by magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. In this embodiment, the drain electrode 7 and the gate electrode 8 are formed simultaneously, i.e., a conductive material layer 70 is formed to fill the drain contact hole 61 and the gate contact hole 62, and then the conductive material layer 70 is patterned to obtain the drain electrode 7 and the gate electrode 8.

[0117] As an example, the drain electrode 7 also covers the upper surface of the second dielectric layer 6 , and the gate electrode 8 is spaced apart from the drain electrode 7 by a preset distance.

[0118] Specifically, while ensuring device performance, the distance between the gate 8 and the drain 7 can be selected according to actual conditions and is not limited here.

[0119] 17 to 20 , step S7 is performed: forming a source electrode 13 electrically connected to at least the substrate 1 and the channel layer 22 .

[0120] As an example, after forming the drain 7 and the gate 8, the step of thinning the substrate 1 from the bottom surface of the substrate 1 is also included, and after thinning the substrate 1, the bottom surface of the device at least exposes the channel layer 22 above the bottom surface of the groove 11, and the source 13 at least covers the bottom surface of the substrate 1 and the exposed surface of the channel layer 22, that is, when the step S7 is not executed before the step S3 is executed, after executing the step S6 and before executing the step S7, the substrate 1 is thinned so that the bottom surface of the structure after forming the drain 7 and the gate 8 exposes the channel layer 22, so as to facilitate the execution of the step S7.

[0121] Specifically, the method for thinning the substrate 1 is chemical mechanical polishing, dry etching, wet etching, laser lift-off or other suitable methods.

[0122] Specifically, while ensuring device performance, the barrier layer 23 or the first dielectric layer 3 can be exposed after thinning the substrate 1, and when the third dielectric layer 4 is formed on the upper surface of the stacked structure 2, the third dielectric layer 4 can also be exposed after thinning the substrate 1.

[0123] Specifically, Figures 17, 18 and 19 are respectively a schematic diagram of a cross-sectional structure after the source electrode 13 is formed on the bottom surface of the substrate 1, another schematic diagram of a cross-sectional structure after the source electrode 13 is formed on the bottom surface of the substrate 1, and a schematic diagram of a third cross-sectional structure after the source electrode 13 is formed on the bottom surface of the substrate 1; the source electrode 13 covers the exposed surface of the device structure after the substrate 1 is thinned, that is, after the substrate 1 is thinned, the source electrode 13 is directly formed on the bottom surface of the structure after the substrate 1 is thinned, and the source electrode 13 forms an ohmic contact with the exposed channel layer 22.

[0124] As an example, after forming the gate 8 and the drain 7, the step of forming a source contact hole 12 at the bottom of the substrate 1 is also included, and the bottom of the source contact hole 12 at least exposes the channel layer 22 above the bottom surface of the trench 11, and the source 13 at least fills the source contact hole 12, that is, when the step S7 is not executed before the step S3 is executed, after executing the step S6 and before executing the step S7, the substrate 1 is etched from the bottom surface of the substrate 1 to obtain the source contact hole 12 with at least the channel layer 22 exposed at the bottom.

[0125] Specifically, when step S7 is not performed before step S3 is performed, after step S6 is performed and before step S7 is performed, the bottom surface of the source contact hole 12 formed at the bottom of the substrate 1 can expose the channel layer 22 above the bottom of the trench 11, can expose the barrier layer 23 above the bottom of the trench 11, and can also expose the first dielectric layer 3 above the bottom of the trench 11, and when the third dielectric layer 4 is formed on the upper surface of the stacked structure 2, the bottom surface of the source contact hole 12 can also expose the third dielectric layer 4 above the bottom of the trench 11.

[0126] Specifically, while ensuring device performance, after forming the drain 7 and the gate 8, the shape and opening size of the source contact hole 12 formed at the bottom of the substrate 1 can be selected according to actual conditions and are not limited here.

[0127] Specifically, after forming the drain electrode 7 and the gate electrode 8 , a method for forming the source contact hole 12 at the bottom of the substrate 1 includes dry etching, wet etching or other suitable methods.

[0128] Specifically, as shown in Figure 20, which is a schematic diagram of the cross-sectional structure after the source 13 filling the source contact hole 12 is formed, after the source contact hole 12 is formed at the bottom of the substrate 1, it also includes forming the source 13 filling the source contact hole 12 and covering the bottom surface of the substrate 1.

[0129] Specifically, since the source 13 is electrically connected to the stacked structure 2 located at the bottom of the groove 11, and the drain 7 is electrically connected to the stacked structure 2 on the upper surface of the substrate 1 between two adjacent grooves 11, the source 13 and the drain 7 are located in different planes, so that only one gate 8 and one drain 7 need to be formed on the front of the device, and the gate 8 and the drain 7 can be formed synchronously, avoiding multiple electrode wirings and simplifying the electrode wiring process of the device.

[0130] Specifically, since the gate 8, the drain 7 and the source 13 are formed on different planes of the device, the arrangement area of ​​each electrode of the device can be increased, the difficulty of manufacturing the electrode of the device is reduced, the lead-out of the electrode of the device is facilitated, and the thermal conductivity of the device can be improved.

[0131] Specifically, by forming the stacked structure 2 including the channel layer 22 and the barrier layer 23 on the bottom surface and the inclined inner wall of the trench 11, the area of ​​the effective two-dimensional electron gas between the source 13 and the drain 7 is greatly increased, thereby reducing the on-resistance per unit area of ​​the device.

[0132] Specifically, the gate holes 31 that are interconnected and have a relatively deep depth are formed by a single etching, and the gate holes 31 are located in the first dielectric layer 3 that fills the groove 11, and the gate conductive layer 5 that fills the gate hole 31 is formed, thereby forming a gate field plate perpendicular to the bottom surface of the groove 11, reducing the electric field strength of the conductive channels on both sides of the gate conductive layer 5 near the drain 7 end, thereby increasing the breakdown voltage of the device, and reducing the probability of electrons in the conductive channels of the device being excited by a strong electric field to enter the surface state, thereby suppressing the current collapse effect of the device and simplifying the process of manufacturing the gate field plate.

[0133] Specifically, when the angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31 is greater than 90° (that is, the inner wall of the gate hole 31 is inclined), the distance between the gate field plate of the device and the barrier layer 23 can be changed, and then the distance between the gate field plate and the stacked structure 2 can be controlled.

[0134] Specifically, the source electrode 13 is electrically connected to the substrate 1, which can effectively reduce the source-drain parasitic capacitance C of the device. ds , which in turn can improve the device switching characteristics.

[0135] Specifically, the substrate 1 is electrically connected to the source electrode 13 , which effectively reduces the dynamic resistance gain of the device and improves the performance of the device.

[0136] The preparation method of the HEMT device of this embodiment improves the structure of the device, forms the inner wall of the trench 11 in the substrate 1 and the stacked structure 2 on the exposed upper surface of the substrate 1, forms the gate conductive layer 5, forms the source electrode 13 electrically connected to the stacked structure 2 at the bottom of the trench 11, and forms the drain electrode 7 electrically connected to the stacked structure 2 located on the upper surface of the substrate 1, so that the source electrode 13 and the drain electrode 7 are located in different planes, and the gate electrode 8 and the drain electrode 7 are simultaneously formed on the front side of the substrate, and the source electrode 13 is formed on the back side of the substrate 1, thereby avoiding multiple wiring on the front side of the device, simplifying the electrode wiring process of the device, increasing the arrangement area of ​​each electrode of the device, and reducing the electrode length of each electrode of the device. The difficulty of manufacturing can also be improved. At the same time, the thermal conductivity of the device can be improved. Since the inner wall of the groove 11 is inclined, the area of ​​the effective electron gas between the source 13 and the drain 7 is increased, thereby reducing the on-resistance per unit area of ​​the device. Since the gate hole 31 is located in the first dielectric layer 3 filling the groove 11 and is interconnected, the gate conductive layer 5 equivalent to the gate field plate of the device is formed in the gate hole 31, which reduces the electric field strength of the conductive channel on both sides of the gate conductive layer 5 near the drain 7 end, thereby increasing the breakdown voltage of the device, reducing the probability of electrons in the conductive channel of the device being excited by the strong electric field and entering the surface state, and suppressing the current collapse effect of the device. There is no need to make the gate field plate multiple times, which simplifies the manufacturing process of the gate field plate. In addition, by electrically connecting the source 13 to the substrate 1, the source-drain parasitic capacitance C of the device can be effectively reduced. ds , thereby effectively improving the switching characteristics of the device, and by electrically connecting the substrate 1 to the source 13, the dynamic resistance increase of the device can also be effectively reduced.

[0137] Example 2

[0138] This embodiment provides a HEMT device, as shown in Figures 15, 17, 18, 19, 20, and 21. Figures 15, 17, 18, 19, 20, and 21 are respectively a schematic cross-sectional structure diagram of the HEMT device, another schematic cross-sectional structure diagram of the HEMT device, a schematic cross-sectional structure diagram of the third, a schematic cross-sectional structure diagram of the fourth, a schematic cross-sectional structure diagram of the fifth, and a schematic three-dimensional structure diagram of the HEMT device. The HEMT device includes: a substrate 1, a stacked structure 2, a first dielectric layer 3, a gate conductive layer 5, a second dielectric layer 6, a drain contact hole 61, a gate contact hole 62, a drain electrode 7, a gate electrode 8, and a source electrode 13. The substrate 1 is provided with a plurality of trenches 11 spaced apart from each other. The stacked structure 2 includes a buffer layer 21, a channel layer 22, and a barrier layer 23 stacked in sequence. The stacked structure 2 covers the exposed surface of the trench 11 and the upper surface of the substrate 1; the first dielectric layer 3 fills the trench 11 and covers the exposed surface of the stacked structure 2, and the first dielectric layer 3 is provided with a gate hole 31 located in the trench 11, and the bottom surface and inner wall of the gate hole 31 are spaced a preset distance from the stacked structure 2; the gate conductive layer 5 fills the gate hole 31; the second dielectric layer 6 covers the first dielectric layer 3 and the exposed upper surface of the gate conductive layer 5; the drain contact hole 61 penetrates the second dielectric layer 6 and the bottom of which at least exposes the barrier layer 23 above the substrate 1 between two adjacent trenches 11; the gate contact hole 62 penetrates the second dielectric layer 6 and the bottom of which exposes the gate conductive layer 5; the drain electrode 7 fills the drain contact hole 61, and the gate electrode 8 fills the gate contact hole 62; the source electrode 13 is electrically connected to at least the substrate 1 and the channel layer 22.

[0139] Specifically, the material of the substrate 1 includes one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire and germanium, and can also be other materials that can grow group III nitride materials.

[0140] Specifically, the angle between the inner wall of the groove 11 and the bottom surface of the groove 11 ranges from 90° to 150°.

[0141] Specifically, a nucleation layer 20 is further provided on the bottom layer of the stacked structure 2 , and the nucleation layer 20 covers the exposed surface of the groove 11 and the exposed upper surface of the substrate 1 .

[0142] Specifically, the material of the nucleation layer 20 includes GaN, AlGaN, AlN, InAlGaN, InGaN, InAlN, InN or other suitable group III nitride materials.

[0143] Specifically, the buffer layer 21 is made of GaN, AlGaN, AlN, InAlGaN, InGaN, InAlN, InN or other suitable Group III nitride materials.

[0144] Specifically, the material of the channel layer 22 includes GaN, AlGaN, AlN, InAlGaN, InGaN, InAlN, InN or other suitable Group III nitride semiconductor materials.

[0145] Specifically, the barrier layer 23 is made of GaN, AlGaN, AlN, InAlGaN, InGaN, InAlN, InN or other suitable Group III nitride semiconductor materials.

[0146] Specifically, the material of the first dielectric layer 3 includes at least one of SiN, SiO 2 , SiON, and Al 2 O 3 , and may also be a suitable dielectric material.

[0147] Specifically, the gate conductive layer 5 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or a combination thereof, or other suitable conductive materials.

[0148] Specifically, the material of the second dielectric layer 6 includes at least one of SiN, SiO2, SiON, and Al2O3, or other suitable dielectric materials. In this embodiment, the first dielectric layer 3 and the second dielectric layer 6 are made of the same material.

[0149] Specifically, the HEMT device is further provided with a third dielectric layer 4 and a conductive block 41. The third dielectric layer 4 covers the stacked structure 2 to expose the upper surface. The conductive block 41 covers the surface of the third dielectric layer 4 located above the inner wall of the trench 11, and the bottom surface of the gate hole 31 exposes the conductive block 41.

[0150] Specifically, the material of the third dielectric layer 4 includes at least one of SiN, SiO 2 , SiON, and Al 2 O 3 , and may also be other suitable dielectric materials.

[0151] Specifically, the conductive block 41 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0152] Specifically, a source contact hole 12 is also provided at the bottom of the groove 11, and the source 13 fills the source contact hole 12. The source contact hole 12 passes through the stacked structure 2 and the bottom surface exposes the substrate 1. When the third dielectric layer 4 is provided in the device, the source contact hole 12 also passes through the third dielectric layer, and the source contact hole 12 is spaced a preset distance from the conductive block 41, and the source 13 is spaced a preset distance from the conductive block 41.

[0153] Specifically, when the device is provided with the third dielectric layer 4 and the conductive block 41 , the distance between the source 13 and the conductive block 41 can be selected according to actual conditions while ensuring device performance, and is not limited here.

[0154] Specifically, while ensuring device performance, the distance between the bottom surface of the gate hole 31 and the source 13 can be selected according to actual conditions and is not limited here.

[0155] Specifically, the angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31 is not less than 90° and not greater than the angle between the bottom surface of the groove 11 and the inner wall of the groove 11, and the inner wall of the gate hole 31 is separated from the inner wall of the groove 11 by a preset distance.

[0156] Specifically, when the source contact hole 12 is not provided at the bottom of the trench 11 and the trench 11 passes through the substrate 1, the source 13 at least covers the exposed surface of the channel layer 22 located at the bottom of the trench 11 and the bottom surface of the substrate 1, that is, the channel layer 22 at the bottom of the trench 11 can cover the source 13 below the trench 11, the barrier layer 23 at the bottom of the trench 11 can cover the source 13 below the trench 11, and the first dielectric layer 3 at the bottom of the trench 11 can also cover the source 13 below the trench 11. When the exposed surface of the stacked structure 2 is provided with the third dielectric layer 4, the third dielectric layer 4 at the bottom of the trench 11 can also cover the source 13 below the trench 11.

[0157] Specifically, when the source contact hole 12 is not provided at the bottom of the trench 11 and the trench 11 does not penetrate the substrate 1, the bottom of the substrate 1 is provided with the source contact hole 12 opening from the bottom surface of the substrate 1, and the bottom surface of the source contact hole 12 at least exposes the channel layer 22 at the bottom of the trench 11, that is, the bottom surface of the source contact hole 12 can expose the channel layer 22 at the bottom of the trench 11, can expose the barrier layer 23 located at the bottom of the trench 11, and can also expose the first dielectric layer 3 at the bottom of the trench 11, and when the third dielectric layer 4 is provided on the upper surface of the stacked structure 2, the bottom surface of the source contact hole 12 can also expose the third dielectric layer 4 at the bottom of the trench 11.

[0158] Specifically, when the bottom of the substrate 1 is provided with the source contact hole 12 opened from the bottom surface of the substrate 1 , the source 13 fills the source contact hole 12 and covers the bottom surface of the substrate 1 .

[0159] Specifically, while ensuring device performance, the opening size of the gate contact hole 62 can be selected according to actual conditions and is not limited here; the opening size of the drain contact hole 61 can be selected according to actual conditions and is not limited here.

[0160] Specifically, the material of the drain electrode 7 includes one or more of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum and other suitable conductive materials; the material of the gate electrode 8 includes one or more of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum and other suitable conductive materials; the material of the source electrode 13 includes one or more of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum and other suitable conductive materials.

[0161] Specifically, by adjusting the angle between the inner wall of the gate hole 31 and the bottom surface of the gate hole 31, the distance between the gate conductive layer 5 and the barrier layer 23 located on the inner wall of the groove 11 can be regulated, and then the influence of the gate conductive layer 5 on the electric field strength in the conductive channel of the device can be regulated, thereby achieving regulation of the device performance.

[0162] Specifically, by setting the third dielectric layer 4 and the conductive block 41, the conductive block 41 is exposed at the bottom of the gate hole 31, that is, the conductive block 41 is electrically connected to the gate conductive layer 5, and then the control ability of the gate 8 on the shutdown of the conductive channel in the device can be enhanced, thereby improving the performance of the device.

[0163] Specifically, by arranging the stacked structure 2 on the inner wall and bottom surface of the groove 11 and the upper surface of the substrate 1, and the inner wall of the groove 11 is inclined, the conductive channel in the device (the area where the two-dimensional electron gas is located) is tilted and distributed, thereby reducing the on-resistance per unit area of ​​the device while ensuring the device performance, shortening the horizontal distance between the source 13 and the drain 7, and thereby reducing the size of the device.

[0164] The HEMT device of this embodiment optimizes its structure by disposing a stacked structure 2 comprising a channel layer 22 and a barrier layer 23 on the inner wall of the trench 11, the bottom surface of the trench 11, and the upper surface of the substrate 11. The source electrode 13 is electrically connected to the stacked structure 2 at the bottom of the trench 11, and the drain electrode 7 is electrically connected to the stacked structure 2 located on the upper surface of the substrate 1. The inclined inner wall of the trench 11 increases the effective area of ​​the two-dimensional electron gas (2DEG), reducing the device's on-resistance per unit area. Furthermore, since the source electrode 13 and the drain electrode 7 are located in different planes, the horizontal distance between them is shortened while maintaining device performance, thereby reducing device size. Furthermore, the provision of the third dielectric layer 4 and the conductive block 41 enhances the gate 8's ability to control device shutdown, thereby improving device performance.

[0165] In summary, the HEMT device and its preparation method of the present invention form a trench with an inclined inner wall in a substrate by improving the device manufacturing process, and form a stacked structure covering the inner wall of the trench, the bottom surface of the trench, and the upper surface of the substrate. The stacked structure includes a stacked channel layer and a barrier layer. A first dielectric layer is filled in the trench, and a gate hole is formed in the first dielectric layer filling the trench. A gate conductive layer is formed to fill the gate hole, a drain electrode electrically connected to the stacked structure located on the upper surface of the substrate, and a source electrode electrically connected to the stacked structure located at the bottom of the trench. The source electrode and the drain electrode are located in different planes, and the gate and drain electrodes are formed simultaneously. This simplifies the wiring process of the device electrodes, increases the arrangement area of ​​each electrode, reduces the difficulty of manufacturing the device electrodes, and improves the thermal conductivity of the device. The inner wall of the trench is tilted to increase the effective area of ​​the two-dimensional electron gas, reduce the on-resistance per unit area of ​​the device, shorten the horizontal distance between the source and drain, and thus reduce the size of the device; a gate hole is formed in the trench, and by adjusting the tilt angle of the inner wall of the gate hole, the distance between the gate conductive layer and the barrier layer is controlled, while the electric field strength of the conductive channel near the drain end on both sides of the gate conductive layer is reduced, thereby increasing the breakdown voltage of the device, suppressing the current collapse effect of the device, avoiding the need to repeatedly manufacture the gate conductive layer equivalent to the gate field plate, and simplifying the manufacturing process of the gate field plate; by forming a third dielectric layer and a conductive block located on the third dielectric layer on the inner wall of the trench and electrically connected to the gate conductive layer, the control capability of the gate can be enhanced and the performance of the device can be improved. In addition, since the source is electrically connected to the substrate, the source-drain parasitic capacitance C of the device can be effectively reduced. ds , thereby improving the switching characteristics of the device. Furthermore, the electrical connection between the source and the substrate can reduce the dynamic resistance gain of the device, further enhancing device performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0166] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a HEMT device, characterized in that: The following steps are involved: Providing a substrate, and forming a plurality of grooves spaced apart from each other on the surface of the substrate; forming a stacked structure with a preset thickness on the exposed surface of the groove and the upper surface of the substrate, wherein the stacked structure includes a buffer layer, a channel layer and a barrier layer stacked in sequence; forming a first dielectric layer filling the trench and covering the exposed surface of the stacked structure, and forming a gate hole in the trench in the first dielectric layer, wherein the bottom surface and inner wall of the gate hole are spaced a preset distance from the stacked structure; forming a gate conductive layer filling the gate hole, and forming a second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer; forming a drain contact hole and a gate contact hole penetrating the second dielectric layer, wherein the bottom of the drain contact hole at least exposes the barrier layer above the substrate between two adjacent trenches, and the bottom of the gate contact hole exposes the gate conductive layer; forming a drain electrode filling the drain contact hole, and forming a gate electrode filling the gate contact hole; A source electrode electrically connected to at least the substrate and the channel layer is formed.

2. The method for preparing a HEMT device according to claim 1, characterized in that: The angle between the inner wall of the groove and the bottom surface of the groove ranges from 90° to 150°.

3. The method for preparing a HEMT device according to claim 1, characterized in that: The stacked structure further includes a nucleation layer located at the bottom layer of the stacked structure, and the nucleation layer covers the exposed surface of the groove and the upper surface of the substrate.

4. The method for preparing a HEMT device according to claim 1, characterized in that: After forming the stacked structure and before forming the first dielectric layer, the method further includes forming a source contact hole located at the bottom of the trench and penetrating the stacked structure, wherein the source electrode fills the source contact hole.

5. The method for preparing a HEMT device according to claim 1, characterized in that: After forming the stacked structure and before forming the first dielectric layer, the method also includes the steps of forming a third dielectric layer and a conductive block, wherein the third dielectric layer covers the exposed upper surface of the stacked structure, the conductive block is located on the surface of the third dielectric layer above the inner wall of the groove, and the conductive block is exposed at the bottom of the gate hole.

6. The method for preparing a HEMT device according to claim 1, characterized in that: The gate holes located in the trenches are connected to each other.

7. The method for preparing a HEMT device according to claim 1, characterized in that: The angle between the inner wall of the gate hole and the bottom surface of the gate hole is not less than 90° and not greater than the angle between the bottom surface of the groove and the inner wall of the groove.

8. The method for preparing a HEMT device according to claim 1, characterized in that: The drain electrode also covers the upper surface of the second dielectric layer, and the gate electrode is spaced apart from the drain electrode by a preset distance.

9. The method for preparing a HEMT device according to claim 1, characterized in that: After forming the drain and the gate, the step of thinning the substrate from the bottom surface of the substrate is also included. After thinning the substrate, the bottom surface of the device at least exposes the channel layer above the bottom surface of the groove, and the source at least covers the bottom surface of the substrate and the exposed surface of the channel layer.

10. The method for preparing a HEMT device according to claim 1, characterized in that: After forming the gate and the drain, the method further includes forming a source contact hole at the bottom of the substrate, wherein the bottom of the source contact hole at least exposes the channel layer above the bottom surface of the trench, and the source at least fills the source contact hole.

11. A HEMT device, characterized in that: include: A substrate having a plurality of grooves arranged at intervals; A stacked structure, comprising a buffer layer, a channel layer and a barrier layer stacked in sequence, the stacked structure covering the exposed surface of the groove and the upper surface of the substrate; A first dielectric layer fills the groove and covers the exposed surface of the stacked structure, and a gate hole is provided in the first dielectric layer and is located in the groove, and the bottom surface and inner wall of the gate hole are spaced a preset distance from the stacked structure; A gate conductive layer filling the gate hole; A second dielectric layer covering the first dielectric layer and the exposed upper surface of the gate conductive layer; a drain contact hole and a gate contact hole, wherein the drain contact hole penetrates the second dielectric layer and the bottom at least exposes the barrier layer above the substrate between two adjacent trenches, and the gate contact hole penetrates the second dielectric layer and the bottom exposes the gate conductive layer; A drain electrode and a gate electrode, wherein the drain electrode fills the drain contact hole, and the gate electrode fills the gate contact hole; The source is electrically connected to at least the substrate and the channel layer.

12. The HEMT device according to claim 11, characterized in that: A source contact hole is also provided at the bottom of the trench. The source electrode fills the source contact hole. The source contact hole penetrates the stacked structure and the bottom surface exposes the substrate.

13. The HEMT device according to claim 12, characterized in that: It also includes a third dielectric layer and a conductive block, wherein the third dielectric layer covers the stacked structure to expose the upper surface, the conductive block covers the surface of the third dielectric layer above the inner wall of the groove, and the bottom surface of the gate hole exposes the conductive block.

14. The HEMT device according to claim 13, characterized in that: The source contact hole penetrates the third dielectric layer, and the source contact hole is spaced apart from the conductive block by a preset distance, and the source is spaced apart from the conductive block by a preset distance.

15. The HEMT device according to claim 11, characterized in that: The angle between the inner wall of the groove and the bottom surface of the groove is in the range of 90° to 150°, and the angle between the inner wall of the gate hole and the bottom surface of the gate hole is not less than 90° and not greater than the angle between the bottom surface of the groove and the inner wall of the groove.

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