Asset information reporting method and apparatus, and non-volatile readable storage medium and electronic device

Abstract

Provided in the embodiments of the present application are an asset information reporting method and apparatus, and a non-volatile readable storage medium and an electronic device. The asset information reporting method comprises: when a target device supports memory expansion, by means of a basic input output system and from a configuration space register of a memory expander controller of the target device, reading serial presence detect (SPD) information of a designated memory bank mounted to the target device, wherein the target device is a device that supports a CXL protocol, which is an open interconnection standard; and when target SPD information has been read, by means of the basic input output system, reporting the target SPD information to a central processing unit of the target device as system asset information.

Description

Asset information reporting method and device, non-volatile readable storage medium and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 27, 2023, with application number 202310767751.5, and application name “Method and device for reporting asset information, storage medium and electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and in particular, to a method and device for reporting asset information, a non-volatile readable storage medium, and an electronic device. Background Art

[0004] At present, the CXL (Computer Express Link, a new open interconnection standard) protocol can effectively solve the problems of CPU (Central Processing Unit), memory expansion and accelerator cache consistency, thereby reducing the number of times data is copied between different devices and saving memory space.

[0005] However, systems that incorporate CXL devices cannot directly use traditional I2C (Inter-Integrated Circuit, a synchronous, half-duplex communication bus) lines to read the SPD (Serial Presence Detect) area of ​​DIMMs (Dual-Inline-Memory-Modules, a type of memory stick). After the MXC (Memory Expander Controller) chip accesses the DIMM's SPD information through I2C, the BMC (Baseboard Management Controller), which is connected to the MXC chip via I2C, must first obtain the SPD information from the MXC. The BIOS (Basic Input Output System) then obtains the SPD information from the BMC through IPMI (Intelligent Platform Management Interface) commands to complete the reporting of DIMM asset information.

[0006] It can be seen that the asset information reporting method in the related art has the problem of low efficiency in reporting asset information due to out-of-band access.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a method and device for reporting asset information, a non-volatile readable storage medium, and an electronic device, so as to at least solve the problem of low efficiency of reporting asset information due to out-of-band access in the asset information reporting method in the related art.

[0009] According to a first aspect, a method for reporting asset information is provided, comprising: when a target device supports memory expansion, reading, via a basic input / output system, sequence presence detection (SPD) information of a specified memory stick attached to the target device from a configuration space register of a memory expansion controller of the target device, wherein the target device is a device supporting the open interconnection standard CXL protocol; when the target SPD information is read, reporting the target SPD information as system asset information to a central processing unit of the target device via the basic input / output system.

[0010] According to a second aspect, an asset information reporting device is provided, comprising: a first reading unit, configured to read, when the target device supports memory expansion, sequence presence detection (SPD) information of a specified memory stick attached to the target device from a configuration space register of a memory expansion controller of the target device through a basic input / output system, wherein the target device is a device supporting the open interconnection standard CXL protocol; and a reporting unit, configured to report the target SPD information as system asset information to a central processing unit of the target device through a basic input / output system when the target SPD information is read.

[0011] According to a third aspect, a computer non-volatile readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0012] According to a fourth aspect, an electronic device is further provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0013] Through the embodiments of the present application, the SPD information of the specified memory stick is stored in the configuration space register of the memory expansion controller. When the target device supports memory expansion, the sequence presence detection SPD information of the specified memory stick under the target device is read from the configuration space register of the memory expansion controller of the target device through the basic input and output system, wherein the target device is a device that supports the open interconnection standard CXL protocol; when the target SPD information is read, the target SPD information is reported to the central processing unit of the target device as system asset information through the basic input and output system. Since the information stored in the configuration space register can be directly accessed by the basic input and output system without the need to be indirectly obtained through the BMC, the purpose of obtaining asset information only through in-band access can be achieved, thereby achieving the technical effect of improving the efficiency of asset information reporting, thereby solving the problem of low efficiency of asset information reporting caused by out-of-band access in the asset information reporting method in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic diagram of a hardware environment of a method for reporting asset information according to an embodiment of the present application;

[0015] FIG2 is a flow chart of a method for reporting asset information according to an embodiment of the present application;

[0016] FIG3 is a schematic diagram of a method for reporting asset information according to an embodiment of the present application;

[0017] FIG4 is a schematic diagram of another method for reporting asset information according to an embodiment of the present application;

[0018] FIG5 is a schematic diagram of another method for reporting asset information according to an embodiment of the present application;

[0019] FIG6 is a schematic diagram of another method for reporting asset information according to an embodiment of the present application;

[0020] 7 is a flowchart of another method for reporting asset information according to an embodiment of the present application;

[0021] FIG8 is a structural block diagram of an asset information reporting device according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] It should be noted that the terms "first", "second", etc. in the description and claims of the embodiments of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 is a hardware environment diagram of a method for reporting asset information according to an embodiment of the present application. As shown in Figure 1, the computer terminal may include one or more (only one is shown in Figure 1) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 configured to store data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 configured to have a communication function. It can be understood by those skilled in the art that the structure shown in Figure 1 is only for illustration, and it does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than those shown in Figure 1, or have a configuration different from that shown in Figure 1.

[0025] The memory 104 can be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the asset information reporting method in the embodiment of the present application. The processor 102 executes the computer program stored in the memory 104 to execute various functional applications and data processing, that is, to implement the above-mentioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 includes memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0026] The transmission device 106 is configured to receive or transmit data via a network. Examples of such networks may include wireless networks provided by a computer terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0027] According to one aspect of an embodiment of the present application, a method for reporting asset information is provided. Taking the method for reporting asset information in this embodiment performed by a computer terminal as an example, FIG2 is a flow chart of the method for reporting asset information according to an embodiment of the present application. As shown in FIG2 , the flow chart includes the following steps:

[0028] Step S202 , when the target device supports memory expansion, reads the sequence presence detection (SPD) information of a specified memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, wherein the target device is a device supporting the open interconnection standard CXL protocol.

[0029] The asset information reporting method in this embodiment can be applied to the scenario of reporting the asset information of a specified memory stick in a CXL device. The CXL device can be a device that supports the CXL protocol. The CXL protocol allows consistency to be maintained between the memory of the CPU (central processing unit) and the memory on the attached device. The specified memory stick in the CXL device can be a DIMM attached to the CXL device. Correspondingly, the asset information of the specified memory stick can be the SPD information of the DIMM, including but not limited to the memory chip and module manufacturer, operating frequency, operating voltage, speed, capacity, voltage, and row and column address bandwidth and other parameters.

[0030] For standard systems that haven't implemented the CXL protocol, the DIMM asset information reporting process typically begins with system power-up. The CPU accesses the DIMMs via the PCH (integrated south bridge) through a multiplexer (MUX) and then accesses the DIMMs via I2C to obtain SPD information. When a CXL device is introduced, the attached DIMMs become visible to the system and can be brought into the system's address space. However, the path from the CPU to the CXL memory is CXL, a composite bus based on the PCIe (Peripheral Component Interconnect Express) physical layer link. Systems that implement the CXL protocol obtain DIMM asset information through an I2C connection between the BMC (Baseboard Management Controller) and the MXC (Memory Expander Controller). The MXC then accesses the DIMM SPD information via I2C. After the BMC obtains the asset information, the BIOS can retrieve the corresponding SPD information from the BMC using IPMI commands. However, although this method can obtain accurate SPD information, it requires out-of-band access, which is not direct enough for BIOS and has low efficiency in obtaining asset information.

[0031] To at least partially address the aforementioned issues, considering that the MXC and CPU are connected via CXL / PCIe, the PCIe protocol stipulates that PCIe devices can make some of their configuration information accessible to the host / CPU via a memory map. The same approach can be used to access the SPD information of the DIMMs attached to the CXL device. For example, by customizing a set of PCIe Extended Capability registers and storing SPD information in these custom registers, the BIOS can directly access the SPD information via a memory map, as shown in Figure 3, eliminating the need for out-of-band access.

[0032] Taking into account that SPD information only exists in storage devices, there is no need to read SPD information for devices that do not have memory expansion capabilities. In this embodiment, when it is determined that the target device supports memory expansion, the corresponding SPD information reading operation can be performed on the target device. The SPD information reading operation can be through the basic input and output system (i.e., BIOS), directly reading the SPD information of the specified memory bar hanging under the target device from the configuration space register of the memory expansion controller of the target device. Here, the target device can be a device that supports the open interconnection standard CXL protocol, i.e., a CXL device. The memory expansion controller and the specified memory bar can be connected via I2C. The configuration space register of the memory expansion controller can refer to the configuration space register in the memory expansion controller that is only set to store SPD information, which can be a register or a group of registers.

[0033] Step S204 : When the target SPD information is read, the target SPD information is reported as system asset information to the central processing unit of the target device via the basic input and output system.

[0034] If the read SPD information of a specified memory bank is determined to be the target SPD information of the target device, the target SPD information can be directly reported as system asset information to the central processing unit (CPU) of the target device via the basic input / output system. This reporting method can be accomplished by adding the read target SPD information to a data table structure recording system asset information, or by directly sending the target SPD information to the CPU. This embodiment does not limit this.

[0035] Through the above steps, when the target device supports memory expansion, the sequence presence detection SPD information of the specified memory bank attached to the target device is read from the configuration space register of the memory expansion controller of the target device through the basic input and output system, wherein the target device is a device that supports the open interconnection standard CXL protocol; when the target SPD information is read, the target SPD information is reported to the central processing unit of the target device as system asset information through the basic input and output system, which can solve the problem of low reporting efficiency of asset information due to out-of-band access in the reporting method of asset information in the related art, thereby achieving the technical effect of improving the reporting efficiency of asset information.

[0036] In an exemplary embodiment, when the target SPD information is read, the target SPD information is reported to the central processing unit of the target device as system asset information through the basic input and output system, including: when the target SPD information is read, the target SPD information is added to the designated data structure of the basic input and output system through the basic input and output system to report the target SPD information as the system asset information of the basic input and output system to the central processing unit of the target device, wherein the designated data structure is a data structure for reporting system asset information.

[0037] Considering that for computers that comply with the SMBIOS (System Management Basic Input / Output System) specification, system asset information can be obtained by accessing the SMBIOS structure. That is, based on a table structure method, the type structure table corresponding to the system asset information is found, and the corresponding system asset information is then obtained. Therefore, in this embodiment, the target SPD information is reported as system asset information to the CPU of the target device by adding the target SPD information to a designated data structure of the BIOS through the BIOS.

[0038] The above-mentioned designated data structure may be a data structure for reporting system asset information, such as a data table structure for recording storage devices, ie, Smbios type 17. (a data table structure in the System Management Basic Input / Output System).

[0039] Through this embodiment, by adding target SPD information to a designated data structure to complete reporting of system asset information, the simplicity of information reporting can be improved.

[0040] In an exemplary embodiment, when a target device supports memory expansion, sequence presence detection (SPD) information of a specified memory bank attached to the target device is read from a configuration space register of a memory expansion controller of the target device via a basic input / output system. This includes: when the target device supports memory expansion, accessing the configuration space register of the memory expansion controller via the basic input / output system in a memory-mapped manner to read the SPD information of the specified memory bank attached to the target device from the configuration space register of the memory expansion controller.

[0041] The memory expansion controller of the target device may have multiple configuration space registers to respectively store configuration information corresponding to the target device and SPD information of a specified memory bank of the target device. The information stored in the configuration space registers may be obtained by memory mapping.

[0042] By means of memory mapping, the configuration space register corresponding to the information to be obtained can be directly determined according to the mapping relationship between the information to be obtained and the configuration space register, and then the configuration space register can be accessed and the information to be obtained can be read from the configuration space register.

[0043] In this embodiment, the reading of SPD information can be done in the same way as the aforementioned method of reading the information to be obtained, and the configuration space register of the memory expansion controller of the target device can be accessed through the basic input and output system in a memory mapping manner to realize reading the SPD information of the specified memory bank from the configuration space register of the memory expansion controller.

[0044] According to this embodiment, the reading of SPD information is completed through internal mapping, which can improve the efficiency of information acquisition.

[0045] In an exemplary embodiment, when the target device supports memory expansion, before reading sequence presence detection (SPD) information of a specified memory bank attached to the target device from a configuration space register of a memory expansion controller of the target device via a basic input / output system, the method further includes: after the memory expansion controller is powered on, reading the SPD information of the specified memory bank attached to the target device via the memory expansion controller; and writing the read SPD information of the specified memory bank into the configuration space register of the memory expansion controller.

[0046] To avoid data delays, in this embodiment, the SPD information of a specified memory bank can be written to the configuration space register of the memory expansion controller immediately after the memory expansion controller is powered on. That is, after the memory expansion controller is powered on, the SPD information of the specified memory bank connected to the target device can be read by the memory expansion controller and written to the configuration space register of the memory expansion controller. This allows the basic input / output system to promptly access the corresponding information (including the SPD information) of the target device upon startup. The result of the write can be either successful or unsuccessful.

[0047] Since MXC can read SPD information immediately after power-on and fill it into its own configuration space registers, and BIOS needs to start reading SPD information after CPU power-on, and MXC is powered on before CPU power-on, when BIOS needs SPD information, MXC is very likely to have prepared SPD information, thereby reducing the possibility of data delay.

[0048] Through this embodiment, the memory expansion controller starts to read and write SPD information after being powered on, which can effectively reduce the possibility of data delay and improve the efficiency of the basic input and output system in obtaining SPD information.

[0049] In an exemplary embodiment, the configuration space register of the memory expansion controller is a designated vendor-specific expansion capability DVSEC register; writing the read SPD information of the designated memory bank into the configuration space register of the memory expansion controller includes: writing the read SPD information of the designated memory bank into a DVSEC register, wherein the space size of the DVSEC register is the designated space size; or, writing the sub-SPD information read from each data block of a plurality of data blocks into a DVSEC register respectively, wherein the SPD information of the designated memory bank is divided into a plurality of sub-SPD information, and each sub-SPD information of the plurality of sub-SPD information is written into a data block in each data block respectively.

[0050] The configuration space register can be a DVSEC (Designated Vendor-Specific Extended Capability) register. Writing the read SPD information of a specified memory bank to the configuration space register of the memory expansion controller can refer to writing the read SPD information into the DVSEC space. As shown in Figure 4, the first version (capability version) can be used to indicate the version of a capability (a structure). The second version (dvsec revision) is a vendor-defined version number used to indicate the version of the DVSEC structure. The DVSEC header can specify the DVSEC space size (DVSEC Length: 0x400). The DVSEC Vendor ID (DVSEC Vendor Identity Document, specifying the vendor-specific extended capability) can be configured to a fixed value corresponding to the device type. Different DVSEC spaces can be distinguished by setting different DVSEC IDs (DVSEC Identity Documents, specifying the vendor-specific extended capability). The device type here can be distinguished by whether the device has memory expansion capability, such as devices with memory expansion capability and devices without memory expansion capability.

[0051] In this embodiment, the read SPD information of a specified memory module can be written into a DVSEC register. The space size of the DVSEC register can be a specified space size, that is, the size of the SPD information of the DIMM. Taking the SPD information of a DDR5 (DDR SDRAM 5, Double Data Rate Synchronous Dynamic Random Access Memory, fifth-generation memory module) DIMM as an example, its SPD information is 1KB, and the corresponding DVSEC space size is also 1KB.

[0052] Considering that the target device may be a block device, the SPD information of the corresponding DIMM may be divided into multiple sub-SPD information, and each sub-SPD information in the multiple sub-SPD information is respectively stored in a data block in each data block. Correspondingly, the format of the SPD information can be as shown in Table 1.

[0053] Table 1

[0054] In this embodiment, when the SPD information is divided into multiple sub-SPD information, the sub-SPD information read from each of the multiple data blocks can be written into a DVSEC register. Correspondingly, a DVSEC ID can be applied for each data block, and each DVSEC register corresponds to the sub-SPD information.

[0055] According to this embodiment, the SPD information is written in different writing modes, which can improve the efficiency of writing the SPD information into the configuration space register.

[0056] In an exemplary embodiment, before writing the sub-SPD information read from each data block of a plurality of data blocks into a DVSEC register respectively, the method further includes: setting a corresponding DVSEC register for each data block according to the space size of each data block, wherein the space size of the DVSEC register corresponding to each data block is greater than or equal to the space size of each data block.

[0057] In the case where multiple data blocks store sub-SPD information respectively, in this embodiment, a corresponding DVSEC register can be set for each data block according to the space size of each data block. The space size of the set DVSEC register can be greater than or equal to the space size of the corresponding data block.

[0058] The above-mentioned data block may be the aforementioned Block, and the size of each Block may be different. Correspondingly, the space size of each DVSEC register (ie, DVSEC Length) may also be different.

[0059] Through this embodiment, the space size of the corresponding register is set according to the size of each data block, which can improve the storage utilization rate of the register.

[0060] In an exemplary embodiment, before writing the sub-SPD information read from each data block of a plurality of data blocks into a DVSEC register respectively, the method further includes: numbering each data block of the plurality of data blocks; setting a corresponding register identifier for each data block, wherein the register identifier corresponding to each data block includes: a first register identifier for identifying a register supplier of the DVSEC register corresponding to each data block, a second register identifier for identifying the DVSEC register corresponding to each data block, and a partial identifier in the second register identifier corresponding to each data block matches the number of each data block.

[0061] For the case where multiple data blocks store sub-SPD information separately, in order to improve the efficiency of filling the read sub-SPD information into the DVSEC register and avoid filling the sub-SPD information read from one data block into the DVSEC register corresponding to other data blocks, in this embodiment, each of the multiple data blocks can be numbered and a corresponding register identifier can be set for each data block according to the number.

[0062] The register identifier corresponding to each data block may include: a first register identifier (i.e., DVSEC Vendor ID) for identifying a register vendor of the DVSEC register corresponding to each data block, and a second register identifier (i.e., DVSEC ID) for identifying the DVSEC register corresponding to each data block. A portion of the identifier in the second register identifier corresponding to each data block may match the number of each data block.

[0063] For example, the DVSEC Vendor ID of the DVSEC register can be set to 1E98 according to the CXL protocol. As for the DVSEC ID of the DVSEC register, since the current CXL official regulations occupy the DVSEC IDs of 0-A (1010 (bits)), bit (4) can be used as the identification bit, that is, starting from (10000), it can correspond to the data block. Since SPD information can correspond to a total of 16 blocks, the 16 blocks can be numbered 0 to 15 as shown in Table 1. Then, the DVSEC IDs of the 16 DVSEC registers can start from (10000) and be set to (10000-11111). When the read sub-SPD information needs to be filled into a DVSEC register, the corresponding DVSEC register can be selected by using the bits in the DVSEC ID of each register that correspond to the data block identifier.

[0064] According to this embodiment, the DVSEC register storing sub-SPD information of different data blocks is distinguished by the second register identifier, so that the efficiency of filling the SPD information into the DVSEC register can be improved.

[0065] In an exemplary embodiment, after reading the SPD information of a specified memory bank attached to a target device through a memory expansion controller, the method further includes: determining a first hash value corresponding to the read SPD information of the specified memory bank; and comparing the first hash value with a second hash value corresponding to the SPD information recorded in a configuration space register of the memory expansion controller, wherein writing the read SPD information of the specified memory bank into the configuration space register of the memory expansion controller is performed when the first hash value and the second hash value are inconsistent.

[0066] In order to avoid the memory expansion controller repeatedly reading and writing the same SPD information each time it is powered on, in this embodiment, a corresponding hash value can be generated for each SPD information read and the hash value can be saved. When the memory expansion controller is powered on and reads the SPD information, the hash value of the currently read SPD information can be compared with the saved hash value. If the current hash value is different from the saved hash value, it is saved to the configuration space register.

[0067] After reading the SPD information of the specified memory bank attached to the target device through the memory expansion controller, a first hash value corresponding to the read SPD information of the specified memory bank can be determined first, and the first hash value is compared with a second hash value corresponding to the SPD information recorded in the configuration space register of the memory expansion controller. If the first hash value and the second hash value are inconsistent, the read SPD information of the specified memory bank is written into the configuration space register of the memory expansion controller.

[0068] According to this embodiment, by recording the hash value of the SPD information read each time, repeated writing of the same SPD information can be avoided.

[0069] In an exemplary embodiment, before reading, through a basic input / output system (BIOS), sequence presence detection (SPD) information of a designated memory bank attached to the target device from a configuration space register of a memory expansion controller of the target device, if the target device supports memory expansion, the method further includes: reading, through the BIOS, memory expansion indication information from a specific configuration space register of the memory expansion controller of the target device, wherein the specific configuration space register is a configuration space register that records the device type of the target device, and the memory expansion indication information is used to indicate whether the target device supports memory expansion; if the memory expansion indication information indicates that the target device supports memory expansion, determining that the target device supports memory expansion. If the memory expansion indication information indicates that the target device does not support memory expansion, determining that the target device does not have SPD information.

[0070] Considering that some devices do not support memory expansion, in this embodiment, after the system is powered on, memory expansion indication information can be read from a specific configuration space register of the target device's memory expansion controller via the basic input / output system. If the memory expansion indication information indicates that the target device supports memory expansion, it is determined that the target device supports memory expansion, and related operations such as reading and writing SPD information are performed as described in the previous embodiment.

[0071] The specific configuration space register may be a configuration space register that records the device type of the target device, or may be a configuration space register that only records the device type of the target device. The specific configuration space register may be of the same type as or different from the aforementioned configuration space register, and this embodiment does not limit this. The memory expansion indication information may be used to indicate whether the target device supports memory expansion.

[0072] When the memory expansion indication information indicates that the target device does not support memory expansion, it can be determined that the target device has no SPD information, and related operations such as reading and writing the SPD information are not performed.

[0073] Through this embodiment, the indication data in the register is read first, and then the reading and writing operations of the SPD information are performed after determining whether the device supports memory expansion. This can avoid performing a long SPD information reading operation on a device without SPD information, thereby improving the information reading efficiency.

[0074] In an exemplary embodiment, after reading, via a basic input / output system, sequence presence detection (SPD) information of a designated memory bank attached to the target device from a configuration space register of a memory expansion controller of the target device, the method further comprises: if no SPD information is read, starting a timer, wherein the timing of the timer is a preset time interval between two adjacent readings of the SPD information of the designated memory bank; and when the timing of the timer expires, rereading, via the basic input / output system, the SPD information of the designated memory bank from the configuration space register of the memory expansion controller.

[0075] Considering that after the CPU is powered on and the BIOS reads the SPD information from the configuration space registers of the memory expansion controller, there is a possibility that the memory expansion controller fails to write the read SPD information into its own configuration space registers, or there is a possibility that the read from the configuration space registers of the memory expansion controller fails. Regarding the possibility of a read failure, considering that a successful read may be possible by rereading, in this embodiment, if the basic input and output system fails to read the SPD information from the configuration space registers, the basic input and output system can be used to read the SPD information again after a period of time. The time interval between two adjacent reads can be pre-set, and the time interval can be set by a timer.

[0076] If the SPD information is not read, a timer may be started, and when the timer expires, the SPD information of the specified memory bank is re-read from the configuration space register of the memory expansion controller via the basic input and output system. Here, the timer may be a preset time interval between two consecutive reads of the SPD information of the specified memory bank.

[0077] Optionally, if the SPD information is still not read after re-reading, an error may be directly returned.

[0078] According to this embodiment, when the SPD information is not read, the time of re-reading is controlled by the timer, thereby avoiding invalid reading in a short period of time and increasing the possibility of successful reading.

[0079] In an exemplary embodiment, before reading, via a basic input / output system, sequence presence detection (SPD) information of a specified memory bank attached to the target device from a configuration space register of a memory expansion controller of the target device, the method further comprises: obtaining, from the configuration space register of the memory expansion controller, first bit information corresponding to the SPD information of the specified memory bank, wherein the first bit information is used to identify whether the SPD information stored in the configuration space register of the memory expansion controller is valid, and reading the SPD information of the specified memory bank from the configuration space register of the memory expansion controller is performed when the first bit information is used to identify that the SPD information stored in the configuration space register of the memory expansion controller is valid.

[0080] In order to prevent the read SPD information from receiving erroneous data, which in turn may result in errors in the reported system asset information, in this embodiment, a corresponding first bit can be added to the SPD information stored in the configuration space register. The first bit can be used to indicate whether the SPD information stored in the configuration space register of the memory expansion controller is valid. For example, a 1 can be used to indicate that the SPD information is valid, and a 0 can be used to indicate that the SPD information is invalid. Here, whether the SPD information is valid can indicate whether the SPD information complies with the relevant provisions of the DDR SPD protocol. That is, valid SPD information indicates that it complies with the relevant provisions of the DDR SPD protocol, and invalid SPD information indicates that it does not comply with the relevant provisions of the DDR SPD protocol.

[0081] Before reading the SPD information of a specified memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, first bit information corresponding to the SPD information of the specified memory bank can be obtained from the configuration space register of the memory expansion controller, and it can be determined whether the first bit information is valid. If the first bit information is valid, the operation of reading the SPD information of the specified memory bank from the configuration space register of the memory expansion controller is performed.

[0082] Through this embodiment, by adding the corresponding first bit information to the SPD information stored in the configuration space register, the basic input and output system can determine whether the SPD information is valid, thereby effectively avoiding reporting erroneous asset information.

[0083] In an exemplary embodiment, the memory bars are designated as a group of memory bars; the method further includes: in the event of a memory fault, obtaining fault indication information corresponding to the group of memory bars from a configuration space register of a memory expansion controller, wherein the fault indication information corresponding to the group of memory bars is used to indicate whether each memory bar in the group of memory bars has a fault; and locating the fault based on the fault indication information corresponding to the group of memory bars to locate the faulty memory bar in the group of memory bars.

[0084] In the prior art, when a memory failure occurs, only the memory expansion controller can be located. When a memory expansion controller has only one memory stick connected to it, the faulty memory stick can be accurately determined. However, if multiple memory sticks are connected to a memory expansion controller as shown in FIG5 , the faulty memory stick cannot be accurately located.

[0085] To at least partially address the above-mentioned issues, when multiple memory sticks are connected to a memory expansion controller, the above-mentioned designated memory sticks are a group of memory sticks. In this embodiment, fault indication information corresponding to each memory stick can be written into the configuration space register of the memory expansion controller.

[0086] In the event of a memory failure, fault indication information corresponding to a group of memory modules can be obtained from the configuration space registers of the memory expansion controller. The fault indication information corresponding to the group of memory modules can be used to indicate whether each memory module in the group has failed. The fault can be located based on the fault indication information to identify the failed memory module in the group.

[0087] According to this embodiment, the faulty memory module is determined based on the fault indication information in the configuration space register of the memory expansion controller, thereby improving the accuracy of memory fault location.

[0088] In an exemplary embodiment, in the event of a memory failure, fault indication information corresponding to a group of memory bars is obtained from a configuration space register of a memory expansion controller, including: in the event of a memory failure, second bit information corresponding to each memory bar in the group of memory bars is obtained from the configuration space register of the memory expansion controller, wherein the second bit information corresponding to each memory bar is used to indicate whether each memory bar has a failure.

[0089] In this embodiment, the fault indication information may be represented by bits. In the event of a memory fault, second bit information corresponding to each memory bank in a group of memory banks may be obtained from a configuration space register of the memory expansion controller.

[0090] The second bit information corresponding to each memory bank can be used to indicate whether each memory bank has a fault. For a healthy memory bank, the corresponding second bit information can be 0, while for a faulty memory bank, the corresponding second bit information can be 1.

[0091] Optionally, when multiple memory modules are connected to a single memory expansion controller, while setting the configuration space register to store the SPD information of the memory modules, a portion of the identifier in the configuration space register can be set to identifiers corresponding to different memory modules. That is, the multiple memory modules can be numbered, and a portion of the identifier in the second register identifier of the DVSEC register can be set to identifiers that can represent the numbers of the different memory modules. For example, the DVSEC ID is 16 bits in total, and the first 8 bits can be used to represent the DIMM number.

[0092] For example, when MXC detects a DIMM error, it can set the corresponding bit in the corresponding configuration space register to indicate that the corresponding DIMM has failed. After the host receives the error, it polls the MXC configuration space register. After reading the register with the corresponding bit as 1, it determines the corresponding DIMM based on the identifier of the register.

[0093] Through this embodiment, when a memory fault occurs, the faulty memory module is determined according to the second bit information in the configuration space register of the memory expansion controller, thereby improving the accuracy of fault location.

[0094] In an exemplary embodiment, the method further includes: when the memory expansion controller is connected to a group of host-side servers, storing SPD information corresponding to each host-side server in different areas of a designated memory bank.

[0095] Taking into account the situation that an MXC can be connected to different hosts as shown in Figure 6, in this embodiment, when the memory expansion controller is connected to a group of host-side servers, the SPD information corresponding to each host-side server in the group of host-side servers can be stored separately in different areas of a designated memory bar.

[0096] For example, if a memory bank is specified as a single memory bank, when an MXC is connected to different hosts, the single memory bank may be partitioned and allocated to different hosts.

[0097] Through this embodiment, SPD information corresponding to each host-side server in a group of host-side servers is respectively stored in different areas of a designated memory bank, which can improve the utilization rate of the memory expansion controller.

[0098] In an exemplary embodiment, after storing SPD information corresponding to each host-side server in a group of host-side servers in different areas of a designated memory bar, the method further includes: after the memory expansion controller is powered on, reading the SPD information of the designated memory bar attached to the target device through the memory expansion controller; updating the memory size in the read SPD information of the designated memory bar according to the size of the different areas of the designated memory bar, and writing it into the configuration space register of the memory expansion controller, wherein the memory size in the SPD information of the designated memory bar before the update is the memory size of the designated memory bar.

[0099] If an MXC only supports connecting to one host, the configuration space register design can be performed according to the aforementioned embodiment. However, if an MXC can connect to different hosts and a memory bank can be partitioned and allocated to different hosts, the configuration space register design can be optionally complex to support multiple logic devices.

[0100] In this embodiment, after the memory expansion controller is powered on, the SPD information of a specified memory bank connected to the target device can be read by the memory expansion controller. Based on the sizes of different regions of the specified memory bank, the memory size in the SPD information of the specified memory bank can be updated and written to the configuration space register of the memory expansion controller.

[0101] The memory size in the SPD information of the designated memory bank before the update may be the memory size of the designated memory bank. The update of the memory size in the read SPD information of the designated memory bank may be performed according to different areas of the designated memory bank that respectively store SPD information corresponding to each host-side server in the group of host-side servers.

[0102] For example, if different partitions of the same DIMM have different sizes, the memory size in the SPD information read by MXC is a total value. However, when reporting the SPD information, MXC can modify the memory size in the SPD information according to the conditions of each partition.

[0103] Through this embodiment, the memory expansion controller can modify the memory size of the read SPD information according to the partitioning status of the attached memory bank, and can make the reported SPD information more accurate without adding other analysis operations.

[0104] The following describes the method for reporting asset information in the embodiment of the present application with reference to an optional example. In this optional example, the target device is a CXL device.

[0105] This optional example provides an asset information reporting method based on CXL memory expansion. By defining a configuration space register for storing DIMM SPD information in the MXC, the MXC will fill the DIMM SPD information into its own configuration space register after powering on. After the CPU is powered on, the BIOS can directly obtain the corresponding SPD information from the MXC configuration space register. This implements in-band asset information reporting for the CXL memory expansion device, which will help to locate faults in future large memory pool application scenarios.

[0106] The process of the asset information reporting method in this optional example may be shown in FIG7 , and may include the following steps:

[0107] Step 1: Power on the system.

[0108] Step 2: Power on the MXC.

[0109] Step 3: MXC reads the DIMM Spd information through I2C and stores it in its own DVSEC space.

[0110] Step 4: BIOS reads the information in the register space of DVSEC Vendor ID: 1e98h.

[0111] Step 5: Based on the read information, determine whether the CXL device has memory expansion capability.

[0112] Step 6: If the CXL device supports memory expansion, read the corresponding register (eg, DVSEC Vendor ID: 30) to obtain SPD information.

[0113] Step 7: Add the read SPD information of the CXL device to Smbios type 17. and report it as a system asset information list.

[0114] This optional example solves the problem that the current CXL device asset information needs to be obtained through the BMC, so that the CXL device asset information can be reported as asset information like normal DIMM.

[0115] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the optional embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily required by this application.

[0116] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the method of each embodiment of the present application.

[0117] According to another aspect of the embodiments of the present application, there is also provided an asset information reporting device, which is configured to implement the asset information reporting method provided in the above embodiments, and will not be repeated hereafter. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0118] FIG8 is a structural block diagram of an asset information reporting device according to an embodiment of the present application. As shown in FIG8 , the device includes:

[0119] The first reading unit 802 is configured to read, when the target device supports memory expansion, sequence presence detection (SPD) information of a specified memory bank attached to the target device from a configuration space register of a memory expansion controller of the target device through a basic input / output system, wherein the target device is a device supporting the open interconnect standard CXL protocol;

[0120] The reporting unit 804 is configured to report the target SPD information as system asset information to the central processor of the target device through the basic input and output system when the target SPD information is read.

[0121] Through the embodiments of the present application, when the target device supports memory expansion, the sequence presence detection SPD information of the specified memory bank attached to the target device is read from the configuration space register of the memory expansion controller of the target device through the basic input and output system, wherein the target device is a device that supports the open interconnection standard CXL protocol; when the target SPD information is read, the target SPD information is reported to the central processor of the target device as system asset information through the basic input and output system, which can solve the problem of low reporting efficiency of asset information due to out-of-band access in the asset information reporting method in the related art, thereby improving the reporting efficiency of asset information.

[0122] Optionally, the reporting unit includes:

[0123] The adding module is configured to add the target SPD information to the specified data structure of the basic input / output system through the basic input / output system when the target SPD information is read, so as to report the target SPD information as the system asset information of the basic input / output system to the central processing unit of the target device, wherein the specified data structure is a data structure for reporting the system asset information.

[0124] Optionally, the first reading unit includes:

[0125] The access module is configured to access the configuration space register of the memory expansion controller in a memory mapping manner through the basic input and output system when the target device supports memory expansion, so as to read the SPD information of the specified memory bank attached to the target device from the configuration space register of the memory expansion controller.

[0126] Optionally, the above device further includes:

[0127] The second reading unit is configured to read the SPD information of the specified memory bank attached to the target device through the memory expansion controller after the memory expansion controller is powered on;

[0128] The writing unit is configured to write the read SPD information of the specified memory bank into the configuration space register of the memory expansion controller.

[0129] Optionally, the configuration space register of the memory expansion controller is a vendor-specific expansion capability DVSEC register; and the writing unit includes:

[0130] The first writing module is configured to write the read SPD information of the specified memory bank into a DVSEC register, wherein the space size of the DVSEC register is the specified space size.

[0131] Optionally, the configuration space register of the memory expansion controller is a vendor-specific expansion capability DVSEC register; and the writing unit includes:

[0132] The second writing module is configured to write the sub-SPD information read from each data block in the multiple data blocks into a DVSEC register respectively, wherein the SPD information of the specified memory bar is divided into multiple sub-SPD information, and each sub-SPD information in the multiple sub-SPD information is written into a data block in each data block respectively.

[0133] Optionally, the above device further includes:

[0134] The first setting unit is configured to set a corresponding DVSEC register for each data block according to the space size of each data block before writing the sub-SPD information read from each data block of the multiple data blocks into a DVSEC register respectively, wherein the space size of the DVSEC register corresponding to each data block is greater than or equal to the space size of each data block.

[0135] Optionally, the above device further includes:

[0136] an execution unit configured to number each of the plurality of data blocks before writing sub-SPD information read from each of the plurality of data blocks into a DVSEC register;

[0137] The second setting unit is configured to set a corresponding register identifier for each data block, wherein the register identifier corresponding to each data block includes: a first register identifier of a register supplier for identifying the DVSEC register corresponding to each data block, a second register identifier for identifying the DVSEC register corresponding to each data block, and a partial identifier in the second register identifier corresponding to each data block matches the number of each data block.

[0138] Optionally, the above device further includes:

[0139] The first determining unit is configured to determine a first hash value corresponding to the read SPD information of the specified memory bank attached to the target device after reading the SPD information of the specified memory bank through the memory expansion controller;

[0140] The comparing unit is configured to compare the first hash value with a second hash value corresponding to the SPD information recorded in the configuration space register of the memory expansion controller, wherein writing the read SPD information of the specified memory bank into the configuration space register of the memory expansion controller is performed when the first hash value and the second hash value are inconsistent.

[0141] Optionally, the above device further includes:

[0142] a third reading unit configured to, before reading, from a configuration space register of a memory expansion controller of the target device through a basic input / output system, sequence presence detection (SPD) information of a designated memory bank attached to the target device, read memory expansion indication information from a specific configuration space register of the memory expansion controller of the target device through a basic input / output system if the target device supports memory expansion, wherein the specific configuration space register is a configuration space register recording a device type of the target device, and the memory expansion indication information is used to indicate whether the target device supports memory expansion;

[0143] The second determining unit is configured to determine that the target device supports memory expansion when the memory expansion indication information indicates that the target device supports memory expansion.

[0144] Optionally, the above device further includes:

[0145] The third determining unit is configured to, after reading memory extension indication information from a specific configuration space register of a memory extension controller of the target device through a basic input / output system, determine that the target device has no SPD information if the memory extension indication information indicates that the target device does not support memory extension.

[0146] Optionally, the above device further includes:

[0147] The starting unit is configured to, after reading sequence presence detection (SPD) information of a designated memory bank attached to the target device from a configuration space register of a memory expansion controller of the target device through a basic input / output system, start a timer if no SPD information is read, wherein a timing time of the timer is a preset time interval between two consecutive readings of the SPD information of the designated memory bank;

[0148] The fourth reading unit is configured to read the SPD information of the designated memory bank from the configuration space register of the memory expansion controller again through the basic input and output system when the timing time of the timer is reached.

[0149] Optionally, the above device further includes:

[0150] The first acquisition unit is configured to acquire first bit information corresponding to the SPD information of the specified memory bank from the configuration space register of the memory expansion controller of the target device before reading the sequence presence detection SPD information of the specified memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, wherein the first bit information is used to identify whether the SPD information stored in the configuration space register of the memory expansion controller is valid, and the SPD information of the specified memory bank from the configuration space register of the memory expansion controller is read when the first bit information is used to identify that the SPD information stored in the configuration space register of the memory expansion controller is valid.

[0151] Optionally, the designated memory stick is a group of memory sticks; and the apparatus further includes:

[0152] a second acquiring unit configured to acquire, in the event of a memory failure, fault indication information corresponding to a group of memory bars from a configuration space register of the memory expansion controller, wherein the fault indication information corresponding to the group of memory bars is used to indicate whether each memory bar in the group of memory bars has failed;

[0153] The locating unit is configured to perform fault locating according to the fault indication information corresponding to a group of memory bars, so as to locate a faulty memory bar in the group of memory bars.

[0154] Optionally, the second acquiring unit includes:

[0155] The acquisition module is configured to obtain second bit information corresponding to each memory stick in a group of memory sticks from a configuration space register of a memory expansion controller in the event of a memory failure, wherein the second bit information corresponding to each memory stick is used to indicate whether each memory stick has failed.

[0156] Optionally, the above device further includes:

[0157] The storage unit is configured to store SPD information corresponding to each host-side server in a group of host-side servers in different areas of a designated memory bank when the memory expansion controller is connected to the group of host-side servers.

[0158] Optionally, the above device further includes:

[0159] a fifth reading unit configured to store SPD information corresponding to each host-side server in a group of host-side servers in different areas of a designated memory bank, and then, after the memory expansion controller is powered on, read the SPD information of the designated memory bank attached to the target device through the memory expansion controller;

[0160] The update unit is configured to update the memory size in the read SPD information of the specified memory bar according to the size of different areas of the specified memory bar, and write the updated memory size into the configuration space register of the memory expansion controller, wherein the memory size in the SPD information of the specified memory bar before the update is the memory size of the specified memory bar.

[0161] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0162] According to another aspect of the embodiments of the present application, a computer non-volatile readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0163] In an exemplary embodiment, the above-mentioned computer non-volatile readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0164] According to another aspect of the embodiments of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0165] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0166] For optional examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0167] Obviously, those skilled in the art should understand that the various modules or steps of the above-mentioned embodiments of the present application can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented using program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0168] The above are merely optional embodiments of the present application and are not intended to limit the embodiments of the present application. For those skilled in the art, the embodiments of the present application may be modified and varied in various ways. Any modifications, equivalent replacements, improvements, etc. made within the principles of the embodiments of the present application shall be included in the scope of protection of the embodiments of the present application.

Claims

1. A method for reporting asset information, characterized in that: include: In the case where the target device supports memory expansion, reading the sequence presence detection SPD information of the specified memory bank under the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, wherein the target device is a device supporting the open interconnection standard CXL protocol; When the target SPD information is read, the target SPD information is reported as system asset information to the central processor of the target device through the basic input and output system.

2. The method according to claim 1, characterized in that In the case where the target device supports memory expansion, reading the sequence presence detection SPD information of the specified memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system includes: In the case where the target device supports memory expansion, the configuration space register of the memory expansion controller is accessed in a memory mapping manner through the basic input and output system to read the SPD information of the specified memory bar hung under the target device from the configuration space register of the memory expansion controller.

3. The method according to claim 1, characterized in that When the target SPD information is read, reporting the target SPD information as system asset information to the central processor of the target device through the basic input and output system includes: When the target SPD information is read, the target SPD information is added to the designated data structure of the basic input / output system through the basic input / output system, so that the target SPD information is reported to the central processor of the target device as the system asset information of the basic input / output system, wherein the designated data structure is a data structure for reporting the system asset information.

4. The method according to claim 1, characterized in that: In the case where the target device supports memory expansion, before reading the sequence presence detection SPD information of the specified memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, the method further includes: After the memory expansion controller is powered on, the SPD information of the designated memory bar attached to the target device is read through the memory expansion controller; The read SPD information of the designated memory bank is written into the configuration space register of the memory expansion controller.

5. The method according to claim 4, characterized in that The configuration space register of the memory expansion controller is a DVSEC register of a specified vendor specific expansion capability; and the step of writing the read SPD information of the specified memory bar into the configuration space register of the memory expansion controller comprises: The read SPD information of the specified memory bank is written into one of the DVSEC registers, wherein the space size of the DVSEC register is the specified space size.

6. The method according to claim 4, characterized in that The configuration space register of the memory expansion controller is a DVSEC register of a specified vendor specific expansion capability; the step of writing the read SPD information of the specified memory bank into the configuration space register of the memory expansion controller further includes: The sub-SPD information read from each data block in the multiple data blocks is written into one of the DVSEC registers respectively, wherein the SPD information of the specified memory bar is divided into multiple sub-SPD information, and each sub-SPD information in the multiple sub-SPD information is stored in one data block in each of the data blocks respectively.

7. The method according to claim 6, characterized in that Before writing the sub-SPD information read from each data block of the plurality of data blocks into one of the DVSEC registers, the method further includes: According to the space size of each data block, the corresponding DVSEC register is set for each data block, wherein the space size of the DVSEC register corresponding to each data block is greater than or equal to the space size of the DVSEC register corresponding to each data block. Describes the space size of each data block.

8. The method according to claim 6, characterized in that Before writing the sub-SPD information read from each data block of the plurality of data blocks into one of the DVSEC registers, the method further includes: numbering each data block in the plurality of data blocks; A corresponding register identifier is set for each data block, wherein the register identifier corresponding to each data block includes: a first register identifier for identifying the register supplier of the DVSEC register corresponding to each data block, a second register identifier for identifying the DVSEC register corresponding to each data block, and a partial identifier in the second register identifier corresponding to each data block matches the number of each data block.

9. The method according to claim 4, characterized in that After reading the SPD information of the designated memory bank attached to the target device through the memory expansion controller, the method further includes: Determine a first hash value corresponding to the read SPD information of the specified memory bank; The first hash value is compared with a second hash value corresponding to the SPD information recorded in the configuration space register of the memory expansion controller, wherein writing the read SPD information of the specified memory bank into the configuration space register of the memory expansion controller is performed when the first hash value and the second hash value are inconsistent.

10. The method according to claim 1, characterized in that In the case where the target device supports memory expansion, before reading the sequence presence detection SPD information of the specified memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, the method further includes: Reading memory extension indication information from a specific configuration space register of a memory extension controller of the target device through the basic input and output system, wherein the specific configuration space register is a configuration space register recording a device type of the target device, and the memory extension indication information is used to indicate whether the target device supports memory extension; In a case where the memory expansion indication information indicates that the target device supports memory expansion, it is determined that the target device supports memory expansion.

11. The method according to claim 10, characterized in that After reading the memory expansion indication information from the specific configuration space register of the memory expansion controller of the target device through the basic input and output system, the method further includes: When the memory expansion indication information indicates that the target device does not support memory expansion, it is determined that the target device has no SPD information.

12. The method according to claim 1, characterized in that After reading the sequence presence detection SPD information of the designated memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, the method further includes: In the case where the SPD information is not read, starting a timer, wherein the timing time of the timer is a preset time interval between two adjacent readings of the SPD information of the designated memory bank; When the timing time of the timer is reached, the SPD information of the designated memory bank is read again from the configuration space register of the memory expansion controller through the basic input and output system.

13. The method according to claim 1, characterized in that Before reading the sequence presence detection SPD information of the designated memory bank attached to the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system, the method further includes: Acquire first bit information corresponding to the SPD information of the specified memory bank from the configuration space register of the memory expansion controller, wherein the first bit information is used to identify the configuration space register of the memory expansion controller. Whether the SPD information stored in the configuration space register of the memory expansion controller is valid, reading the SPD information of the specified memory bank from the configuration space register of the memory expansion controller is performed when the first bit information is used to identify that the SPD information stored in the configuration space register of the memory expansion controller is valid.

14. The method according to claim 1, characterized in that The specified memory bank is a group of memory banks; the method further comprises: In the event of a memory failure, obtaining failure indication information corresponding to the group of memory bars from a configuration space register of the memory expansion controller, wherein the failure indication information corresponding to the group of memory bars is used to indicate whether each memory bar in the group of memory bars fails; Fault location is performed according to the fault indication information corresponding to the group of memory bars, so as to locate the faulty memory bar in the group of memory bars.

15. The method according to claim 14, characterized in that The method of acquiring fault indication information corresponding to the group of memory bars from a configuration space register of the memory expansion controller when a memory fault occurs includes: In the event of a memory failure, second bit information corresponding to each memory bar in the group of memory bars is obtained from the configuration space register of the memory expansion controller, wherein the second bit information corresponding to each memory bar is used to indicate whether each memory bar fails.

16. The method according to claim 1, characterized in that The method further comprises: In a case where the memory expansion controller is connected to a group of host-side servers, SPD information corresponding to each host-side server in the group of host-side servers is respectively stored in different areas of one of the designated memory bars.

17. The method according to claim 16, characterized in that After respectively storing the SPD information corresponding to each host-end server in the group of host-end servers in different areas of the designated memory bank, the method further includes: After the memory expansion controller is powered on, the SPD information of the designated memory bar attached to the target device is read through the memory expansion controller; According to the size of different areas of the designated memory bar, the memory size in the SPD information of the designated memory bar is updated and written into the configuration space register of the memory expansion controller, wherein the memory size in the SPD information of the designated memory bar before the update is the memory size of the designated memory bar.

18. A device for reporting asset information, characterized in that: include: The first reading unit is configured to read the sequence presence detection SPD information of the specified memory bank under the target device from the configuration space register of the memory expansion controller of the target device through the basic input and output system when the target device supports memory expansion, wherein the target device is a device supporting the open interconnection standard CXL protocol; The reporting unit is configured to report the target SPD information as system asset information to the central processor of the target device through the basic input and output system when the target SPD information is read.

19. A computer non-volatile readable storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 17 when executed by a processor.

20. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 17 are implemented.

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