Memory fault processing method, apparatus, electronic device and readable storage medium

Abstract

The present application provides a memory fault processing method, an apparatus, an electronic device and a readable storage medium. The method comprises: determining a faulty first storage unit (S801); isolating the first storage unit (S802); performing stress testing on the first storage unit, so as to obtain a fault level of the first storage unit (S803); and, according to the fault level of the first storage unit, executing a corresponding operation on the first storage unit, wherein when the fault level of the first storage unit indicates that the first storage unit is at a first risk level, the operation executed on the first storage unit comprises releasing the first storage unit from isolation (S804). In the present application, after the faulty storage unit is isolated, the storage unit may be further subjected to stress testing so as to obtain the actual fault level of the storage unit. When the fault level of the first storage unit is the first risk level, the electronic device may release the first storage unit from isolation, and the first storage unit may be continuously used; thus, the present application can increase the number of available storage units.

Description

Memory fault processing method, device, electronic device and readable storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 26, 2023, with application number 202310763323.5 and application name “Memory Fault Handling Method, Device, Electronic Device and Readable Storage Medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of storage technology, and in particular to a memory fault processing method, device, electronic device, and readable storage medium. Background Art

[0003] Memory is a crucial component of electronic devices, used to temporarily store data processed by the processor and exchange data with external devices like hard drives. Electronic devices may include a memory controller, which manages memory and handles data exchange between the memory and the processor.

[0004] Currently, the memory controller can verify whether the data stored in the memory storage unit is correct. When the data is wrong, the memory controller can report memory fault information to the operating system through the processor, and the operating system can isolate the faulty storage unit.

[0005] As the operating time of electronic devices increases, more and more memory cells are isolated, resulting in a decrease in the number of available memory cells.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a memory fault processing method, apparatus, electronic device, and readable storage medium, which can release storage units with low fault levels and increase the number of available storage units.

[0008] On the first aspect, an embodiment of the present application provides a memory fault processing method, and the execution subject of the method can be an electronic device or a chip in the electronic device. The following description will be made using an electronic device as an example. The electronic device can detect the storage unit and determine the faulty first storage unit. In order to avoid obtaining erroneous data from the faulty first storage unit, the electronic device can isolate the first storage unit. In an embodiment of the present application, after isolating the first storage unit, the electronic device can perform a stress test on the first storage unit to obtain the fault level of the first storage unit. Because the failure mode of some faulty storage units is a reversible or recoverable failure such as a soft failure, if the electronic device keeps isolating the first storage unit, the number of available storage units will become smaller and smaller.

[0009] In an embodiment of the present application, the electronic device can perform corresponding operations on the first storage unit based on the fault level of the first storage unit. When the fault level of the first storage unit is a first risk level, the operation includes releasing the isolation of the first storage unit. Because the electronic device can release the isolation of the first storage unit, the first storage unit can continue to be used by the electronic device, thereby increasing the available storage units in the electronic device.

[0010] In one possible implementation, the failure level of the first storage unit may further include a second risk level, the first risk level being lower than the second risk level. When the failure level is the second risk level, performing the corresponding operation on the first storage unit may specifically include: releasing isolation of the first storage unit and establishing a memory pool, the memory pool being used to manage the first storage unit, the first storage unit being used to store data with an external memory backup.

[0011] In this implementation, for a second risk level higher than the first risk level, in order to prevent the first storage unit of the second risk level from continuing to evolve into a storage unit with a higher risk, the electronic device can de-isolate the first storage unit and establish a memory pool, which is used to manage the first storage unit, and the first storage unit is used to store data with external memory backup.

[0012] In this implementation, the electronic device de-isolates the first storage unit, increasing the number of available storage units in the electronic device. Furthermore, the first storage unit can store data that has an external memory backup. This allows the electronic device to retrieve the backup data from the external memory even if the first storage unit fails or reaches a higher risk level, without affecting normal data access by the electronic device.

[0013] In some embodiments, the first risk level and the second risk level may indicate that the failure mode of the first storage unit is a soft failure.

[0014] In a possible implementation, when the fault level is a third risk level, the operation is to continue isolating the first storage unit, and the second risk level is lower than the third risk level.

[0015] In this implementation, the third risk level is used to indicate that the failure level of the first storage unit is high, so the electronic device may continue to isolate the first storage unit to avoid reading erroneous data from the first storage unit.

[0016] In some embodiments, the third risk level may indicate that the failure mode of the first storage unit is a hard failure.

[0017] The following describes the stress testing process of the electronic device on the first failed storage unit:

[0018] In some embodiments, the stress test includes at least one of the following: at least one mode of read and write testing, and at least one mode of write disturb testing. Exemplarily, the stress test may include at least one mode of read and write testing. Alternatively, the stress test may include at least one mode of write disturb testing. Alternatively, the stress test includes at least one mode of read and write testing and at least one mode of write disturb testing.

[0019] In a possible implementation, there is at least one first storage unit, and the stress test may include at least one mode of read and write testing. The electronic device may perform the following steps:

[0020] Step A: writing preset data into at least one first storage unit.

[0021] Step B: reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0022] Step C: When the verification is successful, writing the complement of the preset data into the at least one first storage unit.

[0023] Step D: reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0024] Step E: When the verification is successful, return to step A to step D, repeat the process n times, and after all verifications are successful, execute step F. If any verification fails, determine that the read / write test has failed; or, if the verification fails, determine that the read / write test has failed; wherein n is an integer greater than or equal to 1;

[0025] Step F: writing preset data into the at least one first storage unit.

[0026] Step G: Reading data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0027] Step H: When the verification is successful, writing the complement of the preset data into the at least one first storage unit.

[0028] Step I: Read data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verify the data in the first storage unit.

[0029] Step J, when the verification is successful, return to execute step F-step I, repeat the execution m times and determine that the read-write test has passed after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; said m is an integer greater than or equal to 1.

[0030] In one possible implementation, there is at least one first storage unit, and the stress test may include at least one mode of write disturbance testing. The electronic device may write preset data to a storage unit near the at least one first storage unit, and record the data in the first storage unit and in adjacent rows and columns of the first storage unit. The storage unit near the first storage unit may be understood as a storage unit that is X rows and Y columns away from the first storage unit, where X and Y are both integers greater than or equal to 1.

[0031] The electronic device can read data from the first storage unit and adjacent rows and columns of the first storage unit, and verify the data in the first storage unit and adjacent rows and columns of the first storage unit. If the verification succeeds, the electronic device can determine that the write test has passed; if the verification fails, the electronic device can determine that the write test has failed.

[0032] In some embodiments, when the stress test includes a read / write test and a write disturb test, the electronic device may obtain the fault level of the first storage unit according to the following method: For example, when the first storage unit passes the read / write test and the write disturb test, the fault level is determined to be a first risk level. When the first storage unit passes the read / write test but fails the write disturb test, the fault level is determined to be a second risk level. When the first storage unit fails the read / write test and the write disturb test, the fault level is determined to be a third risk level, where the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

[0033] In some embodiments, when the first storage unit passes the read and write test and the write interference test, or when the first storage unit passes the read and write test but fails the write interference test, the fault level is determined to be the second risk level; when the first storage unit fails the read and write test and the write interference test, the fault level is determined to be the third risk level.

[0034] In one possible implementation, the electronic device can also use a preset processing algorithm based on the faulty first storage unit to predict a faulty second storage unit and isolate the second storage unit. This allows the electronic device to perform a stress test on the second storage unit to determine its fault level, and then perform corresponding operations on the second storage unit based on the fault level. The electronic device can perform a stress test on the second storage unit and perform corresponding operations on the second storage unit based on the fault level, as described above for the first storage unit.

[0035] In an embodiment of the present application, the electronic device can predict the faulty second storage unit based on the faulty first storage unit, and the electronic device can perform stress testing on the faulty first storage unit and the second storage unit, and can more completely detect the fault level of the faulty storage unit so as to accurately handle the faulty storage unit.

[0036] In a possible implementation, a method for isolating storage units by an electronic device is described herein. Taking the first storage unit as an example, the electronic device may use the preset processing algorithm to isolate the first storage unit.

[0037] In a possible implementation, after obtaining the fault level of the first storage unit and the fault level of the second storage unit, the electronic device may optimize the preset processing algorithm according to the fault level of the first storage unit and the fault level of the second storage unit.

[0038] For example, if a preset processing algorithm determines that a storage unit with a number of error reports greater than or equal to a threshold number of times within a preset time period is a faulty storage unit, if this threshold number of times is set too low, many non-faulty storage units may be isolated, and the threshold number of times in the preset processing algorithm may be inaccurate. For example, the electronic device can increase the threshold number of times to optimize the preset processing algorithm.

[0039] For example, when the preset processing algorithm is a machine learning algorithm, the electronic device can optimize the parameters in the machine learning algorithm according to the storage units with medium risk levels and low risk levels, so that the faulty storage unit can be more accurately determined based on the optimized preset processing algorithm.

[0040] In this implementation, the electronic device can also optimize the preset processing algorithm based on the fault level of the first storage unit and the fault level of the second storage unit, which can improve the accuracy of the preset processing algorithm and reduce the number of isolated storage units.

[0041] In a second aspect, an embodiment of the present application provides a memory fault handling device, comprising a module for executing the method in the first aspect.

[0042] In a possible implementation, the memory fault processing device may be an operating system in an electronic device.

[0043] In one possible implementation, the memory fault processing apparatus may include: a fault determination module, an isolation module, a memory fault processing module, and a fault level management module. In some embodiments, the fault determination module may be a central processing unit (CPU) or a memory controller in an electronic device.

[0044] The fault determination module is configured to determine the faulty first storage unit.

[0045] An isolation module is used to isolate the first storage unit.

[0046] A fault level management module is used to perform stress testing on the first storage unit to obtain the fault level of the first storage unit, and perform corresponding operations on the first storage unit according to the fault level of the first storage unit, wherein when the fault level of the first storage unit is the first risk level, the operation includes lifting the isolation of the first storage unit.

[0047] In a possible implementation, the failure level of the first storage unit further includes a second risk level, and the first risk level is lower than the second risk level.

[0048] When the fault level is the second risk level, the fault level management module is specifically used to release the isolation of the first storage unit and establish a memory pool, the memory pool is used to manage the first storage unit, and the first storage unit is used to store data with backup.

[0049] In a possible implementation, when the fault level is a third risk level, the operation is to continue isolating the first storage unit, and the second risk level is lower than the third risk level.

[0050] In a possible implementation, the stress test includes at least one of the following: at least one mode of read and write testing, and at least one mode of write disturb testing.

[0051] In a possible implementation, there is at least one first storage unit, and the stress test includes at least one mode of read and write testing. The fault level management module is specifically configured to perform the following steps:

[0052] Step A: writing preset data into at least one first storage unit.

[0053] Step B: reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0054] Step C: When the verification is successful, writing the complement of the preset data into the at least one first storage unit.

[0055] Step D: reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0056] Step E: When the verification is successful, return to execute steps A-D, repeat n times and execute step F after the verification is successful. When any verification fails, it is determined that the read-write test has failed; or, when the verification fails, it is determined that the read-write test has failed; said n is an integer greater than or equal to 1.

[0057] Step F: writing preset data into the at least one first storage unit.

[0058] Step G: Reading data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0059] Step H: When the verification is successful, writing the complement of the preset data into the at least one first storage unit.

[0060] Step I: Read data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verify the data in the first storage unit.

[0061] Step J, when the verification is successful, return to execute step F-step I, repeat the execution m times and determine that the read-write test has passed after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; said m is an integer greater than or equal to 1.

[0062] In one possible implementation, there is at least one storage unit, and the stress test includes a write disturb test. The fault level management module is specifically configured to write preset data into the at least one storage unit and record data in adjacent rows and columns of the storage unit; read data from adjacent rows and columns of the storage unit and verify the data in adjacent rows and columns of the storage unit; determine that the write test has passed if the verification succeeds, and determine that the write test has failed if the verification fails.

[0063] In one possible implementation, when the stress test includes a read-write test and a write interference test, the fault level management module is specifically used to determine that the fault level is a first risk level when the storage unit passes the read-write test and the write interference test; when the storage unit passes the read-write test but fails the write interference test, the fault level is determined to be a second risk level; when the storage unit fails the read-write test and the write interference test, the fault level is determined to be a third risk level, the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

[0064] In a possible implementation, the memory fault processing module is configured to predict a faulty second storage unit using a preset processing algorithm based on the first storage unit.

[0065] The fault level management module is further used to perform stress testing on the second storage unit to obtain the fault level of the second storage unit, and perform corresponding operations on the second storage unit according to the fault level of the second storage unit.

[0066] In a possible implementation, the isolation module is specifically configured to isolate the first storage unit by adopting the preset processing algorithm.

[0067] In a possible implementation, the fault level management module is further configured to optimize the preset processing algorithm according to the fault level of the first storage unit and the fault level of the second storage unit.

[0068] In a third aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory. The memory is configured to store computer-executable program code, the program code including instructions; when the processor executes the instructions, the instructions cause the electronic device to perform the method described in the first aspect.

[0069] In a fourth aspect, an embodiment of the present application provides an electronic device, which may be the memory fault handling device of the second aspect or the electronic device of the first aspect. The electronic device may include a unit, module, or circuit for executing the method provided in the first aspect.

[0070] In a fifth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the first aspect described above.

[0071] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enables the computer to execute the method in the first aspect above.

[0072] The beneficial effects of the possible implementation methods of the second to sixth aspects mentioned above can be referred to the beneficial effects brought about by the first aspect mentioned above, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0074] FIG2 is a flow chart of an embodiment of a method for handling a memory failure provided by an embodiment of the present application;

[0075] FIG3 is a schematic diagram of a stress test process according to an embodiment of the present application;

[0076] FIG4 is a flow chart of another embodiment of a method for handling a memory failure according to an embodiment of the present application;

[0077] FIG5 is a flow chart of another embodiment of a method for handling a memory failure according to an embodiment of the present application;

[0078] FIG6 is a flow chart of another embodiment of a method for handling a memory failure according to an embodiment of the present application;

[0079] FIG7 is a flow chart of another embodiment of a method for handling a memory failure according to an embodiment of the present application;

[0080] FIG8 is a flow chart of another embodiment of a method for handling a memory failure according to an embodiment of the present application;

[0081] FIG9 is another schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0082] Definitions of terms involved in the embodiments of this application:

[0083] Memory: A storage space within an electronic device used to temporarily store data. Memory can be used to temporarily store data processed by the processor within the electronic device, as well as data exchanged with external devices such as hard drives.

[0084] Memory cell: The smallest unit of data storage. Memory can contain multiple cells, each of which consists of a transistor and a capacitor. The capacitor can store charge, and the charge stored in the capacitor represents the binary digit 0 or 1. A digit is called a bit, and 8 bits make up a byte. Each cell has a unique address, which can be used to access the data in the corresponding cell.

[0085] In some embodiments, the storage unit may also be referred to as a memory unit, or a memory unit, etc., which is not limited in the embodiments of the present application.

[0086] Memory bank: In some embodiments, a memory bank can be understood as a logical storage library in a memory. The memory can include multiple memory banks, each of which can include storage cells arranged in a two-dimensional matrix.

[0087] Memory rows and columns: A memory bank often has multiple memory banks. The memory cells within a bank are arranged in a two-dimensional matrix. The rows and columns in the two-dimensional matrix correspond to the rows and columns in memory. In some embodiments, specifying the row and column in a memory bank uniquely identifies a memory cell.

[0088] A memory row can be understood as the row to which a memory cell belongs, and a memory column can be understood as the column to which a memory cell belongs.

[0089] Physical address: The address of the actual location occupied by a storage unit in the memory. For example, if the memory size is 2GB, the physical address range can be 0-2GB.

[0090] Logical address: This is the representation of the address of a storage unit encountered by the operating system. Currently, segmented memory management can divide memory into multiple logical segments, thereby isolating different data storage. In this case, the address of a storage unit is described in the form of "segment start address + offset address within the segment." The logical address of a storage unit can include the segment start address and the offset address within the segment.

[0091] In some embodiments, the logical address of a storage unit may be viewed as a specific description of the virtual address of the storage unit.

[0092] A virtual address is an address used by the central processing unit (CPU) to locate memory locations. Because the processor can only use physical addresses, virtual addresses must be translated into physical addresses before they can be used by the processor. This translation process is performed by the memory management unit (MMU) in the operating system (OS). For example, in a 32-bit operating system, the virtual memory space can range from 0 to 4GB.

[0093] The page table is used to store the mapping relationship between virtual addresses and physical addresses. The MMU can find the physical address mapped by the virtual address from the page table and then submit the physical address to the processor. The processor can write or read data in the corresponding storage unit based on the physical address. Among them, memory mapping is based on memory pages. Typically, the size of a memory page is 4KB. For example, the size of data that the processor can access at a time is 4KB.

[0094] It can be understood that each storage unit has a corresponding physical address, virtual address and logical address, and the physical address, virtual address and logical address of each storage unit are one-to-one corresponding.

[0095] Correctable error (CE): Usually refers to a single-bit error in the data. The memory controller can detect which bit in the data has an error through verification and achieve error correction by flipping the erroneous bit.

[0096] Uncorrectable error (UCE): This typically refers to a multi-bit error in data. For uncorrectable errors, the memory controller cannot correct them.

[0097] Soft failure: The physical structure of the memory is not damaged, but the data in the storage unit is wrong due to electromagnetic radiation, charge loss, etc., which can be restored to normal by recharging and discharging. For example, when high-energy subatomic particles pass through the storage unit in the memory, free charges are generated at the same time. These free charges will accumulate on the storage unit in a very short time interval. When the accumulated free charges exceed a certain level, the data stored in the storage unit will change, and a data error will occur. The damage to the storage unit caused by soft failure is not permanent. When the data is corrected and written back to the memory, the data error can be recovered.

[0098] Bit flip: A change in the charge stored in a memory cell causes the data read back to be the opposite of what was expected. For example, a memory cell that should store a 0 reads a 1, or a memory cell that should store a 1 reads a 0. In some embodiments, bit flips in a memory cell can be caused by electromagnetic radiation, charge loss, and other factors.

[0099] Hard failure: The physical structure of the memory is damaged and cannot be recovered even if the system is restarted or the storage unit is charged and discharged again.

[0100] Risky memory: refers to a memory unit that has failed. In some embodiments, risky memory may also be referred to as failed memory.

[0101] The electronic device in the embodiments of the present application is a device containing memory, such as a server, a storage controller, a switch, a router, a base station controller, a computing offload card, a computing accelerator card, or a terminal device. In some embodiments, the terminal device can be referred to as user equipment (UE), a terminal, etc. For example, the terminal device can be a mobile phone, a portable Android device (PAD), a personal digital assistant (PDA), a handheld device with wireless communication capabilities, a computing device, an in-vehicle device or a wearable device, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a terminal in industrial control, a terminal in a smart home, etc. The form of the electronic device in the embodiments of the present application is not specifically limited.

[0102] An electronic device may include a memory controller, a processor, and an operating system. Currently, error checking and correction (ECC) algorithms, on-die ECC algorithms, and the like are error checking and correction algorithms applicable to memory, cache, or other storage media.

[0103] Taking the memory controller running ECC as an example, when the memory controller needs to write data to the memory, the memory controller will calculate a check code based on the data to be written, and write the data and the check code of the data together into the storage unit. When the memory controller needs to read data from the storage unit, the memory controller will also read the check code in the storage unit when reading the data from the storage unit. The memory controller can use the obtained data to recalculate the check code and compare the check code read from the storage unit with the recalculated check code. If the check code read from the storage unit is consistent with the recalculated check code, it means that the data is correct and the check is successful. If the check code read from the storage unit is inconsistent with the recalculated check code, it means that the data is wrong and the check failed.

[0104] When verification fails, the memory controller attempts to correct the error using a checksum and reports the memory fault to the processor, which then reports the fault to the operating system. Depending on whether the memory controller can successfully correct the error, the fault information is classified as correctable or uncorrectable. Typically, single-bit inversions are correctable, while multiple-bit inversions are uncorrectable. Currently, hardware or software isolation can be used to handle faulty memory cells.

[0105] Taking hardware isolation as an example, the basic input and output system (BIOS) can handle faulty storage units. For example, the BIOS can count the number of times memory fault information is reported. When the number of reports of memory fault information for the same storage unit exceeds a threshold, the BIOS can issue a command to isolate the storage unit. For example, the BIOS can issue a command to isolate the memory row or memory bank to which the faulty storage unit belongs. The operation of isolating a memory bank is irreversible.

[0106] Taking software isolation as an example, the OS can count the number of times memory fault information is reported. When the number of reports of memory fault information for the same storage unit exceeds a threshold, the OS can issue a command to trigger memory page isolation, isolating the faulty memory unit from the virtual space of the corresponding fault area in the OS. In this method, the OS can only isolate the virtual space of the faulty area in the OS and cannot call the storage unit resources in memory. Furthermore, after OS-level isolation, the memory space will be reduced. Especially for large page isolation, the isolation risk is relatively high and can easily cause system downtime.

[0107] In summary, in the current memory fault handling methods, whether hardware isolation or software isolation, the faulty storage unit will be permanently isolated. Even if the isolation operation is reversible, as the operating time of the electronic device increases, more and more storage units will be isolated, resulting in a decrease in the number of available storage units and a reduction in available memory.

[0108] Given the current advancements in memory technology, memory cell diameters are shrinking. These cells are more susceptible to bit flips caused by the charge and discharge operations of surrounding cells, resulting in row hammering. This can lead to an increase in the rate of soft failures. However, soft failures do not necessarily indicate physical damage to the memory; the cells are still usable. Current hardware and software isolation permanently isolates soft-failed cells, rendering them unusable by electronic devices and reducing the number of available cells.

[0109] Accordingly, an embodiment of the present application provides a method for handling memory failures, which can perform stress testing on a faulty storage unit to determine the fault level of the faulty storage unit. Specifically, when the fault level of a storage unit is low, such as when the storage unit is a soft failure, the electronic device can de-isolate the storage unit so that the storage unit can continue to store data, thereby increasing the number of available storage units. Furthermore, in an embodiment of the present application, the electronic device can perform different operations on storage units with different fault levels, which not only increases the number of available storage units but also improves the flexibility of memory management.

[0110] Before introducing the memory failure processing method provided by the embodiment of the present application, the structure of the electronic device provided by the embodiment of the present application is first introduced:

[0111] Figure 1 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Referring to Figure 1, the electronic device may include a hardware layer and a software layer, and the software layer may include program codes running on the hardware layer.

[0112] In some embodiments, the software layer can be further divided into several layers, and the layers communicate with each other through software interfaces. For example, the software layer can include an application layer, an OS, and a BIOS. It should be understood that Figure 1 only shows the OS involved in the embodiment of the present application.

[0113] OS is a system running on the CPU. In some embodiments, OS may include but is not limited to Linux, Windows, Android or vxWorks, etc., and this embodiment of the application does not limit this.

[0114] Referring to Figure 1 , in some embodiments, the OS may include an isolation module, a memory fault handling module, and a fault level management module. In some embodiments, the OS may also include an MMU, which may store a page table to implement conversion between physical and virtual addresses of storage units. The functions of the MMU may also refer to relevant descriptions in the prior art. It should be understood that Figure 1 only illustrates the isolation module, memory fault handling module, and fault level management module involved in the embodiments of the present application.

[0115] The isolation module is used to receive memory fault information from the processor and report it to the memory fault processing module and the fault level management module.

[0116] The memory fault management module can obtain a processing decision for the faulty storage unit based on a preset processing algorithm and send the processing decision to the isolation module.

[0117] The isolation module is used to isolate the faulty storage unit based on the processing decision.

[0118] The fault level management module is used to perform stress testing on the faulty storage unit according to the memory fault information to obtain the fault level of the storage unit.

[0119] In some embodiments, after obtaining a processing decision, the memory fault management module may also send the processing decision to the fault level management module. Accordingly, the fault level management module may also be configured to perform stress testing on the faulty storage unit based on the memory fault information and the processing decision to determine the fault level of the storage unit.

[0120] The fault level management module can also be used to perform different operations on the storage unit according to the fault level of the storage unit. For details, please refer to the relevant description in the following embodiments.

[0121] It can be understood that the steps executed by the isolation module, the memory fault processing module, and the fault level management module in the following embodiments can be regarded as steps executed by the OS.

[0122] In some embodiments, the hardware layer may include a processor CPU, a memory, a BIOS chip, and a baseboard management controller (BMC).

[0123] In some embodiments, the memory may include internal memory and external memory. It should be understood that FIG1 only illustrates the processor and memory involved in the embodiments of the present application, and FIG1 illustrates that an electronic device may include at least one memory. FIG1 illustrates an electronic device including three memories as an example. In some embodiments, the memory may be a memory stick.

[0124] In some embodiments, the hardware layer may further include a memory controller. In some embodiments, the memory controller may be provided within the processor or separately from the processor, which is not limited in this embodiment of the present application. FIG1 illustrates an example of a memory controller provided within the processor.

[0125] The memory controller is used to verify the data in the storage unit and report memory fault information to the processor when the data is incorrect. It should be understood that when the memory controller is set in the processor, the steps performed by the memory controller can be regarded as steps performed by the processor. In some embodiments, the processor can verify the data in the storage unit and report memory fault information to the operating system (such as the isolation module in the operating system) when the data is incorrect.

[0126] It can be understood that the steps executed by the isolation module, the memory fault processing module, the fault level management module, and the processor in the following embodiments can be regarded as steps executed by the electronic device.

[0127] The following describes the memory fault handling method provided by the embodiments of the present application in conjunction with specific embodiments. The following embodiments may be combined with one another, and identical or similar concepts or processes may not be described in detail in some embodiments. Figure 2 illustrates the memory fault handling method provided by the embodiments of the present application, taking the interaction of internal modules in an electronic device as an example.

[0128] FIG2 is a flow chart of an embodiment of a method for handling a memory failure provided by an embodiment of the present application. Referring to FIG2 , the method for handling a memory failure provided by an embodiment of the present application may include:

[0129] S201: The processor reports memory fault information to the isolation module.

[0130] In an embodiment of the present application, the processor may use an ECC algorithm or an on-die ECC algorithm to verify data in a storage unit. When the verification fails, the processor may determine that the storage unit is faulty and report memory fault information to the isolation module. Alternatively, the memory controller may use an ECC algorithm or an on-die ECC algorithm to verify data in a storage unit. When the verification fails, the memory controller may determine that the storage unit is faulty and report memory fault information to the processor, which may report memory fault information to the isolation module.

[0131] In some embodiments, the memory fault information may include: the physical address and logical address of the failed storage unit. In some embodiments, the logical address of the storage unit may be the logical address of the cache line to which the storage unit belongs, or the logical address of the memory page to which the storage unit belongs, which is not limited in the embodiments of the present application.

[0132] S202: The isolation module sends memory fault information to the memory fault processing module.

[0133] S203: The memory fault processing module obtains a processing decision for the faulty storage unit according to the memory fault information.

[0134] A preset processing algorithm may be preset in the memory fault processing module, and the memory fault processing module may use the preset processing algorithm to process memory fault information and obtain a processing decision for the faulty storage unit.

[0135] In some embodiments, the preset processing algorithm may include determining a storage unit that reports an error a number greater than or equal to a threshold number of times within a preset time period as a faulty storage unit. In this embodiment, each time the memory fault processing module receives memory fault information, it may increment the error count of the faulty unit mentioned in the memory fault information by 1. When the number of error reports of a storage unit reaches the threshold number of times, the memory fault processing module may determine that the storage unit is a faulty storage unit.

[0136] In some embodiments, the handling decision for a failed storage unit may be to "isolate the failed storage unit."

[0137] In some embodiments, for a storage unit in use, the handling decision for a failed storage unit may be "remapping, i.e., migrating the data in the failed storage unit to a safe storage unit and isolating the failed storage unit." The safe storage unit may be a storage unit that has not failed. The physical address of the safe storage unit may be referred to as a safe physical address, and the logical address of the safe storage unit may be referred to as a safe logical address. In some embodiments, the safe physical address and the safe logical address may be referred to as safe addresses.

[0138] In some embodiments, the processing decision may also include the isolation method of the storage unit, which may include but is not limited to hardware isolation and software isolation. For example, hardware isolation may include but is not limited to: isolating the faulty storage unit, isolating the cache line to which the faulty storage unit belongs, isolating the memory page to which the faulty storage unit belongs, etc. Software isolation may include but is not limited to: page isolation, address isolation, process isolation, etc.

[0139] In some embodiments, the memory fault information may further include a fault type, which may include, but is not limited to, a page fault, a single-bit fault, a cell fault, a row fault, a column fault, a bank fault, and the like.

[0140] The preset processing algorithm may be, for example, to determine the isolation method of the processing storage unit according to the fault type. Accordingly, the processing decision may include the isolation method of the faulty storage unit.

[0141] In some embodiments, the preset processing algorithm can be a preset machine learning algorithm. The memory fault processing module can input memory fault information into the machine learning algorithm, and the machine learning algorithm can output a processing decision for the faulty storage unit. Exemplary machine learning algorithms can include, but are not limited to, decision tree algorithms, supervised machine learning algorithms, unsupervised machine learning algorithms, etc. For example, the memory fault processing module can determine the fault type of the storage unit based on a decision tree algorithm, a random forest algorithm, or a neural network algorithm, and based on the fault type, determine whether the isolation method for the storage unit is hardware isolation or software isolation.

[0142] In the embodiment of the present application, there is no limitation on the preset processing algorithm pre-set in the memory fault processing module.

[0143] S204: The memory fault processing module sends a processing decision to the isolation module.

[0144] In some embodiments, the processing decision may include: an address to be isolated and an isolation method. The address to be isolated may include, but is not limited to: the address of a failed storage unit, the address of a cache line to which the failed storage unit belongs, the address of a memory page to which the failed storage unit belongs, etc.

[0145] In some embodiments, the address to be isolated may be a physical address, a logical address, or a virtual address.

[0146] In some embodiments, the processing decision may include: an address to be isolated, an isolation method, and a secure address, wherein the secure address is used to indicate that data at the address to be isolated is to be migrated to the secure address.

[0147] S205: The isolation module isolates the faulty storage unit according to the processing decision.

[0148] In some embodiments, the isolation module can isolate the faulty storage unit based on the address to be isolated and the isolation method. Specifically, the isolation module can isolate the faulty storage unit, isolate the cache line to which the faulty storage unit belongs, or isolate the memory page to which the faulty storage unit belongs.

[0149] In some embodiments, the isolation module may further migrate the data corresponding to the address to be isolated to the safe address according to the address to be isolated and the safe address, and then isolate the faulty storage unit.

[0150] In the embodiment of the present application, the reason why the isolation module isolates the faulty storage unit first according to the processing decision is that: because the faulty storage unit is the storage unit that reports an error, and the data in the storage unit is erroneous, the isolation module isolates the faulty storage unit first in order to prevent the electronic device from accessing the risky memory, reading erroneous data, and preventing the electronic device from malfunctioning.

[0151] S206: The isolation module sends memory fault information to the fault level management module.

[0152] There is no order distinction between S206 and S202, and the two can be executed simultaneously.

[0153] S207 , the fault level management module performs stress testing on the faulty storage unit according to the memory fault information to obtain the fault level of the faulty storage unit.

[0154] The fault level management module can determine the faulty storage unit based on the memory fault information. In the embodiment of the present application, the fault level management module can perform stress testing on the faulty storage unit to obtain the fault mode and fault level of the faulty storage unit. Stress testing can be understood as stress testing.

[0155] In some embodiments, to avoid affecting the normal execution of services in the electronic device, the fault level management module can perform stress testing on the faulty storage unit when the electronic device is idle. Idleness of the electronic device can be understood as: CPU utilization is lower than a preset utilization rate, or when the user is not using the electronic device in the early morning.

[0156] In some embodiments, the stress test on the failed memory cell may include a read / write test or a write disturb test.

[0157] Exemplarily, when the stress test includes a read and write test, the fault level management module may send a write instruction to the processor, and the write instruction is used to instruct the processor to write preset data in the faulty storage unit. After the processor writes the preset data in the faulty storage unit, the fault level management module may send a read instruction to the processor, and the read instruction is used to instruct the processor to read the preset data in the faulty storage unit and verify whether the data in the faulty storage unit is correct. When the data in the faulty storage unit is correct, such as the preset data, it can be determined that the verification of the faulty storage unit is successful, and the faulty storage unit can be a low-risk level fault. When the data in the faulty storage unit is wrong, such as not the preset data, it can be determined that the verification of the faulty storage unit fails, and the faulty storage unit can be a high-risk level fault.

[0158] In some embodiments, high-risk level faults may include hard failures, and low-risk level faults may include soft failures. In the embodiments of the present application, there is no limitation on which failure modes high-risk level faults and low-risk level faults specifically include.

[0159] In some embodiments, the read / write test may include at least one mode of read / write testing. Exemplarily, the at least one mode of read / write testing includes: a first read / write test; and a second read / write test. The present embodiment of the application does not elaborate on the process of the fault level management module and the processor interacting to complete the first read / write test and the second read / write test. For details, please refer to the above description of the read / write test.

[0160] Among them, when the faulty storage unit passes the first read-write test and the second read-write test, it can be determined that the faulty storage unit may be a low-risk level fault; when the faulty storage unit passes the first read-write test but fails the second read-write test, it can be determined that the faulty storage unit may be a medium-risk level fault; when the faulty storage unit fails the first read-write test and the second read-write test, it can be determined that the faulty storage unit may be a high-risk level fault.

[0161] Exemplarily, when the stress test includes a write disturb test, the fault level management module may issue a write instruction to the processor, the write instruction instructing the processor to write preset data near the faulty storage cell. In some embodiments, the vicinity of the faulty storage cell may be, for example, a storage cell located X rows and Y columns away from the faulty storage cell, where X and Y are both integers greater than or equal to 1. Before the processor writes the preset data to the faulty storage cell, the processor may record the data in the faulty storage cell and the storage cells in its adjacent rows and columns. After the processor has written the preset data near the faulty storage cell at least once, the fault level management module may issue a read instruction to the processor, the read instruction instructing the processor to read data from the faulty storage cell and the storage cells in its adjacent rows and columns. If the data read from the faulty storage cell and the storage cells in its adjacent rows and columns is correct, the faulty storage cell may be determined to have a low-risk level fault. If the data read from the faulty storage cell and the storage cells in its adjacent rows and columns is incorrect, the faulty storage cell may be determined to have a high-risk level fault.

[0162] In some embodiments, the write disturb test may include at least one mode of write disturb testing. Exemplarily, the at least one mode of write disturb testing includes: a first write disturb test and a second write disturb test. The present embodiment of the application does not elaborate on the process of the fault level management module and the processor interacting to complete the first write disturb test and the second write disturb test. For details, please refer to the above description of the write disturb test.

[0163] Among them, when the faulty storage unit passes the first write disturbance test and the second write disturbance test, it can be determined that the faulty storage unit may be a low-risk level fault; when the faulty storage unit passes the first write disturbance test but fails the second write disturbance test, it can be determined that the faulty storage unit may be a medium-risk level fault; when the faulty storage unit fails the first write disturbance test and the second write disturbance test, it can be determined that the faulty storage unit may be a high-risk level fault.

[0164] In some embodiments, stress testing of a faulty storage unit may include: a read / write test and a write disturb test. In some embodiments, stress testing may include at least one mode of read / write testing and at least one mode of write disturb testing. The following example illustrates stress testing including multiple read / write tests and one write disturb test. The embodiments of the present application do not limit the stress testing method for a faulty storage unit.

[0165] In some embodiments, there may be at least one faulty storage unit, and the fault level management module may perform stress testing on each faulty storage unit in turn, or perform stress testing on at least one faulty storage unit at the same time. In order to improve the stress testing efficiency, in an embodiment of the present application, stress testing may be performed on at least one faulty storage unit at the same time.

[0166] For example, referring to FIG3 , the stress testing process provided in the embodiment of the present application may include:

[0167] S301: The fault level management module sends a first write instruction to the processor, where the first write instruction is used to instruct the processor to write preset data into a faulty storage unit.

[0168] The preset data may be all 0s or all 1s, or data arranged in a preset pattern. The preset pattern may be alternating 0s and 1s, or alternating M 0s and N 1s, which are not limited in this embodiment of the present application. It should be understood that both M and N are integers greater than or equal to 1.

[0169] S302: The processor writes preset data into the failed storage unit.

[0170] S303: The fault level management module sends a first read instruction to the processor, where the first read instruction is used to instruct the processor to read data from the faulty storage unit in order from low address to high address.

[0171] The address can be the physical address, logical address, or virtual address of the storage unit. The physical address is obtained by sorting the actual location of the storage unit in the memory. The logical address and virtual address are obtained by mapping the physical address. Therefore, the addresses of the storage units are sorted. For example, taking the physical address as an example, if the physical address of the memory is 0-2GB, the address increases from 0 to 2GB. 0 is a lower address than 1GB, and 1GB is a lower address than 2GB.

[0172] At step S304, the processor reads preset data from the faulty storage unit in order from low address to high address, and verifies the data in the faulty storage unit. If the verification succeeds, step S305 is executed; if the verification fails, step S319 is executed.

[0173] The embodiment of the present application does not elaborate on the process of the processor verifying the data in the faulty storage unit, and reference may be made to the relevant description in the above embodiment.

[0174] S305: The processor feeds back a message indicating that the verification is successful to the fault level management module.

[0175] S306 , the fault level management module sends a second write instruction downward, where the second write instruction is used to instruct the processor to write a complementary set of preset data into the faulty storage unit.

[0176] The complement of a data set can be understood as data that is the opposite of the default data. For example, if the default data is all 1s, the complement of the default data is all 0s. If the default data is alternating between 0s and 1s, the complement of the default data is alternating between 1s and 0s. For example, if the default data is alternating between M 0s and N 1s, the complement of the default data is alternating between M 1s and N 0s.

[0177] S307: The processor writes the complement of the preset data into the failed storage unit.

[0178] S308 , the fault level management module sends a second read instruction to the processor, where the second read instruction is used to instruct the processor to read data from the faulty storage unit in sequence from low address to high address.

[0179] At step S309, the processor reads the preset data from the faulty storage unit in order from the lowest address to the highest address, and verifies the data in the faulty storage unit. If the verification is successful, the processor returns to executing steps S301-S309. This is repeated n times, and if all verifications are successful, the processor executes step S310. If any verification fails, the processor executes step S319. If the verification fails, the processor executes step S319 again.

[0180] Here, n is an integer greater than or equal to 1.

[0181] S310: The fault level management module sends a third write instruction to the processor, where the third write instruction is used to instruct the processor to write preset data into the faulty storage unit.

[0182] S311: The processor writes preset data into the failed storage unit.

[0183] S312, the fault level management module sends a third read instruction to the processor, where the third read instruction is used to instruct the processor to read data from the faulty storage unit in sequence from high address to low address.

[0184] At step S313, the processor reads preset data from the faulty storage unit in order from high address to low address, and verifies the data in the faulty storage unit. If the verification succeeds, the processor executes step S314; if the verification fails, the processor executes step S319.

[0185] S314: The processor feeds back a message indicating that the verification is successful to the fault level management module.

[0186] S315 , the fault level management module sends a fourth write instruction downward, where the fourth write instruction is used to instruct the processor to write a complementary set of preset data into the faulty storage unit.

[0187] S316: The processor writes the complement of the preset data into the failed storage unit.

[0188] S317, the fault level management module sends a fourth read instruction to the processor, where the fourth read instruction is used to instruct the processor to read data from the faulty storage unit in sequence from high address to low address.

[0189] At step S318, the processor reads the preset data from the faulty storage unit in order from high address to low address, and verifies the data in the faulty storage unit. If the verification is successful, the processor returns to executing steps S310-S317. This is repeated m times, and if all verifications are successful, the read / write test is determined to be successful. If any verification fails, the processor executes step S319. If the verification fails, the processor executes step S319.

[0190] Wherein, m is an integer greater than or equal to 1, and m and n may be the same or different.

[0191] S319: The processor feeds back a verification failure message to the fault level management module.

[0192] S301-S319 can be regarded as a read and write test. Among them, S301-S304 can be regarded as a read and write test of a mode, S306-S309 can be regarded as a read and write test of a mode, S310-S313 can be regarded as a read and write test of a mode, and S315-S318 can be regarded as a read and write test of a mode.

[0193] In the embodiment of the present application, when the storage unit passes the read / write test in all modes, it can be determined that the storage unit has passed the read / write test. When the storage unit fails the read / write test in any mode or fails any verification, it can be determined that the storage unit has failed the read / write test.

[0194] S320: The fault level management module sends a fifth write instruction to the processor, where the fifth write instruction is used to instruct the processor to write preset data into a storage unit adjacent to the faulty storage unit.

[0195] S321: The processor writes preset data into storage cells adjacent to the failed storage cell, and records the data in the failed storage cell, as well as the data in adjacent rows and adjacent columns of the failed storage cell.

[0196] In some embodiments, the processor may record data in x adjacent rows and y adjacent columns of the failed storage unit, where x and y are both integers greater than or equal to 1, and x and y may be the same or different.

[0197] S322, the fault level management module sends a fifth read instruction to the processor, where the fifth read instruction is used to instruct the processor to read data in the faulty storage unit, and read data in adjacent rows and adjacent columns of the faulty storage unit.

[0198] At step S323, the processor reads data from the failed storage cell and data in adjacent rows and columns of the failed storage cell, and verifies the data in the failed storage cell and data in adjacent rows and columns of the failed storage cell. If the verification succeeds, the processor executes step S324; if the verification fails, the processor executes step S319.

[0199] S324: The processor feeds back a message indicating that the verification is successful to the fault level management module.

[0200] S320-S323 can be regarded as a write disturbance test. In S323, when the verification succeeds, it can be determined that the storage unit has passed the write disturbance test. When the verification fails, it can be determined that the storage unit has not passed the write disturbance test.

[0201] It should be understood that the present application does not limit the order of the read / write test and the write disturb test, nor the number of times the read / write test and the write disturb test are performed. FIG3 is an example. In one embodiment, some of the steps shown in FIG3 are optional steps, and the steps can be combined with each other.

[0202] In some embodiments, when the faulty storage unit passes the read and write test, as well as the write interference test, the fault level management module can determine that the fault level is a low risk level; when the faulty storage unit passes the read and write test but fails the write interference test, the fault level management module can determine that the fault level is a medium risk level; when the faulty storage unit fails the read and write test and the write interference test, the fault level management module can determine that the fault level is a high risk level.

[0203] In some embodiments, in scenarios with high reliability requirements, when a faulty storage unit passes both the read / write test and the write disturb test, or when the faulty storage unit passes both the read / write test but fails the write disturb test, the fault level management module may determine the fault level to be a medium risk level. When the faulty storage unit fails both the read / write test and the write disturb test, the fault level management module may determine the fault level to be a high risk level.

[0204] In an embodiment of the present application, the fault level management module can adaptively adjust the method for determining the fault level of a faulty storage unit based on specific application scenarios and stress testing results. In some embodiments, the fault level management module can store a mapping relationship between application scenarios and methods for determining the fault level of a faulty storage unit. When determining the fault level of a faulty storage unit based on stress testing results, the fault level management module can use the method for determining the fault level of a faulty storage unit corresponding to the application scenario to determine the fault level of the storage unit.

[0205] S208: The fault level management module performs corresponding operations on the storage unit according to the fault level of the faulty storage unit.

[0206] In some embodiments, the failure of a storage unit with a high risk level can be regarded as a hard failure, and the failure of a storage unit with a medium risk or low risk level can be regarded as a soft failure. In the embodiments of the present application, different processing methods are used for storage units with different failure levels.

[0207] In some embodiments, high-risk storage units may continue to be prohibited from use, such as by continuing to isolate them. In some embodiments, for high-risk storage units, the fault level management module may report the high-risk storage units to the memory fault processing module, which may then write the fault into a log or report it to a backend management page for operation and maintenance alerts.

[0208] To prevent medium-risk storage units from evolving into high-risk storage units, their use can be restricted. For example, the failure level management module can establish a separate memory pool to manage these storage units. These storage units are used to store data that is not sensitive to hardware failures. For example, these storage units can store files, documents, and other data that has an external storage backup. This allows the electronic device to access the corresponding data from the backup even if the storage unit fails.

[0209] For storage units with low risk levels, normal use can be restored. For example, the fault level management module can send a release isolation request to the isolation module to request the isolation module to release the isolation of the storage unit so that the storage unit can continue to store data.

[0210] In some embodiments, medium- and low-risk storage units are still usable and do not present any physical structural irreversibility issues. It may be that the pre-set processing algorithm in the memory fault handling module is inaccurate. In this embodiment, the fault level management module can provide feedback to the memory fault handling module regarding medium- and low-risk storage units so that the memory fault handling module can optimize the pre-set processing algorithm.

[0211] For example, if a preset processing algorithm determines that a storage unit with a number of error reports greater than or equal to a threshold within a preset time period is a faulty storage unit, if this threshold is set too low, many non-faulty storage units may be isolated, making the threshold in the preset processing algorithm inaccurate. For example, the memory fault processing module can increase the threshold to optimize the preset processing algorithm.

[0212] For example, when the preset processing algorithm is a machine learning algorithm, the memory fault processing module can optimize the parameters in the machine learning algorithm according to the storage units with medium risk level and low risk level, so that the faulty storage unit can be more accurately determined based on the optimized preset processing algorithm.

[0213] In some embodiments, a low risk level may be used as the first risk level, a medium risk level may be used as the second risk level, and a high risk level may be used as the third risk level, wherein the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

[0214] In some embodiments, low risk level and medium risk level may be used as the first risk level, and high risk level may be used as the second risk level.

[0215] In some embodiments, the fault levels may be further divided into fewer or more levels, which is not limited in this embodiment of the present application.

[0216] FIG4 exemplarily shows a process in which the fault level management module performs stress testing on a faulty storage unit and performs corresponding operations on the storage unit according to the stress testing result. For details, please refer to the description in S207 - S208 .

[0217] In an embodiment of the present application, the faulty storage unit can be isolated first based on the memory fault information reported by the processor to avoid access to erroneous data in the storage unit. In addition, the operating system can further perform stress testing on the faulty storage unit to obtain the fault level of the faulty storage unit, and the operating system can perform different operations for storage units with different fault levels. For example, for medium-risk and low-risk storage units, the failure is due to soft failure, and the operating system can de-isolate these storage units, and these storage units can continue to store data, which can increase the available storage units in the electronic device. However, in order to avoid the evolution of medium-risk storage units to high-risk, medium-risk storage units can be used to store insensitive data. In an embodiment of the present application, different operations can be performed for faulty storage units with different fault levels, which can not only increase the available storage units but also improve the flexibility of memory management.

[0218] In some embodiments, referring to FIG. 5 , after S205 , S205A may be further executed:

[0219] S205A: The isolation module detects whether the faulty storage unit is successfully isolated. If so, the process continues with S207-S208. If not, the process uses the native fault tolerance mechanism.

[0220] In some embodiments, whether the faulty storage unit is successfully isolated can be tested based on whether the faulty storage unit can still be accessed. It should be noted that when the faulty storage unit is successfully isolated, the fault level management module can continue to perform stress testing on the faulty storage unit. When the faulty storage unit fails to be isolated, a native fault tolerance mechanism can be used to avoid accessing erroneous data in the storage unit.

[0221] In some embodiments, the native fault-tolerance mechanism may be: re-isolating the failed storage unit until isolation is successful, or killing the process using the storage unit and then isolating the storage unit. The embodiments of the present application do not elaborate on the native fault-tolerance mechanism, and reference may be made to the fault-tolerance mechanism of isolating storage units in current operating systems.

[0222] In the embodiment of the present application, it is also possible to detect whether the faulty storage unit is successfully isolated, thereby improving the isolation accuracy and avoiding access to erroneous data.

[0223] In some embodiments, the memory fault processing module can not only obtain the processing decision of the faulty storage unit based on the preset processing algorithm pre-installed therein, but also predict the storage unit that has not currently reported memory fault information but may have a fault based on the memory fault information. In this way, the operating system can isolate the predicted storage unit in advance to avoid accessing erroneous data in these storage units, thereby improving the isolation accuracy.

[0224] In some embodiments, the handling decision for a failed storage unit may further include: a predicted address of the failed storage unit, an isolation method, and a safe address.

[0225] 6 , the memory fault handling method provided in the embodiment of the present application may include:

[0226] S601: The processor reports memory fault information to the isolation module.

[0227] S602: The isolation module sends memory fault information to the memory fault processing module.

[0228] S603: The isolation module sends memory fault information to the fault level management module.

[0229] There is no order distinction between S602 and S603, and the two can be executed simultaneously.

[0230] S604: The memory fault processing module obtains a processing decision for the faulty storage unit according to the memory fault information.

[0231] In some embodiments, the processing decision for a faulty storage unit may include: the address, isolation method, and safety address of the faulty storage unit indicated by the memory fault information, and the address, isolation method, and safety address of the faulty storage unit predicted based on the memory fault information. The faulty storage unit indicated by the memory fault information may be understood as the faulty storage unit included in the memory fault information, and the faulty storage unit predicted based on the memory fault information may be understood as the faulty storage unit predicted based on the memory fault information using a preset processing algorithm.

[0232] In some embodiments, a faulty storage unit indicated by the memory fault information may be referred to as a first storage unit, and a faulty storage unit predicted based on the memory fault information may be referred to as a second storage unit.

[0233] S605: The memory fault processing module sends a processing decision to the isolation module.

[0234] S606: The isolation module isolates the faulty storage unit according to the processing decision.

[0235] S607: The memory fault processing module sends a processing decision to the fault level management module.

[0236] There is no order distinction between S605 and S607, and they can be executed simultaneously.

[0237] Among them, S601-S606 can refer to the description in S201-S206.

[0238] S608 , the fault level management module performs stress testing on the faulty storage unit according to the memory fault information and the processing decision, and obtains the fault level of the faulty storage unit.

[0239] Different from S207, because the memory fault processing module in the embodiment of the present application can predict the faulty storage unit based on a preset processing algorithm, in S608, the fault level management module not only needs to perform stress testing on the faulty storage unit indicated by the memory fault information, but also needs to perform stress testing on the predicted faulty storage unit. The specific stress testing method can be referred to the description in S207.

[0240] S609: The fault level management module performs corresponding operations on the storage unit according to the fault level of the faulty storage unit.

[0241] S609 may refer to the description in S208.

[0242] FIG7 is a schematic diagram of a process flow for processing memory fault information provided by an embodiment of the present application. Referring to FIG7 , the memory fault processing method provided by an embodiment of the present application may include:

[0243] Step 1: Report memory fault information.

[0244] Reporting of memory fault information may include: the processor reporting the memory fault information to the operating system (such as an isolation module in the operating system), and the isolation module reporting the memory fault information to the memory fault processing module and the fault level management module.

[0245] Step 2: Remap the faulty memory.

[0246] In an embodiment of the present application, the memory fault processing module can obtain a processing decision for the faulty storage unit based on the memory fault information. In some embodiments, the processing decision can include: the address and safety address of the faulty storage unit indicated by the memory fault information, and the address and safety address of the faulty storage unit predicted based on the memory fault information. For example, referring to FIG. 7 , the CE address and UCE address can be considered as the address of the faulty storage unit indicated by the memory fault information, and the predicted address can be considered as the address of the faulty storage unit predicted based on the memory fault information.

[0247] Step 3: Stress testing.

[0248] For stress testing, refer to the description in S207.

[0249] Step 4: Process the faulty storage unit according to the fault level.

[0250] For example, the isolation of high-risk storage units can continue, while the isolation of medium-risk and low-risk storage units can be lifted. The medium-risk storage units can be restricted in use, while the low-risk storage units can resume normal use.

[0251] Step 5: Information feedback.

[0252] Exemplarily, the information feedback may include: the fault level management module feeding back high-risk storage units to the memory fault processing module so that the memory fault processing module can perform operations and maintenance alerts. Exemplarily, the information feedback may include: the fault level management module feeding back medium-risk and low-risk storage units to the memory fault processing module so that the memory fault processing module can optimize a preset processing algorithm. The information feedback method can be referred to the description in S208.

[0253] In an embodiment of the present application, when the memory fault processing module can predict the faulty storage unit based on the memory fault information, the fault level management module can also perform stress testing on the faulty storage unit based on the processing decision and the memory fault information, and can more completely detect the fault level of the faulty storage unit so as to accurately process the faulty storage unit.

[0254] Taking the electronic device as the execution subject, in some embodiments, referring to FIG8 , the memory failure processing method provided in the embodiment of the present application may include:

[0255] S801, determine a faulty first storage unit.

[0256] In the embodiment of the present application, a processor or a memory controller in the electronic device can detect the memory to determine the faulty first storage unit.

[0257] S802, isolate the first storage unit.

[0258] In some embodiments, the electronic device may adopt a preset processing algorithm to obtain a processing decision of the first storage unit based on memory fault information, and then isolate the first storage unit based on the processing decision. For details, please refer to the description in S203-S205.

[0259] S803: Perform stress testing on the first storage unit to obtain a fault level of the first storage unit.

[0260] S803 may refer to the description in S207.

[0261] S804 , performing a corresponding operation on the first storage unit according to the fault level of the first storage unit, wherein when the fault level of the first storage unit is a first risk level, performing the operation on the first storage unit includes releasing isolation of the first storage unit.

[0262] In some embodiments, the first risk level may include a low risk level. In some embodiments, the first risk level may include a low risk level and a medium risk level.

[0263] In some embodiments, the first risk level may be used to indicate that the failure mode of the memory cell is a soft failure.

[0264] S804 may refer to the description in S208.

[0265] The principles and technical effects of the memory fault handling method provided in the embodiment of the present application are the same as those in the above embodiment. Please refer to the description in the above embodiment and will not be repeated here.

[0266] It should be noted that the data involved in this application (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0267] In one embodiment, the present application also provides an electronic device. Referring to FIG9 , the electronic device may include: a processor 901 (e.g., a CPU) and a memory 902. The memory 902 may include a high-speed random-access memory (RAM) and may also include a non-volatile memory (NVM), such as at least one disk storage. The memory 902 may store various instructions for performing various processing functions and implementing the method steps of the present application.

[0268] Optionally, the electronic device involved in this application may further include: a power supply 903, a communication bus 904, and a communication port 905. The communication port 905 is used to enable communication between the electronic device and other peripheral devices. In the embodiment of the present application, the memory 902 is used to store computer-executable program code, which includes instructions; when the processor 901 executes the instructions, the instructions cause the processor 901 of the electronic device to perform the actions in the above-mentioned method embodiment. The implementation principles and technical effects are similar and will not be repeated here.

[0269] It should be noted that the modules or components described in the above embodiments may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), one or more microprocessors (digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by scheduling program code through a processing element, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code, such as a controller. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0270] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0271] The term "plurality" in this article refers to two or more. The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship; in the formula, the character " / " indicates that the previous and next associated objects are in a "division" relationship. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0272] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0273] It can be understood that in the embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Claims

1. A memory fault processing method, characterized in that: Applied to electronic equipment, the method comprises: determining a failed first storage unit; isolating the first storage unit; Performing a stress test on the first storage unit to obtain a fault level of the first storage unit; According to the fault level of the first storage unit, a corresponding operation is performed on the first storage unit, wherein when the fault level of the first storage unit is a first risk level, the operation includes releasing the isolation of the first storage unit.

2. The method according to claim 1, characterized in that The failure level of the first storage unit further includes a second risk level, the first risk level being lower than the second risk level; When the fault level is the second risk level, performing a corresponding operation on the first storage unit includes: The first storage unit is de-isolated, and a memory pool is established, wherein the memory pool is used to manage the first storage unit, and the first storage unit is used to store data with an external memory backup.

3. The method according to claim 2, characterized in that When the fault level is a third risk level, the operation is to continue isolating the first storage unit, and the second risk level is lower than the third risk level.

4. The method according to any one of claims 1 to 3, characterized in that The stress test includes at least one of the following: at least one mode of read and write test, and at least one mode of write disturbance test.

5. The method according to claim 4, characterized in that There is at least one first storage unit, and the stress test includes at least one mode of read and write test; and the stress test on the first storage unit includes: Step A, writing preset data into at least one first storage unit; Step B, reading data from the at least one first storage unit in order from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step C, when the verification is successful, writing the complement of the preset data into the at least one first storage unit; Step D, reading data from the at least one first storage unit in order from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step E, when the verification is successful, return to execute step A-step D, repeat the execution n times and execute step F after all the verifications are successful, and determine that the read-write test has not passed when any verification fails; or, when the verification fails, determine that the read-write test has not passed; wherein n is an integer greater than or equal to 1; Step F, writing preset data into the at least one first storage unit; Step G, reading data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step H, when the verification is successful, writing the complement of the preset data into the at least one first storage unit; Step I, reading data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step J, when the verification is successful, return to execute step F-step I, repeat the execution m times and determine that the read-write test has passed after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; m is an integer greater than or equal to 1.

6. The method according to claim 4 or 5, characterized in that: There is at least one first storage unit, and the stress test includes a write disturbance test; and the stress test on the first storage unit includes: Writing preset data into a storage unit near the at least one first storage unit, and recording the data in the first storage unit, and in adjacent rows and columns of the first storage unit; Reading data from the first storage unit, and adjacent rows and adjacent columns of the first storage unit, and verifying the data in the first storage unit, and adjacent rows and adjacent columns of the first storage unit; When the verification succeeds, it is determined that the write test has passed, and when the verification fails, it is determined that the write test has not passed.

7. The method according to claim 6, characterized in that When the stress test includes a read / write test and a write disturb test, obtaining the failure level of the first storage unit includes: When the first storage unit passes the read / write test and the write disturb test, determining the fault level to be a first risk level; When the first storage unit passes the read-write test but fails the write disturb test, determining the fault level to be a second risk level; When the first storage unit fails the read / write test and the write disturb test, the fault level is determined to be a third risk level, the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: According to the first storage unit, a preset processing algorithm is used to predict a faulty second storage unit; isolating the second storage unit; Performing a stress test on the second storage unit to obtain a fault level of the second storage unit; According to the fault level of the second storage unit, a corresponding operation is performed on the second storage unit.

9. The method according to claim 8, characterized in that The isolating the first storage unit comprises: The preset processing algorithm is used to isolate the first storage unit.

10. The method according to claim 9, characterized in that The method further comprises: The preset processing algorithm is optimized according to the fault level of the first storage unit and the fault level of the second storage unit.

11. A memory failure device, characterized in that: include: Module for performing the method according to any one of claims 1-10.

12. The memory failure device according to claim 11, characterized in that: The memory failure device is an operating system in an electronic device.

13. An electronic device, characterized in that: include: Processor and memory; The memory stores computer instructions; The processor executes the computer instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 10.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program or instruction, and when the computer program or instruction is executed, the method according to any one of claims 1 to 10 is implemented.

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