Light-emitting substrate and display apparatus

Abstract

A light-emitting substrate (110) and a display apparatus (1000). The light-emitting substrate (110) comprises a substrate (10), a plurality of signal line groups (30), a plurality of columns of element groups (40), and a plurality of columns of control chips (50), wherein the plurality of signal line groups (30) are disposed on the substrate (10) and are arranged in a first direction (X); each signal line group (30) comprises a plurality of signal lines which are arranged in the first direction (X); the plurality of columns of element groups (40) are arranged in the first direction (X), each column of element groups (40) comprises a plurality of element groups (40) that are arranged to be spaced apart from each other in a second direction (Y), one column of element groups (40) is electrically connected to some signal lines in one signal line group (30), and each element group (40) comprises a plurality of light-emitting elements (41) that are arranged to be spaced apart from each other in the first direction (X) and are electrically connected in sequence; the plurality of columns of control chips (50) are arranged in the first direction (X), and each column of control chips (50) comprises a plurality of control chips (50) that are arranged to be spaced apart from each other in the second direction (Y); and one column of control chips (50) is disposed on the side of one column of element groups (40) in the first direction (X), and is electrically connected to one column of element groups (40) and some signal lines in one signal line group (30).

Description

Light-emitting substrate and display device

[0001] This application claims priority to Chinese patent application No. 202310798947.0, filed on June 29, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a light-emitting substrate and a display device. Background Art

[0003] With the development of light-emitting diode technology, backlight sources using submillimeter light-emitting diodes (Mini-LEDs) and micro-LEDs (Micro-LEDs) have become widely used. Mini-LEDs range in size from approximately 100μm to 300μm, while Micro-LEDs are approximately less than 100μm. Due to their small size and high brightness, Mini-LEDs and Micro-LEDs, when used in backlight modules, allow for fine-tuning of the backlight, enabling high-dynamic range (HDR) displays, and are therefore attracting increasing attention.

[0004] Summary of the Invention

[0005] On the one hand, a light-emitting substrate is provided. The light-emitting substrate includes a substrate, multiple signal line groups, multiple columns of component groups, and multiple columns of control chips. The multiple signal line groups are provided on the substrate and arranged along a first direction. Each signal line group includes multiple signal lines arranged along the first direction. The multiple columns of component groups are arranged along the first direction, and each column of component groups includes multiple component groups arranged at intervals along a second direction. A column of component groups is electrically connected to some signal lines of a signal line group, and each component group includes multiple light-emitting elements arranged at intervals along the first direction and electrically connected in sequence. The multiple columns of control chips are arranged along the first direction, and each column of control chips includes multiple control chips arranged at intervals along the second direction. A column of control chips is provided on one side of a column of component groups along the first direction, and is electrically connected to the column of component groups and some signal lines of a signal line group.

[0006] In some embodiments, the plurality of light-emitting elements in the element group include a first light-emitting element and at least one second light-emitting element; the first light-emitting element is located at one end of the element group along the first direction. The signal line group includes a ground line and a first voltage signal line. The ground line is located between the first light-emitting element and the at least one second light-emitting element, and the first voltage signal line is located on a side of the at least one second light-emitting element away from the first light-emitting element. The control chip is disposed on one side of the first light-emitting element along the second direction.

[0007] In some embodiments, the light-emitting substrate further includes a first bridge portion configured to connect the first light-emitting element and a second light-emitting element closest to the first light-emitting element.

[0008] In some embodiments, the element group includes a plurality of second light-emitting elements. The signal line group further includes a first connecting line. The first connecting line is disposed between two adjacent second light-emitting elements and is configured to connect the two adjacent second light-emitting elements. The light-emitting substrate further includes a first connecting pattern. The first connecting pattern is electrically connected to the second light-emitting element closest to the first light-emitting element and is electrically connected to the first bridge portion. The dimension of the first connecting pattern along the second direction is greater than the dimension of the first connecting line along the second direction.

[0009] In some embodiments, the resistivity of the first bridge portion is less than the resistivity of the first connecting line.

[0010] In some embodiments, the signal line group further includes a second connection pattern. The second connection pattern is electrically connected to the first light-emitting element and to the first bridge portion. The second connection pattern has a dimension along the second direction that is larger than a dimension of the first connection line along the second direction. The second connection pattern is located on one side of the first light-emitting element along the second direction, or between the first light-emitting element and the ground trace.

[0011] In some embodiments, the ground trace includes a first main portion and a plurality of first protrusions. The first main portion extends along the second direction and is located between the first light-emitting element and the at least one second light-emitting element. The plurality of first protrusions are located on a side of the first main portion proximal to the at least one second light-emitting element and are connected to the first main portion. The first protrusion extends along the first direction and is located between two adjacent element groups along the second direction.

[0012] In some embodiments, at least one of the plurality of first voltage signal lines included in the plurality of signal line groups is a first target signal line. The first target signal line includes a second main portion and a plurality of second protrusions. The second main portion extends along the second direction and is located on a side of the at least one second light-emitting element away from the first light-emitting element. The plurality of second protrusions are located on a side of the second main portion proximal to the ground trace and are connected to the second main portion. The second protrusion extends along the first direction and is located between two adjacent element groups along the second direction.

[0013] In some embodiments, at least one of the plurality of first voltage signal lines included in the plurality of signal line groups is a second target signal line. The second target signal line includes a plurality of second protrusions. The plurality of second protrusions are spaced apart along the second direction; each second protrusion is connected to a corresponding component group, and the second protrusion is located on one side of the component group along the second direction. The light-emitting substrate also includes a plurality of second bridging portions, each of which is configured to connect two adjacent second protrusions along the second direction.

[0014] In some embodiments, among the plurality of first voltage signal lines included in the plurality of signal line groups, the outermost first voltage signal line along the first direction is the second target signal line, and the second target signal line is adjacent to the border area of ​​the light-emitting substrate.

[0015] In some embodiments, a first protrusion and a second protrusion are disposed between two adjacent element groups along the second direction. The first protrusion and the second protrusion are disposed side by side along the first direction. In some embodiments, the first connection pattern of the light-emitting substrate is located between the second light-emitting element closest to the first light-emitting element and the ground trace.

[0016] In some embodiments, along the second direction, a first protrusion and a second protrusion are provided between two adjacent element groups, and the first protrusion and the second protrusion are provided side by side along the second direction.

[0017] In some embodiments, the first connection pattern of the light-emitting substrate is located on a side of the second light-emitting element closest to the first light-emitting element along the second direction.

[0018] In some embodiments, along the first direction, the first connection pattern of the light emitting substrate and the second protrusion are arranged side by side along the first direction. The size of the first protrusion along the first direction is larger than the size of the second protrusion along the first direction.

[0019] In some embodiments, a dimension of the first main body portion along the first direction is 1.9 mm to 2.1 mm, and a dimension of the second main body portion along the first direction is 3.4 mm to 3.7 mm.

[0020] In some embodiments, the signal line group further includes an addressing signal line, a power signal line, and a feedback signal line. Along the first direction, the addressing signal line, the power signal line, the ground line, the feedback signal line, and the first voltage signal line are arranged sequentially. Portions of the addressing signal line and the power signal line are located between the first light-emitting element and the at least one second light-emitting element. The feedback signal line is located on a side of the ground line away from the control chip and extends along a boundary of the ground line away from the control chip.

[0021] In some embodiments, the light-emitting substrate has a device area and a binding area arranged side by side along the second direction, and the multiple component groups and multiple light-emitting elements are arranged in the device area. The light-emitting substrate also includes a first boundary, a second boundary, and a binding pin. The ground trace closest to the first boundary in the signal line group is closer to the first boundary than the first voltage signal trace closest to the first boundary, and the spacing between the first boundary and the signal line group is 2.0 mm to 2.3 mm. The first boundary and the second boundary are opposite along the first direction. The first voltage signal trace closest to the second boundary in the signal line group is closer to the second boundary than the ground trace closest to the second boundary, and the spacing between the second boundary and the signal line group is 2.0 mm to 2.3 mm. Along the second direction, the minimum spacing between the binding pin and the signal line group is 1.3 mm to 1.6 mm.

[0022] In some embodiments, the signal line group includes a ground line and a first voltage signal line, and the plurality of light-emitting elements of the element group are disposed between the ground line and the first voltage signal line.

[0023] In some embodiments, the light-emitting substrate further includes a second connecting wire. The second connecting wire is located between two adjacent light-emitting elements in the element group and is configured to connect the two adjacent light-emitting elements. The dimension of the second connecting wire along the second direction is greater than the dimension of the light-emitting element along the second direction. The spacing between two adjacent second connecting wires along the second direction is less than the dimension of the second connecting wire along the second direction.

[0024] In some embodiments, the ground trace includes a third main portion and at least one third protrusion. The third main portion extends along the second direction. The at least one third protrusion is located on a side of the third main portion close to the first voltage signal line and is connected to the third main portion. The third protrusion extends along the first direction and is located between two adjacent component groups. The first voltage signal line includes a fourth main portion and at least one fourth protrusion. The fourth main portion extends along the second direction. The at least one fourth protrusion is located on a side of the fourth main portion close to the ground trace and is connected to the fourth main portion; the fourth protrusion extends along the first direction and is located between two adjacent component groups. The light-emitting substrate also includes a third bridging portion and a fourth bridging portion. One end of the third bridging portion is electrically connected to the end of the third protrusion away from the third main portion, and the other end is electrically connected to the ground trace of the adjacent signal line group. One end of the fourth bridging portion is electrically connected to the end of the fourth protrusion away from the fourth main portion, and the other end is electrically connected to the first voltage signal line of the adjacent signal line group.

[0025] In some embodiments, at least one element group is provided between a third protrusion and a fourth protrusion adjacent to each other along the second direction. Along the second direction, the third protrusion is smaller than the second connecting line, and the fourth protrusion is smaller than the second connecting line.

[0026] In some embodiments, the light-emitting substrate includes a device region and a binding region arranged side by side along the second direction, and the plurality of light-emitting elements of the plurality of element groups are disposed in the device region. The light-emitting substrate further includes a first voltage signal pin and a fifth bridge portion. The first voltage signal pin is disposed in the binding region. The fifth bridge portion is configured to connect the first voltage signal line and the first voltage signal pin.

[0027] In some embodiments, the signal line group further includes an addressing signal line, a data signal line and a power signal line; along the first direction, the first voltage signal line, the power signal line, the data signal line, the addressing signal line and the ground line are arranged in sequence.

[0028] In another aspect, a display device is provided. The display device includes a display panel and the light-emitting substrate described in any one of the above embodiments. The light-emitting substrate is located on the non-display side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] FIG1 is a planar structural diagram of a display device according to some embodiments;

[0031] FIG2 is a cross-sectional structural diagram of a display device according to some embodiments;

[0032] FIG3 is a schematic structural diagram of a light-emitting substrate according to some embodiments;

[0033] FIG4 is a partial enlarged view of area A in FIG3 ;

[0034] FIG5 is a cross-sectional structural diagram of C1-C1, C2-C2, and C3-C3 in FIG4;

[0035] FIG6 is a partial enlarged view of area B in FIG3 ;

[0036] FIG7 is a schematic structural diagram of a control chip according to some embodiments;

[0037] FIG8 is another structural schematic diagram of a light-emitting substrate according to some embodiments;

[0038] FIG9 is a schematic diagram of another structure of a light-emitting substrate according to some embodiments;

[0039] FIG10 is a partial enlarged view of area D in FIG9 ;

[0040] FIG11 is a schematic diagram of another structure of a light-emitting substrate according to some embodiments;

[0041] FIG12 is a schematic diagram of another structure of a light-emitting substrate according to some embodiments;

[0042] FIG13 is a partial enlarged view of the E region in FIG12 . DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0047] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0048] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0049] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0050] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0051] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0052] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0053] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0054] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0055] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0056] 1 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays either moving (eg, video) or fixed (eg, still images), and either text or images.

[0057] Exemplarily, the display device 1000 may be a mobile phone, a wireless device, a personal digital assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, an automobile display (e.g., an odometer display, etc.), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, packaging and aesthetic structures (e.g., a display of an image of a piece of jewelry), etc.

[0058] In some embodiments, the display device 1000 may be rectangular, circular, or any other shape, and the embodiments of the present disclosure do not specifically limit this. Below, a rectangular display device is used as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0059] In some embodiments, the display device 1000 may be a liquid crystal display (LCD) device. Referring to FIG2 , the display device 1000 may include a backlight module 100, a display panel 200, and a glass cover 300. The display panel 200 includes a display side and a non-display side. The display side refers to the side of the display panel 200 used to display the image (the upper side of the display panel 200 in FIG2 ), and the non-display side refers to the other side opposite to the display side. The backlight module 100 is arranged on the non-display side of the display panel 200 (the lower side of the display panel 200 in FIG2 ), and the backlight module 100 is used to provide a backlight source for the display panel 200. The glass cover 300 is arranged on the display side of the display panel 200 to shield and protect the display panel 200.

[0060] In some embodiments, referring to FIG. 2 , when the display device 1000 is a liquid crystal display device, the display panel 200 may be a liquid crystal display panel. The display panel 200 may include an array substrate 210, a cell substrate 220, and a liquid crystal layer 230 disposed between the array substrate 210 and the cell substrate 220. A thin-film transistor 212 (TFT) and a pixel electrode 213 are disposed on the array substrate 210 and located on a first substrate 211. The thin-film transistor 212 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer. The source electrode and the drain electrode are respectively in contact with the active layer, and the pixel electrode 213 is electrically connected to the drain electrode of the thin-film transistor 212.

[0061] In some embodiments, as shown in FIG2 , the array substrate 210 further includes a common electrode 214 disposed on the first substrate 211. The pixel electrode 213 and the common electrode 214 may be disposed on different layers. In this case, as shown in FIG2 , a first insulating layer 215 is disposed between the pixel electrode 213 and the common electrode 214. When the common electrode 214 is disposed between the thin film transistor 212 and the pixel electrode 213, a second insulating layer 216 is further disposed between the common electrode 214 and the thin film transistor 212, as shown in FIG2 .

[0062] The pixel electrode 213 and the common electrode 214 may also be provided on the same layer (not shown in the figure). In this case, both the pixel electrode 213 and the common electrode 214 have a comb-tooth structure including a plurality of strip-shaped sub-electrodes. In other embodiments, the common electrode 214 may also be provided in the cell substrate 220.

[0063] As shown in FIG2 , the alignment substrate 220 may include a color filter layer 222 disposed on a second substrate 221. In this case, the alignment substrate 220 may also be referred to as a color filter substrate (CF). When the backlight module 100 is configured to emit white light, the color filter layer 222 includes at least red, green, and blue photoresist units. The red, green, and blue photoresist units are aligned with the sub-pixels of the display panel 200, respectively. The alignment substrate 220 also includes a black matrix pattern 223 disposed on the second substrate 221. The black matrix pattern 223 is configured to separate the red, green, and blue photoresist units.

[0064] As shown in FIG2 , the display panel 200 may further include a first polarizer 240 disposed on a side of the cell substrate 220 away from the liquid crystal layer 230, and a second polarizer 250 disposed on a side of the array substrate 210 away from the liquid crystal layer 230. In addition, the display panel 200 may further include other layers or structures, which are not listed in detail in the embodiments of the present disclosure.

[0065] In some embodiments, the backlight module 100 includes a light-emitting substrate 110. The light-emitting substrate 110 can directly emit white light, and the white light is emitted to the display panel 200 after being evenly treated. Alternatively, the light-emitting substrate 110 can also emit light of other colors, and the light of other colors is emitted to the display panel 200 after being color converted and evenly treated. The backlight module 100 can also include an optical film 120, and the optical film 120 can include a diffuser plate and / or an optical brightening film, which is not specifically limited in the embodiments of the present disclosure. Among them, the diffuser plate has a scattering and diffusion effect, which can further mix the above-mentioned white light; the optical brightening film can improve the light output efficiency of the backlight module 100. In addition, the backlight module 100 can also include other film layers or structures, which are not listed one by one in the embodiments of the present disclosure.

[0066] In some embodiments, referring to both Figures 3 and 4 , a light-emitting substrate 110 includes a substrate 10, multiple signal line groups 30, multiple columns of component groups 40, and multiple columns of control chips 50. Figure 3 is a schematic diagram of the structure of the light-emitting substrate when the first protrusion and the second protrusion are arranged side by side along a first direction; Figure 4 is a structural diagram of the connection relationship between a component group, a signal line group, and a control chip.

[0067] The light-emitting substrate 110 may include a device area AA and a border area BB. The device area AA is used to arrange multiple columns of component groups 40 and multiple columns of control chips 50. In addition, at least a portion of the multiple signal lines included in the signal line group 30 is arranged in the device area AA. The device area AA is also used to emit light. The border area BB is located on at least one side of the device area AA. For example, the border area BB is arranged around the device area AA. The border area BB is used to arrange signal lines. For example, the border area BB includes a binding area BB1 located on one side of the device area AA along the second direction Y. The binding area BB1 can be used to arrange fan-out lines and binding pins of the signal line group 30.

[0068] The substrate 10 may be a rigid substrate or a flexible substrate. For example, the material of the substrate 10 may include any one of glass, quartz, plastic, FR-4 grade material, resin, polyimide (PI), or polymethyl methacrylate (PMMA). The embodiments of the present disclosure are not particularly limited in this regard.

[0069] A plurality of signal line groups 30 are disposed on the substrate 10 and arranged along a first direction X. Each signal line group 30 includes a plurality of signal lines arranged along the first direction X. Each signal line group 30 is electrically connected to a column of component groups 40 and a column of control chips 50, and is configured to control a column of control chips 50 and a column of component groups 40, thereby controlling the component groups 40 to emit light through the control chips 50.

[0070] For example, as shown in FIG3 and FIG4 , the plurality of signal lines of the signal line group 30 may include a first voltage signal line VLED, a ground signal line GND, an address signal line ADDR, a power signal line PWR, and a feedback signal line FB. Of course, the signal line group 30 may also include other signal lines, such as connection lines for connecting the component group 40 and the control chip 50 (see below), which are not listed here one by one.

[0071] In some embodiments, refer to Figure 5, which is a cross-sectional structural diagram of the light-emitting substrate 110. The light-emitting substrate 110 can be a single metal layer structure. In other words, the light-emitting substrate 110 only includes a conductive metal layer. At this time, the multiple signal lines of the signal line group 30 are made of the same material and are arranged in the same layer. Based on this, multiple signal line groups 30 can be prepared and formed through a single patterning process. This is conducive to simplifying the preparation process of the light-emitting substrate 110, thereby reducing the production cost of the light-emitting substrate 110. Exemplarily, the light-emitting substrate 110 may also include an insulating layer 20, which is arranged on the side of the signal line group 30 away from the substrate 10. The insulating layer 20 can cover the conductive layer where the signal line group 30 is located to play a role of electrical isolation. Of course, the light-emitting substrate 110 may also include other layer structures, which are no longer listed one by one in the embodiments of the present disclosure.

[0072] Multiple columns of element groups 40 are arranged along the first direction X. Each column of element groups 40 includes multiple element groups 40 arranged at intervals along the second direction Y. One column of element groups 40 is electrically connected to part of the signal lines of one signal line group 30. Each element group 40 includes multiple light-emitting elements 41 arranged at intervals along the first direction X and electrically connected in sequence.

[0073] The multiple component groups 40 in each column of component groups 40 are connected to a corresponding signal line group 30. Thus, the number of signal line groups 30 is equal to the number of columns of component groups 40. The multiple light-emitting elements 41 in each component group 40 are arranged along the first direction X. While maintaining the number and density of light-emitting elements 41, the space occupied by the component groups 40 along the first direction X can be maximized, thereby reducing the number of columns of component groups 40 and the number of signal line groups 30.

[0074] For example, as shown in FIG4 , each element group 40 is electrically connected to the first voltage signal line VLED of the signal line group 30 , and the element group 40 is electrically connected to the control chip 50 . Each element group 40 may include, for example, two, four, six, or eight light-emitting elements 41 , which is not specifically limited in the embodiments of the present disclosure. The following embodiments of the present disclosure are described using the example of each element group 40 including four light-emitting elements 41 .

[0075] For example, if an element group 40 includes four light-emitting elements 41 arranged in two rows and two columns (2*2), 2N columns of element groups 40 can be set on the substrate 10. Assuming that the size of the substrate 10 remains unchanged and the arrangement density of the light-emitting elements 41 remains unchanged, an element group 40 includes four light-emitting elements 41 arranged along the first direction X (1*4), then N columns of element groups 40 can be set on the substrate 10. That is, through the arrangement of the element groups 40 of the present application, the number of columns of the element groups 40 can be reduced to half of the original number. Based on this, the number of signal line groups 30 can be reduced to half of the original number. This is conducive to reducing the number of fan-out lines, thereby reducing the width of the peripheral area BB, especially reducing the width of the binding area BB1. Moreover, due to the reduction in the number of signal line groups 30, the wiring space of the signal line group 30 can be greatly improved when the area of ​​the substrate 110 remains unchanged and the arrangement density of the light-emitting elements 41 remains unchanged, which is beneficial to increase the width of the multiple signal lines included in the signal line group 30, thereby reducing the resistance of the multiple signal lines included in the signal line group 30. Based on this, the thickness of the signal lines included in the signal line group 30 can be reduced, and the amount of etching solution used in the preparation process of the signal line group 30 can be reduced.

[0076] It should be understood that the preparation process of the signal line group 30 may include forming a continuous, entire metal layer on the substrate 10 through a magnetron sputtering process. Of course, the preparation process of the above-mentioned continuous, entire metal layer is not limited to this. For example, it can also be prepared by processes such as evaporation, chemical vapor deposition, or material vapor deposition, as long as a continuous, entire metal layer can be prepared. Then, a mask layer is formed on the continuous, entire metal layer. The process of forming the mask layer may include, for example, coating, exposure, and development. Then, the above-mentioned continuous, entire metal layer is etched using an etching solution to obtain the signal line group 30. Finally, the mask layer is removed through an etching process. Based on the preparation process of the above-mentioned signal line group 30, reducing the thickness of the signal lines included in the signal line group 30 is conducive to reducing the thickness of the formed continuous, entire metal layer, thereby reducing the amount of etching solution used in the subsequent etching process. The material of the entire metal layer may be, for example, copper.

[0077] In some embodiments, the type of the light emitting element 41 can be an LED with a quantum well junction, an LED with a columnar structure, an LED with a double heterojunction, etc. In terms of the size of the light emitting element 41, the light emitting element 41 can be a structure with a size of hundreds of microns. For example, the area of ​​the light emitting area of ​​the light emitting element 41 can be 1 mm 2 Alternatively, the light emitting area of ​​the light emitting element 41 may be 10000 μm 2 Alternatively, the light emitting area of ​​the light emitting element 41 may be 3000 μm 2 Below, the area of ​​the light emitting region of the light emitting element 41 can be 700 μm 2 Below, the area of ​​the light emitting region of the light emitting element 41 can be 200 μm 2 Of course, the embodiments of the present disclosure are not limited thereto, and the light emitting element 41 may also be a light emitting element of other structures, as long as the same technical concept as that of the present application is applied.

[0078] The light-emitting element 41 may include a P-pole (positive electrode) and an N-pole (negative electrode). The P-pole of the light-emitting element 41 may be electrically connected to the first voltage signal line VLED, and the N-pole may be electrically connected to the control chip 50. Of the two light-emitting elements 41 connected to each other in an element group 40, the N-pole of one light-emitting element 41 (the light-emitting element 41 closer to the first voltage signal line VLED) is electrically connected to the P-pole of the other light-emitting element 41. In other words, the two light-emitting elements 41 connected to each other are arranged in series.

[0079] Multiple columns of control chips 50 are arranged along a first direction X. Each column of control chips 50 includes multiple control chips 50 spaced apart along a second direction Y. A column of control chips 50 is disposed on one side of a column of component groups 40 and is electrically connected to the column of component groups 40 and a portion of the signal lines of a signal line group 30.

[0080] Among them, one control chip 50 can control one component group 40 or multiple component groups 40, and the embodiments of the present disclosure do not specifically limit this. In the following embodiments of the present disclosure, the control chip 50 is used to control one component group 40 and four component groups 40 for exemplary description, respectively. It is understandable that the control chip 50 can also be used to control other numbers of component groups 40, as long as the same technical concepts as those of the present application are applied.

[0081] For example, when a control chip 50 is used to control an element group 40, as shown in Figure 6, the control chip 50 may include a signal input pin Di (an input pin for an addressing signal ADDR), a signal output pin Do, a ground pin 57, and a power pin 58. A plurality of control chips 50 in a column of control chips 50 are cascaded (not shown in the figure), and in two cascaded control chips 50, the signal output pin Do of the upper control chip 50 is electrically connected to the signal input pin Di of the lower control chip 50. The ground pin 57 is electrically connected to the ground trace GND, and the power pin 58 can be electrically connected to the power signal line PWR. The signal output pin Do is also electrically connected to the plurality of light-emitting elements 41 of the element group 40. For example, the signal output pin Do is electrically connected to the N pole of the light-emitting element 41. The P pole of the light-emitting element 41 is electrically connected to the first voltage signal line VLED.

[0082] For example, when a single control chip 50 is used to control four component groups 40, as shown in FIG7 , the control chip 50 may include a signal input pin Di, a signal output pin Do, a power signal input pin VCC-In, a power signal output pin VCC-Out, a data signal input pin Data-In, a data signal output pin Data-Out, a first ground pin 571, a second ground pin 572, and four output pins CH, each of which is electrically connected to the four component groups 40. The first ground pin 571 and the second ground pin 572 are both electrically connected to the ground trace GND. In the two cascaded control chips 50, the signal output pin Do of the upper control chip 50 is electrically connected to the signal input pin Di of the lower control chip 50, and the power signal output pin VCC-Out of the upper control chip 50 is electrically connected to the power signal input pin VCC-In of the lower control chip via the power signal line PWR. The signal line group 30 may also include a data connection line. The data signal output pin Data-Out of the upper control chip 50 is electrically connected to the data signal input pin Data-In of the lower control chip 50 through the data connection line.

[0083] It is understandable that the structures of the above two control chips 50 are merely exemplary, and the embodiments of the present disclosure are not limited thereto, as long as the same technical concept as that of the present application is adopted.

[0084] In some embodiments, the signal line group 30 includes a ground line GND and a first voltage signal line VLED. The first voltage signal line VLED is disposed on one side of the plurality of light-emitting elements 41 of the component group 40 along the first direction X. The ground line GND can be disposed between two adjacent light-emitting elements 41 of the plurality of light-emitting elements 41 (as shown in Figures 3 and 4 ), or the ground line GND can be disposed on the other side of the plurality of light-emitting elements 41 of the component group 40 along the first direction X (as shown in Figures 12 and 13 ).

[0085] In the case where the ground trace GND is provided between two adjacent light-emitting elements 41 among the plurality of light-emitting elements 41, referring to FIG4 , the plurality of light-emitting elements 41 of the element group 40 include a first light-emitting element 42 and at least one second light-emitting element 43. The first light-emitting element 42 is located at one end of the element group 40 along the first direction X. The following embodiments of the present disclosure are described illustratively using the example of an element group 40 including four light-emitting elements 41, with the first light-emitting element 42 being the leftmost of the four light-emitting elements 41. Thus, the four light-emitting elements 41 include a first light-emitting element 42 located at the leftmost side and three second light-emitting elements 43 located to the right of the first light-emitting element 42.

[0086] As shown in FIG4 , the signal line group 30 includes a ground line GND and a first voltage signal line VLED. The first voltage signal line VLED is used to provide a power supply voltage to the light-emitting elements 41. The first voltage signal line VLED is located on a side of at least one second light-emitting element 43 away from the first light-emitting element 41. In other words, the first voltage signal line VLED is located to the right of the multiple light-emitting elements 41 included in the element group 40. The ground line GND is located between the first light-emitting element 42 and at least one second light-emitting element 43 (all second light-emitting elements 43). This allows the ground line GND and the first voltage signal line VLED to utilize the gap between two adjacent element groups 40 (see below), further increasing their area, reducing their resistance, and reducing their thickness. This optimizes the layout of the multiple signal lines in the signal line group 30 and improves the space utilization of the substrate 10.

[0087] For example, as shown in FIG4 , taking the example of one control chip 50 controlling one element group 40, the control chip 50 can be disposed on one side of the first light-emitting element 42 along the second direction Y. In this way, the control chip 50 is also located on the side of the ground trace GND close to the first light-emitting element 42. For example, the control chip 50 is disposed on the lower side of the first light-emitting element 42.

[0088] As shown in FIG4 , the ground trace GND is provided between the first light-emitting element 42 and the second light-emitting element 43. The first light-emitting element 42 and the second light-emitting element 43 cannot be directly electrically connected via a connection line provided on the same layer as the signal line group 30. Therefore, the light-emitting substrate 110 further includes a first bridge portion 51. The first bridge portion 51 is configured to connect the first light-emitting element 42 and the second light-emitting element 43 closest to the first light-emitting element 42, thereby sequentially connecting the plurality of light-emitting elements 41.

[0089] For example, the first bridge portion 51 can be a chip resistor or a jumper resistor. A jumper resistor, also known as a zero-ohm resistor, is a special-purpose resistor with a very low resistance value. An automatic chip placement machine or an automatic insertion machine can be used to place a jumper resistor between two points in the wiring substrate that cannot be directly connected via wiring, thereby achieving an electrical connection between the two points. This also helps reduce the resistance between the first light-emitting element 42 and the second light-emitting element 43.

[0090] In some embodiments, as shown in FIG4 , the element group 40 includes a plurality of second light emitting elements 43. The signal line group 30 further includes a first connecting line 33. The first connecting line 33 is disposed between two adjacent second light emitting elements 43 and is configured to connect the two adjacent second light emitting elements 43.

[0091] Exemplarily, the resistivity of the first bridge portion 51 is smaller than the resistivity of the first connecting line 33 , which is beneficial for reducing the resistance between the first light-emitting element 42 and the second light-emitting element 43 .

[0092] In some embodiments, as shown in FIG4 , the first connecting wires 33 extend along the first direction X, and the plurality of first connecting wires 33 electrically connected to the plurality of second light-emitting elements 43 of the same element group 40 are arranged approximately along the first direction X. In this way, the space occupied by the plurality of first connecting wires 33 along the second direction Y can be minimized, thereby improving the utilization rate of the wiring space on the substrate 10.

[0093] Continuing with FIG4 , the light-emitting substrate 110 further includes a first connection pattern 31 and a second connection pattern 32. The first connection pattern 31 is electrically connected to the second light-emitting element 43 closest to the first light-emitting element 42, while the second connection pattern 32 is electrically connected to the first light-emitting element 42. The first bridge 51 has two ends electrically connected to the first connection pattern 31 and the second connection pattern 32, respectively. Thus, the second light-emitting element 43 closest to the first light-emitting element 42 is electrically connected to the first light-emitting element 42 via the first connection pattern 31, the first bridge 51, and the second connection pattern 32, in sequence.

[0094] As shown in FIG4 , the dimension of the first connection pattern 31 along the second direction Y is larger than the dimension of the first connection line 33 along the second direction Y. This increases the area of ​​the first connection pattern 31, thereby reducing the difficulty of connecting the first connection pattern 31 to the first bridge portion 51. It also helps improve the heat dissipation capability of the first connection pattern 31 and prevents heat accumulation on the first connection pattern 31. As shown in FIG4 , the first connection pattern 31 can be located on one side of the second light-emitting element 43 along the second direction Y; alternatively, as shown in FIG8 , the first connection pattern 31 can be located between the second light-emitting element 43 and the ground trace GND.

[0095] For example, as shown in FIG4 , when the first connection pattern 31 is located on one side of the second light-emitting element 43 along the second direction Y, the first connection pattern 31 may include a first sub-pattern 311, a second sub-pattern 312, and a third sub-pattern 313. The first sub-pattern 311, the second sub-pattern 312, and the third sub-pattern 313 are arranged side by side along the second direction Y. The first sub-pattern 311 extends along the first direction X, with one end electrically connected to the second light-emitting element 43 closest to the first light-emitting element 42 and the other end electrically connected to the second sub-pattern 312. The size of the first sub-pattern 311 along the second direction Y can be equal to the size of the first connection line 33 along the second direction Y. This ensures that the size of the pads electrically connected to each second light-emitting element 43 on the signal line group 30 is equal, which helps improve the structural uniformity of the light-emitting substrate 110. The second sub-pattern 312 extends along the second direction Y, with one end electrically connected to the end of the first sub-pattern 311 closest to the first light-emitting element 42 and the other end electrically connected to the third sub-pattern 313. The third sub-pattern 313 can extend along the first direction X, and its dimension along the first direction X is larger than that of the first sub-pattern 311. Furthermore, its dimension along the second direction Y is larger than that of the first sub-pattern 311. The first bridge 51 connects to the third sub-pattern 313 of the first connection pattern 31, increasing the area of ​​the third sub-pattern 313 (compared to the first sub-pattern 311), facilitating connection between the third sub-pattern 313 and the first bridge 51, and reducing the resistance of the first connection pattern 31. Furthermore, the first connection pattern 31 is located on one side of the second light-emitting element 43 along the second direction Y. This allows for more signal lines (first and second protrusions) to be arranged between two adjacent element groups 40 along the second direction Y, thereby improving the utilization of the wiring space on the substrate 10.

[0096] For example, as shown in FIG8 , when the first connection pattern 31 is located between the second light-emitting element 43 and the ground trace GND, the first connection pattern 31 may include a first sub-pattern 311 and a fourth sub-pattern 314, which are arranged side by side along the first direction X. The first sub-pattern 311 extends along the first direction X, with one end of the first sub-pattern 311 electrically connected to the second light-emitting element 43 closest to the first light-emitting element 42, and the other end connected to the fourth sub-pattern 314. The dimension of the first sub-pattern 311 along the second direction Y can be equal to the dimension of the first connection line 33 along the second direction Y. This ensures that the size of the pads on the signal line group 30 electrically connected to each light-emitting element 41 is equal, which helps improve the structural uniformity of the light-emitting substrate 110. The fourth sub-pattern 314 can be rectangular, and the dimension of the third sub-pattern 313 along the second direction Y is larger than the dimension of the first sub-pattern 311 along the second direction Y. The first bridge portion 51 is connected to the fourth sub-pattern 314 of the first connection pattern 31. This increases the area of ​​the fourth sub-pattern 314 (compared to the first connection pattern 31), which facilitates the connection between the fourth sub-pattern 314 and the first bridge portion 51. The first connection pattern 31 is located between the second light-emitting element 43 and the ground trace GND, which helps simplify the structure of the first connection pattern 31.

[0097] It is understandable that the specific shapes of the two first connection patterns 31 are merely examples, and the embodiments of the present disclosure are not limited thereto, as long as the first connection pattern 31 can connect the second light emitting element 43 closest to the first light emitting element 42 to the first bridge portion 51 .

[0098] In some embodiments, as shown in Figures 4 and 8, for reasons similar to those of the first connection pattern 31, the second connection pattern 32 is electrically connected to the first light-emitting element 42 and the first bridge portion 51, and the size of the second connection pattern 32 along the second direction Y is larger than the size of the first connection line 33 along the second direction Y. This is beneficial to increasing the area of ​​the second connection pattern 32, thereby reducing the difficulty of connecting the second connection pattern 32 to the first bridge portion 51 and reducing the resistance of the second connection pattern 32.

[0099] 4 , the second connection pattern 32 may be located on one side of the first light emitting element 42 along the second direction Y. Alternatively, referring to FIG. 8 , the second connection pattern 32 may be located between the first light emitting element 42 and the ground trace GND.

[0100] When the second connection pattern 32 is located on one side of the first light-emitting element 42 along the second direction Y, as shown in FIG4 , the second connection pattern 32 may include a fifth sub-pattern 321, a sixth sub-pattern 322, and a seventh sub-pattern 323. The fifth sub-pattern 321 extends along the first direction X, with one end electrically connected to the first light-emitting element 42 and the other end connected to the sixth sub-pattern 322. The size of the fifth sub-pattern 321 along the second direction Y can be equal to the size of the first connection line 33 along the second direction Y. This ensures that the size of the pads electrically connected to the first light-emitting element 42 and the second light-emitting element 43 are equal, which helps improve the structural uniformity of the light-emitting substrate 110. The sixth sub-pattern 322 extends along the second direction Y, with the fifth sub-pattern 321 and the sixth sub-pattern 322 connected at their middle portions along the second direction Y. The sixth sub-pattern 322, at its end (lower end) along the second direction Y near the bridge portion 51, is connected to the seventh sub-pattern 323. The seventh sub-pattern 323 is generally rectangular, and its dimension along the first direction X is greater than that of the fifth sub-pattern 321. Furthermore, its dimension along the second direction Y is greater than that of the fifth sub-pattern 321. The first bridge portion 51 is connected to the seventh sub-pattern 323 of the second connection pattern 32. This increases the area of ​​the seventh sub-pattern 323 (compared to the fifth sub-pattern 321), facilitates connection between the seventh sub-pattern 323 and the first bridge portion 51, and improves utilization of the wiring space on the substrate 10.

[0101] In the case where the second connection pattern 32 can be located between the first light-emitting element 42 and the ground trace GND, as shown in FIG8 , the second connection pattern 32 can include a fifth sub-pattern 321 and an eighth sub-pattern 324, which are arranged side by side along the first direction X. The fifth sub-pattern 321 extends along the first direction X, with one end electrically connected to the first light-emitting element 42 and the other end connected to the eighth sub-pattern 324. The dimension of the fifth sub-pattern 321 along the second direction Y can be equal to the dimension of the first connection line 33 along the second direction Y, which helps improve the structural uniformity of the light-emitting substrate 110. The eighth sub-pattern 324 can be rectangular, with a dimension along the second direction Y greater than that of the fifth sub-pattern 321. The first bridge portion 51 connects to the eighth sub-pattern 324 of the second connection pattern 32, increasing the area of ​​the eighth sub-pattern 324 (compared to the fifth sub-pattern 321) and facilitating the connection between the eighth sub-pattern 324 and the first bridge portion 51. The second connection pattern 32 is located between the first light emitting element 42 and the ground trace GND, which helps to simplify the structure of the second connection pattern 32 .

[0102] In the embodiment of the present disclosure, a wiring may be provided between two adjacent element groups 40 along the second direction Y to improve the utilization of the wiring space on the substrate 10 and reduce the resistance of the corresponding signal line.

[0103] In some embodiments, the ground trace GND includes a first main portion 22 and a plurality of first protrusions 23. The first main portion 22 extends along the second direction Y and is located between the first light-emitting element 42 and at least one second light-emitting element 43 (all the second light-emitting elements 43). The plurality of first protrusions 23 are located on a side of the first main portion 22 close to the at least one second light-emitting element 43 and are connected to the first main portion 23. The first main portion 22 is also used to connect the plurality of first protrusions 23 into a whole. The first protrusion 23 extends along the first direction and is located between two adjacent element groups 40 along the second direction Y. In the embodiment of the present disclosure, the first protrusion 23 is set by utilizing the gap between two adjacent element groups 40. This can increase the area of ​​the ground trace GND without increasing the area of ​​the substrate 10, thereby reducing the resistance of the ground trace GND, which is beneficial to reducing the size of the first main portion 22 along the first direction X and reducing the size of the signal line group 30 along the first direction X. Moreover, it is beneficial to reduce the thickness of the ground trace GND, reduce the amount of etching solution used in the preparation process of the ground trace GND, and reduce the preparation difficulty and preparation cost of the ground trace GND.

[0104] In some embodiments, as shown in FIG4 , the first main portion 22 has a dimension D1 along the first direction X, and D1 is 1.9 mm to 2.1 mm, which helps increase the area of ​​the first main portion 22 and thereby reduce the resistance and thickness of the ground trace GND. For example, the dimension D1 of the first main portion 22 along the first direction X can be 1.9 mm, 2.0 mm, or 2.1 mm. Of course, the embodiments of the present disclosure are not limited thereto. As long as the dimension D1 of the first main portion 22 along the first direction X is within the range of 1.9 mm to 2.1 mm, the dimension D1 of the first main portion 22 along the first direction X can be any value.

[0105] It is understood that if the dimension D1 of the first main body 22 along the first direction X is too large (e.g., greater than 2.1 mm), on the one hand, the distance between the first light-emitting element 42 and the second light-emitting element 43 is large, which is not conducive to the uniform distribution of the light-emitting elements 41. On the other hand, the signal line group 30 occupies a large space along the first direction X, which does not effectively increase the wiring density of the light-emitting substrate 110 and the arrangement density of the light-emitting elements. If the dimension D1 of the first main body 22 along the first direction X is too small (e.g., greater than 1.9 mm), it is not conducive to reducing the resistance of the ground trace GND.

[0106] In some embodiments, referring to FIG9 , at least one of the plurality of first voltage signal lines VLED included in the plurality of signal line groups 30 is a first target signal line VLED1. The light-emitting substrate 110 includes a plurality of signal line groups 30, each signal line group 30 including a first voltage signal line VLED. Thus, the light-emitting substrate 110 includes a plurality of first voltage signal lines VLED, and at least one of the plurality of first voltage signal lines VLED is a first target signal line VLED1.

[0107] Referring to Figure 9 , the first target signal line VLED1 includes a second main portion 24 and multiple second protrusions 25. The second main portion 24 extends along the second direction Y and is located on the side of at least one second light-emitting element 43 (all second light-emitting elements 43 of a component group 40) away from the first light-emitting element 42. The multiple second protrusions 25 are located on the side of the second main portion 24 near the ground trace GND and are connected to the second main portion 24. The second main portion 24 also serves to connect the multiple first protrusions 23 into a single unit. The second protrusions 25 extend along the first direction X and are located between two adjacent component groups 40 along the second direction Y. In the embodiments of the present disclosure, the second protrusions 25 are provided by utilizing the gap between two adjacent component groups 40. This increases the area of ​​the first target signal line VLED1 without increasing the area of ​​the substrate 10, thereby reducing the resistance of the first target signal line VLED1. This helps reduce the size of the second main portion 24 along the first direction X, thereby reducing the size occupied by the signal line group 30 along the first direction X. Moreover, it is beneficial to reduce the thickness of the first target signal line VLED1, reduce the amount of etching solution used in the preparation process of the ground trace GND, and reduce the preparation difficulty and preparation cost of the first target signal line VLED1.

[0108] For example, the second light emitting element 43 farthest from the first light emitting element 42 can be connected to the second main body 24. In addition, along the second direction Y, there is a gap between the first connecting line 33 and the first protrusion 23 to avoid signal interference between the first connecting line 33 and the first protrusion 23.

[0109] In some embodiments, as shown in FIG4 , the second main portion 24 has a dimension D2 along the first direction X, and D2 is 3.4 mm to 3.7 mm. This helps increase the area of ​​the second main portion 24, thereby reducing the resistance and thickness of the first voltage signal line VLED. For example, the dimension D1 of the first main portion 22 along the first direction X can be 3.4 mm, 3.5 mm, or 3.7 mm. Of course, the embodiments of the present disclosure are not limited to this. As long as the dimension D2 of the first main portion 22 along the first direction X is within the range of 3.4 mm to 3.7 mm, the dimension D2 of the second main portion 24 along the first direction X can be any value.

[0110] It is understood that if the dimension D2 of the second main body 24 along the first direction X is too large (e.g., greater than 3.7 mm), the signal line assembly 30 occupies a large space along the first direction X, which does not effectively increase the wiring density of the light-emitting substrate 110 and the arrangement density of the light-emitting elements. If the dimension D1 of the second main body 24 along the first direction X is too small (e.g., greater than 3.4 mm), it is not conducive to reducing the resistance of the ground trace GND.

[0111] In some embodiments, referring to Figures 9, 10, and 11, at least one of the plurality of first voltage signal lines VLED included in the plurality of signal line groups 30 is a second target signal line VLED2. The second target signal line VLED2 includes a plurality of second protrusions 25. The plurality of second protrusions 25 are spaced apart along the second direction Y. Each second protrusion VLED2 is connected to a corresponding component group 40, and each second protrusion VLED2 is located on one side of the component group 40 (connected to the second protrusion VLED2) along the second direction Y. The light-emitting substrate 110 also includes a plurality of second bridges 52, each configured to connect two adjacent second protrusions 25 along the second direction Y. In other words, the second target signal line VLED2 includes a plurality of second protrusions 25 spaced apart along the second direction Y, and the plurality of second protrusions 25 are electrically connected via the second bridges 52. This further reduces the space occupied by the signal line group 30 along the first direction X, thereby enabling the light-emitting substrate 110 to achieve a narrow bezel.

[0112] In some embodiments, as shown in Figure 10, the second protrusion 25 of the second target signal line VLED2 can be arranged side by side with the first protrusion 23 along the first direction X, or, as shown in Figure 11, the second protrusion 25 of the second target signal line VLED2 can be arranged side by side with the first protrusion 23 along the second direction Y.

[0113] In some embodiments, as shown in FIG9 , among the plurality of first voltage signal lines VLED included in the plurality of signal line groups 30, the outermost first voltage signal line VLED along the first direction X is the second target signal line VLED2, and the second target signal line VLED2 is adjacent to the border area BB of the light-emitting substrate 110. In other words, the first voltage signal line VLED in the signal line group 30 that is adjacent to the border area BB is the second voltage signal line VLED2. This helps reduce the border width of the border area BB on the side adjacent to the second voltage signal line VLED2, thereby reducing the width of the border area BB of the light-emitting substrate 110, and helping to achieve a narrow border for the display device 1000.

[0114] Exemplarily, in this way, along the first direction X, the two first voltage signal lines VLED in the two outermost signal line groups 30 are both the outermost first voltage signal lines VLED. However, referring to FIG9 , in one signal line group 30, the first voltage signal line VLED is located to the right of the ground trace GND. In this way, the signal line of the signal line group 30 on the left, which is close to the border area BB, is a GND trace, and the signal line of the signal line group 30 on the right, which is close to the border area BB, is a first voltage signal trace. Based on this, in the light-emitting substrate 110, the first voltage signal line VLED adjacent to the border area BB only includes the first voltage signal line VLED of the rightmost signal line group 30. In other words, the first voltage signal line VLED of the rightmost signal line group 30 is the second target signal line VLED2. This is beneficial for reducing the width of the right border area of ​​the light-emitting substrate 110, and is beneficial for the display device 1000 to achieve an ultra-narrow border.

[0115] It can be understood that the embodiments of the present disclosure are not limited to this. In some other embodiments, any one of the multiple first voltage signal lines VLED can be set as the first target signal line VLED1 or the second target signal line VLED2. The embodiments of the present disclosure do not make specific limitations on this, as long as the same technical ideas are adopted.

[0116] In some embodiments, referring to FIG. 10 , a first protrusion 23 and a second protrusion 25 are disposed between two adjacent component groups 40 along the second direction Y. The first protrusion 23 and the second protrusion 25 are disposed side by side along the second direction Y. This advantageously increases the dimensions of the first protrusion 23 and the second protrusion 25 along the second direction Y, thereby increasing the length of the connection between the first protrusion 23 and the first main body 22 and the connection between the second protrusion 25 and the second main body 24, thereby further reducing the resistance of the ground trace GND and the first voltage signal line VLED (first target signal line VLED1).

[0117] For example, the dimension of the first protrusion 23 along the first direction X can be equal to the dimension of the second protrusion 25 along the first direction X. Furthermore, the dimension of the first protrusion 23 along the second direction Y can be equal to the dimension of the second protrusion 25 along the second direction Y. This helps to increase the structural consistency of the first protrusion 23 and the second protrusion 25, improve the structural uniformity of the signal line assembly 30, and reduce the difficulty of manufacturing the signal line assembly 30.

[0118] In some embodiments, as shown in FIG10 , the first connection pattern 31 of the light-emitting substrate 110 is located on the side of the second light-emitting element 43 closest to the first light-emitting element 42 along the second direction Y. Between two adjacent element groups 40, of the first protrusion 23 and the second protrusion 25, the second protrusion 25 is closer to the first connection pattern 31. Furthermore, the first connection pattern 31 and the second protrusion 25 are arranged side by side along the first direction X. This effectively improves the space utilization between two adjacent element groups 40 and maximizes the area for the ground trace GND and the first voltage signal line VLED.

[0119] In some embodiments, when the first protrusion 23 and the second protrusion 25 are arranged side by side along the first direction X, referring to FIG. 11 , the first connection pattern 31 of the light-emitting substrate 110 is located between the second light-emitting element 43 closest to the first light-emitting element 42 and the ground trace GND. This minimizes the size of the first connection pattern 31 along the second direction Y, thereby increasing the wiring space for the first protrusion 23 and the size of the first protrusion 23 along the second direction Y.

[0120] In some embodiments, along the first direction X, the first connection pattern 31 of the light-emitting substrate 110 and the second protrusion 25 are arranged side by side along the first direction X. The dimension of the first protrusion 23 along the first direction X is larger than the dimension of the second protrusion 25 along the first direction X. In this way, the wiring space between two adjacent component groups 40 can be maximized, reducing the resistance of the ground trace GND and the first voltage signal line VLED.

[0121] In some embodiments, referring to FIG. 11 , a first protrusion 23 and a second protrusion 25 are disposed between two adjacent component groups 40 along the second direction Y. The first protrusion 23 and the second protrusion 25 are disposed side by side along the second direction Y. This helps increase the space utilization between two adjacent component groups 40.

[0122] For example, as shown in FIG11 , the dimension of the third sub-pattern 313 of the first connection pattern 31 along the second direction Y is substantially equal to the dimension of the second protrusion 25 along the second direction Y, and the dimension of the second protrusion 25 along the second direction Y may be greater than the dimension of the first protrusion 23 along the second direction Y. The dimension of the second protrusion 25 along the first direction X may be greater than the dimension of the third sub-pattern 313 along the first direction X.

[0123] It should be understood that in other embodiments, when the first voltage signal line VLED of the signal line group 30 is the first target signal line VLED1, one of the first protrusions 23 and the second protrusions 25 may be included between two adjacent component groups 40. Furthermore, the arrangement order and distribution density of the first protrusions 23 and the second protrusions 25 along the second direction Y may be arbitrarily selected, as long as the same technical principles are applied. When the second voltage signal line VLED of the signal line group 30 is the second target signal line VLED2, at least one second protrusion 25 may be included between two adjacent component groups 40, and the distribution density of the first protrusions 23 may be arbitrarily selected. For example, two, three, or four component groups 40 may be included between each pair of adjacent first protrusions 23.

[0124] In some embodiments, as shown in FIG11 , the signal line group 30 further includes an addressing signal line ADDR, a power signal line, and a feedback signal line. Along a first direction, the addressing signal line ADDR, the power signal line PWR, the ground line GND, the feedback signal line FB, and the first voltage signal line VLED are arranged in sequence. Portions of the addressing signal line ADDR and the power signal line PWR are located between the first light-emitting element 42 and the at least one second light-emitting element 43. The feedback signal line FB is located on the side of the ground line GND away from the control chip 50 and extends along the boundary of the ground line GND away from the control chip 50.

[0125] In some embodiments, referring to FIG. 9 , the light-emitting substrate 110 further includes a first boundary 1101, a second boundary 1102, and a binding pin 1103. The ground trace GND closest to the first boundary 1101 in the signal line group 30 is closer to the first boundary 1101 than the first voltage signal line VLED closest to the first boundary 1101. The spacing D3 between the first boundary 1101 and the signal line group 30 is 2.0 mm to 2.3 mm. Exemplarily, the spacing D3 between the first boundary 1101 and the signal line group 30 is 2.0 mm, 2.2 mm, or 2.3 mm.

[0126] The first boundary 1101 and the second boundary 1102 are opposite each other along the first direction X. The first voltage signal line VLED closest to the second boundary 1102 in the signal line group 30 is closer to the second boundary 1102 than the ground line GND closest to the second boundary 1102. The distance D4 between the second boundary 1102 and the signal line group 30 is 2.0 mm to 2.3 mm. Exemplarily, the distance D4 between the second boundary 1102 and the signal line group 30 is 2.0 mm, 2.1 mm, or 2.3 mm, which is not specifically limited in the embodiments of the present disclosure.

[0127] The spacing D3 between the first boundary 1101 and the signal line group 30 and the spacing D4 between the second boundary 1102 and the signal line group 30 may be equal or unequal, and the embodiments of the present disclosure are not limited thereto. For example, the spacing D3 between the first boundary 1101 and the signal line group 30 and the spacing D4 between the second boundary 1102 and the signal line group 30 are equal. In this way, the widths of the border regions on opposite sides of the light-emitting substrate 110 along the first direction X are equal, which facilitates symmetrical arrangement of the border widths of the display device 1000.

[0128] Along the second direction, the minimum distance D5 between the binding pins 1103 and the signal line group 30 is 1.3 mm to 1.6 mm. For example, the minimum distance D5 between the binding pins 1103 and the signal line group 30 is 1.3 mm, 1.45 mm, or 1.6 mm, etc., which is not specifically limited in the embodiments of the present disclosure.

[0129] In other embodiments, when the plurality of light-emitting elements 41 of the element group 40 are arranged between the ground trace GND and the first voltage signal line VLED, referring to Figures 12 and 13, the light-emitting substrate 110 further includes a second connecting line 34. The second connecting line 34 is located between two adjacent light-emitting elements 41 of the element group 40 and is configured to connect the two adjacent light-emitting elements 41. The dimension of the second connecting line 34 along the second direction Y is greater than the dimension of the light-emitting element 41 along the second direction Y. Along the second direction Y, the interval between two adjacent second connecting lines 34 is less than the dimension of the second connecting line 34 along the second direction. In the embodiments of the present disclosure, the gap between two adjacent element groups 40 is utilized to form a second connecting line 34 with a larger area, which is beneficial to reducing the resistance of the second connecting line 34, accelerating the heat dissipation efficiency of the second connecting line 34, and is beneficial to reducing the thickness of the signal line group 30, thereby reducing the amount of etching solution used during the formation of the signal line group 30.

[0130] In some embodiments, the ground trace GND includes a third main portion 35 and at least one third protruding portion 36. The third main portion 35 extends along the second direction Y. The third protruding portion 36 is located on a side of the third main portion 35 close to the first voltage signal line VLED and is connected to the third main portion 35. The third protruding portion 36 extends along the first direction X and is located between two adjacent component groups 40.

[0131] For example, the dimension of the third protrusion 36 along the first direction X is larger than the dimension of the second connection line 34 along the first direction X. In this way, the dimension of the third protrusion 36 along the first direction X can be maximized to reduce the span of the third bridge portion 53. The dimension of the third protrusion 36 along the second direction Y is smaller than the dimension of the second connection line 34 along the second direction Y, which helps to increase the area of ​​the second connection line 34 and thereby reduce the resistance of the second connection line 34.

[0132] The first voltage signal line VLED includes a fourth main portion 37 and at least one fourth protrusion 38. The fourth main portion 37 extends along the second direction Y. The at least one fourth protrusion 38 is located on a side of the fourth main portion 37 close to the ground trace GND and is connected to the fourth main portion 37. The fourth protrusion 38 extends along the first direction X and is located between two adjacent component groups 40.

[0133] The light-emitting substrate 110 further includes a third bridging portion 53 and a fourth bridging portion 54. One end of the third bridging portion 53 is electrically connected to the end of the third protrusion 36 away from the third main portion 35, and the other end is electrically connected to the ground trace GND of an adjacent signal line group 30. In other words, the third bridging portion 53 can electrically connect the two ground traces GND of two adjacent signal line groups 30, thereby interconnecting the multiple ground traces GND of multiple signal line groups 30 to form a mesh structure, thereby reducing the resistance of the ground traces GND.

[0134] One end of the fourth bridging portion 54 is electrically connected to the end of the fourth protrusion 38 away from the fourth main portion 37, and the other end is electrically connected to the first voltage signal line VLED of an adjacent signal line group 30. In other words, the fourth bridging portion 54 can electrically connect the two first voltage signal lines VLED of two adjacent signal line groups 30, thereby interconnecting the multiple first voltage signal lines VLED of multiple signal line groups 30 to form a mesh structure, thereby reducing the resistance of the first voltage signal lines VLED.

[0135] In some embodiments, at least one component group 40 is disposed between adjacent first protrusions 36 and second protrusions 38 along the second direction Y. That is, between two adjacent component groups 40 along the second direction Y, at most one of the first protrusions 36 and the second protrusions 38 is included. This allows for more wiring space to be reserved between two adjacent component groups 40 for arranging the second connecting wires 34, thereby increasing the size of the second connecting wires 34 along the second direction Y and thereby reducing the resistance of the second connecting wires 34.

[0136] Exemplarily, referring to FIG. 12 , along the second direction Y, a dimension D6 of the third protrusion 36 is smaller than a dimension D7 of the second connection line 34 , and a dimension D8 of the second protrusion 38 is smaller than a dimension D7 of the second connection line 34 .

[0137] In some embodiments, referring again to FIG. 12 , the light-emitting substrate 110 has a device area AA and a bonding area BB1 arranged side by side along a second direction Y. The plurality of light-emitting elements 41 of the plurality of element groups 40 are disposed in the device area AA. The light-emitting substrate 110 also includes bonding pins 1103 and a fifth bridge portion 55. The bonding pins 1103 include a first voltage signal pin Vled for transmitting a first voltage signal and a ground pin Gnd. The fifth bridge portion 55 is configured to connect the first voltage signal line VLED to the first voltage signal pin Vled. A ground trace GEN is connected to the ground pin Gnd.

[0138] In some embodiments, referring to both Figures 12 and 13 , the signal line group 30 further includes an address signal line ADDR, a data signal line Data, and a power signal line PWR. Along the first direction, the first voltage signal line VLED, the power signal line PWR, the data signal line Data, the address signal line ADDR, and the ground line GND are arranged in sequence.

[0139] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A light-emitting substrate, comprising: substrate; A plurality of signal line groups are disposed on the substrate, the plurality of signal line groups are arranged along a first direction, and each signal line group includes a plurality of signal lines arranged along the first direction; A plurality of columns of element groups are arranged along the first direction, each column of element groups includes a plurality of element groups arranged at intervals along the second direction, one column of element groups is electrically connected to part of the signal lines of one signal line group, and each element group includes a plurality of light-emitting elements arranged at intervals along the first direction and electrically connected in sequence; the first direction intersects the second direction; Multiple columns of control chips are arranged along the first direction, and each column of control chips includes multiple control chips arranged at intervals along the second direction; a column of control chips is set on one side of a column of component groups and is electrically connected to the column of component groups and part of the signal lines of a signal line group.

2. The light-emitting substrate according to claim 1, wherein: The plurality of light emitting elements of the element group include a first light emitting element and at least one second light emitting element; The first light emitting element is located at one end of the element group along the first direction; The signal line group includes: a ground line and a first voltage signal line, the ground line is located between the first light-emitting element and the at least one second light-emitting element, and the first voltage signal line is located on a side of the at least one second light-emitting element away from the first light-emitting element; The control chip is disposed on one side of the first light emitting element along the second direction.

3. The light-emitting substrate according to claim 2, further comprising: A first bridge portion is configured to connect the first light emitting element and a second light emitting element that is closest to the first light emitting element.

4. The light-emitting substrate according to claim 3, wherein: The element group includes a plurality of the second light-emitting elements; The signal line group further includes: a first connecting line, the first connecting line is disposed between two adjacent second light-emitting elements and is configured to connect two adjacent second light-emitting elements; The light-emitting substrate further includes: a first connection pattern electrically connected to a second light-emitting element closest to the first light-emitting element and electrically connected to the first bridge portion; Wherein, a size of the first connection pattern along the second direction is greater than a size of the first connection line along the second direction.

5. The light emitting substrate according to claim 4, wherein: The resistivity of the first bridge portion is smaller than the resistivity of the first connection line.

6. The light-emitting substrate according to any one of claims 4 or 5, wherein: The signal line group further includes: a second connection pattern electrically connected to the first light emitting element and to the first bridge portion; Wherein, a size of the second connection pattern along the second direction is greater than a size of the first connection line along the second direction.

7. The light-emitting substrate according to claim 6, wherein: The second connection pattern is located at one side of the first light emitting element along the second direction, or between the first light emitting element and the ground trace.

8. The light emitting substrate according to any one of claims 2 to 7, wherein The grounding wiring includes: A first main body portion extending along the second direction and located between the first light emitting element and the at least one second light emitting element; A plurality of first protrusions are located on a side of the first main body close to the at least one second light-emitting element and connected to the first main body; the first protrusions extend along the first direction and are located between two adjacent element groups along the second direction.

9. The light emitting substrate according to claim 8, wherein: At least one of the plurality of first voltage signal lines included in the plurality of signal line groups is a first target signal line, and the first target signal line includes: A second main body portion extending along the second direction and located on a side of the at least one second light-emitting element away from the first light-emitting element; A plurality of second protrusions are located on a side of the second main body close to the ground trace and connected to the second main body; the second protrusions extend along the first direction and are located between two adjacent component groups along the second direction.

10. The light-emitting substrate according to claim 8 or 9, wherein: At least one of the plurality of first voltage signal lines included in the plurality of signal line groups is a second target signal line, and the second target signal line includes: A plurality of second protrusions are spaced apart along the second direction; each second protrusion is connected to a corresponding component group, and the second protrusion is located on one side of the component group along the second direction; The light emitting substrate further includes: a plurality of second bridge portions, wherein the second bridge portions are configured to electrically connect two second protruding portions adjacent to each other along the second direction.

11. The light emitting substrate according to claim 10, wherein: Among the plurality of first voltage signal lines included in the plurality of signal line groups, the outermost first voltage signal line along the first direction is the second target signal line, and the second target signal line is adjacent to the frame area of ​​the light emitting substrate.

12. The light emitting substrate according to any one of claims 8 to 11, wherein Along the second direction, a first protruding portion and a second protruding portion are provided between two adjacent element groups; The first protrusion and the second protrusion are arranged side by side along the first direction.

13. The light emitting substrate according to claim 12, wherein: The first connection pattern of the light-emitting substrate is located between the second light-emitting element closest to the first light-emitting element and the ground trace.

14. The light emitting substrate according to any one of claims 8 to 11, wherein Along the second direction, a first protrusion and a second protrusion are provided between two adjacent element groups; The first protrusion and the second protrusion are arranged side by side along the second direction.

15. The light emitting substrate according to claim 14, wherein: The first connection pattern of the light emitting substrate is located on a side of the second light emitting element that is closest to the first light emitting element along the second direction.

16. The light emitting substrate according to claim 15, wherein: Along the first direction, the first connection pattern of the light-emitting substrate and the second protrusion are arranged side by side along the first direction; A dimension of the first protrusion along the first direction is greater than a dimension of the second protrusion along the first direction.

17. The light emitting substrate according to any one of claims 10 to 16, wherein The dimension of the first main body along the first direction is 1.9 mm to 2.1 mm; A dimension of the second main body along the first direction is 3.4 mm to 3.7 mm.

18. The light emitting substrate according to any one of claims 2 to 17, wherein The signal line group also includes an addressing signal line, a power signal line and a feedback signal line; Along the first direction, the addressing signal line, the power signal line, the ground line, the feedback signal line and the first voltage signal line are arranged in sequence; Part of the addressing signal line and part of the power signal line are located between the first light-emitting element and the at least one second light-emitting element, and the feedback signal line is located on a side of the ground line away from the control chip, and extends along a boundary of a side of the ground line away from the control chip.

19. The light emitting substrate according to any one of claims 2 to 18, wherein The light emitting substrate comprises a device area and a binding area arranged side by side along the second direction, and the plurality of element groups and the plurality of light emitting elements are arranged in the device area; The light-emitting substrate further comprises: A first boundary, a ground trace in the signal line group closest to the first boundary is closer to the first boundary than a first voltage signal line closest to the first boundary, and a spacing between the first boundary and the signal line group is 2.0 mm to 2.3 mm; a second boundary, the first boundary and the second boundary are opposite in the first direction; a first voltage signal line in the signal line group closest to the second boundary is closer to the second boundary than a ground line closest to the second boundary, and a spacing between the second boundary and the signal line group is 2.0 mm to 2.3 mm; The binding pins, along the second direction, have a minimum spacing between the binding pins and the signal line group of 1.3 mm to 1.6 mm.

20. The light emitting substrate according to claim 1, wherein: The signal line group includes: a ground line and a first voltage signal line; the plurality of light emitting elements of the element group are arranged between the ground line and the first voltage signal line.

21. The light emitting substrate according to claim 20, further comprising: a second connecting line, located between two adjacent light emitting elements of the element group, and configured to connect the two adjacent light emitting elements; The dimension of the second connecting line along the second direction is greater than the dimension of the light emitting element along the second direction; Along the second direction, a distance between two adjacent second connecting lines is smaller than a dimension of the second connecting line along the second direction.

22. The light emitting substrate according to claim 21, wherein: The grounding wiring includes: a third main body portion extending along the second direction; at least one third protrusion, located on a side of the third main body close to the first voltage signal line and connected to the third main body; the third protrusion extends along the first direction and is located between two adjacent element groups; The first voltage signal line comprises: a fourth main body portion extending along the second direction; at least one fourth protrusion, located on a side of the fourth main body close to the ground trace and connected to the fourth main body; the fourth protrusion extends along the first direction and is located between two adjacent component groups; The light-emitting substrate further comprises: A third bridging portion, one end of which is electrically connected to an end of the third protruding portion away from the third main body portion, and the other end of which is electrically connected to the ground trace of the adjacent signal line group; The fourth bridge portion has one end electrically connected to the end of the fourth protrusion away from the fourth main body portion, and the other end electrically connected to the first voltage signal line of the adjacent signal line group.

23. The light emitting substrate according to claim 22, wherein: At least one element group is arranged between the third protrusion and the fourth protrusion adjacent to each other along the second direction; along the second direction, the size of the third protrusion is smaller than the size of the second connecting line, and the size of the fourth protrusion is smaller than the size of the second connecting line.

24. The light emitting substrate according to any one of claims 20 to 23, wherein The light emitting substrate comprises a device area and a binding area arranged side by side along the second direction, and the plurality of light emitting elements of the plurality of element groups are arranged in the device area; The light-emitting substrate further comprises: A first voltage signal pin, wherein the first voltage signal pin is arranged in the binding area; The fifth bridge portion is configured to connect the first voltage signal line and the first voltage signal pin.

25. The light emitting substrate according to any one of claims 20 to 24, wherein The signal line group further includes an addressing signal line, a data signal line and a power signal line; along the first direction, the first voltage signal line, the power signal line, the data signal line, the addressing signal line and the ground line are arranged in sequence.

26. A display device comprising: The light-emitting substrate according to any one of claims 1 to 25; The display panel is provided with the light emitting substrate being located on the non-display side of the display panel.

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