Initialization method for resistive random access memory, apparatus, and electronic device

Abstract

Disclosed in the present application are an initialization method for a resistive random access memory, an apparatus, and an electronic device. The method comprises: inputting into a resistive random access memory a plurality of pulses under a first voltage until a storage unit in the resistive random access memory is suddenly changed from a high-resistance state into a low-resistance state; sequentially inputting into the resistive random access memory a plurality of pulses under a second voltage, a plurality of pulses under a third voltage, ... , a plurality of pulses under an Nth voltage, such that the resistance value of the storage unit in the resistive random access memory separately reaches a second preset value, a third preset value, ... , and an Nth preset value, the voltage values of the first voltage, the second voltage, the third voltage, ... , the Nth voltage gradually decreasing; if the total number of pulses under the input ith voltage is greater than a second preset threshold and the rate of resistance change is less than a rate threshold, increasing the ith voltage, and inputting into the resistive random access memory a plurality of pulses under the increased ith voltage until the resistance value of the storage unit in the resistive random access memory reaches an ith preset value.

Description

Method, device and electronic device for initializing variable resistance memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 29, 2023, with application number 202310781608.1, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of variable resistance memory, and in particular to a method, device and electronic device for initializing a variable resistance memory. Background Art

[0004] Initialization of resistive random access memory (RRAM) primarily involves changing the state of RRAM memory cells from a high-resistance state to a low-resistance state. Currently, pulses with increasing voltage and pulse width are primarily used for rapid RRAM initialization, followed by pulses with decreasing voltage and pulse width for precise initialization. However, during the precise initialization phase, for memory cells composed of transistors and resistors, the energy received by the resistors is low when initializing with pulses with decreasing voltage and pulse width due to voltage division in the transistors. Furthermore, the migration and interface crossing of oxygen ions in the resistors require energy above a certain threshold, resulting in some memory cells failing to initialize completely. Furthermore, for large-scale arrays of memory cells, there is also the issue of voltage division related to the physical address, which can lead to voltage loss at the far end of the same row or column. Consequently, during the precise initialization phase, when pulses with decreasing voltage and pulse width are used for initialization, the energy received by the far end memory cells is low, potentially preventing them from completing initialization. Furthermore, in large-scale arrays, some memory cells are difficult to initialize. During the precise initialization phase, if pulses with gradually decreasing voltage and pulse width are used for initialization, these difficult-to-initialize memory cells may fail to initialize due to insufficient energy. Therefore, improving the success rate of RRAM initialization is an urgent issue that needs to be addressed.

[0005] Summary of the Invention

[0006] In view of this, the embodiments of the present application provide a method, device, and electronic device for initializing a variable resistance memory to at least solve the above-mentioned technical problems in the prior art.

[0007] According to a first aspect of the present application, an embodiment of the present application provides a method for initializing a variable resistance memory, comprising:

[0008] Inputting a plurality of pulses of a first voltage into the variable resistance memory until a memory cell in the variable resistance memory suddenly changes from a high resistance state to a low resistance state;

[0009] Inputting a plurality of pulses of a second voltage into the variable resistance memory until the resistance value of a memory cell in the variable resistance memory reaches a second preset value, wherein the second preset value is less than the resistance value of the memory cell when the memory cell suddenly changes from a high resistance state to a low resistance state;

[0010] Inputting a plurality of pulses of a third voltage into the variable resistance memory until the resistance value of a storage unit in the variable resistance memory reaches a third preset value, wherein the third preset value is less than the second preset value;

[0011] This process is repeated in this manner until a plurality of pulses of an Nth voltage are input into the variable resistive memory until the resistance value of the memory cell in the variable resistive memory reaches an Nth preset value; wherein N is greater than or equal to 3, the voltage values ​​of the first voltage, the second voltage, the third voltage, ... the Nth voltage gradually decrease, the Nth preset value is less than the N-1th preset value, and the Nth preset value is the target resistance value that the memory cell needs to reach to complete initialization;

[0012] The method of inputting a plurality of pulses of an i-th voltage into the variable resistive memory until the resistance value of a storage unit in the variable resistive memory reaches an i-th preset value includes: inputting a plurality of pulses of an i-th voltage into the variable resistive memory, and if the total number of pulses of the i-th voltage inputted is greater than a second preset threshold value and the resistance change rate is less than a rate threshold value, increasing the i-th voltage, and inputting a plurality of pulses of the increased i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, where i is any one of 2, 3…N-1, or N.

[0013] Optionally, inputting a plurality of pulses of the first voltage into the variable resistance memory until a memory cell in the variable resistance memory suddenly changes from a high resistance state to a low resistance state includes:

[0014] Acquiring a first electrical parameter of a memory cell in a variable resistance memory; the first electrical parameter includes at least one of a first current value and a first resistance value;

[0015] If it is determined based on the first electrical parameter that the memory cell in the variable resistance memory has not suddenly changed from the high resistance state to the low resistance state, a first voltage pulse is input into the variable resistance memory; then the process returns to the step of obtaining the first electrical parameter of the memory cell in the variable resistance memory until it is determined that the memory cell in the variable resistance memory has suddenly changed from the high resistance state to the low resistance state.

[0016] Optionally, if it is determined based on the first electrical parameter that the variable resistance memory does not suddenly change from the high resistance state to the low resistance state, inputting a first voltage pulse into the variable resistance memory includes:

[0017] If the total number of input first voltage pulses is less than the first preset threshold, and it is determined based on the first electrical parameter that the storage unit in the variable resistance memory has not suddenly changed from a high resistance state to a low resistance state, a first voltage pulse is input into the variable resistance memory.

[0018] Optionally, inputting a plurality of pulses of the i-th voltage into the variable resistance memory includes:

[0019] Obtaining an i-th electrical parameter of a memory cell in a variable resistance memory; the i-th electrical parameter includes at least one of an i-th current value and an i-th resistance value;

[0020] If it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory does not reach the i-th preset value, a pulse of the i-th voltage is input into the variable resistive memory; then the process returns to the step of obtaining the i-th electrical parameter of the storage unit in the variable resistive memory.

[0021] Optionally, if it is determined based on the i-th electrical parameter that the resistance value of the memory cell in the variable resistive memory does not reach the i-th preset value, inputting a pulse of the i-th voltage into the variable resistive memory includes:

[0022] If the total number of pulses of the i-th voltage that have been input is less than the second preset threshold, the total number of pulses that have been input is less than the third preset threshold, and it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory has not reached the i-th preset value, then a pulse of the i-th voltage is input into the variable resistive memory.

[0023] Optionally, if the total number of pulses of the i-th voltage inputted is greater than a second preset threshold value and the resistance change rate is less than a rate threshold value, increasing the i-th voltage and inputting a plurality of pulses of the increased i-th voltage into the variable resistive memory until the resistance value of a memory cell in the variable resistive memory reaches an i-th preset value, comprising:

[0024] If the total number of pulses of the i-th voltage that have been input is greater than the second preset threshold, the total number of pulses that have been input is less than the third preset threshold, and the resistance change rate is less than the rate threshold, then multiple pulses of the increased i-th voltage are input into the variable resistive memory until the resistance value of the storage cell in the variable resistive memory reaches the i-th preset value.

[0025] Optionally, the resistance change rate calculation formula includes:

[0026] Wherein Δσ is the resistance change rate, I2 is the current value when the total number of pulses of the i-th voltage inputted is the second preset threshold value, I1 is the current value when the total number of pulses of the i-th voltage inputted is 1, and V is the voltage value of the i-th voltage.

[0027] According to a second aspect of the present application, an embodiment of the present application provides an initialization device for a variable resistance memory, comprising:

[0028] A first input unit is used to input a plurality of pulses of a first voltage into the variable resistance memory until a storage unit in the variable resistance memory suddenly changes from a high resistance state to a low resistance state;

[0029] a second input unit, configured to input a plurality of pulses of a second voltage into the variable resistance memory until the resistance value of a storage unit in the variable resistance memory reaches a second preset value, wherein the second preset value is less than the resistance value of the storage unit when the storage unit suddenly changes from a high resistance state to a low resistance state;

[0030] a third input unit, configured to input a plurality of pulses of a third voltage into the variable resistance memory until the resistance value of a storage unit in the variable resistance memory reaches a third preset value, wherein the third preset value is less than the second preset value;

[0031] This is repeated in this manner until the Nth input unit is used to input multiple Nth voltage pulses into the variable resistive memory until the resistance value of the memory cell in the variable resistive memory reaches the Nth preset value; wherein N is greater than or equal to 3, the voltage values ​​of the first voltage, the second voltage, the third voltage ... the Nth voltage gradually decrease, the Nth preset value is less than the N-1th preset value, and the Nth preset value is the target resistance value that the memory cell needs to reach to complete initialization;

[0032] The method of inputting a plurality of pulses of an i-th voltage into the variable resistive memory until the resistance value of a storage unit in the variable resistive memory reaches an i-th preset value includes: inputting a plurality of pulses of an i-th voltage into the variable resistive memory, and if the total number of pulses of the i-th voltage inputted is greater than a second preset threshold value and the resistance change rate is less than a rate threshold value, increasing the i-th voltage, and inputting a plurality of pulses of the increased i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, where i is any one of 2, 3…N-1, or N.

[0033] According to a third aspect of the present application, an embodiment of the present application provides an electronic device, including:

[0034] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to cause the at least one processor to perform the variable resistive memory initialization method as described in the first aspect or any embodiment of the first aspect.

[0035] According to the fourth aspect of the present application, an embodiment of the present application provides a computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the initialization method of the variable resistive memory as in the first aspect or any embodiment of the first aspect.

[0036] The variable resistive memory initialization method, device, and electronic device provided by the embodiments of the present application first initialize the variable resistive memory using multiple high-voltage pulses, allowing memory cells in the variable resistive memory to quickly change from a high-resistance state to a low-resistance state. After the memory cells in the variable resistive memory change to the low-resistance state, the resistance values ​​of the memory cells are fine-tuned in multiple stages, with the pulse voltages in each stage being the same. This converges the resistance distribution after initialization and improves consistency among cells in the array. Furthermore, during each stage of fine-tuning, if the total number of pulses input in that stage is greater than a second preset threshold and the resistance change rate is less than a rate threshold, the voltage for that stage is increased, and multiple pulses with increased voltage are input to the variable resistive memory until the resistance values ​​of the memory cells in the variable resistive memory reach the target resistance value for that stage. This further prevents some memory cells from not receiving sufficient energy and failing to complete initialization due to transistor voltage division or physical address-related voltage division. It also prevents memory cells that are inherently difficult to initialize from failing to complete initialization due to insufficient energy, significantly improving the success rate of memory cell initialization.

[0037] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a flow chart of a method for initializing a variable resistance memory according to an embodiment of the present application.

[0039] FIG. 2 is a schematic diagram of inputting pulses into a variable resistance memory in stages according to an embodiment of the present application.

[0040] FIG3 is a schematic diagram showing how to improve the resistance state convergence success rate by increasing the pulse energy in an embodiment of the present application.

[0041] FIG4 is a schematic diagram comparing the resistance state range after equal voltage pulse initialization and staged initialization of the present application.

[0042] FIG5 is a schematic diagram comparing the oxygen vacancies and O2- concentrations around the conductive filament after equal voltage pulse initialization and staged initialization of the present application.

[0043] FIG6 is a schematic structural diagram of an initialization device for a variable resistance memory according to an embodiment of the present application.

[0044] FIG7 is a schematic diagram of the hardware structure of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0046] An embodiment of the present application provides a method for initializing a variable resistance memory, as shown in FIG1 , including:

[0047] S101 , inputting a plurality of pulses of a first voltage into a variable resistance memory until a memory cell in the variable resistance memory suddenly changes from a high resistance state to a low resistance state.

[0048] In this embodiment, the resistance change of the memory cell in the variable resistance memory is related to the energy accumulation of the current flowing through it. As the energy accumulation of the current flowing through it exceeds a certain critical value, its resistance value will undergo a drastic change. This drastic change process is the process in which the memory cell suddenly changes from a high resistance state to a low resistance state, which is also the process in which the conductive channel of the variable resistance memory is formed.

[0049] In this embodiment, as shown in FIG. 2 , pulses of a first voltage may be inputted into the variable resistance memory one by one in the first stage until the target resistance value or target voltage value (1 st target), that is, the memory cell in the variable resistance memory is suddenly changed from a high resistance state to a low resistance state.

[0050] In one implementation, each time a first voltage pulse is input into the variable resistive memory, the current value of the memory cell is detected by a current measuring instrument. The detected current value is then compared with a target current value to determine whether the memory cell in the variable resistive memory has suddenly changed from a high-resistance state to a low-resistance state. The target current value can be determined through multiple tests and is used to characterize the sudden change from a high-resistance state to a low-resistance state of the memory cell in the variable resistive memory. If it is determined that the memory cell in the variable resistive memory has suddenly changed from a high-resistance state to a low-resistance state, the input of the first voltage pulse is stopped. If it is determined that the memory cell in the variable resistive memory has not suddenly changed from a high-resistance state to a low-resistance state, the input of the first voltage pulse continues.

[0051] In another implementation, each time a first voltage pulse is input into the variable resistive memory, the resistance value of the memory cell is detected by a resistance measuring instrument. The detected resistance value is then compared with a target resistance value to determine whether the memory cell in the variable resistive memory has suddenly changed from a high-resistance state to a low-resistance state. The target resistance value can be determined through multiple tests and is used to characterize the sudden change from a high-resistance state to a low-resistance state of the memory cell in the variable resistive memory. If it is determined that the memory cell in the variable resistive memory has suddenly changed from a high-resistance state to a low-resistance state, the input of the first voltage pulse is stopped. If it is determined that the memory cell in the variable resistive memory has not suddenly changed from a high-resistance state to a low-resistance state, the input of the first voltage pulse continues.

[0052] S102, inputting a plurality of pulses of a second voltage into the variable resistance memory until the resistance value of a memory cell in the variable resistance memory reaches a second preset value, wherein the second preset value is smaller than the resistance value of the memory cell when the memory cell suddenly changes from a high resistance state to a low resistance state.

[0053] In this embodiment, after the memory cell suddenly changes from a high-resistance state to a low-resistance state, it is still necessary to control the specific resistance value of the memory cell, that is, even if the resistance value of the memory cell reaches a first preset value, this process can be called a resistance state fine-tuning process, that is, a fine-tuning process of the resistance value of the memory cell.

[0054] In this embodiment, a plurality of stage targets are set during the resistance state fine-tuning process, so that the resistance state fine-tuning can be divided into a plurality of stages, which facilitates the convergence of the resistance state of the storage unit. In addition, during the fine-tuning process of each stage, the energy of the pulse is kept unchanged, which can prevent the storage unit from having no resistance state change or slow change due to insufficient accumulated energy, consuming a large amount of operation time and failing to achieve the effect of resistance state convergence.

[0055] In specific implementation, as shown in FIG2 , when fine-tuning the resistance value of the memory cell, multiple fine-tuning stages can be set, that is, the resistance value when the memory resistor changes state suddenly is adjusted to the target resistance value to be reached after the memory cell is initialized, and each fine-tuning stage corresponds to a resistance value to be reached (2 nd target, 3 rd target…), and as the number of fine-tuning stages increases, the resistance value to be achieved becomes smaller, so that the target of the last fine-tuning stage is the target resistance value. Then, for the first fine-tuning stage, multiple pulses of the second voltage are input into the variable resistive memory. If the total number of pulses of the input second voltage is greater than a second preset threshold and the resistance change rate is less than the rate threshold, the second voltage is increased. As shown in FIG3 , multiple pulses of the increased second voltage are input into the variable resistive memory until the resistance value of the storage cell in the variable resistive memory reaches the second preset value.

[0056] The resistance change rate calculation formula includes:

[0057] Wherein Δσ is the resistance change rate, I2 is the current value when the total number of pulses of the i-th voltage inputted is the second preset threshold value, I1 is the current value when the total number of pulses of the i-th voltage inputted is 1, V is the voltage value of the i-th voltage, and i is any one of 2, 3…N-1, N.

[0058] In this embodiment, after the pulse of the second voltage of the second preset threshold, if the rate of change of the resistance of the storage unit is less than the rate threshold, the success rate of the initialization of the storage unit in the first fine-tuning stage can be improved by increasing the pulse energy, and the fine-tuning time of the first fine-tuning stage can be greatly reduced.

[0059] S103 , inputting a plurality of pulses of a third voltage into the variable resistance memory until the resistance value of a memory cell in the variable resistance memory reaches a third preset value, wherein the third preset value is smaller than the second preset value.

[0060] In this embodiment, the specific implementation process of step S103 may refer to step S102.

[0061] By analogy, until S10N, multiple pulses of an Nth voltage are input into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches an Nth preset value; wherein N is greater than or equal to 3, the voltage values ​​of the first voltage, the second voltage, the third voltage...the Nth voltage gradually decrease, the Nth preset value is less than the N-1th preset value, and the Nth preset value is the target resistance value that the storage unit needs to reach to complete initialization; wherein, multiple pulses of an i-th voltage are input into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches an i-th preset value, including: inputting multiple pulses of an i-th voltage into the variable resistive memory, if the total number of pulses of the i-th voltage input is greater than a second preset threshold and the resistance change rate is less than a rate threshold, increasing the i-th voltage, and inputting multiple pulses of the increased i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, where i is any one of 2, 3...N-1, or N.

[0062] In this embodiment, the specific implementation process of step S10N may refer to step S102.

[0063] In this embodiment, after a memory cell in a variable resistive memory suddenly changes to a low-resistance state, the resistance value of the memory cell is fine-tuned in multiple stages. The closer the resistance value of the memory cell is to a first preset value, the smaller the pulse voltage used. This allows for better convergence of the resistance value of the memory cell in the variable resistive memory during fine-tuning, preventing overshoot from causing the resistance value range of the memory cell to be too wide, thereby affecting subsequent operating performance. As shown in FIG4 , initializing the variable resistive memory using the present application's phased, gradually decreasing voltage pulses allows for better convergence of the resistance value of the memory cell in the variable resistive memory, resulting in a narrower resistance value range after initialization.

[0064] In this embodiment, after the memory cell in the variable resistance memory suddenly changes to a low resistance state, the resistance value of the memory cell is fine-tuned in multiple stages. The closer the resistance value of the memory cell is to the first preset value, the smaller the pulse voltage used is, which can reduce the oxygen vacancies and O 2- concentration, which is beneficial to reduce O 2- The probability of oxygen vacancies recombining with the conductive filaments or free oxygen vacancies diffusing into the conductive channel improves the data retention performance of the memory cell. As shown in Figure 5, the variable resistance memory is initialized by the staged voltage pulse of the present application. There are fewer oxygen vacancies around the conductive filaments. 2- The concentration is small.

[0065] The variable resistive memory initialization method provided by an embodiment of the present application first initializes the variable resistive memory using multiple high-voltage pulses, allowing memory cells in the variable resistive memory to quickly change from a high-resistance state to a low-resistance state. After the memory cells in the variable resistive memory change to the low-resistance state, the resistance values ​​of the memory cells are fine-tuned in multiple stages, converging the resistance distribution after initialization and improving consistency among cells in the array. Furthermore, during each stage of fine-tuning, if the total number of pulses input in that stage is greater than a second preset threshold and the resistance change rate is less than a rate threshold, the voltage for that stage is increased, and multiple pulses with increased voltage are input to the variable resistive memory until the resistance values ​​of the memory cells in the variable resistive memory reach the target resistance value for that stage. This further prevents some memory cells from not receiving sufficient energy and failing to complete initialization due to transistor voltage division or physical address-related voltage division. It also prevents memory cells that are inherently difficult to initialize from failing to complete initialization due to insufficient energy. The success rate of memory cell initialization can be significantly improved.

[0066] In an optional embodiment, step S101, inputting a plurality of pulses of a first voltage into the variable resistance memory until a memory cell in the variable resistance memory suddenly changes from a high resistance state to a low resistance state, includes:

[0067] S1011, obtaining a first electrical parameter of a memory cell in a variable resistance memory; the first electrical parameter includes at least one of a first current value and a first resistance value.

[0068] S1012: If it is determined based on the first electrical parameter that the memory cell in the variable resistive memory has not suddenly changed from the high-resistance state to the low-resistance state, a first voltage pulse is input into the variable resistive memory; then the process returns to the step of obtaining the first electrical parameter of the memory cell in the variable resistive memory until it is determined that the memory cell in the variable resistive memory has suddenly changed from the high-resistance state to the low-resistance state.

[0069] In this embodiment, with respect to step S1011, when the initialization process is initiated, a first current value or a first resistance value of a memory cell in the variable resistive memory may be obtained. The first current value of the memory cell in the variable resistive memory may be measured using a current measuring instrument, and the first resistance value of the memory cell in the variable resistive memory may be measured using a resistance measuring instrument.

[0070] In this embodiment, in step S1012, when determining whether a memory cell in the variable resistance memory has suddenly changed from a high-resistance state to a low-resistance state based on a first electrical parameter, the first electrical parameter may be compared with a target resistance value or a target voltage value. If the first electrical parameter reaches the target resistance value or the target voltage value, it is determined that the memory cell has suddenly changed from a high-resistance state to a low-resistance state. Otherwise, it is determined that the memory cell has not suddenly changed from a high-resistance state to a low-resistance state. If the memory cell has not suddenly changed from a high-resistance state to a low-resistance state, pulses of the first voltage may be repeatedly outputted.

[0071] In one implementation, for step S1012, the duration of initialization is taken into consideration. That is, to ensure initialization efficiency, the total number of pulses of the first voltage already input may also be considered before continuing to input a pulse of the first voltage into the variable resistive memory. If the total number of pulses of the first voltage already input is greater than a first preset threshold, a prompt indicating initialization failure may be given. If the total number of pulses of the first voltage already input is less than the first preset threshold, and it is determined based on the first electrical parameter that the storage unit in the variable resistive memory has not suddenly changed from a high-resistance state to a low-resistance state, then a pulse of the first voltage is input into the variable resistive memory. Therefore, in step S1012, if it is determined based on the first electrical parameter that the variable resistive memory has not suddenly changed from a high-resistance state to a low-resistance state, then a pulse of the first voltage is input into the variable resistive memory. Specifically, this may include: if the total number of pulses of the first voltage already input is less than the first preset threshold, and it is determined based on the first electrical parameter that the storage unit in the variable resistive memory has not suddenly changed from a high-resistance state to a low-resistance state, then a pulse of the first voltage is input into the variable resistive memory. If the total number of pulses of the first voltage already input is greater than the first preset threshold, then a prompt indicating initialization failure is given.

[0072] In this embodiment, by inputting pulses of the first voltage into the memory cells in the variable resistive memory one by one and determining in real time based on the first electrical parameter whether the memory cells in the variable resistive memory have suddenly changed from a high-resistance state to a low-resistance state, the memory cells can be quickly suddenly changed from a high-resistance state to a low-resistance state while avoiding overshoot.

[0073] In an optional embodiment, inputting a plurality of pulses of the i-th voltage into the variable resistance memory includes:

[0074] Obtaining an i-th electrical parameter of a memory cell in the variable resistive memory; the i-th electrical parameter includes at least one of an i-th current value and an i-th resistance value; if it is determined based on the i-th electrical parameter that the resistance value of the memory cell in the variable resistive memory does not reach an i-th preset value, inputting a pulse of an i-th voltage into the variable resistive memory; and then returning to the step of obtaining the i-th electrical parameter of the memory cell in the variable resistive memory.

[0075] In one embodiment, to consider the duration of initialization, that is, to ensure initialization efficiency, before inputting a pulse of the i-th voltage into the variable resistive memory, the total number of pulses input during the resistance fine-tuning phase and the total number of pulses of the i-th voltage input during the current phase may also be considered. If the total number of pulses input during the resistance fine-tuning phase is greater than a third preset threshold, or the total number of pulses of the i-th voltage input is greater than a second preset threshold, an initialization failure message is directly displayed. If the total number of pulses input during the resistance fine-tuning phase is less than the third preset threshold, the total number of pulses of the i-th voltage input is less than the second preset threshold, and it is determined based on the i-th electrical parameter that the resistance value of the memory cell in the variable resistive memory has not reached the i-th preset value, a pulse of the second voltage is input into the variable resistive memory.

[0076] Therefore, if it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory does not reach the i-th preset value, then a pulse of the i-th voltage is input into the variable resistive memory. Specifically, the method may include: if the total number of pulses of the i-th voltage that have been input is less than the second preset threshold, the total number of pulses that have been input is less than the third preset threshold, and if it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory does not reach the i-th preset value, then a pulse of the i-th voltage is input into the variable resistive memory.

[0077] In this embodiment, by inputting pulses of the i-th voltage into the memory cells of the variable resistance memory one by one and determining in real time based on the i-th electrical parameter whether the memory cells in the variable resistance memory have completed the target of the i-th stage, the overshoot phenomenon can be avoided.

[0078] In an optional embodiment, if the total number of pulses of the i-th voltage inputted is greater than a second preset threshold value and the resistance change rate is less than a rate threshold value, the i-th voltage is increased, and a plurality of pulses of the increased i-th voltage are inputted into the variable resistive memory until the resistance value of a memory cell in the variable resistive memory reaches an i-th preset value, including:

[0079] If the total number of pulses of the i-th voltage that have been input is greater than the second preset threshold, the total number of pulses that have been input is less than the third preset threshold, and the resistance change rate is less than the rate threshold, then multiple pulses of the increased i-th voltage are input into the variable resistive memory until the resistance value of the storage cell in the variable resistive memory reaches the i-th preset value.

[0080] In this embodiment, for some memory cells whose resistance states are difficult to converge, when a pulse of the i-th voltage of the second preset threshold is input into the variable resistance memory and it still cannot reach the stage target, in order to successfully complete the initialization, meet the requirements of resistance state convergence, and improve the efficiency of resistance state convergence, that is, to balance the efficiency and success rate of initialization, in the resistance state fine-tuning stage, when the total number of pulses inputted is less than the third preset threshold, the total number of pulses of the i-th voltage inputted is greater than the second preset threshold, and the resistance change rate is less than the rate threshold, it can be considered to input a pulse with stronger energy into the variable resistance memory.

[0081] In a specific implementation, in the initial stage of resistance state fine-tuning, the voltage acceleration coefficient can be set to 1, and then the voltage acceleration coefficient is multiplied by the i-th voltage to obtain the voltage value of the i-th voltage. The i-th voltage corresponding to the voltage value is input into the variable resistance memory. If the total number of pulses of the i-th voltage input is greater than the second preset threshold, and the total number of pulses input is less than the third preset threshold, the total number of pulses of the i-th voltage input is set to 0. The resistance change rate is calculated based on the calculation formula. The calculation formula is:

[0082] Wherein Δσ is the resistance change rate, I2 is the current value when the total number of pulses of the i-th voltage inputted is the second preset threshold value, I1 is the current value when the total number of pulses of the i-th voltage inputted is 1, and V is the voltage value of the i-th voltage.

[0083] The resistance change rate and the rate threshold are then determined. If the resistance change rate is less than the rate threshold, the predetermined voltage acceleration coefficient is updated based on a preset formula: β = β1 * (1 + x%), where β is the new voltage acceleration coefficient, β1 is the previously set voltage acceleration coefficient, and x is the preset value. The updated voltage acceleration coefficient is then multiplied by the i-th voltage to obtain the i-th voltage value. The i-th voltage corresponding to this voltage value is then input into the variable resistance memory until it is determined that the resistance value of the storage cell in the variable resistance memory has reached the i-th preset value.

[0084] The embodiment of the present application further provides an initialization device for a variable resistance memory, as shown in FIG6 , comprising:

[0085] The first input unit 61 is used to input a plurality of pulses of a first voltage into the variable resistance memory until the memory cell in the variable resistance memory suddenly changes from a high resistance state to a low resistance state;

[0086] a second input unit 62 for inputting a plurality of second voltage pulses into the variable resistance memory until the resistance value of a memory cell in the variable resistance memory reaches a second preset value, wherein the second preset value is less than the resistance value of the memory cell when the memory cell suddenly changes from a high resistance state to a low resistance state;

[0087] a third input unit 63 for inputting a plurality of pulses of a third voltage into the variable resistance memory until the resistance value of a storage unit in the variable resistance memory reaches a third preset value, wherein the third preset value is less than the second preset value;

[0088] This is repeated in this manner until the Nth input unit 6N is used to input a plurality of Nth voltage pulses into the variable resistance memory until the resistance value of the memory cell in the variable resistance memory reaches an Nth preset value; wherein N is greater than or equal to 3, the voltage values ​​of the first voltage, the second voltage, the third voltage, ... the Nth voltage gradually decrease, the Nth preset value is less than the N-1th preset value, and the Nth preset value is the target resistance value that the memory cell needs to reach to complete initialization;

[0089] The method of inputting a plurality of pulses of an i-th voltage into the variable resistive memory until the resistance value of a storage unit in the variable resistive memory reaches an i-th preset value includes: inputting a plurality of pulses of an i-th voltage into the variable resistive memory, and if the total number of pulses of the i-th voltage inputted is greater than a second preset threshold value and the resistance change rate is less than a rate threshold value, increasing the i-th voltage, and inputting a plurality of pulses of the increased i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, where i is any one of 2, 3…N-1, or N.

[0090] The variable resistive memory initialization device provided in an embodiment of the present application first initializes the variable resistive memory using multiple high-voltage pulses, allowing memory cells in the variable resistive memory to quickly change from a high-resistance state to a low-resistance state. After the memory cells in the variable resistive memory change to the low-resistance state, the resistance value of the memory cells is fine-tuned in multiple stages, with the pulse voltage in each stage being the same. This converges the resistance distribution after initialization and improves consistency among cells in the array. Furthermore, during each stage of fine-tuning, if the total number of pulses input in that stage is greater than a second preset threshold and the resistance change rate is less than a rate threshold, the voltage for that stage is increased, and multiple pulses with increased voltage are input to the variable resistive memory until the resistance value of the memory cells in the variable resistive memory reaches the target value for that stage. This further prevents some memory cells from not receiving sufficient energy and failing to complete initialization due to transistor voltage division or physical address-related voltage division. It also prevents memory cells that are inherently difficult to initialize from failing to complete initialization due to insufficient energy, significantly improving the success rate of memory cell initialization.

[0091] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

[0092] FIG7 shows a schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0093] As shown in Figure 7, electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In RAM 803, various programs and data required for the operation of electronic device 800 can also be stored. Computing unit 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to bus 804.

[0094] Multiple components in the electronic device 800 are connected to the I / O interface 805, including an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0095] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the initialization method of the variable resistance memory. For example, in some embodiments, the initialization method of the variable resistance memory may be implemented as a computer software program that is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the initialization method of the variable resistance memory described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the initialization method of the variable resistance memory in any other appropriate manner (for example, by means of firmware).

[0096] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the program code is executed by the processor or controller, the functions / operations specified in the flow charts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0098] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0100] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0101] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0102] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not a limitation herein.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0104] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for initializing a variable resistance memory, wherein: include: Inputting a plurality of pulses of a first voltage into the variable resistance memory until a storage unit in the variable resistance memory suddenly changes from a high resistance state to a low resistance state; Inputting a plurality of pulses of a second voltage into the variable resistance memory until the resistance value of a storage unit in the variable resistance memory reaches a second preset value, wherein the second preset value is less than the resistance value of the storage unit when the storage unit suddenly changes from a high resistance state to a low resistance state; Inputting a plurality of pulses of a third voltage into the variable resistance memory until the resistance value of a storage unit in the variable resistance memory reaches a third preset value, wherein the third preset value is less than the second preset value; And so on, until a plurality of Nth voltage pulses are input into the variable resistive memory, until the resistance value of the storage unit in the variable resistive memory reaches the Nth preset value; wherein N is greater than or equal to 3, the voltage values ​​of the first voltage, the second voltage, the third voltage ... the Nth voltage gradually decrease, the Nth preset value is less than the N-1th preset value, and the Nth preset value is the target resistance value that the storage unit needs to reach to complete initialization; Among them, inputting multiple pulses of the i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, includes: inputting multiple pulses of the i-th voltage into the variable resistive memory, if the total number of pulses of the i-th voltage input is greater than a second preset threshold value, and the resistance change rate is less than a rate threshold, then increasing the i-th voltage, and inputting multiple pulses of the increased i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, i is any one of 2, 3...N-1, N.

2. The method for initializing a variable resistance memory according to claim 1, wherein: Inputting a plurality of pulses of a first voltage into a variable resistance memory until a storage unit in the variable resistance memory changes from a high resistance state to a low resistance state, comprising: Acquire a first electrical parameter of a storage unit in the variable resistance memory; the first electrical parameter includes at least one of a first current value and a first resistance value; If it is determined based on the first electrical parameter that the storage unit in the variable resistance memory has not suddenly changed from a high resistance state to a low resistance state, a pulse of a first voltage is input into the variable resistance memory; then the process returns to the step of obtaining the first electrical parameter of the storage unit in the variable resistance memory until it is determined that the storage unit in the variable resistance memory has suddenly changed from a high resistance state to a low resistance state.

3. The method for initializing a variable resistance memory according to claim 2, wherein: If it is determined based on the first electrical parameter that the variable resistance memory does not suddenly change from a high resistance state to a low resistance state, inputting a first voltage pulse into the variable resistance memory, comprising: If the total number of pulses of the input first voltage is less than a first preset threshold, and it is determined based on the first electrical parameter that the storage unit in the variable resistance memory has not suddenly changed from a high resistance state to a low resistance state, a first voltage pulse is input into the variable resistance memory.

4. The method for initializing a variable resistance memory according to claim 1, wherein: Inputting a plurality of pulses of an i-th voltage into the variable resistance memory comprises: Acquire an i-th electrical parameter of a storage unit in the variable resistive memory; the i-th electrical parameter comprises at least one of an i-th current value and an i-th resistance value; If it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory does not reach the i-th preset value, a pulse of the i-th voltage is input into the variable resistive memory; then the step of obtaining the i-th electrical parameter of the storage unit in the variable resistive memory is returned to.

5. The method for initializing a variable resistance memory according to claim 4, wherein: If it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory does not reach the i-th preset value, inputting a pulse of an i-th voltage into the variable resistive memory, comprising: If the total number of pulses of the i-th voltage that have been input is less than the second preset threshold, the total number of pulses that have been input is less than the third preset threshold, and it is determined based on the i-th electrical parameter that the resistance value of the storage unit in the variable resistive memory has not reached the i-th preset value, then a pulse of the i-th voltage is input into the variable resistive memory.

6. The method for initializing a variable resistance memory according to claim 1, wherein: If the total number of pulses of the i-th voltage inputted is greater than a second preset threshold value, and the resistance change rate is less than a rate threshold value, the i-th voltage is increased, and a plurality of pulses of the i-th voltage after the increase are inputted into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, comprising: If the total number of pulses of the i-th voltage that have been input is greater than the second preset threshold, the total number of pulses that have been input is less than the third preset threshold, and the resistance change rate is less than the rate threshold, then a plurality of pulses of the increased i-th voltage are input into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value.

7. The method for initializing a variable resistance memory according to claim 1, wherein: The resistance change rate calculation formula includes: Wherein Δσ is the resistance change rate, I2 is the current value when the total number of pulses of the i-th voltage input is the second preset threshold, I1 is the current value when the total number of pulses of the i-th voltage input is 1, and V is the voltage value of the i-th voltage.

8. An initialization device for a variable resistance memory, wherein: include: A first input unit, used for inputting a plurality of pulses of a first voltage into the variable resistance memory, until a storage unit in the variable resistance memory suddenly changes from a high resistance state to a low resistance state; A second input unit, used for inputting a plurality of second voltage pulses into the variable resistive memory until the resistance value of a storage unit in the variable resistive memory reaches a second preset value, wherein the second preset value is less than the resistance value of the storage unit when the storage unit suddenly changes from a high resistance state to a low resistance state; a third input unit, configured to input a plurality of pulses of a third voltage into the variable resistive memory until the resistance value of a storage unit in the variable resistive memory reaches a third preset value, wherein the third preset value is less than the second preset value; And so on, until the Nth input unit is used to input multiple Nth voltage pulses into the variable resistive memory, until the resistance value of the storage unit in the variable resistive memory reaches the Nth preset value; wherein N is greater than or equal to 3, the voltage values ​​of the first voltage, the second voltage, the third voltage ... the Nth voltage gradually decrease, the Nth preset value is less than the N-1th preset value, and the Nth preset value is the target resistance value that the storage unit needs to reach to complete initialization; Among them, inputting multiple pulses of the i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, includes: inputting multiple pulses of the i-th voltage into the variable resistive memory, if the total number of pulses of the i-th voltage input is greater than a second preset threshold value, and the resistance change rate is less than a rate threshold, then increasing the i-th voltage, and inputting multiple pulses of the increased i-th voltage into the variable resistive memory until the resistance value of the storage unit in the variable resistive memory reaches the i-th preset value, i is any one of 2, 3...N-1, N.

9. An electronic device, wherein: include: at least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor executes the variable resistive memory initialization method as described in any one of claims 1-7.

10. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the variable resistance memory initialization method according to any one of claims 1 to 7.

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