Microphone signal conversion module and microphone module

Abstract

A microphone signal conversion module (1) comprises: a buffer circuit (2) that outputs a second analog signal (Sa2) obtained by performing level conversion with a first gain (G1) for a first analog signal (Sa1) inputted from a transducer; an analog-digital conversion circuit (3) that converts the level of the second analog signal (Sa2) into a digital value with a second gain (G2); and a control circuit (4) that controls the first gain (G1) and the second gain (G2). The second analog signal (Sa2) is inputted to the control circuit (4). The control circuit (4) controls, on the basis of the level of the second analog signal (Sa2), the magnitudes of the first gain (G1) and the second gain (G2) in directions opposite to each other.

Description

Microphone signal conversion module and microphone module

[0001] The present invention relates to a microphone signal conversion module and a microphone module.

[0002] Conventionally, transducers that convert various types of energy into different types of energy have been widely used in both industrial and consumer applications. Microphones are one example of such transducers. With the development of interactive devices due to recent dramatic advances in natural language processing technology and voice recognition technology, the usefulness and demand for microphone devices have increased. A transducer functioning as a microphone detects sound and converts it into an analog electrical signal. Therefore, in many applications, the electrical signal generated by the microphone is converted into a digital signal and input to a signal processing device such as a microcomputer, as in the microphone device disclosed in Patent Document 1, for example.

[0003] Japanese Patent Application Laid-Open No. 2004-120310

[0004] In a device such as that disclosed in Patent Document 1, which converts analog electrical signals such as audio signals into digital signals, the electrical signal input from a microphone or the like is amplified to a level suitable for an analog-to-digital converter (AD converter) before conversion. Such an electronic module that converts the level and form of the analog signal is required to ensure a sufficient signal-to-noise ratio (SNR) so that the signal detected by the microphone is not buried in noise such as conversion errors.

[0005] On the other hand, electronic modules that amplify and convert signals from small transducers, such as MEMS (Micro Electro Mechanical Systems) microphones, are often required to operate at low voltages and low current consumption. Furthermore, to meet the ongoing demand for miniaturization of various devices that incorporate microphones, there is also a constant demand for miniaturization of microphone electronic modules themselves. In theory, it can be difficult to ensure a sufficient signal-to-noise ratio with low-voltage, low-current, and small-sized electronic modules that amplify and convert signals from such microphones.

[0006] One way to improve the S / N ratio is to increase the gain of amplifier (preamplifier) ​​901 in the stage preceding AD converter 910 in a microphone amplifier 900 as shown in Fig. 8A. AD converter 910 is a typical delta-sigma AD converter, and includes a subtractor 902, an integrator 903, a quantizer 904, and a 1-bit DA converter 905.

[0007] Increasing the gain of the preamplifier 901 increases the signal input to the AD converter 910, thereby increasing the apparent S / N ratio. However, when the gain of the preamplifier 901 is increased in this manner, if the amplitude of the input signal Vi is large, the output signal Vo may become saturated, as shown by the signal Voa in FIG. 8B. Note that the signal Voa shown in FIG. 8B is an analog signal obtained by passing the output signal Vo of the AD converter 910 through an appropriate low-pass filter (the output signals So and Voa shown in FIGS. 6A, 9, and 10, respectively, which will be referred to sequentially below, are also output signals that have passed through a low-pass filter).

[0008] That is, in FIG. 8B, the signal Via input to the AD converter 910 is saturated near the extreme value of the amplitude of the input signal Vi (within part P in FIG. 8B). As a result, the delta-sigma AD converter 910 does not perform an appropriate conversion operation, and the signal Voa does not reproduce the input signal Vi. As such, simply increasing the gain of the amplifier in the stage preceding the AD converter to improve the S / N ratio can result in a reduced dynamic range. Therefore, there is a problem in that it is difficult for an electronic module that handles microphone signals to fully achieve the required performance in both S / N ratio and dynamic range.

[0009] In view of the above problems, an object of the present invention is to enable conversion of an analog signal from a transducer into a digital value without sacrificing the dynamic range and with a good S / N ratio.

[0010] A microphone signal conversion module according to one embodiment of the present invention includes a buffer circuit that performs level conversion with a first gain on a first analog signal input from a transducer and outputs a second analog signal obtained by the level conversion, an analog-to-digital conversion circuit that converts the level of the second analog signal into a digital value with a second gain, and a control circuit that controls the first gain and the second gain, wherein the second analog signal is input to the control circuit and the control circuit is configured to control the magnitudes of the first gain and the second gain in opposite directions based on the level of the second analog signal.

[0011] A microphone module according to one embodiment of the present invention includes the microphone signal conversion module and a MEMS transducer that generates the first analog signal.

[0012] According to the microphone signal conversion module and microphone module of the present invention, an analog signal from a transducer can be converted into a digital value with a good S / N ratio without sacrificing the dynamic range.

[0013] 1 is a block diagram showing an example of a microphone signal conversion module and a microphone module according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a buffer circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a buffer circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a buffer circuit according to an embodiment of the present invention. FIG. 4 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 5 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 6 is a block diagram showing an example of an AD conversion circuit according to an embodiment of the present invention. FIG. 7 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 8 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 9 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 10 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 11 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 12 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. FIG. 13 is a block diagram showing an example of a control circuit according to an embodiment of the present invention.

[0014] Embodiments of a microphone signal conversion module and a microphone module of the present invention will be described with reference to the drawings. Note that the embodiments described below merely show some of the possible aspects of the microphone signal conversion module and the microphone module of the present invention. The microphone signal conversion module and the microphone module of the present invention are not limited to the embodiments described below.

[0015] 1 shows a microphone signal conversion module 1, which is an example of a microphone signal conversion module of an embodiment, and a microphone module 10, which is an example of a microphone module of an embodiment and includes the microphone signal conversion module 1. The microphone signal conversion module of the embodiment described below is also simply referred to as a "microphone signal module."

[0016] 1, a microphone signal module 1 of this embodiment includes a buffer circuit 2 that converts the level of an analog signal and outputs it, an analog-to-digital conversion circuit (AD conversion circuit) 3 that converts the level of the analog signal into a digital value, and a control circuit 4. In the example of FIG. 1, a microphone module 10 of this embodiment includes the microphone signal module 1 and a microphone 11.

[0017] The microphone signal module 1 of FIG. 1 further includes a constant voltage source 5 and an output buffer 6. The constant voltage source 5 generates a constant voltage Vc as a bias voltage for operating the microphone 11 and provides it to the microphone 11. The constant voltage source 5 is configured, for example, by a linear regulator such as a low dropout (LDO) regulator or a switching regulator. The output buffer 6 receives a digital signal Sd1 from the AD conversion circuit 3. The output buffer 6 outputs the digital signal Sd1 with an output impedance and driving capability required for an external device (not shown) connected to the output terminal Sout of the microphone signal module 1. The output buffer 6 is configured, for example, by a non-inverting inverter or a composite circuit of transistors.

[0018] The buffer circuit 2 performs level conversion on the first analog signal Sa1 input from the microphone 11 using a first gain G1 and outputs a second analog signal Sa2 obtained by the level conversion. The AD conversion circuit 3 converts the level of the second analog signal Sa2 into a digital value using a second gain G2 and outputs a digital signal Sd1, which is the converted signal. The second analog signal Sa2 is input to the control circuit 4 from the buffer circuit 2. The control circuit 4 controls the first gain G1 of the buffer circuit 2 and the second gain G2 of the AD conversion circuit 3 by outputting control signals Sc1 and Sc2 based on the level of the second analog signal Sa2. That is, the buffer circuit 2 is configured so that the first gain G1 can be controlled, i.e., adjusted, from outside the buffer circuit 2. The AD conversion circuit 3 is configured so that the second gain G2 can be controlled, i.e., adjusted, from outside the AD conversion circuit 3.

[0019] As is commonly used, the first gain G1 of the buffer circuit 2 is the ratio of the level (absolute value) of the output signal output based on the input signal to the level (absolute value) of the input signal. Meanwhile, the second gain G2 of the AD conversion circuit 3 indicates the amount of change in the output digital value applied per unit change in the level of the input analog signal. For example, when the second gain G2 is 0 dB, converting the output signal of the AD conversion circuit 3 into an analog signal results in an analog signal having a voltage amplitude that is 1 times the voltage amplitude of the analog signal input to the AD conversion circuit 3. In another example, when the second gain G2 is 20 dB, similarly converting the output signal of the AD conversion circuit 3 into an analog signal results in an analog signal having a voltage amplitude that is 10 times the voltage amplitude of the input analog signal.

[0020] Specifically, the control circuit 4 is configured to control the magnitudes of the first gain G1 and the second gain G2 in opposite directions based on the level of the second analog signal Sa2. That is, the control circuit 4 decreases the second gain G2 when increasing the first gain G1 based on the level of the second analog signal Sa2, and increases the second gain G2 when decreasing the first gain G1. By controlling the first gain G1 and the second gain G2 in this manner, the linearity of the output signal relative to the input signal of the microphone signal module 1 can be maintained constant.

[0021] In the microphone signal module 1 of the embodiment including the control circuit 4 configured as described above, as an example, the first gain G1 in the default state (basic state, initial state, or factory default state) is set to a relatively large value. By doing so, the amplitude of the second analog signal Sa2 can be increased even when the amplitude of the input signal (first analog signal Sa1) is small. Therefore, the S / N ratio can be improved. The second gain G2 is set to a relatively small value corresponding to the relatively large first gain G1. Therefore, the digital signal Sd1 having a magnitude corresponding to the level of the first analog signal Sa1 is obtained as the output of the AD conversion circuit 3.

[0022] On the other hand, when the amplitude of the first analog signal Sa1 is large enough to cause signal saturation within the microphone signal module 1, the control circuit 4 reduces the first gain G1 to reduce (compress) the amplitude of the second analog signal Sa2. This prevents signal saturation within the microphone signal module 1, thereby avoiding a reduction in the dynamic range.

[0023] When the control circuit 4 reduces the first gain G1 in this manner, it also increases the second gain G2. That is, the signal is expanded during the conversion from the second analog signal Sa2 to the digital signal Sd1. This compensates for the attenuation of the output signal (digital signal Sd1) caused by reducing the first gain G1. This makes it possible to obtain an output signal (digital signal Sd1) that can faithfully reproduce the relatively large amplitude of the input signal (first analog signal Sa1). That is, it is possible to prevent, or at least suppress, a reduction in the dynamic range.

[0024] Furthermore, the gain (sensitivity) of the entire microphone signal module 1 can be kept constant regardless of the amplitude of the input signal, from small to large. Moreover, a good S / N ratio can be ensured even when the amplitude of the input signal is small. Therefore, according to this embodiment, an analog signal from a transducer such as the microphone 11 can be converted into a digital value with a good S / N ratio without sacrificing the dynamic range.

[0025] The microphone signal module 1 of this embodiment can receive an input signal (first analog signal Sa1) from a transducer of any type and structure that can convert sound into an electrical signal, not limited to the microphone 11. In other words, the transducer that inputs the input signal to the microphone signal module 1 does not have to be intended for use as a microphone. The microphone signal module 1 can receive, as the first analog signal Sa1, a signal from any transducer that can convert air vibrations at any frequency, not limited to the audible range, into an electrical signal.

[0026] In particular, a signal generated by a MEMS transducer that uses MEMS technology as a mechanism for detecting air vibrations may be input to the microphone signal module 1 as the first analog signal Sa1. Therefore, the microphone 11 in the example of FIG. 1 may be a MEMS microphone. Similarly, the microphone module 10 of the embodiment may include the microphone signal module 1 and a MEMS transducer that generates the first analog signal Sa1. The microphone 11 included in the microphone module 10 in the example of FIG. 1 may be a MEMS microphone. It is believed that including a MEMS microphone will result in a microphone module 10 that has good performance, such as small size and high heat resistance.

[0027] Below, we will explain an example and some modified examples of each of the buffer circuit 2, the control circuit 4, and the AD conversion circuit 3. Note that the configuration of each circuit described below is merely an example of each circuit, and the configuration of each circuit is not limited to the configuration described below.

[0028] <Example of Buffer Circuit (Inverting Type)> Figure 2A shows an example of a possible configuration of the buffer circuit 2 of the microphone signal module of this embodiment. As shown in Figure 2A, the buffer circuit 2 includes an operational amplifier 21 and multiple capacitors (capacitors 22 and 23). The operational amplifier 21 has an inverting input terminal that receives a first analog signal Sa1 from a transducer such as the microphone 11, and a non-inverting input terminal to which a reference potential Vref is applied. The capacitors 22 and 23 are arranged in parallel between the output terminal and the inverting input terminal of the operational amplifier 21. In Figure 2A, the capacitance of the capacitor 22 is fixed, while the capacitor 23 is a variable capacitor whose capacitance is adjustable.

[0029] The reference potential Vref is generated independently of the constant voltage Vc by, for example, a voltage source (not shown) separate from the constant voltage source 5 in Fig. 1. The reference potential Vref may be, for example, the midpoint potential of the maximum amplitude of the first analog signal Sa1 or the midpoint potential between the positive and negative power supplies of the operational amplifier 21 (between the power supply and ground in the case of a single power supply).

[0030] If the microphone 11 is a capacitive transducer such as a capacitive MEMS microphone, it has an inherent capacitance. Therefore, the first gain G1 of the buffer circuit 2 with respect to the AC component of the first analog signal Sa1 is expressed by the following (Equation 1): G1=C11 / (C22+C23) (Equation 1), where C11, C22, and C23 are the capacitances of the microphone 11, capacitor 22, and capacitor 23, respectively. Therefore, the control circuit 4 (see FIG. 1) can adjust the first gain G1 by adjusting the capacitance of capacitor 23.

[0031] 2B shows a more specific example of the configuration of the buffer circuit 2 of FIG. 2A. FIG. 2B shows a more specific example of the capacitor 23, the capacitance of which is adjustable. As shown in FIG. 2B, the capacitor 23 is made up of a plurality of capacitors for adjusting the first gain G1, namely, capacitors 231, 232, 233, ..., 23n. In this way, the buffer circuit 2 includes a plurality of capacitors arranged between the output terminal and the inverting input terminal of the operational amplifier 21.

[0032] Furthermore, the buffer circuit 2 includes a plurality of switches 24 and a plurality of switches 25. Each switch 25 is arranged between one end of one of capacitors 231 to 23n, which are part of the plurality of capacitors between the output terminal and inverting input terminal of the operational amplifier 21, and the inverting input terminal of the operational amplifier 21. Each switch 25 connects or disconnects one of the capacitors 231 to 23n to which the switch 25 is connected, and the inverting input terminal of the operational amplifier 21. Meanwhile, each switch 24 is connected in parallel with one of the capacitors 231 to 23n. When each switch 24 is closed, the capacitor of the capacitors 231 to 23n that is connected in parallel to the closed switch 24 is discharged.

[0033] In the buffer circuit 2 configured as shown in FIG. 2B, the combined capacitance of capacitor 22 and capacitor 23 can be adjusted by closing a desired number of switches 25. That is, the first gain G1 can be adjusted. According to the above (Equation 1), by closing switch 25, the capacitances 231 to 23n connected to operational amplifier 21 via switch 25 can be increased, thereby reducing first gain G1. Therefore, control circuit 4 may be configured to control first gain G1 by opening and closing switch 25. For example, when the amplitude of first analog signal Sa1 is large, control circuit 4 (see FIG. 1) can attenuate second analog signal Sa2 by closing switch 25.

[0034] 2B, by closing switch 24, it is possible to discharge, among capacitors 231 to 23n, those that do not contribute to the adjustment of first gain G1, i.e., those that are not connected to operational amplifier 21 via switch 25. Control circuit 4 is configured to discharge, by closing switch 24, those of capacitors that make up capacitor 23 that do not contribute to setting first gain G1.

[0035] As described above, the capacitors 231 to 23n are preferably configured to discharge when they are isolated from the inverting input terminal of the operational amplifier 21 by the switch 25. By discharging the capacitors 231 to 23n in this manner, the amount of charge stored between the input and output terminals of the operational amplifier 21 is correctly maintained when these isolated capacitors are connected to the operational amplifier 21 and the first gain G1 is switched. Therefore, theoretically, no DC offset occurs in the second analog signal Sa2 due to switching of the first gain G1. Therefore, the first gain G1 can be switched even when the first analog signal Sa1 is not crossing zero (or crossing the midpoint potential).

[0036] As described above, when the second analog signal Sa2 is to be attenuated, the switch 25 is closed. On the other hand, a state in which all the switches 25 are open and all the switches 24 are closed may be the default state of the microphone signal module. In this state in which all the switches 25 are open, as is clear from the above (Equation 1), the first gain G1 is determined by the ratio between the capacitance of the capacitor 22 and the capacitance of the microphone 11. Not limited to this default state, the first gain G1 depends on the capacitance of a transducer such as the microphone 11, as shown in (Equation 1).

[0037] However, the amount of change in the first gain G1 caused by closing the switch 25 (e.g., the amount of attenuation of the second analog signal Sa2 caused by closing one switch 25) is determined by the ratio of C22 to C23 in the denominator of the above equation (1). That is, the attenuation rate ∂G1 of the first gain G1 caused by adjusting the capacitance of the capacitor 23 is expressed by the following equation (2): ∂G1 = 1 + (C22 / C23) (Equation 2). As an example, if the microphone signal module of the embodiment is configured on a semiconductor substrate, the capacitors 22 and 23 are formed on the semiconductor substrate. In such a case, it is relatively easy to accurately configure the ratio between the capacitance of the capacitor 22 and the capacitance of each of the capacitors 231 to 23n. Therefore, it may be relatively easy to correctly configure the amount of change in the first gain G1 caused by closing the switch 25.

[0038] Therefore, by configuring the element that determines the second gain G2 on a semiconductor substrate, like the capacitors 22 and 23, it may be possible to easily ensure good linearity in the microphone signal module even if the capacitance of the microphone 11 varies. Thus, in the inverting buffer circuit 2 illustrated in Figures 2A and 2B, the first gain G1 depends on the variation in capacitance of the transducer, such as the microphone 11. However, it is considered relatively easy to ensure linearity in the signal conversion of the microphone signal module, which involves controlling each gain. Incidentally, fluctuations in the first gain G1 due to variations in the capacitance of the transducer can be compensated for using conventional adjustment methods.

[0039] <Another Example of Buffer Circuit (Normal Type)> FIG. 3A shows another example of a possible configuration of the buffer circuit 2 of the microphone signal module of this embodiment. In the example shown in FIG. 3A , the buffer circuit 2 includes a non-inverting buffer 26 and a capacitor 27. The non-inverting buffer 26 has an input terminal that receives the first analog signal Sa1 sent from the microphone 11. As an example, the non-inverting buffer 26 is an operational amplifier whose inverting input terminal and output terminal are connected to form a voltage follower. The non-inverting input terminal of the operational amplifier may be the input terminal of the non-inverting buffer 26 in FIG. 3A . In the example of FIG. 3A , the microphone 11 is a capacitive transducer such as a capacitive MEMS microphone. The capacitor 27 is arranged between the input terminal of the non-inverting buffer 26 and a reference potential Vref, which is a predetermined constant potential. The capacitor 27 is a variable capacitor whose capacitance is adjustable.

[0040] The reference potential Vref is generated independently of the constant voltage Vc by, for example, a voltage source (not shown) separate from the constant voltage source 5 in Fig. 1. The reference potential Vref may be, for example, the midpoint potential of the maximum amplitude of the first analog signal Sa1 or the midpoint potential between the positive and negative power supplies of the operational amplifier 21 (between the power supply and ground in the case of a single power supply).

[0041] The microphone 11, which is a capacitive transducer, has an inherent capacitance. Therefore, the first gain G1 of the buffer circuit 2 with respect to the AC component of the first analog signal Sa1 is expressed by the following equation (3): G1=C11 / (C11+C27) (Equation 3), where C11 and C27 are the capacitances of the microphone 11 and capacitor 27, respectively. Therefore, the control circuit 4 (see FIG. 1) can adjust the first gain G1 by adjusting the capacitance of the capacitor 27.

[0042] 3B shows a more specific example of the configuration of the buffer circuit 2 of FIG. 3A. FIG. 3B shows a more specific example of the capacitor 27, the capacitance of which is adjustable. As shown in FIG. 3B, the capacitor 27 is made up of a plurality of capacitors, 271, 272, 273, ... 27n, for adjusting the first gain G1. That is, the buffer circuit 2 includes a plurality of capacitors, each of which is arranged between the input terminal of the non-inverting buffer 26 and a reference potential Vref, which is a predetermined constant potential.

[0043] Furthermore, the buffer circuit 2 includes a plurality of switches 28 and a plurality of switches 29. Each switch 29 is disposed between the input terminal of the non-inverting buffer 26 and one end of one of the capacitors 271 to 27n. The switch 29 connects or disconnects the plurality of capacitors 271 to 27n and the input terminal of the non-inverting buffer 26. Meanwhile, each switch 28 is connected in parallel with one of the capacitors 271 to 27n. When each switch 28 is closed, the capacitor among the capacitors 271 to 27n that is connected in parallel to the closed switch 28 is discharged.

[0044] In the buffer circuit 2 configured as shown in FIG. 3B, the capacitance of the capacitor 27 can be adjusted, thereby adjusting the first gain G1, by closing a desired number of switches 29. According to the above (Equation 3), by closing the switch 29, the capacitances 271 to 27n connected to the non-inverting buffer 26 can be increased, thereby decreasing the first gain G1. Therefore, the control circuit 4 may be configured to control the first gain G1 by opening and closing the switch 29. For example, when the amplitude of the first analog signal Sa1 is large, the control circuit 4 (see FIG. 1) can attenuate the second analog signal Sa2 by closing the switch 29.

[0045] 3B, the capacitors of capacitors 271 to 27n that are not connected to non-inverting buffer 26 via switch 29 can be discharged by closing switch 28. Control circuit 4 is configured to discharge the capacitors that do not contribute to setting first gain G1, among the capacitors that make up capacitor 27, by closing switch 28.

[0046] The capacitors 271 to 27 n are preferably configured to discharge when they are isolated from the input terminal of the non-inverting buffer 26 by the switch 29 as described above. By discharging the capacitors 271 to 27 n in this manner, when these isolated capacitors are connected to the non-inverting buffer 26 and the first gain G1 is switched, the amount of charge stored in the capacitor connected to the non-inverting buffer 26 is maintained correctly. Therefore, theoretically, no DC offset occurs in the second analog signal Sa2 due to switching of the first gain G1. Therefore, the first gain G1 can be switched even when the first analog signal Sa1 is not crossing zero (or crossing the midpoint potential).

[0047] As described above, when the second analog signal Sa2 is to be attenuated, the switch 29 is closed. On the other hand, the default state of the microphone signal module may be a state in which all the switches 29 are open and all the switches 28 are closed. In this state in which all the switches 29 are open, as is clear from the above (Equation 3), the first gain G1 is 1 (0 dB). Therefore, in the example of FIG. 3B, it is considered that there is little variation in the first gain G1 in the default state.

[0048] On the other hand, the amount of change in the first gain G1 caused by closing the switch 29 (for example, the amount of attenuation of the second analog signal Sa2 caused by closing one switch 29) is determined by the ratio of C11 to C27 in the denominator of the above (Equation 3). That is, the attenuation rate ∂G1 of the first gain G1 caused by adjusting the capacitance of the capacitor 27 is expressed by the following (Equation 4): ∂G1=1+(C11 / C27) (Equation 4) Therefore, the amount of change in the first gain G1 depends on the variation in the capacitance C11 of the capacitive transducer.

[0049] Because capacitance C11 varies independently of capacitance C27 of capacitor 27, the amount of change in first gain G1 relative to the amount of adjustment of capacitance C27 varies depending on the variation in capacitance C11. Therefore, in the operating region where one of switches 29 is closed to attenuate second analog signal Sa2, linearity between the input of buffer circuit 2 and the output of AD conversion circuit 3 (see FIG. 1) may not be maintained depending on the variation in the capacitance of the transducer. For example, in a plot diagram where the horizontal and vertical axes represent the input and output, the relationship between the two is shown as a straight line in the region of small input values, but as the input value increases or decreases, the relationship is shown as a curve with a gradually increasing or decreasing slope. Therefore, to compensate for the variation in the capacitance of the transducer, the amount of feedback within AD conversion circuit 3 (see FIG. 1) is preferably adjusted. This adjustment will be described in detail later with reference to FIG. 7.

[0050] The capacitors 231 to 23n in Fig. 2B and the capacitors 271 to 27n in Fig. 3B are arranged in numbers corresponding to the number of set values ​​required for the first gain G1. The same number of switches 24 and switches 25 as the number of capacitors 231 to 23n are provided. Similarly, the same number of switches 28 and switches 29 as the number of capacitors 271 to 27n are provided. By providing n capacitors 231 to 23n or n capacitors 271 to 27n, the first gain G1 can be set to n values ​​other than the value in the default state.

[0051] <Control Circuit> Figure 4 is a block diagram showing an example of a possible configuration of the control circuit 4 of the microphone signal module of this embodiment. The control circuit 4 shown in Figure 4 includes a comparison circuit 40, an OR gate 43, a counter 44, a detector 45, an edge detection circuit 46, a pulse generation circuit 47, and an OR gate 48. The pulse generation circuit 47 includes a timer 471 and a pulse generator 472. The comparison circuit 40 compares the level of the second analog signal Sa2 with a predetermined upper threshold Vth+ and a predetermined lower threshold Vth-. In the example of Figure 4, the comparison circuit 40 includes a comparator 41 and a comparator 42.

[0052] An upper threshold Vth+ is input to the inverting input terminal of the comparator 41, and a lower threshold Vth− is input to the non-inverting input terminal of the comparator 42. The non-inverting input terminal of the comparator 41 and the inverting input terminal of the comparator 42 are connected to the output terminal of the buffer circuit 2 (see FIG. 1). Therefore, a second analog signal Sa2 is input to the non-inverting input terminal of the comparator 41 and the inverting input terminal of the comparator 42. The comparator 41 compares the second analog signal Sa2 with a predetermined upper threshold Vth+. The comparator 42 compares the second analog signal Sa2 with a predetermined lower threshold Vth−. The output voltages of the comparators 41 and 42 are input to the input terminals of an OR gate 43. The comparators 41 and 42 form a window comparator having a range from the lower threshold Vth− to the upper threshold Vth+ as its comparison target.

[0053] The counter 44 has an increment input terminal 441, a decrement terminal 442, and an output terminal 443. The counter 44 increments the count value by one in response to a rising edge or a falling edge input to the increment input terminal, and decrements the count value by one in response to a rising edge or a falling edge input to the decrement input terminal. The counter 44 outputs the count value stored therein serially or in parallel from one or more output terminals 443.

[0054] The OR gate 43 outputs the logical sum of the logical value of the output voltage of the comparator 41 and the logical value of the output voltage of the comparator 42 to an increment input terminal 441 of the counter 44. Therefore, the count value of the counter 44 is incremented every time the second analog signal Sa2 exceeds the upper threshold Vth+, and is further incremented every time the second analog signal Sa2 falls below the lower threshold Vth−.

[0055] The detector 45 is composed of a comparator. The inverting input terminal of the detector 45 is connected to the output terminal of the buffer circuit 2. The second analog signal Sa2 is input to the inverting input terminal of the detector 45, and the midpoint potential Vcom of the maximum amplitude of the second analog signal Sa2 is input to the non-inverting input terminal. Therefore, the detector 45 detects an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom (a crossing of the second analog signal Sa2 and the midpoint potential Vcom on a time series basis, which is a zero crossing when the midpoint potential Vcom is 0 V). Each time this inversion is detected, the logic of the output voltage of the detector 45 changes from "positive ("1")" (high-level potential) to "negative ("0")" (low-level potential) or from "negative" to "positive."

[0056] 4, when the level of the second analog signal Sa2 reaches the midpoint potential Vcom from a side lower than the midpoint potential Vcom or exceeds the midpoint potential Vcom, the logic of the output voltage of the detector 45 changes from "positive" to "negative." On the other hand, when the level of the second analog signal Sa2 reaches the midpoint potential Vcom from a side higher than the midpoint potential Vcom or falls below the midpoint potential Vcom, the logic of the output voltage of the detector 45 changes from "negative" to "positive." Note that, unlike in FIG. 4, the second analog signal Sa2 may be input to the non-inverting input terminal of the detector 45, and the midpoint potential Vcom may be input to the inverting input terminal.

[0057] The edge detection circuit 46 detects the rising edge of the output voltage of the detector 45 and the falling edge of the output voltage of the detector 45. The edge detection circuit 46 outputs a pulse to the OR gate 48 each time it detects either of these edges. One of the two input terminals of the OR gate 48 is connected to the output terminal of the edge detection circuit 46, and the other is connected to the output terminal of the pulse generator 472. The output terminal of the OR gate 48 is connected to the decrement input terminal 442 of the counter 44. When a low level is input from the pulse generator 472, the OR gate 48 outputs a pulse substantially identical to the input pulse from the edge detection circuit 46 to the decrement input terminal 442 of the counter 44 each time the OR gate 48 receives the pulse. Therefore, the count value of the counter 44 is decremented each time an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom is detected.

[0058] That is, the counter 44 is incremented when the comparator circuit 40 detects that the level of the second analog signal Sa2 is outside the range from the lower threshold Vth− to the upper threshold Vth+, and is decremented when the detector 45 detects an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom. As an example, the upper threshold Vth+ and the lower threshold Vth− are selected according to the maximum and minimum values ​​of the maximum input voltage range of the AD conversion circuit 3, respectively. As an example, the upper threshold Vth+ is a voltage value that is lower by a predetermined voltage step than the maximum value of the maximum input voltage range of the AD conversion circuit 3. Similarly, the lower threshold Vth− may be a voltage value that is higher by a predetermined voltage step than the minimum value of the maximum input voltage range of the AD conversion circuit 3.

[0059] Since the count value is increased or decreased as described above, the count value of the counter 44 gradually increases if, for example, the level of the second analog signal Sa2 continues to approach or exceed the maximum or minimum value of the maximum input voltage range of the AD conversion circuit 3. On the other hand, if the level of the second analog signal Sa2 repeatedly crosses the midpoint potential Vcom without reaching a value near the maximum or minimum value of the maximum input voltage range of the AD conversion circuit 3, the count value of the counter 44 gradually decreases.

[0060] Therefore, by adjusting the first gain G1 in accordance with the count value of the counter 44, it is possible to suppress the generation of a second analog signal Sa2 that exceeds, for example, the maximum input voltage range of the AD conversion circuit 3. In other words, it is possible to prevent signal saturation within the microphone signal module. Furthermore, by adjusting the second gain G2 in accordance with the count value of the counter 44 in the same manner as the first gain G1, it is possible to compensate for the attenuation of the output signal of the AD conversion circuit 3 (see FIG. 1) caused by reducing the first gain G1. Therefore, the control circuit 4 configured as in the example of FIG. 4 may be configured to control the first gain G1 and the second gain G2 in accordance with the count value of the counter 44.

[0061] The count value output serially or in parallel from the output terminal 443 of the counter 44 may be output to the buffer circuit 2 as a control signal Sc1 for controlling the first gain G1, or may be output to the AD conversion circuit 3 as a control signal Sc2 for controlling the second gain G2. Alternatively, the control circuit 4 may perform necessary signal processing, such as processing or distribution, on the output signal from the counter 44, which includes information about the count value, using an appropriate signal processing circuit (not shown). The control circuit 4 may then output the processed signals as control signals Sc1 and Sc2 to the buffer circuit 2 and the AD conversion circuit 3, respectively.

[0062] In the control circuit 4 of the example of FIG. 4 , when an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom is detected, a reset signal Rst is input from the edge detection circuit 46 to the timer 471. Each time the reset signal Rst is input, the timer 471 resets the timing state up to that point and measures the elapsed time thereafter. Then, when a predetermined time has elapsed, the timer 471 outputs an enable signal En to the pulse generator 472, resets the internal timing state, and repeats timing. When the enable signal En is input, the pulse generator 472 outputs a pulse Pr at predetermined time intervals.

[0063] In this way, the pulse generating circuit 47 outputs a pulse Pr to the counter 44 when a predetermined time has elapsed since the detector 45 detected an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom until the next inversion is detected. Specifically, the pulse generating circuit 47 in the example of FIG. 4 outputs a pulse Pr to the OR gate 48. When a low level signal is input from the edge detection circuit 46, the OR gate 48 outputs a pulse Pr to the decrement input terminal 442 of the counter 44 every time the pulse Pr is input from the pulse generating circuit 47. That is, the counter 44 is configured to decrement the count value every time a pulse Pr is output. Therefore, the count value of the counter 44 is decremented every time a predetermined time set in the timer 471 elapses, during the period from the detection of an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom until the detection of the next inversion.

[0064] 4 including the pulse generating circuit 47, the count value of the counter 44 can be forcibly decremented by operating the pulse generator 472 upon the passage of a predetermined time. With this configuration, the count value of the counter 44 can be decremented when the second analog signal Sa2 is a small signal or no signal that cannot be detected by the detector 45. Alternatively, the count value of the counter 44 can be decremented when the small-amplitude second analog signal Sa2 does not cross the midpoint potential Vcom due to a slight offset from the midpoint potential Vcom. Forcibly decrementing the count value in this manner may allow the first gain G1 and the second gain G2 to be controlled to appropriate values.

[0065] The predetermined time set in the timer 471 is, for example, 50 ms or more. When such a time is set in the timer 471, it can be returned to its initial state even if a small signal or no signal is received. Note that even if the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom is reversed when the count value is 0, the pulse Pr input to the decrement input terminal 442 of the counter 44 is ignored. Therefore, the count value does not change.

[0066] <AD Conversion Circuit> Figure 5A is a block diagram showing an example of a possible configuration of the AD conversion circuit 3 of the microphone signal module of this embodiment. The AD conversion circuit 3 shown in Figure 5A is a delta-sigma AD conversion circuit that performs delta-sigma modulation on the input signal (a "delta-sigma AD conversion circuit" is also called a "sigma-delta AD conversion circuit"). Therefore, the AD conversion circuit 3 includes a subtractor 31, an integrator 32, a quantizer 33, and a 1-bit digital-to-analog converter (DA converter) 34. The DA converter 34 mainly constitutes a feedback circuit FB that feeds back the output value of the AD conversion circuit 3 from the output terminal Vado to the input terminal Vadi of the AD conversion circuit 3.

[0067] The subtractor 31 subtracts the positive or negative reference voltage (+Vr or −Vr) output by the DA converter 34 from the second analog signal Sa2 and outputs the result to the integrator 32. The integrator 32 cumulatively adds the output of the subtractor 31 and outputs the result to the quantizer 33. The quantizer 33 outputs a digital value of “positive (“1”)” (high-level potential) if the voltage input from the integrator 32 is equal to or greater than a reference value, and outputs a digital value of “negative (“0”)” (low-level potential) if the voltage input from the integrator 32 is equal to or less than the reference value. The DA converter 34 outputs the positive reference voltage +Vr to the subtractor 31 if the output of the quantizer 33 is “positive,” and outputs the negative reference voltage (−Vr) to the subtractor 31 if the output of the quantizer 33 is “negative.” By performing such delta-sigma modulation on the second analog signal Sa2, a PDM (pulse density modulation) format digital output value corresponding to the magnitude of the second analog signal Sa2 is obtained. The AD conversion circuit 3 that operates in this manner is suitable for combination with the inverting buffer circuit 2 exemplified in FIGS. 2A and 2B.

[0068] The AD conversion circuit 3 shown in FIG. 5A is configured so that the feedback amount of the feedback circuit FB is adjustable. The "feedback amount" refers to the magnitude of the voltage applied to the input side of the AD conversion circuit 3 based on the output of the quantizer 33. More specifically, in the example of FIG. 5A, the "feedback amount" refers to the magnitude of the positive or negative reference voltage Vr input to the subtractor 31 based on the positive or negative output of the quantizer 33. As the feedback amount increases, the amount of change in the subtraction result for each subtraction process by the subtractor 31 increases, thereby decreasing the digital value output from the quantizer 33 for the input second analog signal Sa2 and decreasing the second gain G2. Conversely, as the feedback amount decreases, the digital value output for the input second analog signal Sa2 increases and the second gain G2 increases. In other words, the second gain G2 of the AD conversion circuit 3 can be controlled by increasing or decreasing the feedback amount of the feedback circuit FB. Therefore, the control circuit 4 (see FIG. 1) may be configured to control the second gain G2 by increasing or decreasing the feedback amount of the feedback circuit FB. Such a configuration is believed to facilitate control of the second gain G2.

[0069] FIG. 5B shows a more specific configuration example of one example of the AD conversion circuit 3 of FIG. 5A. FIG. 5B shows a more specific example of the feedback circuit FB, which is capable of adjusting the feedback amount. As shown in FIG. 5B, the feedback circuit FB is composed of multiple feedback circuits, namely, feedback circuits FB0, FB1, FB2, FB3, ..., FBn. The feedback circuit FB0 is mainly composed of a DA converter 340. Similarly, the feedback circuits FB1, FB2, FB3, ..., FBn are mainly composed of DA converters 341, 342, 343, ..., 34n, respectively. In this way, the AD conversion circuit 3 may have any number of feedback circuits, each of which is composed of a DA converter.

[0070] 5B further includes a plurality of switches 35. Each switch 35 is provided in each of the feedback circuits FB1 to FBn. Each switch 35 is disposed between the output of each of the DA converters 341 to 34n and the subtractor 31, and connects or disconnects the output of each of the DA converters 341 to 34n and the subtractor 31.

[0071] As described above, each of the DA converters 340, 341 to 34n outputs a positive or negative reference voltage Vr depending on the logic of the output of the quantizer 33. Therefore, the greater the number of DA converters 341 to 34n connected to the subtractor 31 by the switch 35, the greater the feedback amount of the entire feedback circuit FB. Conversely, the fewer the number of connected DA converters, the smaller the feedback amount. In other words, the feedback amount of the feedback circuit FB can be adjusted by controlling the opening and closing of each switch 35. Therefore, the control circuit 4 (see FIG. 1) may be configured to control the second gain G2 by opening and closing the switch 35.

[0072] As an example, the default state of the microphone signal module 1 may be a state in which all of the switches 35 are closed. In this state, the feedback circuit FB is formed by the DA converters 340 to 340n. Each time one of the switches 35 is opened, the feedback amount of the feedback circuit FB decreases by the reference voltage Vr output by one of the DA converters 341 to 34n connected to that open switch 35. The second gain G2 increases in response to this decrease in the feedback amount. Note that the reference voltages Vr output by the DA converters 340, 341 to 34n may all be the same or different.

[0073] The number of feedback circuits FB1 to FBn is set according to the number of set values ​​required for the second gain G2. The same number of switches 35 as the number of feedback circuits FB1 to FBn are also provided. By providing n feedback circuits FB1 to FBn, the second gain G2 can be set to n values ​​other than the value in the default state.

[0074] The AD conversion circuit 3 is preferably configured so that the rate of change of the second gain G2 caused by closing one of the switches 35 is approximately the same as the rate of change of the first gain G1 caused by closing one of the switches 25 in the buffer circuit 2 of the example of FIG. 2B. The rate of change of the second gain G2 caused by closing one of the switches 35 may be, and preferably is, approximately the same as the rate of change of the first gain G1 caused by closing one of the switches 29 in the buffer circuit 2 of the example of FIG. 3B. Furthermore, the first gain G1 and the second gain G2 may be reciprocals of each other (numbers with approximately the same absolute value and opposite sign) in decibel notation. When the AD conversion circuit 3 and the buffer circuit 2 are configured in this manner, it may be easier to maintain the linearity of the microphone signal module when controlling the first gain G1 and the second gain G2.

[0075] As one example, the control circuit 4 (see FIG. 1 ) may output a plurality of control signals including control signals for the plurality of switches 24 and 25 in FIG. 2B . As another example, the control circuit 4 may output a plurality of control signals including control signals for the plurality of switches 28 and 29 in the example of FIG. 3B . Furthermore, the control circuit 4 may output a plurality of control signals including control signals for the plurality of switches 35 in the example of FIG. 5B . Each of the plurality of control signals may then be input to a control terminal of each of the switches 24 and 25, the switches 28 and 29, or the switch 35 that controls its opening or closing. Alternatively, the control signal output from the control circuit 4 may be distributed via an appropriate multiplexer (not shown) to the control terminals of the switches 24 and 25, or the switches 28 and 29, and also to the control terminal of the switch 35.

[0076] <Example Waveforms of Each Signal> Figure 6A shows an example waveform of the first analog signal Sa1 and the second analog signal Sa2 generated by inputting the first analog signal Sa1 in the microphone signal module 1 (see Figure 1) of this embodiment. Figure 6A also shows an example waveform of the output signal So obtained from the AD conversion circuit 3 (see Figure 1) for the first analog signal Sa1 of Figure 6A. Note that, as described above with reference to Figure 8B, the output signal So of Figure 6A is a waveform of a signal obtained by passing the digital signal Sd1 (see Figure 1) output from the AD conversion circuit 3 through a low-pass filter. Figure 6B shows an enlarged view of the first analog signal Sa1 and the second analog signal Sa2 in section VIB of Figure 6A. Figure 6B also shows an example of changes in the count value Nc, first gain G1, and second gain G2 of the counter 44 (see Figure 4) included in the control circuit 4.

[0077] As shown in FIG. 6A , in the time domain before time T1, the amplitude of the first analog signal Sa1 is relatively small. Therefore, by amplifying the first analog signal Sa1 by a first gain G1, a second analog signal Sa2 having an amplitude larger than that of the first analog signal Sa1 is generated. Generating a second analog signal Sa2 with a larger amplitude is believed to improve the signal-to-noise ratio. The first gain G1 at this time may be, for example, C11 / C22 based on Equation 1 described above with reference to FIG. 2A . Here, C11 is the capacitance of a transducer such as microphone 11 (see FIG. 2A ), and C22 is the capacitance between the input and output of buffer circuit 2 in FIG. 2A .

[0078] In the time domain up to time T1, the AD conversion circuit 3 (see FIG. 5B) converts the level of the second analog signal Sa2 into a digital value with a second gain G2 corresponding to the first gain G1, resulting in the output signal So almost faithfully reproducing the first analog signal Sa1.

[0079] After time T1, the amplitude of the first analog signal Sa1 increases, so the first gain G1 is made smaller than the value in the time domain before time T1. That is, as shown in FIG. 6B , at time T11, the second analog signal Sa2 reaches the lower threshold Vth−, so the count value Nc is incremented. Therefore, the first gain G1 is made smaller than the value up to time T11. As a result, the amplitude of the second analog signal Sa2 decreases by an amount corresponding to the decrease in the first gain G1, so signal saturation does not occur in the AD conversion circuit 3. In addition, the second gain G2 is increased in accordance with the increment in the count value Nc, so the second analog signal Sa2 is converted into a digital value of an appropriate magnitude.

[0080] Since the level of the first analog signal Sa1 continues to increase after time T11, the second analog signal Sa2 again reaches the lower threshold Vth− at time T12. Therefore, the count value Nc is further incremented, the first gain G1 is decreased, and the second gain G2 is increased. Therefore, the second analog signal Sa2 continues to be converted into a digital value of an appropriate magnitude without saturating. Even after time T12, each time the second analog signal Sa2 reaches the lower threshold Vth−, the count value Nc is incremented, and the first gain G1 is decreased and the second gain G2 is increased accordingly.

[0081] Thereafter, when the second analog signal Sa2 reaches the midpoint potential Vcom at time T2, the count value Nc is decremented, and accordingly the first gain G1 is increased and the second gain G2 is decreased. Thereafter, when the second analog signal Sa2 reaches the upper limit threshold Vth+ at time T3, the count value Nc is again incremented, and accordingly the first gain G1 is decreased and the second gain G2 is increased.

[0082] Since the first gain G1 and the second gain G2 are controlled in this manner, the first analog signal Sa1 is reproduced almost faithfully in the output signal So even after time T1, as shown in Fig. 6A. As described above, according to this embodiment, it is possible to ensure a sufficient dynamic range with good linearity, while also ensuring a sufficient S / N ratio when the amplitude of the input signal (first analog signal Sa1) is small.

[0083] <Another Example of AD Conversion Circuit> Figure 7 shows an AD conversion circuit 3x, which is another example of the AD conversion circuit in the microphone signal module of this embodiment. The AD conversion circuit 3x includes a second feedback circuit FBx in addition to the AD conversion circuit 3 of Figure 5A. The second feedback circuit FBx is added mainly to correct variations in capacitance of a transducer such as the microphone 11 connected to the input terminal of the buffer circuit 2 (see Figures 3A and 3B). The AD conversion circuit 3x is suitable for combination with the non-inverting buffer circuit 2 illustrated in Figures 3A and 3B.

[0084] When the buffer circuit 2 is a non-inverting type, unlike the inverting type, the buffer circuit 2 outputs a second analog signal Sa2 having the same polarity with respect to the reference potential Vref (see FIG. 3A) as the polarity of the first analog signal Sa1 (see FIG. 3A) to the AD conversion circuit 3x. Therefore, the DA converter 34 in the AD conversion circuit 3x in FIG. 7 outputs a negative reference voltage −Vr to the subtractor 31 if the output of the quantizer 33 is “positive,” and outputs a positive reference voltage (+Vr) to the subtractor 31 if the output of the quantizer 33 is “negative.” Therefore, in the subtractor 31, the absolute value Vr is essentially added when the output of the quantizer 33 is “positive,” and the absolute value Vr is subtracted when the output of the quantizer 33 is “negative.” By operating in this manner, the DA converter 34 achieves appropriate delta-sigma modulation of the second analog signal Sa2 from the non-inverting buffer circuit 2. In the example of FIG. 7, the DA converter 34 may operate in the same manner as in the example of FIG. 5A, and in that case, the subtractor 31 may have a function as an adder for the output from the DA converter 34.

[0085] On the other hand, the second feedback circuit FBx is mainly composed of a DA converter 34x that operates in the same manner as the DA converter 34 in Fig. 5A. That is, if the output of the quantizer 33 is "positive," the DA converter 34x outputs a positive reference voltage +Vrx to the subtractor 31, and if the output of the quantizer 33 is "negative," the DA converter 34x outputs a negative reference voltage -Vrx to the subtractor 31. The positive or negative reference voltage (+Vrx or -Vrx) output by the DA converter 34x, together with the reference voltage (+Vr or -Vr) output from the DA converter 34, is subtracted from the second analog signal Sa2 by the subtractor 31.

[0086] The second feedback circuit FBx is configured to allow adjustment of the feedback amount, similar to the feedback circuit FB. Therefore, similar to the feedback circuit FB in FIG. 5B, the second feedback circuit FBx may be configured with multiple feedback circuits, each including a switch and a DA converter. The feedback amount of the second feedback circuit FBx can be adjusted by opening and closing the switch. The feedback amount of the second feedback circuit FBx is set according to the ratio between the capacitance of a transducer, such as the microphone 11, connected to the buffer circuit 2 (see FIGS. 3A and 3B) and the input capacitance of the buffer circuit 2. The "input capacitance of the buffer circuit 2" refers to the capacitance of a capacitive element (such as the capacitor 27 in FIGS. 3A and 3B) other than a transducer, such as the microphone 11, connected to the input terminal of the buffer circuit 2.

[0087] 3A and 3B, the amount of change in first gain G1 caused by closing switch 29 is determined by the ratio of C27 to C11 according to Equation 4 above. C11 is the capacitance of a transducer such as microphone 11 connected to buffer circuit 2. C27 is the capacitance of capacitor 27 in FIGS. 3A and 3B, and is the input capacitance of buffer circuit 2. Therefore, to accurately convert second analog signal Sa2 into a digital signal, it is necessary to correct variations in the ratio between the capacitance of the transducer connected to buffer circuit 2 and the input capacitance of buffer circuit 2.

[0088] 7, as described above, the second feedback circuit FBx has a feedback amount that is set in accordance with the ratio between the capacitance of the transducer connected to the buffer circuit 2 and the input capacitance of the buffer circuit 2. Therefore, the second feedback circuit FBx can correct variations in the first gain G1. Therefore, it is believed that the input analog signal can be accurately converted into a digital signal.

[0089] For example, if the second feedback circuit FBx includes multiple sets of switches and DA converters, such as the switch 35 and DA converters 341-34n of the feedback circuit FB in FIG. 5B, the feedback amount of the second feedback circuit FBx can be adjusted by controlling the opening and closing of the switches. That is, variations in the first gain G1 can be corrected. For example, the feedback amount of the second feedback circuit FBx is determined by measuring the capacitance of a transducer connected to the buffer circuit 2 and the input impedance of the buffer circuit 2 using a known analog signal. Then, for example, the opening and closing of a switch that functions similarly to the switch 35 in FIG. 5B for the DA converter 34x of the second feedback circuit FBx is controlled to achieve the determined feedback amount. Note that the feedback amount of the second feedback circuit FBx may also be adjusted by adjusting the reference voltage Vrx by means other than adjusting the capacitance within the second feedback circuit FBx.

[0090] The second gain G2 of the AD conversion circuit 3x also depends on the feedback amount of the second feedback circuit FBx. Therefore, in the example of Fig. 7, the first gain G1 and the second gain G2 do not have to be the inverse of each other in decibel expression. For example, the first gain G1 and the second gain G2 may differ in magnification expression by approximately the same ratio as the ratio between the capacitance of the transducer connected to the buffer circuit 2 and the input capacitance of the buffer circuit 2.

[0091] 1 to 7, in the microphone signal module of this embodiment, the second gain G2 of the AD conversion circuit 3 is controlled to maintain linearity by compensating for an increase or decrease in the first gain G1 of the buffer circuit 2 due to control. With respect to the configuration of this embodiment, it is also possible to maintain linearity by using a DSP (digital signal processor) or the like to perform processing such as expansion / compression on the digital signal after AD conversion.

[0092] However, in signal processing in the digital domain after AD conversion using a DSP or other device, gain switching occurs at the zero crossing of the input analog signal to avoid noise due to DC offset or ensure sufficient signal processing time in the DSP. As a result, the first wave immediately following an increase in the amplitude of the input signal may be clipped (missing), as shown in the output signal Voa from the P1 section in FIG. 9 . Note that FIG. 9 also shows the waveforms of the signals in the conventional microphone amplifier 900 of FIG. 8A when the gain of the preamplifier 901 is controlled and the resulting increase or decrease in the gain of the preamplifier 901 is compensated for by digital processing of the output signal from the AD converter 910. In FIG. 9 , signals Vi, Via, and Voa are, similar to FIG. 8B , examples of the input signal to the preamplifier 901, the input signal to the AD converter 910, and the output signal from the AD converter 910 (analog signal after passing through an appropriate low-pass filter), respectively. In FIG. 9 , a DC offset Vof also occurs in the output signal Voa after the preamplifier gain is switched.

[0093] Furthermore, similar to FIG. 9 , FIG. 10 shows another observation example of the input signal Vi and the output signal Voa when digital processing is performed in the microphone amplifier 900 of FIG. 8A to compensate for increases or decreases in the gain of the preamplifier 901. In the example of FIG. 10 , the first wave of the output signal Voa is clipped, as shown in part P2. In the time domain from part P2 onward, clipping of the output signal Voa occurs, as shown in part P3, due to the input voltage range of the AD converter 910 being exceeded by a DC offset. Furthermore, a delay td occurs between the input signal Vi and the output signal Voa. The defects shown in FIGS. 9 and 10 can be avoided by providing a cancellation circuit for a DC offset or the like, but adding such a circuit would increase the size of the microphone amplifier 900 of FIG. 8A.

[0094] On the other hand, in this embodiment, the increase or decrease in the first gain G1 of the buffer circuit 2 due to control is compensated for in the analog domain by controlling the second gain G2 of the AD conversion circuit 3. Because both the first gain G1 and the second gain G2 are controlled in the analog domain, it is possible to control the first gain G1 and the second gain G2 in near real time or at a very high frequency of several MHz relative to the audio signal. This reduces signal delay, and therefore waveform distortion such as clipping due to signal delay is also less likely to occur. Furthermore, because a DSP is not used, the circuit size can be reduced and current consumption during operation can be saved. While maintaining these advantages, it is sometimes possible to achieve performance equivalent to or better than that achieved when a DSP is used.

[0095] <Comparison with Other Buffer Circuit Configurations> FIG. 11A shows, as a comparative example, a buffer circuit 92 having a configuration different from the buffer circuit 2 illustrated in FIGS. 2B and 3B. FIG. 11B shows an example of a first analog signal Sa1 and a second analog signal Sa2 when the buffer circuit 92 is used in the microphone signal module of the embodiment in place of the buffer circuit 2 of FIG. 2B. The buffer circuit 92 includes an operational amplifier 921, capacitors 922 and 923, multiple switches 924, and multiple switches 925. The operational amplifier 921, capacitors 922 and 923 (capacitors 9231 to 923n), and switch 925 function similarly to the operational amplifier 21, capacitors 22 and 23, and switch 25 of the buffer circuit 2 of FIG. 2B, respectively. Meanwhile, each switch 924 connects or disconnects one of the capacitors 9231 to 923n to the non-inverting input terminal of the operational amplifier 921, to which the reference potential Vref is applied. In the buffer circuit 92 as well, the gain of the buffer circuit 92 can be controlled by switching the opening and closing of each switch 925 .

[0096] Furthermore, in the buffer circuit 92, one of the capacitors 9231 to 923n, which is isolated from the inverting input terminal of the operational amplifier 921 by the switch 925, is charged by closing the switch 924. This suppresses sudden fluctuations in the output signal of the buffer circuit 92 when the gain is switched, thereby reducing so-called pop noise. However, because the amount of charge stored between the output terminal and the inverting input terminal of the operational amplifier 921 changes when the gain is switched, a DC offset Vof occurs in the second analog signal Sa2, as shown in FIG. 11B. Note that the significant attenuation in amplitude of the second analog signal Sa2 after the DC offset occurs in FIG. 11B is due to the second analog signal Sa2 having the DC offset being mistaken for a large-amplitude signal by the control circuit 4 (see FIG. 1). Such a DC offset can be prevented, for example, by switching the gain at the zero-crossing of the second analog signal Sa2. However, such restrictions on the timing of the gain switching can cause the signal clipping described above due to a delay in the switching.

[0097] In contrast, in the buffer circuit 2 shown in FIG. 2B or FIG. 3B, the timing of switching the first gain G1 is not restricted by the DC offset suppression, and therefore it is possible to suppress switching delays and the accompanying signal clipping.

[0098] 1 Microphone signal conversion module (microphone signal module) 10 Microphone module 11 Microphone 2 Buffer circuit 21 Operational amplifier 22 Capacitor 23 Variable capacitance capacitor 24, 25 Switch 26 Non-inverting buffer 27 Variable capacitance capacitor 28, 29 Switch 3, 3x AD conversion circuit 34, 34x, 340, 341 to 34n DA converter 4 Control circuit 40 Comparison circuit 44 Counter 45 Detector (comparator) 47 Pulse generation circuit 471 Timer 472 Pulse generator FB Feedback circuit FBx Second feedback circuit G1 First gain G2 Second gain Sa1 First analog signal Sa2 Second analog signal Pr Pulse Vcom Midpoint potential Vth+ Upper threshold Vth- Lower threshold

Claims

1. A microphone signal conversion module comprising: a buffer circuit that performs level conversion with a first gain on a first analog signal input from a transducer, and outputs a second analog signal obtained by the level conversion; an analog-to-digital conversion circuit that converts the level of the second analog signal into a digital value with a second gain; and a control circuit that controls the first gain and the second gain, wherein the second analog signal is input to the control circuit, and the control circuit is configured to control the magnitudes of the first gain and the second gain in opposite directions based on the level of the second analog signal.

2. The microphone signal conversion module of claim 1, wherein the buffer circuit includes: an operational amplifier having an inverting input terminal that receives the first analog signal; a plurality of capacitors arranged between the output terminal and the inverting input terminal of the operational amplifier; and a switch that connects or disconnects some of the plurality of capacitors to or from the inverting input terminal; and the control circuit is configured to control the first gain by opening and closing the switch.

3. A microphone signal conversion module as claimed in claim 2, wherein said portion of said plurality of capacitors is configured to discharge when isolated from said inverting input terminal by said switch.

4. A microphone signal conversion module as described in claim 1, wherein the buffer circuit includes: a non-inverting buffer having an input terminal for receiving the first analog signal sent from a capacitive transducer; a plurality of capacitors each arranged between the input terminal and a predetermined constant potential; and a switch for connecting or disconnecting each of the plurality of capacitors to or from the input terminal; and the control circuit is configured to control the first gain by opening and closing the switch.

5. The microphone signal conversion module of claim 4, wherein the plurality of capacitors are configured to discharge when isolated from the input terminal by the switch.

6. A microphone signal conversion module as described in claim 1, wherein the control circuit includes: a comparison circuit that compares the level of the second analog signal with a predetermined upper threshold and a predetermined lower threshold; a detector that detects an inversion of the magnitude relationship between the level of the second analog signal and the midpoint potential of the maximum amplitude of the second analog signal; and a counter that is incremented when the comparison circuit detects that the level of the second analog signal is outside the range from the lower threshold to the upper threshold and that is decremented when the detector detects the inversion, and the control circuit is configured to control the first gain and the second gain according to the count value of the counter.

7. The microphone signal conversion module according to claim 6, wherein the control circuit further includes a pulse generating circuit that outputs a pulse when a predetermined time has elapsed since the detector detected the inversion, and the counter is configured to decrement the count value each time the pulse is output.

8. A microphone signal conversion module as described in claim 1, wherein the analog-to-digital conversion circuit is a delta-sigma type analog-to-digital conversion circuit having a feedback circuit constituted by a digital-to-analog converter, and the control circuit is configured to control the second gain by increasing or decreasing the amount of feedback of the feedback circuit.

9. A microphone signal conversion module as described in claim 8, wherein said analog-to-digital conversion circuit further includes a second feedback circuit having a feedback amount set according to a ratio between the capacitance of a transducer connected to said buffer circuit and the input capacitance of said buffer circuit.

10. A microphone module comprising: a microphone signal conversion module according to any one of claims 1 to 9; and a MEMS transducer that generates the first analog signal.

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