Capacitor, mounting board, and method for manufacturing capacitor

Abstract

Provided is a capacitor comprising: a conductive base material having a first main surface and a second main surface on an opposite side from the first main surface; a plurality of through-holes formed in the base material and passing through from the first main surface to the second main surface; a dielectric film covering a surface of the base material including an inner wall surface of each of the plurality of through-holes; and a plurality of internal electrodes each filling each of the plurality of through-holes inside the dielectric film.

Description

Capacitor, mounting board, and capacitor manufacturing method

[0001] The present disclosure relates to a capacitor, a mounting substrate, and a method for manufacturing a capacitor.

[0002] A capacitor has been proposed in which multiple bottomed trenches are formed in a conductive silicon substrate, multiple dielectric films are formed on the bottom and side surfaces of the trenches, and electrodes are formed inside the dielectric films to fill the trenches.

[0003] Japanese Patent Application Publication No. 2019-029537

[0004] It is not easy to stably obtain a large capacitance with conventional capacitors.

[0005] An object of the present disclosure is to provide a capacitor, a mounting substrate, and a method for manufacturing a capacitor that can stably obtain a large capacitance.

[0006] According to one aspect of the present disclosure, a capacitor includes a conductive substrate having a first main surface and a second main surface opposite the first main surface, a plurality of through holes formed in the substrate and penetrating from the first main surface to the second main surface, a dielectric film covering a surface of the substrate including inner wall surfaces of the plurality of through holes, and a plurality of internal electrodes filling each of the plurality of through holes inside the dielectric film.

[0007] According to the present disclosure, a large capacity can be stably obtained.

[0008] FIG. 1 is a cross-sectional view showing a capacitor according to the first embodiment. FIG. 2 is a plan view showing the arrangement of internal electrodes in the capacitor according to the first embodiment. FIG. 3 is a flowchart showing a method for manufacturing the capacitor according to the first embodiment. FIG. 4 is a perspective view (part 1) showing the method for manufacturing the capacitor according to the first embodiment. FIG. 5 is a perspective view (part 2) showing the method for manufacturing the capacitor according to the first embodiment. FIG. 6 is a perspective view (part 3) showing the method for manufacturing the capacitor according to the first embodiment. FIG. 7 is a perspective view (part 4) showing the method for manufacturing the capacitor according to the first embodiment. FIG. 8 is a cross-sectional view showing a capacitor according to the second embodiment. FIG. 9 is a plan view showing the arrangement of internal electrodes in the capacitor according to the second embodiment. FIG. 10 is a perspective view (part 1) showing the method for manufacturing the capacitor according to the second embodiment. FIG. 11 is a perspective view (part 2) showing the method for manufacturing the capacitor according to the second embodiment. FIG. 12 is a perspective view (part 3) showing the method for manufacturing the capacitor according to the second embodiment. FIG. 13 is a cross-sectional view showing a capacitor according to the third embodiment. FIG. 14 is a cross-sectional view showing a capacitor according to the fourth embodiment. FIG. 15 is a cross-sectional view showing a capacitor according to the fifth embodiment. Fig. 16 is a cross-sectional view showing a capacitor according to a sixth embodiment. Fig. 17 is a front view showing a capacitor according to a seventh embodiment. Fig. 18 is a cross-sectional view showing a capacitor according to an eighth embodiment. Fig. 19 is a cross-sectional view showing a capacitor according to a ninth embodiment. Fig. 20 is a cross-sectional view showing a mounting board according to a tenth embodiment.

[0009] Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be designated by the same reference numerals to avoid redundant description. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the capacitor and the mounting board. When viewed from an arbitrary point, the +Z side may be referred to as the upper side, top side, or top, and the −Z side may be referred to as the lower side, bottom side, or bottom. In this disclosure, "planar view" refers to viewing an object from above, and "planar shape" refers to the shape of an object viewed from above.

[0010] First Embodiment First, the first embodiment will be described. The first embodiment relates to a capacitor. FIG. 1 is a cross-sectional view showing a capacitor according to the first embodiment. FIG. 2 is a plan view showing the arrangement of internal electrodes in the capacitor according to the first embodiment. FIG. 1 corresponds to a cross-sectional view taken along line II in FIG. 2.

[0011] 1 and 2, the capacitor 1 according to the first embodiment has a substrate 10, a plurality of through holes 20, a dielectric film 30, a plurality of internal electrodes 50, a plurality of internal electrodes 60, an external electrode 70, an external electrode 80, an insulating layer 91, and an insulating layer 92. Note that the external electrode 80 and the insulating layer 92 are omitted from FIG.

[0012] The substrate 10 is electrically conductive. The substrate 10 includes, for example, silicon (Si), hafnium (Hf), lanthanum (La), niobium (Nb), tantalum (Ta), titanium (Ti), or zirconium (Zr). The substrate 10 may be composed of Si, Hf, La, Nb, Ta, Ti, or Zr. When Si is used as the material of the substrate 10, the substrate 10 is doped with an impurity. The substrate 10 has a main surface 11 and a main surface 12 opposite to the main surface 11. In one example, the main surface 11 and the main surface 12 are perpendicular to the Z-axis direction, the main surface 11 is the bottom surface, and the main surface 12 is the top surface. The main surface 11 is an example of a first main surface, and the main surface 12 is an example of a second main surface. The shape of the substrate 10 is, for example, a substantially rectangular parallelepiped. For example, the dimension of the substrate 10 in the X-axis direction is 100 μm to 5000 μm, the dimension in the Y-axis direction is 50 μm to 3000 μm, and the dimension in the Z-axis direction is 10 μm to 3000 μm.

[0013] A plurality of through holes 20 are formed in the substrate 10. The through holes 20 penetrate the substrate 10 from the main surface 11 to the main surface 12. The cross-sectional shape of the through holes 20 perpendicular to the longitudinal direction is, for example, a circle with a diameter of 0.01 μm to 20 μm. In this embodiment, the plurality of through holes 20 are arranged in a triangular lattice pattern in a planar view. For example, the plurality of through holes 20 are arranged in a regular triangular lattice pattern with one side of the smallest triangle aligned in the X-axis direction. The pitch of the through holes 20 is, for example, 0.02 μm to 50 μm. The cross-sectional shape of the through holes 20 perpendicular to the longitudinal direction does not have to be circular and may be, for example, rectangular or elliptical, but a circular shape is preferable from the viewpoint of ease of processing. The plurality of through holes 20 can be arranged in various ways in a planar view. For example, when arranged in a triangular lattice pattern, it is preferable that the cross-sectional shape of the through holes 20 perpendicular to the longitudinal direction be hexagonal rather than circular, considering the opposing surfaces of the through holes 20. The shape of the cross section perpendicular to the longitudinal direction of the through-hole 20 can be appropriately set depending on the arrangement of the plurality of through-holes 20 in a plan view and the ease of processing.

[0014] The dielectric film 30 covers the surface of the substrate 10. The surface of the substrate 10 includes the inner wall surface of the through hole 20. The dielectric film 30 is, for example, an oxide film, nitride film, or oxynitride film containing the same elements as the substrate 10. For example, if the substrate 10 is a conductive Si substrate, the dielectric film 30 is a Si oxide film, nitride film, or oxynitride film. The thickness of the dielectric film 30 is, for example, 1 nm to 1000 nm. The dielectric film 30 is homogeneous and has a uniform thickness, which allows for a capacitor with little variation in capacitance and excellent voltage resistance characteristics. For this reason, separately forming the dielectric film 30 on the surface of the substrate 10 using a thin-film process is not preferable because it is difficult to achieve homogeneity and a uniform thickness in the portions of the inner wall surface of the through hole 20 close to and far from the main surface.

[0015] Each of the multiple internal electrodes 50 fills one through hole 20 inside the dielectric film 30. Also, each of the multiple internal electrodes 60 fills another through hole 20 inside the dielectric film 30. For example, two internal electrodes 50 and one internal electrode 60 are repeatedly arranged between multiple through holes 20 arranged in a direction parallel to the sides of the smallest triangle unit of a regular triangular lattice formed by the multiple through holes 20. In this embodiment, the directions parallel to the sides of the smallest triangle unit of a regular triangular lattice formed by the multiple through holes 20 are the X-axis direction and two directions inclined by 60° clockwise or counterclockwise from the X-axis direction in the XY plane. In other words, two internal electrodes 50 and one internal electrode 60 are repeatedly arranged between multiple internal electrodes 50 and multiple internal electrodes 60 arranged in the closest-packed direction in a plan view perpendicular to the main surface 12. The internal electrodes 50 and 60 may contain, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), ruthenium (Ru), tungsten (W), molybdenum (Mo), titanium (Ti), or conductive silicon. The internal electrodes 50 and 60 may contain an alloy material containing one or more of these metal elements. The internal electrodes 50 and 60 may also contain other metal elements. The internal electrode 50 is an example of a first internal electrode, and the internal electrode 60 is an example of a second internal electrode. The arrangement of the multiple through holes 20 in a planar view is such that the first internal electrode and the second internal electrode have a large opposing area. For example, the internal electrode 50, which is part of the first internal electrode, and the internal electrode 60, which is part of the second internal electrode, may be arranged at two diagonal points of each unit cell of a square lattice, a rectangular lattice, or a rhombic lattice. Although an asymmetric arrangement such as a parallelepiped lattice may be used, a symmetric arrangement is preferable in terms of realizing uniform capacitor characteristics.

[0016] The insulating layer 91 covers the main surface 11 of the substrate 10 from below, with the dielectric film 30 sandwiched therebetween. The insulating layer 91 also covers the lower surfaces of the internal electrodes 50 and 60. The insulating layer 92 also covers the main surface 12 of the substrate 10 from above, with the dielectric film 30 sandwiched therebetween. The insulating layer 92 also covers the upper surfaces of the internal electrodes 50 and 60. The insulating layers 91 and 92 are made of a material such as a resin material, e.g., polyimide, or silicon oxide (SiO２ The insulating layer 91 and the insulating layer 92 may be made of an inorganic material such as silicon nitride (SiN), silicon oxynitride (SiON), or the like. The insulating layer 91 and the insulating layer 92 may be made of an insulating material other than these. The insulating layer 91 and the insulating layer 92 can protect the substrate 10, the dielectric film 30, the internal electrode 50, and the internal electrode 60 from the external environment. The thickness of the insulating layer 91 and the insulating layer 92 is, for example, 10 nm to 5000 nm.

[0017] A plurality of contact holes 91A are formed in the insulating layer 91, penetrating the insulating layer 91 in the Z-axis direction and reaching the lower surfaces of the internal electrodes 50. At least a portion of the lower surfaces of the internal electrodes 50 is exposed from each of the contact holes 91A. A plurality of contact holes 92A are formed in the insulating layer 92, penetrating the insulating layer 92 in the Z-axis direction and reaching the upper surfaces of the internal electrodes 60. At least a portion of the upper surfaces of the internal electrodes 60 is exposed from each of the contact holes 92A.

[0018] The external electrode 70 is disposed so as to contact the lower surface of the insulating layer 91. The external electrode 70 has multiple lead portions 71, each located within a contact hole 91A. The upper ends of the lead portions 71 contact the internal electrodes 50, and the external electrode 70 is electrically connected to the multiple internal electrodes 50. The external electrode 80 is disposed so as to contact the upper surface of the insulating layer 92. The external electrode 80 has multiple lead portions 81, each located within a contact hole 92A. The lower ends of the lead portions 81 contact the internal electrodes 60, and the external electrode 80 is electrically connected to the multiple internal electrodes 60. The external electrodes 70 and 80 may contain, for example, copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), or gold (Au). The external electrodes 70 and 80 may contain an alloy material containing one or more of these metal elements. The external electrodes 70 and 80 may also contain other metal elements. The thickness of the external electrode 70 and the external electrode 80 is, for example, 100 nm to 10,000 nm. The lead portions 71 and 81 may be formed independently of the external electrode 70 and the external electrode 80, respectively. The lead portions 71 and 81 may be part of the internal electrode 50 and the internal electrode 60, respectively, and may be made of the same material as the internal electrode 50 and the internal electrode 60, respectively. The lead portions 71 and 81 are conductor portions independent of the internal electrode 50 and the external electrode 70, and the internal electrode 60 and the external electrode 80, respectively, and may be made of a different material from each other. However, taking into consideration the thermal shrinkage rate of the material, it is preferable that the lead portions 71 and 81 be made of the same material as either or both of the materials.

[0019] Voltages of opposite polarities are applied between the external electrode 70 and the external electrode 80. As a result, the internal electrode 50 functions as a first internal electrode of a first polarity, and the internal electrode 60 functions as a second internal electrode of a second polarity. The external electrode 70 is an example of a first external electrode, and the external electrode 80 is an example of a second external electrode.

[0020] Next, a method for manufacturing the capacitor 1 according to the first embodiment will be described. Fig. 3 is a flowchart showing the method for manufacturing the capacitor according to the first embodiment. Figs. 4 to 7 are perspective views showing the method for manufacturing the capacitor according to the first embodiment.

[0021] First, as shown in FIG. 4 , a substrate 10 having a main surface 11 and a main surface 12 is prepared, and a plurality of through holes 20 are formed in the substrate 10 (step S1). To form the through holes 20, for example, a resist mask having openings exposing the areas where the through holes 20 are to be formed is formed on the main surface 11 or the main surface 12 by photolithography, and deep reactive ion etching (RIE) is performed using this resist mask. Deep RIE can be performed, for example, by the Bosch method. Instead of the Bosch method, a wet etching process such as photo-assisted electrolytic etching may be used. Using the wet etching process can reduce costs compared to the Bosch method. Furthermore, while the Bosch method uses greenhouse gases, the wet etching process does not require greenhouse gases, thereby reducing the burden on the global environment.

[0022] Next, as shown in FIG. 5 , a dielectric film 30 is formed on the surface of the substrate 10, including the inner wall surfaces of the through holes 20 (step S2). The dielectric film 30 is formed, for example, by thermally oxidizing the substrate 10. By thermally oxidizing the substrate 10, an oxide film containing the same elements as the substrate 10 is formed as the dielectric film 30. When forming the dielectric film 30, the substrate 10 may be thermally nitrided or thermally oxynitrided. By thermally nitriding the substrate 10, a nitride film containing the same elements as the substrate 10 is formed as the dielectric film 30, and by thermally oxynitriding the substrate 10, an oxynitride film containing the same elements as the substrate 10 is formed as the dielectric film 30. Next, internal electrodes 50 and 60 are formed to fill the through holes 20 inside the dielectric film 30 (step S3). The internal electrodes 50 and 60 can be formed, for example, by plating. Alternatively, the internal electrodes 50 and 60 may be formed by filling and firing a conductive paste.

[0023] 6, an insulating layer 91 is formed to cover the main surface 11 of the substrate 10 from below, with the dielectric film 30 sandwiched therebetween, and an insulating layer 92 is formed to cover the main surface 12 of the substrate 10 from above, with the dielectric film 30 sandwiched therebetween (step S4). Next, a plurality of contact holes 91A are formed in the insulating layer 91, and a plurality of contact holes 92A are formed in the insulating layer 92. The insulating layer 91 and the insulating layer 92 can be formed by, for example, chemical vapor deposition (CVD). The contact holes 91A and the contact holes 92A can be formed by, for example, etching using a mask.

[0024] 7, the external electrode 70 having the lead portion 71 is formed so as to contact the lower surface of the insulating layer 91, and the external electrode 80 having the lead portion 81 is formed so as to contact the upper surface of the insulating layer 92 (step S5). The external electrode 70 and the external electrode 80 can be formed by, for example, a sputtering method.

[0025] In this manner, the capacitor 1 according to the first embodiment can be manufactured.

[0026] Alternatively, the external electrode 70 may be formed after the insulating layer 91 is formed, and the insulating layer 92 and the external electrode 80 may be formed in this order after the external electrode 70 is formed. Alternatively, the external electrode 80 may be formed after the insulating layer 92 is formed, and the insulating layer 91 and the external electrode 70 may be formed in this order after the external electrode 80 is formed.

[0027] In the capacitor 1 according to the first embodiment, a plurality of through holes 20 penetrate the substrate 10, and a dielectric film 30 covers the surface of the substrate 10, including the inner wall surfaces of the plurality of through holes 20. Such a dielectric film 30 can be formed by thermal oxidation, thermal nitridation, or thermal oxynitridation of the substrate 10. The formation of the through holes 20 increases the area of ​​the substrate 10 facing the internal electrode 50 or the internal electrode 60 compared to when bottomed holes are formed instead of the through holes 20. This allows for a large capacitance to be obtained. Furthermore, even when the substrate 10 is thick, a thin dielectric film 30 can be formed with a consistent thickness by thermal oxidation, thermal nitridation, or thermal oxynitridation. This is because the oxidizing gas or nitriding gas used to form the dielectric film 30 can be uniformly supplied into the through holes 20. Furthermore, the through holes 20 can be easily filled with a conductive material without forming voids. Therefore, the capacitor 1 allows for a stable and high capacitance to be easily obtained.

[0028] Furthermore, in the capacitor 1, a dielectric film 30, a conductive substrate 10, and a dielectric film 30 are sandwiched in this order between adjacent internal electrodes 50 of a first polarity and internal electrodes 60 of a second polarity. This ensures a high degree of symmetry between the internal electrodes 50 of a first polarity and the internal electrodes 60 of a second polarity. Therefore, when the material of the internal electrodes 50 and the material of the internal electrodes 60 are the same, the influence of polarity on the characteristics of the capacitor 1 can be suppressed. In particular, by repeatedly arranging two internal electrodes 50 and one internal electrode 60 between the multiple internal electrodes 50 and the multiple internal electrodes 60 that are arranged in the closest-packed direction in a plan view perpendicular to the main surface 12, it is easy to ensure a higher degree of symmetry.

[0029] When the dielectric film 30 is a silicon nitride film, a higher dielectric constant is more easily obtained and the electric field strength is reduced than when the dielectric film 30 is a silicon oxide film. Furthermore, when the dielectric film 30 is a silicon nitride film, the barrier properties of the substrate 10 can be improved compared to when the dielectric film 30 is a silicon oxide film.

[0030] Furthermore, when the dielectric film 30 is formed by thermal oxidation, thermal nitridation, or thermal oxynitridation of the substrate 10, the manufacturing cost and time can be reduced more easily than when it is formed by atomic layer deposition (ALD) or CVD.

[0031] Furthermore, by arranging the internal electrodes 50 and 60 inside the through hole 20, the equivalent series inductance (ESL) and equivalent series resistance (ESR) can be reduced compared to when they are arranged inside a bottomed hole.

[0032] Second Embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the internal electrodes. FIG. 8 is a cross-sectional view showing a capacitor according to the second embodiment. FIG. 9 is a plan view showing the arrangement of internal electrodes in the capacitor according to the second embodiment. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG. 9.

[0033] 8 and 9, the capacitor 2 according to the second embodiment includes a substrate 10, a plurality of through holes 20, a dielectric film 30, a plurality of internal electrodes 40, an external electrode 70, an external electrode 80, and a plurality of insulating layers 95. Note that the external electrodes 70 and the insulating layers 95 are omitted from FIG.

[0034] The configurations of the substrate 10 and the through-hole 20 are the same as those in the first embodiment. The configuration of the dielectric film 30 is the same as that in the first embodiment, except that it is not formed on the main surface 12 of the substrate 10.

[0035] Each of the multiple internal electrodes 40 fills one through-hole 20 inside the dielectric film 30. The internal electrodes 40 are made of the same material as the internal electrodes 50 and 60, for example.

[0036] Each of the plurality of insulating layers 95 covers the upper surface of the internal electrode 40. The insulating layer 95 is made of, for example, the same material as the insulating layers 91 and 92. The thickness of the insulating layer 95 is, for example, 10 nm to 5000 nm.

[0037] The external electrode 70 is provided so as to contact the main surface 12 of the substrate 10 and the upper surfaces of the multiple insulating layers 95. The external electrode 70 is electrically connected to the substrate 10. The external electrode 80 is provided so as to contact the lower surfaces of the multiple internal electrodes 40 and the lower surface of the dielectric film 30. The external electrode 80 is electrically connected to the internal electrode 40. As in the first embodiment, voltages of opposite polarities are applied between the external electrode 70 and the external electrode 80. As a result, the conductive substrate 10 functions as an internal electrode of a first polarity, and the internal electrode 40 functions as an internal electrode of a second polarity.

[0038] Next, a method for manufacturing the capacitor 2 according to the second embodiment will be described. Figures 10 to 12 are perspective views showing the method for manufacturing the capacitor according to the second embodiment.

[0039] First, as in the first embodiment, a substrate 10 is prepared, and a plurality of through holes 20 are formed in the substrate 10 (see FIG. 4 ). Next, as shown in FIG. 10 , a dielectric film 30 is formed on the surface of the substrate 10, including the inner wall surfaces of the through holes 20. Next, internal electrodes 40 are formed to fill the through holes 20 inside the dielectric film 30. The internal electrodes 40 can be formed by, for example, a plating method. Alternatively, the internal electrodes 40 may be formed by filling and firing a conductive paste. Next, the portion of the dielectric film 30 covering the main surface 12 of the substrate 10 is removed by etching. As a result, the main surface 12 of the substrate 10 is exposed.

[0040] 11 , a plurality of insulating layers 95 are formed to cover the upper surfaces of the internal electrodes 40. The plurality of insulating layers 95 can be formed, for example, by forming and processing the main surfaces 12 of the insulating layers that will become the plurality of insulating layers 95 and the upper surfaces of the internal electrodes 40 as a whole.

[0041] Next, as shown in FIG. 12 , an external electrode 70 is formed so as to contact the main surface 12 of the substrate 10 and the upper surface of the insulating layer 95, and an external electrode 80 is formed so as to contact the lower surfaces of the multiple internal electrodes 40 and the lower surface of the dielectric film 30.

[0042] In this manner, the capacitor 2 according to the second embodiment can be manufactured.

[0043] As with the first embodiment, the capacitor 2 according to the second embodiment can easily and stably obtain a large capacitance.

[0044] Third Embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the external electrodes. Fig. 13 is a cross-sectional view showing a capacitor according to the third embodiment.

[0045] 13 , in addition to the configuration of capacitor 1, capacitor 3 according to the third embodiment has collector electrode 72, collector electrode 82, insulating layer 93, insulating layer 94, and connecting portion 74. Capacitor 3 has external electrodes 370 and 380 instead of external electrodes 70 and 80.

[0046] The configurations of the substrate 10, through-hole 20, dielectric film 30, internal electrode 50, internal electrode 60, and insulating layer 91 are the same as those in the first embodiment. The configuration of the insulating layer 92 is the same as that in the first embodiment, except that a contact hole 92B is formed in addition to multiple contact holes 92A. The contact hole 92B penetrates the insulating layer 92 in the Z-axis direction and reaches the top surface of one internal electrode 50. At least a portion of the top surface of the internal electrode 50 is exposed from the contact hole 92B.

[0047] The collecting electrode 72 is provided so as to contact the lower surface of the insulating layer 91. The collecting electrode 72 has a plurality of lead portions 73, each located within a contact hole 91A. The upper ends of the lead portions 73 contact the internal electrode 50, and the collecting electrode 72 is electrically connected to the internal electrode 50. The collecting electrode 82 is provided so as to contact the upper surface of the insulating layer 92. The collecting electrode 82 has a plurality of lead portions 83, each located within a contact hole 92A. The lower ends of the lead portions 83 contact the internal electrode 60, and the collecting electrode 82 is electrically connected to the internal electrode 60. The connecting portion 74 is provided away from the collecting electrode 82 so as to contact the upper surface of the insulating layer 92. The connecting portion 74 has a lead portion 75 located within a contact hole 92B. The lower ends of the lead portions 75 contact the internal electrode 50, and the connecting portion 74 is electrically connected to the internal electrode 50. The collector electrodes 72, 82 and connecting portions 74 are made of, for example, the same material as the external electrodes 70 and 80. The collector electrodes 72, 82 and connecting portions 74 have a thickness of, for example, 10 nm to 5000 nm.

[0048] The insulating layer 93 covers the lower surface of the insulating layer 91 from below, sandwiching the collecting electrode 72 therebetween. The insulating layer 94 covers the upper surface of the insulating layer 92 from above, sandwiching the collecting electrode 82 and the connecting portion 74 therebetween. The insulating layers 93 and 94 are made of, for example, the same material as the insulating layers 91 and 92. The thicknesses of the insulating layers 93 and 94 are, for example, 10 nm to 5000 nm.

[0049] A contact hole 94A is formed in the insulating layer 94, penetrating the insulating layer 94 in the Z-axis direction to reach the upper surface of the connecting portion 74, and a contact hole 94B is formed in the insulating layer 94, penetrating the insulating layer 94 in the Z-axis direction to reach the upper surface of the collecting electrode 82. At least a portion of the upper surface of the connecting portion 74 is exposed from the contact hole 94A, and at least a portion of the upper surface of the collecting electrode 82 is exposed from the contact hole 94B.

[0050] The external electrode 370 is provided so as to contact the upper surface of the insulating layer 94. The external electrode 370 has a lead portion 371 located within the contact hole 94A. The lower end of the lead portion 371 contacts the connection portion 74, and the external electrode 370 is electrically connected to the internal electrode 50 via the connection portion 74. The multiple internal electrodes 50 are also electrically connected to the collecting electrode 72. Therefore, the external electrode 370 is electrically connected to the multiple internal electrodes 50. The external electrode 380 is provided so as to contact the upper surface of the insulating layer 94. The external electrode 380 has a lead portion 381 located within the contact hole 94B. The lower end of the lead portion 381 contacts the collecting electrode 82, and the external electrode 380 is electrically connected to the multiple internal electrodes 60 via the collecting electrode 82. The external electrodes 370 and 380 are made of, for example, the same material as the external electrodes 70 and 80.

[0051] The third embodiment can also provide the same effects as the first embodiment.

[0052] The capacitor 3 according to the third embodiment is mounted on a circuit board, for example, with the main surface 12 facing the circuit board.

[0053] Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in the configuration of the external electrodes. Fig. 14 is a cross-sectional view showing a capacitor according to the fourth embodiment.

[0054] As shown in FIG. 14 , the capacitor 4 according to the fourth embodiment has external electrodes 470 and 480 instead of the external electrodes 370 and 380. The external electrode 470 is in contact with the upper surface of the insulating layer 94 and is provided so as to cover the side surface of the substrate 10 on the +X side over the dielectric film 30. The external electrode 470 has a lead portion 471 located within the contact hole 94A. The lower end of the lead portion 471 is in contact with the connection portion 74, and the external electrode 470 is electrically connected to the internal electrode 50. The external electrode 480 is in contact with the upper surface of the insulating layer 94 and is provided so as to cover the side surface of the substrate 10 on the -X side over the dielectric film 30. The external electrode 480 has a lead portion 481 located within the contact hole 94B. The lower end of the lead portion 481 is in contact with the collecting electrode 82, and the external electrode 480 is electrically connected to the internal electrode 60. The external electrodes 470 and 480 are made of, for example, the same material as the external electrodes 70 and 80 .

[0055] Other configurations of the fourth embodiment are the same as those of the third embodiment. The fourth embodiment can also achieve the same effects as those of the third embodiment. Furthermore, in the fourth embodiment, when a fluid conductive adhesive is used for mounting on a circuit board, the conductive adhesive can be made to wet and spread over a wide area of ​​the external electrodes 470 and 480, thereby achieving higher mounting reliability.

[0056] Fifth Embodiment Next, a fifth embodiment will be described. The fifth embodiment differs from the fourth embodiment mainly in the configuration of the external electrodes. Fig. 15 is a cross-sectional view showing a capacitor according to the fifth embodiment.

[0057] As shown in FIG. 15 , the capacitor 5 according to the fifth embodiment has external electrodes 570 and 580 instead of the external electrodes 470 and 480. In addition to the components of the capacitor 4, the capacitor 5 also has a connection portion 84. In the capacitor 5, in addition to multiple contact holes 91A, a contact hole 91B is formed in the insulating layer 91. The contact hole 91B penetrates the insulating layer 91 in the Z-axis direction and reaches the lower surface of one internal electrode 60. At least a portion of the lower surface of the internal electrode 60 is exposed through the contact hole 91B. The connection portion 84 is provided away from the collecting electrode 72 so as to contact the lower surface of the insulating layer 91. The connection portion 84 has a lead portion 85 located within the contact hole 91B. The upper end of the lead portion 85 contacts the internal electrode 60, and the connection portion 84 is electrically connected to the internal electrode 60.

[0058] A contact hole 93A is formed in the insulating layer 93, penetrating the insulating layer 93 in the Z-axis direction to reach the lower surface of the collecting electrode 72, and a contact hole 93B is formed in the insulating layer 93, penetrating the insulating layer 93 in the Z-axis direction to reach the lower surface of the connecting portion 84. At least a part of the lower surface of the collecting electrode 72 is exposed from the contact hole 93A, and at least a part of the lower surface of the connecting portion 84 is exposed from the contact hole 93B.

[0059] In addition to the configuration of the external electrode 470, the external electrode 570 has a portion in contact with the lower surface of the insulating layer 93 and a lead portion 576 located in the contact hole 93A. The upper end of the lead portion 576 contacts the collecting electrode 72, and the external electrode 570 is electrically connected to the internal electrode 50 via the collecting electrode 72 in addition to the connecting portion 74. In addition to the configuration of the external electrode 480, the external electrode 580 has a portion in contact with the lower surface of the insulating layer 93 and a lead portion 586 located in the contact hole 93B. The upper end of the lead portion 586 contacts the connecting portion 84, and the external electrode 580 is electrically connected to the internal electrode 60 via the connecting portion 84 in addition to the collecting electrode 82. The external electrodes 570 and 580 are made of, for example, the same materials as the external electrodes 70 and 80.

[0060] Other configurations of the fifth embodiment are the same as those of the fourth embodiment. The fifth embodiment also provides the same effects as those of the fourth embodiment.

[0061] The capacitor 3 according to the fifth embodiment can be mounted on a circuit board with either the main surface 11 or the main surface 12 facing the circuit board.

[0062] Sixth Embodiment Next, a sixth embodiment will be described. The sixth embodiment differs from the fifth embodiment mainly in the configuration of the external electrodes. Fig. 16 is a cross-sectional view showing a capacitor according to the sixth embodiment.

[0063] As shown in FIG. 16 , the capacitor 6 according to the sixth embodiment has an external electrode 370 and an external electrode 670 instead of the external electrode 570, and an external electrode 380 and an external electrode 680 instead of the external electrode 580. The external electrode 670 is provided so as to contact the lower surface of the insulating layer 93 and has a lead portion 676 located within the contact hole 93A. The upper end of the lead portion 676 contacts the collector electrode 72, and the external electrode 670 is electrically connected to the internal electrode 50 via the collector electrode 72. The external electrode 680 is provided so as to contact the lower surface of the insulating layer 93 and has a lead portion 686 located within the contact hole 93B. The upper end of the lead portion 686 contacts the connection portion 84, and the external electrode 680 is electrically connected to the internal electrode 60 via the connection portion 84. The external electrodes 670 and 680 are made of, for example, the same material as the external electrodes 70 and 80.

[0064] Other configurations of the sixth embodiment are the same as those of the fifth embodiment. The sixth embodiment also provides the same effects as those of the fifth embodiment.

[0065] Seventh Embodiment Next, a seventh embodiment will be described. The seventh embodiment differs from the fifth embodiment mainly in the configuration of the external electrodes. Fig. 17 is a front view showing a capacitor according to the seventh embodiment.

[0066] As shown in FIG. 17 , the capacitor 7 according to the seventh embodiment has external electrodes 770 and 780 instead of the external electrodes 570 and 580. The external electrode 770 has a lead portion 771 located in the contact hole 94A and a lead portion 772 located in the contact hole 93A. The lower end of the lead portion 771 contacts the connecting portion 74, and the upper end of the lead portion 772 contacts the collecting electrode 72, so that the external electrode 770 is electrically connected to the internal electrode 50. The external electrode 780 has a lead portion 781 located in the contact hole 94B and a lead portion 782 located in the contact hole 93B. The lower end of the lead portion 781 contacts the collecting electrode 82, and the upper end of the lead portion 782 contacts the connecting portion 84, so that the external electrode 780 is electrically connected to the internal electrode 60.

[0067] The external electrodes 770 and 780 have the same configuration as the external electrodes 570 and 580, respectively, but also have portions that cover two side surfaces perpendicular to the Y-axis direction. That is, the external electrode 770 covers five surfaces of the substrate 10: the +Z side surface (main surface 12), the -Z side surface (main surface 11), the +X side surface, the +Y side surface, and the -Y side surface. The external electrode 780 also covers five surfaces of the substrate 10: the +Z side surface (main surface 12), the -Z side surface (main surface 11), the -X side surface, the +Y side surface, and the -Y side surface. The +Y side surface and the -Y side surface of the substrate 10 are covered by the dielectric film 30, and the external electrodes 770 and 780 cover the +Y side surface and the -Y side surface of the substrate 10 from above the dielectric film 30. The +Y side surface and the −Y side surface of the substrate 10 may be covered with the dielectric film 30 and an insulating layer made of the same material as the insulating layers 91 and 92. The external electrodes 770 and 780 are made of, for example, the same material as the external electrodes 70 and 80.

[0068] Other configurations of the seventh embodiment are the same as those of the fifth embodiment. The seventh embodiment can also achieve the same effects as those of the fifth embodiment. Furthermore, in the seventh embodiment, when a fluid conductive adhesive is used for mounting on a circuit board, the conductive adhesive can be made to wet and spread over a wide area of ​​the external electrodes 770 and 780, thereby achieving higher mounting reliability.

[0069] Eighth Embodiment Next, an eighth embodiment will be described. The eighth embodiment differs from the first embodiment mainly in the configuration of the external electrodes. Fig. 18 is a cross-sectional view showing a capacitor according to the eighth embodiment.

[0070] 18 , like the third embodiment, the capacitor 8 according to the eighth embodiment has a collector electrode 72, a collector electrode 82, an insulating layer 93, and an insulating layer 94 in addition to the components of the capacitor 1. Furthermore, the capacitor 8 according to the eighth embodiment has external electrodes 870 and 880 instead of the external electrodes 70 and 80.

[0071] A plurality of internal electrodes 50 and a collector electrode 72 are exposed from the side surface of the substrate 10 on the +X side, and a plurality of internal electrodes 60 and a collector electrode 82 are exposed from the side surface of the substrate 10 on the -X side. The external electrode 870 is in contact with the plurality of internal electrodes 50 and the collector electrode 72 exposed from the side surface of the substrate 10 on the +X side. The external electrode 880 is in contact with the plurality of internal electrodes 60 and the collector electrode 82 exposed from the side surface of the substrate 10 on the -X side. Therefore, the external electrode 870 is electrically connected to the plurality of internal electrodes 50 via the collector electrode 72, and the external electrode 880 is electrically connected to the plurality of internal electrodes 60 via the collector electrode 82. In addition, the external electrodes 870 and 880 have portions that contact the upper surface of the insulating layer 94. The external electrodes 870 and 880 are made of, for example, the same material as the external electrodes 70 and 80.

[0072] Other configurations of the eighth embodiment are the same as those of the first embodiment. The eighth embodiment can also achieve the same effects as those of the first embodiment.

[0073] The capacitor 8 according to the eighth embodiment is mounted on a circuit board, for example, with the main surface 12 facing the circuit board. Furthermore, when a fluid conductive adhesive is used for mounting on the circuit board, the conductive adhesive can be made to wet and spread over a wide area of ​​the external electrodes 870 and 880, thereby achieving higher mounting reliability.

[0074] Ninth Embodiment Next, a ninth embodiment will be described. The ninth embodiment differs from the eighth embodiment mainly in the configuration of the external electrodes. Fig. 19 is a cross-sectional view showing a capacitor according to the ninth embodiment.

[0075] 19 , the capacitor 9 according to the ninth embodiment has external electrodes 970 and 980 instead of the external electrodes 870 and 880. The external electrodes 970 and 980 do not have portions that contact the upper surface of the insulating layer 94.

[0076] Other configurations of the ninth embodiment are the same as those of the eighth embodiment. The ninth embodiment also provides the same effects as the first embodiment.

[0077] Tenth Embodiment Next, a tenth embodiment will be described. The tenth embodiment relates to a mounting board having a capacitor. Fig. 20 is a cross-sectional view showing a mounting board according to the tenth embodiment.

[0078] 20 , the mounting board 100 according to the tenth embodiment has a circuit board 110 and the capacitor 3 according to the third embodiment. The circuit board 110 is provided with a connection land 101 and a connection land 102. The capacitor 3 is mounted on the circuit board 110. An external electrode 370 is joined to the connection land 101, and an external electrode 380 is joined to the connection land 102.

[0079] The mounting board 100 can be mounted on various electronic devices. Examples of electronic devices that include the mounting board 100 include smartphones, mobile phones, tablet terminals, and game consoles.

[0080] Instead of the capacitor 3, the capacitors 1, 2, 4, 5, 6, 7, 8, and 9 may be used.

[0081] The shape of the cross section perpendicular to the longitudinal direction of the through hole 20 is not limited to a circular shape, and may be other shapes such as a square, rectangular, triangular, hexagonal, or zigzag shape. Furthermore, the plurality of through holes 20 may be arranged in other layouts, such as a square lattice pattern. Furthermore, the arrangement of the plurality of internal electrodes 50 and the plurality of internal electrodes 60 aligned in the closest-packed direction in a plan view perpendicular to the main surface 12 is not limited to the above example. For example, one internal electrode 50 and one internal electrode 60 may be arranged repeatedly. Furthermore, the through hole 20 may have a tapered inner wall surface in which the opening area narrows with increasing distance from the main surface 11, or may have a tapered inner wall surface in which the opening area narrows with increasing distance from the main surface 12.

[0082] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0083] This application claims priority based on Japanese Patent Application No. 2023-108377 filed with the Japan Patent Office on June 30, 2023, the entire contents of which are incorporated herein by reference.

[0084] Aspects of the present disclosure are, for example, as follows.

[0085] <1> A capacitor comprising: a conductive substrate having a first main surface and a second main surface opposite the first main surface; a plurality of through holes formed in the substrate, the through holes penetrating from the first main surface to the second main surface; a dielectric film covering a surface of the substrate including inner wall surfaces of the plurality of through holes; and a plurality of internal electrodes filling each of the plurality of through holes inside the dielectric film.

[0086] <2> The capacitor according to <1>, wherein the plurality of internal electrodes include: a plurality of first internal electrodes of a first polarity; and a plurality of second internal electrodes of a second polarity different from the first polarity.

[0087] <3> The capacitor according to <2>, comprising: a first external electrode electrically connected to the plurality of first internal electrodes; and a second external electrode electrically connected to the plurality of second internal electrodes.

[0088] <4> The capacitor according to <2> or <3>, wherein two of the first internal electrodes and one of the second internal electrodes are repeatedly arranged between the plurality of first internal electrodes and the plurality of second internal electrodes that are arranged in a closest-packed direction in a plan view perpendicular to the second main surface.

[0089] <5> The capacitor according to <1>, comprising: a first external electrode electrically connected to the substrate; and a second external electrode electrically connected to the plurality of internal electrodes.

[0090] <6> The capacitor according to any one of <1> to <5>, wherein the dielectric film is an oxide film, a nitride film, or an oxynitride film containing the same element as the substrate.

[0091] <7> The capacitor according to any one of <1> to <6>, wherein the substrate contains silicon, hafnium, lanthanum, niobium, tantalum, titanium, or zirconium.

[0092] <8> A mounting board comprising: a circuit board; and the capacitor according to any one of <1> to <7> mounted on the circuit board.

[0093] <9> A method for manufacturing a capacitor, comprising: a step of forming a plurality of through holes in a conductive base material having a first main surface and a second main surface opposite to the first main surface, the through holes penetrating from the first main surface to the second main surface; a step of forming a dielectric film covering a surface of the base material including inner wall surfaces of the plurality of through holes by oxidizing, nitriding, or oxynitriding the base material; and a step of forming a plurality of internal electrodes inside the dielectric film, each filling the through holes.

[0094] <10> The method for manufacturing a capacitor according to <9>, wherein the plurality of internal electrodes include a plurality of first internal electrodes of a first polarity and a plurality of second internal electrodes of a second polarity different from the first polarity.

[0095] <11> The method for manufacturing a capacitor according to <10>, comprising: a step of forming a first external electrode electrically connected to the plurality of first internal electrodes; and a step of forming a second external electrode electrically connected to the plurality of second internal electrodes.

[0096] <12> The method for manufacturing a capacitor according to <9>, comprising: a step of forming a first external electrode electrically connected to the base material; and a step of forming a second external electrode electrically connected to the plurality of internal electrodes.

[0097] 1, 2, 3, 4, 5, 6, 7, 8, 9: Capacitor 10: Substrate 11, 12: Main surface 20: Through hole 30: Dielectric film 40, 50, 60: Internal electrode 70, 80, 370, 380, 470, 480, 570, 580, 670, 680, 770, 780, 870, 880, 970, 980: External electrode 100: Mounting substrate 101, 102: Connection land 110: Circuit board

Claims

1. A capacitor comprising: a conductive substrate having a first main surface and a second main surface opposite the first main surface; a plurality of through holes formed in the substrate and penetrating from the first main surface to the second main surface; a dielectric film covering a surface of the substrate including inner wall surfaces of the plurality of through holes; and a plurality of internal electrodes filling each of the plurality of through holes inside the dielectric film.

2. The capacitor of claim 1, wherein the plurality of internal electrodes comprises: a plurality of first internal electrodes of a first polarity; and a plurality of second internal electrodes of a second polarity different from the first polarity.

3. The capacitor according to claim 2, comprising: a first external electrode electrically connected to said plurality of first internal electrodes; and a second external electrode electrically connected to said plurality of second internal electrodes.

4. A capacitor as described in claim 2 or 3, wherein two of the first internal electrodes and one of the second internal electrodes are repeatedly arranged between the plurality of first internal electrodes and the plurality of second internal electrodes which are arranged in a close-packed direction in a plan view perpendicular to the second principal surface.

5. The capacitor of claim 1, comprising: a first external electrode electrically connected to said substrate; and a second external electrode electrically connected to said plurality of internal electrodes.

6. The capacitor according to claim 1, 2, 3 or 5, wherein the dielectric film is an oxide film, a nitride film or an oxynitride film containing the same elements as the substrate.

7. The capacitor of claim 1, 2, 3 or 5, wherein the substrate comprises silicon, hafnium, lanthanum, niobium, tantalum, titanium or zirconium.

8. A mounting board comprising: a circuit board; and a capacitor according to any one of claims 1 to 3 mounted on the circuit board.

9. A method for manufacturing a capacitor, comprising the steps of: forming a plurality of through holes in a conductive substrate having a first main surface and a second main surface opposite the first main surface, the through holes penetrating from the first main surface to the second main surface; forming a dielectric film covering a surface of the substrate including inner wall surfaces of the plurality of through holes by oxidizing, nitriding or oxynitriding the substrate; and forming a plurality of internal electrodes inside the dielectric film, each filling the through holes.

10. The method for manufacturing a capacitor according to claim 9, wherein the plurality of internal electrodes are formed as a plurality of first internal electrodes of a first polarity and a plurality of second internal electrodes of a second polarity different from the first polarity.

11. The method of manufacturing a capacitor as set forth in claim 10, comprising the steps of: forming a first external electrode electrically connected to said plurality of first internal electrodes; and forming a second external electrode electrically connected to said plurality of second internal electrodes.

12. The method for manufacturing a capacitor according to claim 9, comprising the steps of: forming a first external electrode electrically connected to the base material; and forming a second external electrode electrically connected to the plurality of internal electrodes.

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