Transistor preparation method and electronic device
By performing anisotropic etching of the gate material on the second silicon layer during the preparation of the vertical gate fully surround transistor, the problem of the source/drain being easily contaminated by metal is solved, short circuits with the gate are avoided, and the reliability of the preparation process is improved.
Patent Information
- Application Number
- PCT/CN2023/116357
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-07-06
- Filing Date
- 2023-08-31
- Publication Date
- 2025-03-06
AI Technical Summary
During the deposition of the vertical gate fully surrounds the metal gate of the transistor, the source/drain is prone to metal contamination and difficult to remove, which may lead to a short circuit between the source/drain and the metal gate.
By performing anisotropic etching of the gate material on the second silicon layer, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer is removed, and then the remaining gate material in the second silicon layer is removed again, avoiding short circuits between the source/drain and the gate.
It effectively prevents the transistor's source/drain from being contaminated by metal, avoids short circuit between the source/drain and the gate, and improves the reliability of the transistor preparation process.
Smart Images
Figure CN2023116357_06032025_PF_FP_ABST
Abstract
Description
Transistor manufacturing method and electronic device
[0001] This application claims priority to Chinese patent application No. 202310827205.6, filed on July 6, 2023, entitled “Transistor Manufacturing Method and Electronic Device,” the entire contents of which are incorporated herein by reference. Technical Field
[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor and an electronic device. Background Art
[0003] The vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a smaller projected area and an unlimited channel length.
[0004] In the related art, during the process of depositing the metal gate of a VGAA transistor, metal contamination is easily generated on the exposed source / drain and is difficult to remove, which may cause a short circuit between the source / drain and the metal gate.
[0005] Summary of the Invention
[0006] The embodiments of the present application provide a method for manufacturing a transistor and an electronic device, which effectively prevents the source / drain of the transistor from being contaminated by metal. The technical solution is as follows:
[0007] In one aspect, a method for preparing a transistor is provided, the method comprising:
[0008] A first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 are sequentially stacked on a silicon substrate 300, wherein the first silicon layer 301 is in contact with the silicon substrate 300;
[0009] By etching the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303, a plurality of first silicon pillars 304 are formed along a first direction;
[0010] A plurality of columns of second masks 305 are formed along a second direction on the plurality of first silicon pillars 304, wherein the second masks 305 include sidewall spacers 305-1; the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 are etched according to the plurality of columns of second masks 305; the silicon germanium layer 302 is further etched based on the grooves obtained by etching to form lateral grooves; epitaxial silicon is laterally grown on the first silicon layer 301, the lateral grooves, and the second silicon layer 303; a gate material is deposited above the first silicon layer 301; anisotropic etching of the gate material is performed according to the plurality of sidewall spacers 305-1 to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer 303; the gate material within the plurality of sidewall spacers 305-1 and the second silicon layer 303 is then removed to form a plurality of second silicon pillars 306, wherein the plurality of second silicon pillars 306 are arranged in an array along the first direction and the second direction;
[0011] Based on the plurality of second silicon pillars 306 , a vertical all-around gate transistor is formed.
[0012] In another aspect, an electronic device is provided, comprising a logic device fabricated using the above transistor fabrication method. The electronic device comprises a smartphone, computer, tablet computer, artificial intelligence device, wearable device, or smart mobile terminal.
[0013] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:
[0014] By performing anisotropic etching on the gate material of the second silicon layer 303, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source / drain and the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0016] FIG1 is a schematic diagram of a VGAA transistor provided by one or more exemplary embodiments of the present application;
[0017] FIG2 is a flow chart of a method for manufacturing a transistor according to one or more exemplary embodiments of the present application;
[0018] FIG3 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
[0019] FIG4 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
[0020] FIG5 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
[0021] FIG6 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
[0022] FIG7 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0023] FIG8 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
[0024] FIG9 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
[0025] FIG10 is a flow chart of a method for manufacturing a transistor according to one or more exemplary embodiments of the present application;
[0026] FIG11 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0027] FIG12 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0028] FIG13 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0029] FIG14 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0030] FIG15 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0031] FIG16 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided in one or more exemplary embodiments of the present application;
[0032] FIG17 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0033] FIG18 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0034] FIG19 is a schematic diagram of a process for forming a stacked structure according to one or more exemplary embodiments of the present application;
[0035] FIG20 is a schematic diagram of a process for forming a stacked structure according to one or more exemplary embodiments of the present application;
[0036] FIG21 is a schematic diagram of a process for forming a stacked structure according to one or more exemplary embodiments of the present application;
[0037] FIG. 22 is a schematic diagram of a process for forming a stacked structure according to one or more exemplary embodiments of the present application. DETAILED DESCRIPTION
[0038] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.
[0039] In an embodiment of the present application, a method for preparing a transistor is provided. Optionally, the method for preparing the transistor is mainly used in the preparation process of a VGAA transistor.
[0040] First, the structure of the VGAA transistor is introduced. As shown in FIG1 , a transistor array 100 includes multiple transistor units. Each transistor unit includes a bit line (BL) 111 , a word line (WL) 112 , a source / drain 113 , and a gate 114 .
[0041] Among them, multiple transistor units in the same column of the transistor array 100 are coupled to the extended bit line 111 to connect the multiple transistor units in the same column; multiple transistor units in the same row of the transistor array 100 are coupled to the extended word line 112 to connect the multiple transistor units in the same row.
[0042] The word line 112 is connected to the gate 114 and serves as a gate line to turn on the transistor unit. The bit line 111 is connected to the source / drain 113 and serves as a data signal writing line. The word line 112 surrounds the gate 114.
[0043] FIG2 shows a flow chart of a method for manufacturing a transistor provided by an exemplary embodiment of the present application, the method comprising:
[0044] Step 201 , stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
[0045] With reference to FIG. 3 , FIG. 3 shows that a first silicon layer 301 , a silicon germanium layer 302 , and a second silicon layer 303 are sequentially stacked on a silicon substrate 300 ; wherein the first silicon layer 301 is in contact with the silicon substrate 300 .
[0046] Step 202 , forming a plurality of first silicon pillars along a first direction by etching the first silicon layer, the silicon germanium layer, and the second silicon layer;
[0047] In one embodiment, multiple columns of first masks are formed on the second silicon layer along a first direction; the first silicon layer, silicon germanium layer, and second silicon layer are etched according to the multiple columns of first masks to form multiple first silicon pillars along the first direction.
[0048] Multiple columns of first masks are formed on the second silicon layer 303 along a first direction. Optionally, the first direction is the direction of the bit lines of the transistor to be ultimately generated. Optionally, the mask material includes a photoresist, a photoresist, an anti-reflective material, and some hard mask materials. The multiple columns of first masks extend along the first direction.
[0049] With reference to FIG. 4 , FIG. 4 illustrates a three-dimensional structure obtained by etching a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 using multiple columns of a first mask. FIG. 4 illustrates multiple first silicon pillars 304 along a first direction. In one embodiment, a SADP (Self-Aligned Double Patterning) process is used to etch the silicon substrate 300, the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303. In one embodiment, SADP is used for etching based on the array period size or critical dimension. In one embodiment, SAQP (Self-aligned Quadruple Patterning) is used for etching based on the array period size or critical dimension. In one embodiment, LELE (Litho-Etch-Lith-Etch) is used for etching based on the array period size or critical dimension. In one embodiment, a dry process is used for etching.
[0050] Step 203, forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars, wherein the second masks include sidewalls;
[0051] With reference to Figure 5 , which shows multiple columns of second masks 305 , the multiple columns of second masks 305 extend along a second direction. Optionally, the second direction is the direction of word lines of transistors ultimately generated.
[0052] Step 204, etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the plurality of columns of the second mask; based on the grooves obtained by etching, further etching the silicon germanium layer to form lateral grooves; and performing lateral epitaxial silicon growth on the first silicon layer, the lateral grooves, and the second silicon layer;
[0053] 6 , FIG6 (A) shows a three-dimensional structure formed after performing a silicon lateral epitaxy operation, and FIG6 (B) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0054] Step 205: depositing a gate material on the first silicon layer; performing anisotropic etching on the gate material along the plurality of sidewalls to remove the gate material except for the epitaxial silicon sidewalls of the second silicon layer; and then removing the gate material within the plurality of sidewalls and the second silicon layer to form a plurality of second silicon pillars.
[0055] Optionally, the gate material includes at least one of a gate oxide layer, a high-K material and a gate metal layer.
[0056] Optionally, the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
[0057] With reference to FIG7 , FIG7 (A) shows a three-dimensional structure obtained by depositing a gate material within the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of spacers 305-1. FIG7 (B) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure viewed along the second direction. In other words, FIG7 shows a three-dimensional structure obtained by filling the first silicon layer 301 with a gate material.
[0058] With reference to FIG8 , portion (A) of FIG8 illustrates a three-dimensional structure obtained by performing anisotropic etching of the gate material using the plurality of sidewall spacers 305-1 in the plurality of columns of the second mask 305. FIG8 (B) illustrates a two-dimensional schematic diagram of the corresponding three-dimensional structure as viewed along the second direction. In one embodiment, after performing the anisotropic etching of the gate material, metal residues on the sidewalls of the plurality of sidewall spacers 305-1 and the epitaxial silicon sidewalls of the second silicon layer 303 are also removed. In one embodiment, after performing the anisotropic etching of the gate material, the sidewalls of the silicon germanium layer 302 are also aligned with the sidewalls of the plurality of sidewall spacers 305-1.
[0059] With reference to FIG9 , FIG9 (A) shows a three-dimensional structural diagram of multiple second silicon pillars 306 formed by further removing multiple sidewall spacers 305-1 and gate material within the second silicon layer 303. FIG9 (B) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure viewed along the second direction. FIG9 shows multiple second silicon pillars 306 arranged in an array along the first direction and the second direction.
[0060] Step 206 : forming a vertical all-around gate transistor based on the plurality of second silicon pillars.
[0061] In one embodiment, a vertical all-around gate transistor is formed based on the plurality of second silicon pillars 306 by adding contact pins.
[0062] In summary, by performing anisotropic etching on the gate material of the second silicon layer 303, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source / drain and the gate.
[0063] FIG10 shows a flow chart of a method for manufacturing a transistor provided by an exemplary embodiment of the present application, the method comprising:
[0064] Step 1001: stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
[0065] With reference to FIG. 11 , part (A) of FIG. 11 shows that a first silicon layer 301 , a silicon germanium layer 302 , and a second silicon layer 303 are sequentially stacked on a silicon substrate 300 , wherein the first silicon layer 301 is in contact with the silicon substrate 300 .
[0066] Step 1002 : forming a plurality of first silicon pillars along a first direction by etching the first silicon layer, the silicon germanium layer, and the second silicon layer.
[0067] In one embodiment, multiple columns of first masks are formed on the second silicon layer along a first direction; the first silicon layer, silicon germanium layer, and second silicon layer are etched according to the multiple columns of first masks to form multiple first silicon pillars along the first direction.
[0068] Multiple columns of first masks are formed on the second silicon layer 301 along a first direction. Optionally, the first direction is the direction of the bit lines of the transistor to be formed. Mask materials include photoresist, photoresist, anti-reflective materials, and some hard mask materials. Optionally, the first masks extend along the first direction.
[0069] With reference to FIG11 , FIG11B shows etching of the first silicon layer 301, silicon germanium layer 302, and second silicon layer 303 using multiple columns of first masks to form a three-dimensional structure of multiple first silicon pillars 304 along a first direction. In one embodiment, the etching removes portions of the first silicon layer 301, silicon germanium layer 302, and second silicon layer 303 not covered by the first mask. In one embodiment, the etching is performed using a dry process.
[0070] In one embodiment, SADP is used for etching according to the array period size or critical size. In one embodiment, SAQP (Self-aligned Quadruple Patterning) is used for etching according to the array period size or critical size. In one embodiment, LELE (Litho-Etch-Lith-Etch) is used for etching according to the array period size or critical size.
[0071] Step 1003, filling oxide between the plurality of first silicon pillars;
[0072] 11 , portion (C) of FIG11 shows a three-dimensional structure formed by oxide between the plurality of first silicon pillars 304. Optionally, the oxide is silicon dioxide.
[0073] Step 1004, forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars, the second masks including sidewalls;
[0074] 12 , part (A) of FIG12 shows a three-dimensional structure obtained by forming multiple columns of second masks 305 along the second direction on the multiple first silicon pillars 304. The second masks 305 extend along the second direction.
[0075] Step 1005 , etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to multiple columns of the second mask to form a plurality of first grooves;
[0076] With reference to FIG12 , portion (B) of FIG12 illustrates a three-dimensional structure obtained by etching the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 using multiple columns of second masks 305 to form multiple first grooves 307. In one embodiment, portions of the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 not covered by the multiple columns of second masks 305 are etched away. FIG12 (B) also illustrates any one of the multiple columns of second masks 305, including a three-layer structure comprising a sidewall 305-1, a mandrel 305-2, and a sidewall 305-1. In one embodiment, etching is performed using a dry process.
[0077] Step 1006, performing a first lateral etching on the silicon germanium layer;
[0078] With reference to FIG. 12 , portion ( C1 ) of FIG. 12 shows a three-dimensional structure obtained by performing a first lateral etching on the silicon germanium layer 302 .
[0079] Part (C2) of Figure 12 shows a two-dimensional plan view of the corresponding three-dimensional structure observed from a second direction. In one embodiment, the second direction is the word line direction. The second direction is the direction of the word line of the transistor finally generated.
[0080] In one embodiment, the first lateral etching is performed using an ALE (Atomic Layer Etch) process.
[0081] Step 1007 , performing a first lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer, and the second silicon layer to form a first lateral groove; filling the first lateral groove with oxide and grinding it flat; filling the first groove with oxide and grinding it flat;
[0082] With reference to FIG13 , portion (A1) of FIG13 illustrates a three-dimensional structure formed by performing a first lateral epitaxial silicon growth on the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 to form a first lateral groove 308. Portion (A2) of FIG13 illustrates a two-dimensional plan view of the corresponding three-dimensional structure viewed along a second direction.
[0083] Part (B1) of Figure 13 shows the three-dimensional structure obtained by filling the first lateral groove 308 and the first groove 307 with oxide and then grinding them flat. Part (B2) of Figure 13 shows a two-dimensional plan view of the corresponding three-dimensional structure viewed along the second direction. In one embodiment, the grinding operation is performed by CMP (Chemical Mechanical Polishing).
[0084] Step 1008 , etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the plurality of mandrels in the plurality of columns of the second mask to form a plurality of second grooves;
[0085] With reference to FIG13 , portion (C1) of FIG13 illustrates a three-dimensional structure in which the first silicon layer 301, the silicon-germanium layer 302, and the second silicon layer 303 are etched according to multiple mandrels 305-2 in multiple columns of second mask 305 to form multiple second grooves 309. Portion (C2) of FIG13 illustrates a two-dimensional plan view of the corresponding three-dimensional structure as viewed along the second direction.
[0086] In one embodiment, the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 are partially covered by the mandrels 305-2. In one embodiment, the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 are partially covered by the spacers 305-1.
[0087] In one embodiment, a wet process or an ALE (Atomic Layer Etch) process is used to etch the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 to form a plurality of second grooves 309 .
[0088] Step 1009, performing a second lateral etching on the silicon germanium layer;
[0089] With reference to FIG14 , portion (A1) of FIG14 illustrates a three-dimensional structure obtained by performing a second lateral etching on silicon-germanium layer 302. Portion (A2) of FIG14 illustrates a two-dimensional plan view of the corresponding three-dimensional structure as viewed along the second direction. Combined with the first lateral etching of silicon-germanium layer 302 in step 1007, these two lateral etching steps result in the complete removal of the silicon-germanium material from silicon-germanium layer 302.
[0090] Step 1010, performing a second lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer, and the second silicon layer to form a second lateral groove, filling the second lateral groove with oxide and grinding it flat; filling the second groove with oxide and grinding it flat;
[0091] With reference to FIG14 , portion (B1) of FIG14 illustrates a three-dimensional structure in which a second lateral epitaxial silicon growth is performed on first silicon layer 301, silicon germanium layer 302, and second silicon layer 303 to form second lateral groove 310. Portion (B2) of FIG14 illustrates a two-dimensional plan view of the corresponding three-dimensional structure as viewed along a second direction.
[0092] Part (C1) of Figure 14 shows the three-dimensional structure obtained by filling the second lateral groove 310 with oxide and then grinding it flat, and filling the second groove 309 with oxide and then grinding it flat. Part (C2) of Figure 14 shows a two-dimensional plan view of the corresponding three-dimensional structure. Optionally, the oxide is silicon dioxide.
[0093] In one embodiment, the planarizing operation is performed by CMP (Chemical Mechanical Polishing).
[0094] Step 1011, etching the oxide above the first silicon layer;
[0095] With reference to Figure 15 , part (A1) of Figure 15 shows the three-dimensional structure after the oxide between the second silicon layer 303 and the plurality of sidewalls 305-1 is etched. Part (A2) of Figure 15 shows a two-dimensional plan view of the corresponding three-dimensional structure. With reference to Figure 15 , part (B1) of Figure 15 shows the three-dimensional structure after the oxide of the further silicon germanium layer 302 is etched. Part (B2) of Figure 15 shows a two-dimensional plan view of the corresponding three-dimensional structure. That is, parts (A1), (A2), (B1), and (B2) of Figure 15 show schematic diagrams after the oxide above the first silicon layer is etched.
[0096] In one embodiment, the oxide on the silicon germanium layer 302 is etched by a dry process; and then the oxide on the silicon germanium layer 302 is etched by a wet process.
[0097] Step 1012, depositing a gate material in the gaps between the silicon germanium layer, the second silicon layer, and the plurality of spacers;
[0098] Optionally, the gate material includes at least one of a gate oxide layer, a high-K material, and a gate metal layer. Optionally, the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and zirconium oxide, as well as conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
[0099] With reference to FIG15 , portion (C1) of FIG15 illustrates a three-dimensional structure obtained by depositing a gate material within the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of spacers 305-1. Portion (C2) of FIG15 illustrates a two-dimensional plan view of the corresponding three-dimensional structure. Specifically, portions (C1) and (C2) of FIG15 illustrate schematic diagrams of a three-dimensional structure obtained by depositing a gate material within the gaps above the first silicon layer 301.
[0100] Step 1013: performing anisotropic etching of the gate material on the layer where the multiple spacers are located, etching to the sidewalls of the multiple spacers; performing anisotropic etching of the gate material on the second silicon layer, etching to the epitaxial silicon sidewalls of the second silicon layer; and performing anisotropic etching of the gate material on the silicon germanium layer outside the coverage of the multiple spacers in the multiple columns of the second mask;
[0101] With reference to FIG16 , portion (A1) of FIG16 illustrates a three-dimensional structure obtained by performing anisotropic etching of the gate material on the layer containing the multiple spacers 305-1, the second silicon layer 303, and the silicon germanium layer 302. The anisotropic etching of the metal in the layer containing the multiple spacers 305-1 will etch to the sidewalls of the multiple spacers, the anisotropic etching of the metal in the second silicon layer 303 will etch to the epitaxial silicon sidewalls, and the anisotropic etching of the metal in the silicon germanium layer 302 will etch to the coverage boundary of the multiple spacers 305-1. Portion (A2) of FIG16 illustrates a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0102] In one embodiment, after performing anisotropic etching of the gate material, metal residues are removed from the sidewalls of the plurality of spacers 305-1 and the epitaxial silicon sidewalls of the second silicon layer 303. In one embodiment, after performing anisotropic etching of the gate material, the sidewalls of the silicon germanium layer 302 are aligned with the sidewalls of the plurality of spacers 305-1.
[0103] Step 1014, filling oxide in the gaps between the silicon germanium layer, the second silicon layer, and the plurality of spacers;
[0104] With reference to FIG16 , portion (B1) of FIG16 illustrates a three-dimensional structure obtained by filling the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of sidewall spacers 305-1 with oxide. Portion (B2) of FIG16 illustrates a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction. Specifically, portions (B1) and (B2) of FIG16 illustrate a three-dimensional structure obtained by filling the gaps above the first silicon layer 301 with oxide. Optionally, the oxide is silicon dioxide.
[0105] Step 1015, removing multiple sidewalls;
[0106] Step 1016, removing the remaining gate material in the second silicon layer to form a plurality of second silicon pillars;
[0107] With reference to FIG16 , portion (C1) of FIG16 illustrates a three-dimensional structure obtained by removing the plurality of spacers 305-1 and the remaining gate material within the second silicon layer 303. Portion (C2) of FIG16 illustrates a two-dimensional plan view of the corresponding three-dimensional structure observed along a second direction. Portions (C1) and (C2) of FIG16 illustrate the second silicon pillar 306.
[0108] Step 1017 , forming a vertical all-around gate transistor based on the plurality of second silicon pillars.
[0109] In one embodiment, a vertical all-around gate transistor is formed by adding contact pins based on the plurality of second silicon pillars 306. In this embodiment, the vertical all-around gate transistor is also referred to as a metal-all-around gate transistor or a metal-replaceable gate transistor.
[0110] In summary, by performing anisotropic etching on the gate material of the second silicon layer 303, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source / drain and the gate.
[0111] In one embodiment, step 202 or step 1002 includes: forming a plurality of first silicon pillars along a first direction by etching the silicon substrate, the first silicon layer, the silicon germanium layer, and the second silicon layer.
[0112] Based on the method embodiments shown in FIG. 2 and FIG. 10 , when executing step 201 and step 1001 , well isolation is also formed in the stack structure.
[0113] In one embodiment, with reference to FIG17 , portion (A1) of FIG17 shows a stacked structure after forming well isolation. Portion (A2) of FIG17 shows a two-dimensional plan view of the stacked structure. Consider that the stacked structure after well isolation includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303. Further, the silicon substrate 300 includes an upper silicon substrate 300-1 and a lower silicon substrate 300-2. Optionally, the lower silicon substrate 300-2 is doped to N-type, the upper silicon substrate 300-1 is doped to P-type, and the first silicon layer 301 is doped to P-type. Optionally, the lower silicon substrate 300-2 is doped to P-type, the upper silicon substrate 300-1 is doped to N-type, and the first silicon layer 301 is doped to N-type.
[0114] It should be noted that portion (B1) of FIG. 17 illustrates the three-dimensional structure of the plurality of first silicon pillars 307 after well isolation is considered. A plan view of the corresponding three-dimensional structure is shown in portion (B2) of FIG. At this point, the longitudinal etching depth of the first silicon pillars 307 only reaches the upper portion of the silicon substrate 300-1. The plurality of first silicon pillars 307 (i.e., bit lines) are isolated from each other by PN junction structures, preventing leakage between the first silicon pillars 307.
[0115] In one embodiment, with reference to FIG18 , portion (A1) of FIG18 illustrates a stacked structure after well isolation is formed. Portion (A2) of FIG18 illustrates a two-dimensional plan view of the stacked structure. Consider that the stacked structure after well isolation includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, a second silicon layer 303, and a third silicon layer 304 located between the silicon substrate 300 and the first silicon layer. Optionally, the silicon substrate 300 is doped to a P-type, and the first silicon layer 301 and the third silicon layer 304 are doped to an N-type.
[0116] It can be noted that portion (B1) of FIG. 18 illustrates the three-dimensional structure of the plurality of first silicon pillars 307 after considering well isolation. Part (B2) of FIG. 18 illustrates a plan view of the corresponding three-dimensional structure. At this point, the vertical etching depth of the first silicon pillars 307 only reaches the third silicon layer 304. The plurality of first silicon pillars 307 (i.e., bit lines) are isolated from each other by PN junction structures, preventing leakage between the first silicon pillars 307.
[0117] Illustratively, the following four possible implementations of step 201 and step 1001 are provided.
[0118] A first possible implementation method involves obtaining a silicon substrate; doping the lower portion of the silicon substrate to N-type and the upper portion of the silicon substrate to P-type; sequentially stacking a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and doping the first silicon layer to P-type. Optionally, after doping, the silicon substrate is annealed to restore the silicon substrate's lattice.
[0119] With reference to FIG19 , FIG19 (A) shows a silicon substrate 300; FIG19 (B) shows a lower silicon substrate 300-1 doped to N-type and an upper silicon substrate 300-2 doped to P-type. FIG19 (C) shows a stacked first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303, where the first silicon layer 301 is doped to P-type.
[0120] A second possible implementation method involves obtaining a silicon substrate; doping the lower portion of the silicon substrate to P-type and the upper portion of the silicon substrate to N-type; sequentially stacking a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and doping the first silicon layer to N-type. Optionally, after doping the silicon substrate, annealing is performed to restore the silicon substrate lattice.
[0121] With reference to FIG20 , FIG20 (A) shows a silicon substrate 300; FIG20 (B) shows a lower silicon substrate 300-1 doped to P-type and an upper silicon substrate 300-2 doped to N-type. FIG20 (C) shows a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 stacked together, where the first silicon layer 301 is doped to N-type.
[0122] A third possible implementation method is to obtain a silicon substrate; dope the silicon substrate to N-type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer to P-type.
[0123] With reference to FIG21 , FIG21 (A) shows a silicon substrate 300, and FIG21 (B) shows an N-type doped silicon substrate 300. FIG21 (C) shows a stacked third silicon layer 304, a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303. The third silicon layer 304 is doped to a P-type, and the first silicon layer 301 is doped to a P-type.
[0124] A fourth possible implementation method includes obtaining a silicon substrate; doping the silicon substrate into a P-type silicon; sequentially stacking a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and doping the third silicon layer and the first silicon layer into an N-type silicon layer.
[0125] With reference to FIG22 , FIG22 (A) shows a silicon substrate 300, and FIG22 (B) shows a silicon substrate 300 doped to P-type. FIG22 (C) shows the stacked third silicon layer 304, first silicon layer 301, silicon germanium layer 302, and second silicon layer 303. Third silicon layer 304 is doped to N-type, and first silicon layer 301 is doped to N-type.
[0126] An embodiment of the present application provides an electronic device, which includes a logic device, wherein the logic device includes a 3D NAND gate circuit as provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc.
[0127] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0128] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise clearly defined.
[0129] In this application, the term "and / or" simply describes an association between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.
[0130] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.
Claims
1. A method for preparing a transistor, characterized in that: The method comprises: A first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303) are sequentially stacked on a silicon substrate (300), wherein the first silicon layer (301) is in contact with the silicon substrate (300); Forming a plurality of first silicon pillars (304) along a first direction by etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303); Forming a plurality of columns of second masks (305) along a second direction on the plurality of first silicon pillars (304), the second masks (305) comprising sidewalls (305-1); etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of columns of second masks (305); etching the silicon germanium layer (302) on the basis of the grooves obtained by etching to form lateral grooves; etching the first silicon layer (301), the lateral grooves and the second silicon layer (303) lateral epitaxial silicon; depositing gate material on the first silicon layer (301); performing anisotropic etching on the gate material according to the plurality of sidewalls (305-1) to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer (303); then removing the plurality of sidewalls (305-1) and the gate material in the second silicon layer (303) to form a plurality of second silicon pillars (306), wherein the plurality of second silicon pillars (306) are distributed in an array along the first direction and the second direction; Based on the plurality of second silicon pillars (306), a vertical all-around gate transistor is formed.
2. The method according to claim 1, characterized in that The anisotropic etching of the gate material is performed according to the plurality of sidewalls (305-1), comprising: Anisotropic etching of the gate material is performed on the layer where the multiple sidewalls (305-1) are located, and the etching is performed to the sidewalls of the multiple sidewalls (305-1); and anisotropic etching of the gate material is performed on the second silicon layer (303), and the etching is performed to the epitaxial silicon sidewalls of the second silicon layer (303); and, outside the coverage range of the multiple sidewalls (305-1), anisotropic etching of the gate material is performed on the silicon germanium layer (302).
3. The method according to claim 1 or 2, characterized in that: The first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are etched according to the plurality of second masks (305); based on the grooves obtained by etching, the silicon germanium layer (302) is further etched to form lateral grooves; Laterally epitaxial silicon is grown on the first silicon layer (301), the lateral groove and the second silicon layer (303), comprising: Etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of second masks (305) to form a plurality of first grooves (307); performing a first lateral etching on the silicon germanium layer (302), and then performing a first lateral epitaxial silicon growth on the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) to form first lateral grooves (308); The first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are etched according to the multiple core shafts (305-2) in the multiple columns of the second mask (305) to form a plurality of second grooves (309); a second lateral etching is performed on the silicon germanium layer (302), and then a second lateral epitaxial silicon growth is performed on the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) to form second lateral grooves (310), and the two lateral etchings enable the silicon germanium material of the silicon germanium layer (302) to be completely removed.
4. The method according to claim 3, characterized in that After forming the first lateral groove (308), the method further includes: filling the first lateral groove (308) with oxide and grinding it flat; filling the first groove (307) with oxide and grinding it flat; After forming the second lateral groove (310), the method further includes: filling the second lateral groove (310) with oxide and grinding it flat; and filling the second groove (309) with oxide and grinding it flat.
5. The method according to claim 4, characterized in that The step of depositing a gate material on the first silicon layer (301) comprises: Etching the oxide above the first silicon layer (301); The gate material is deposited in the gaps between the silicon germanium layer (302), the second silicon layer (303) and the plurality of spacers (305-1).
6. The method according to claim 5, characterized in that The etching of the oxide on the first silicon layer 301 includes: Etching the oxide above the silicon germanium layer (302) by a dry process; The oxide of the silicon germanium layer (302) is then etched using a wet process.
7. The method according to claim 5, characterized in that The step of removing the plurality of sidewalls (305-1) and the gate material in the second silicon layer (303) to form a plurality of second silicon pillars (306) comprises: Filling oxide in the gaps between the silicon germanium layer (302), the second silicon layer (303), and the plurality of sidewalls (305-1); Removing the plurality of side walls (305-1); The remaining gate material in the second silicon layer (303) is removed to form the plurality of second silicon pillars (306).
8. The method according to claim 1 or 2, characterized in that: Any second mask (305) in the plurality of columns of second masks (305) comprises a three-layer structure of a side wall (305-1), a core shaft (305-2) and a side wall (305-1).
9. An electronic device, characterized in that: The electronic device comprises a logic device, and the logic device comprises a transistor manufactured according to the method for manufacturing a transistor as claimed in any one of claims 1 to 8.
10. The electronic device according to claim 9, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.